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US20100044860 Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer  
An interconnection element can include a substrate, e.g., a connection substrate, element of a package, circuit panel or microelectronic substrate, e.g., semiconductor chip, the substrate having a...
US20110215472 Through Silicon via Bridge Interconnect  
An integrated circuit bridge interconnect device includes a first die and a second die provided in a side-by-side configuration and electrically interconnected to each other by a bridge die. The...
US20070132097 Projected contact structures for engaging bumped semiconductor devices  
A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom for contacting at least one solder...
US20130099379 SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, CIRCUIT SUBSTRATE, ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC EQUIPMENT  
A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers which are electrically connected to...
US20060131747 Carrier with metal bumps for semiconductor die packages  
A carrier for a semiconductor die package is disclosed. In one embodiment, the carrier includes a metal layer and a plurality of bumps formed in the metal layer. The bumps can be formed by stamping.
US20050051887 Clock distribution networks and conductive lines in semiconductor integrated circuits  
A clock distribution network (110) is formed on a semiconductor interposer (320) which is a semiconductor integrated circuit. An input terminal (120) of the clock distribution network is formed on...
US20050012225 Wafer-level chip scale package and method for fabricating and using the same  
A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned...
US20150035144 HIGH DENSITY INTERCONNECT DEVICE AND METHOD  
Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments,...
US20120261817 Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution  
A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed...
US20050161794 Semiconductor device, method for manufacturing the semiconductor device and semiconductor substrate  
The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing...
US20150054153 FLIP CHIP INTERCONNECTION WITH DOUBLE POST  
A method of assembling a packaged microelectronic element is disclosed that includes the steps of providing a microelectronic element having a plurality of conductive posts extending away from a...
US20140145329 FINE PITCH MICROCONTACTS AND METHOD FOR FORMING THEREOF  
A method includes applying a final etch-resistant material to an in-process substrate so that the final etch-resistant material at least partially covers first microcontact portions integral with...
US20120038045 Stacked Semiconductor Device And Method Of Fabricating The Same  
A stacked semiconductor device may have a plurality of chips stacked in three-dimension. The stacked semiconductor device may include a first semiconductor chip and at least one second...
US20110215469 METHOD FOR FORMING A DOUBLE EMBOSSING STRUCTURE  
A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in...
US20110186989 Semiconductor Device and Bump Formation Process  
A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a...
US20110101523 PILLAR BUMP WITH BARRIER LAYER  
A copper pillar bump has a surface covered with by a barrier layer formed of a copper-containing material layer including a group III element, a group IV element, a group V element or combinations...
US20090115047 Robust multi-layer wiring elements and assemblies with embedded microelectronic elements  
An interconnect element 130 can include a dielectric layer 116 having a top face 116b and a bottom face 116a remote from the top face, a first metal layer defining a plane extending along the...
US20060131748 Ball limiting metallurgy split into segments  
The present invention discloses a novel layout and process for a device with segmented BLM for the I/Os. In a first embodiment, each BLM is split into two segments. The segments are close to each...
US20060001156 Semiconductor device  
In a semiconductor device comprising a semiconductor chip, electrodes formed on the major surface of the semiconductor chip, and a wiring board for mounting the semiconductor chip, for example,...
US20170141062 COPPER-CONTAINING C4 BALL-LIMITING METALLURGY STACK FOR ENHANCED RELIABILITY OF PACKAGED STRUCTURES AND METHOD OF MAKING SAME  
The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy...
US20160148890 Method and Apparatus for Cooling Semiconductor Device Hot Blocks and Large Scale Integrated Circuit (IC) Using Integrated Interposer for IC Packages  
A method, system, and apparatus for improved IC device packaging is described. In an aspect, an (IC) device package includes an IC die having at one or more contact pads, each contact pad located...
US20150228627 STACKED SEMICONDUCTOR PACKAGES, METHODS FOR FABRICATING THE SAME, AND /OR SYSTEMS EMPLOYING THE SAME  
An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate....
US20120326301 THERMOSETTING RESIN COMPOSITION, FLIP-CHIP MOUNTING ADHESIVE, SEMICONDUCTOR DEVICE FABRICATION METHOD, AND SEMICONDUCTOR DEVICE  
The present invention is aimed to provide a thermosetting resin composition which is easily produced, has excellent storage stability and thermal stability while maintaining high transparency and...
US20110079900 MICROFEATURE WORKPIECES AND METHODS FOR FORMING INTERCONNECTS IN MICROFEATURE WORKPIECES  
Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a...
US20100295176 SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, CIRCUIT SUBSTRATE, ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC EQUIPMENT  
A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers which are electrically connected to...
US20050269714 Semiconductor device components with structures for stabilizing the semiconductor device components upon flip-chip arrangement with high-level substrates  
Semiconductor device components include a substrate with contact pads and at least one stabilizer protruding from the contact pad-bearing surface of the substrate. The at least one stabilizer may...
US20150357274 Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV  
A semiconductor device has a TSV wafer and semiconductor die mounted over the TSV wafer. A channel is formed through the TSV wafer. An encapsulant is deposited over the semiconductor die and TSV...
US20140015127 CONTACT SUPPORT PILLAR STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURE THEREFORE  
In one aspect, there is provided a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and...
US20120217634 Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier  
A semiconductor device includes a first semiconductor die or component having a plurality of bumps, and a plurality of first and second contact pads. In one embodiment, the first and second...
US20080122078 Systems and methods to passivate on-die redistribution interconnects  
An integrated circuit apparatus comprises a semiconductor substrate having a plurality of devices formed thereon, one or more metallization layers to interconnect the plurality of devices, and a...
US20160126264 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME  
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the...
US20120286423 Doping Minor Elements into Metal Bumps  
A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A...
US20120086003 SEMICONDUCTOR DEVICE AND TEST SYSTEM FOR THE SEMICONDUCTOR DEVICE  
A semiconductor package including a stress mitigation unit that mitigates stress to the semiconductor chip. The semiconductor package includes a substrate, a semiconductor chip on the substrate,...
US20080185718 Nanostructure-Based Package Interconnect  
An embodiment of the present invention is an interconnect technique. A nanostructure bump is formed on a die. The nanostructure bump has a template defining nano-sized openings and metallic...
US20170098628 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME  
A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor body and a conductive structure disposed below the semiconductor body. The semiconductor...
US20160268225 CHIP AND MANUFACTURING METHOD THEREOF  
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least...
US20130127049 Method for Stacking Devices and Structure Thereof  
A semiconductor device that has a first device that includes a first through-silicon via (TSV) structure, a first coating material disposed over the first device, the first coating material...
US20130001773 Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump  
A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A...
US20120267779 SEMICONDUCTOR PACKAGE  
The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive...
US20120126399 THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH BUMP/BASE/FLANGE HEAT SPREADER AND BUILD-UP CIRCUITRY  
A semiconductor assembly includes a semiconductor device, a heat spreader, an adhesive and a build-up circuitry. The heat spreader includes a bump, a base and a flange. The bump defines a cavity....
US20100102433 APPARATUS FOR USE IN SEMICONDUCTOR WAFER PROCESSING FOR LATERALLY DISPLACING INDIVIDUAL SEMICONDUCTOR DEVICES AWAY FROM ONE ANOTHER  
A chip-scale or wafer-level package, having passivation layers on substantially all surfaces thereof to form a hermetically sealed package, is provided. The package may be formed by disposing a...
US20080174013 SEMICONDUCTOR DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF  
A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper...
US20080173477 Circuit board and method for manufacturing the same and semiconductor device and method for manufacturing the same  
A circuit board includes a film substrate, a plurality of wiring layers arranged in order on the film substrate, and bumps formed on the wiring layers, respectively. Each of the bumps is provided...
US20070267725 Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package  
In a semiconductor chip, a body has a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces. A plurality of electrode pads are...
US20070170586 Printed circuit board for semiconductor package and method of manufacturing the same  
Disclosed are a printed circuit board for a semiconductor package and a method of manufacturing the same. Specifically, a printed circuit board for a semiconductor package includes predetermined...
US20060017161 Semiconductor package having protective layer for re-routing lines and method of manufacturing the same  
An apparatus and method for manufacturing a semiconductor package are disclosed. The apparatus may include at least a semiconductor chip having input/output (I/O) pads arranged on a surface...
US20050127508 Solder bump structure for flip chip package and method for manufacturing the same  
A solder bump structure may have a metal stud formed on a chip pad of a semiconductor chip. Surfaces of the metal stud may be plated with a solder. The metal stud may be located on a substrate pad...
US20160284671 Integrated Circuit Assembly and Method of Making  
An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal...
US20160035636 Manufacturing Method of Semiconductor Device  
Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and...
US20130320522 Re-distribution Layer Via Structure and Method of Making Same  
An embodiment is a semiconductor device comprising a contact pad over a substrate, wherein the contact pad is disposed over an integrated circuit on the substrate and a first passivation layer...