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US20130341783 INTERPOSER WITH IDENTIFICATION SYSTEM  
Various interposers and method of manufacturing related thereto are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an identification structure to an...
US20080001286 Shielded via  
A system may include a first conductive ground pad, a second conductive ground pad, a first conductive via coupling the first ground pad to the second ground pad, a first conductive signal trace,...
US20120119352 ELECTROLESS GOLD PLATING SOLUTION FOR FORMING FINE GOLD STRUCTURE, METHOD OF FORMING FINE GOLD STRUCTURE USING SAME, AND FINE GOLD STRUCTURE FORMED USING SAME  
An electroless gold plating solution with which one or more openings formed in a resist overlying a substrate can be filled in a short time, the openings having a width on the order of micrometer,...
US20050082668 Radio card  
A radio card includes a board, an LSI having a bump on one surface thereof and mounted on the board with the bump interposed therebetween, an SUS board having a rib which is bonded to the other...
US20110266539 High Performance Compliant Wafer Test Probe  
An electrical connection includes a first electrical contact made of electrically conductive material. The first electrical contact is formed with a depression therein. Also included are a...
US20130307151 METHOD TO RESOLVE HOLLOW METAL DEFECTS IN INTERCONNECTS  
A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are...
US20140264822 THERMOSETTING RESIN COMPOSITIONS WITH LOW COEFFICIENT OF THERMAL EXPANSION  
Thermosetting resin compositions with low coefficient of thermal expansion are provided herein.
US20120205793 SEED LAYER PASSIVATION  
A method of processing a microfeature workpiece generally includes depositing a first conducting layer, at least partially reducing oxides on the first conducting layer to provide a reduced first...
US20120112341 METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT  
A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add...
US20070210448 ELECTROLESS COBALT-CONTAINING LINER FOR MIDDLE-OF-THE-LINE (MOL) APPLICATIONS  
A semiconductor structure that includes a Co-containing liner disposed between an oxygen-getter layer and a metal-containing conductive material is provided. The Co-containing liner, the...
US20060284310 Offset via on pad  
A printed circuit board with an electrically conductive bonding pad disposed on an outer surface of the printed circuit board. The bonding pad has a bonding pad perimeter at immediately bounding...
US20140205780 LOW ALPHA PARTICLE EMISSION ELECTRICALLY-CONDUCTIVE COATING  
An electrically conductive paste providing low alpha particle emission is provided. A resin and conductive particles are mixed, and a curing agent is added. A solvent is subsequently added. The...
US20140203427 LOW ALPHA PARTICLE EMISSION ELECTRICALLY-CONDUCTIVE COATING  
An electrically conductive paste providing low alpha particle emission is provided. A resin and conductive particles are mixed, and a curing agent is added. A solvent is subsequently added. The...
US20140159227 PATTERNING TRANSITION METALS IN INTEGRATED CIRCUITS  
Fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines and depositing a protective cap on at least some of the one or...
US20050104207 Corrosion-resistant bond pad and integrated device  
The invention provides an integrated device with corrosion-resistant capped bond pads. The capped bond pads include at least one aluminum bond pad on a semiconductor substrate. A layer of...
US20070096309 Semiconductor device, method of forming wiring pattern, and method of generating mask wiring data  
A semiconductor device includes a first wiring portion and a second wiring portion. The first wiring portion is configured to include a plurality of fine wirings placed densely. The second wiring...
US20110316145 NANO/MICRO-STRUCTURE AND FABRICATION METHOD THEREOF  
A nano/micro-structure and a fabrication method thereof are provided. The method combines electroless plating and metal-assist etching to fabricate nano/micro-structure on a silicon substrate.
US20080042268 Void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same  
Void boundary structures, semiconductor devices having the void boundary structures, and methods of forming the same are provided. The structures, semiconductor devices and methods present a way...
US20120248608 SELF-FORMING, SELF-ALIGNED BARRIERS FOR BACK-END INTERCONNECTS AND METHODS OF MAKING SAME  
Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at...
US20140104968 METALLIZATION SCHEME FOR INTEGRATED CIRCUIT  
For multi-level interconnect metallization, each metal level maintains a parallel line arrangement within a region, and the lines of each adjacent metal level are orthogonal or otherwise cross...
US20050194678 Bonding pad structure, display panel and bonding pad array structure using the same and manufacturing method thereof  
A bonding pad structure is provided. The bonding pad is suitable for, such as display device including liquid crystal panel, printed circuit board (PCB) or other loader requiring a plurality of...
US20130313692 ANTENNA IN PACKAGE WITH REDUCED ELECTROMAGNETIC INTERACTION WITH ON CHIP ELEMENTS  
A IC package for a wireless device includes an antenna that is attached to the chip. The electrically conductive elements of the antenna are spaced away from the antenna and particularly the...
US20050184388 Seal ring design without stop layer punch through during via etch  
In accordance with the objective of the invention a new method is provided for the creation of a seal ring having dissimilar elements. The Critical Dimensions of the seal ring are selected with...
US20130105965 CHIP  
A chip includes: a chip body; and a metal layer formed on the chip body, and including a metal interconnect region electrically connected to the chip body, a light trapping region, and a light...
US20060076677 Resist sidewall spacer for C4 BLM undercut control  
A method and system for preventing undercutting of the solder bump in a C4 package by forming a barrier of resist that effectively widens the footprint of the solder bump. The BLM is then etched...
US20120217641 Preventing the Cracking of Passivation Layers on Ultra-Thick Metals  
A device includes a top metal layer; a UTM line over the top metal layer and having a first thickness; and a passivation layer over the UTM line and having a second thickness. A ratio of the...
US20060055032 Packaging with metal studs formed on solder pads  
A semiconductor assembly has solder bumps with increased reliability. One embodiment of an assembly comprises a first substrate having at least one conductive pad on its surface; a second...
US20100207269 Integrated Circuit Nanowires  
Implementations of encapsulated nanowires are disclosed.
US20120235295 BARRIER-METAL-FREE COPPER DAMASCENE TECHNOLOGY USING ENHANCED REFLOW  
A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single...
US20070164429 PACKAGE BOARD HAVING INTERNAL TERMINAL INTERCONNECTION AND SEMICONDUCTOR PACKAGE EMPLOYING THE SAME  
A package board is provided. The package board includes a board body having a front surface and a back surface. A first power pad, a first ground pad, a first signal pad, a first internal terminal...
US20150170926 DIELECTRIC LAYERS HAVING ORDERED ELONGATE PORES  
Embodiments of the present disclosure describe dielectric layers and methods for their fabrication and use. In some embodiments, a dielectric layer may include a dielectric material and a...
US20050161809 Power converter, power system provided with same, and mobile body  
To provide a power converter equipped with a current detector which is small and can carry out highly accurate current detection, in the power converter equipped with a power module 16 having a...
US20120097970 ATOMIC LAYER DEPOSITION ENCAPSULATION FOR POWER AMPLIFIERS IN RF CIRCUITS  
Power amplifiers and methods of coating a protective film of alumina (Al2O3) on the power amplifiers are disclosed herein. The protective film is applied through an atomic layer deposition (ALD)...
US20150130082 Configurable Routing for Packaging Applications  
Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die to a first side of a component using...
US20100308455 Method for Manufacturing Hetero-Bonded Wafer  
A method for manufacturing a hetero-bonded wafer having a large mismatch of thermal expansion coefficient comprises forming a wafer bonding means and an electrical interconnection means on at...
US20060290689 Semiconductor half-bridge module with low inductance  
A power module that includes embedded power bus bars and output bus arranged to lower the parasitic inductance.
US20100314752 FORMING AN ETCHED PLANARISED PHOTONIC CRYSTAL STRUCTURE  
A method of forming a photonic crystal (PhC) structure and a PhC structure formed by such method. The method comprises forming holes in a Si-based host layer; filling the holes with a high-density...
US20050051893 SBGA design for low-k integrated circuits (IC)  
A method of forming a ball grid array package, and the resultant ball grid array package, comprising the following steps. A semiconductor chip/die is provided. A ball grid substrate having: a heat...
US20090243089 MODULE INCLUDING A ROUGH SOLDER JOINT  
A module includes a metallized substrate including a metal layer, a base plate, and a joint joining the metal layer to the base plate. The joint includes solder contacting the base plate and an...
US20130187264 LOW OHMIC CONTACTS  
A method for forming a device is disclosed. A substrate with a contact region is provided. Vacancy defects are formed in the substrate. The vacancy defects have a peak concentration at a depth DV....
US20080012127 Insulation structure for multilayer passive elements and fabrication method thereof  
The present invention discloses an insulation structure for multilayer passive elements and a fabrication method thereof, wherein a protective insulation film is formed on the surface of a...
US20060091535 Fine pitch bonding pad layout and method of manufacturing same  
Disclosed herein is a bonding pad formed on an IC chip for electrically coupling the IC chip to another device or component, and associated methods of manufacturing the bonding pad. In one...
US20070158835 Method for designing interconnect for a new processing technology  
A method is disclosed for determining a size of an interconnect between a first and a second conductor respectively in two layers of an integrated circuit while scaling from a reference processing...
US20120071037 ELASTIC CONTACT DEVICE FOR ELECTRONIC COMPONENTS WITH BUCKLING COLUMNS  
An embodiment of an elastic contact device for electrically contacting electronic components is proposed. The contact device includes at least one basic module, which has a longitudinal axis. In...
US20110241200 ULTRA LOW DIELECTRIC CONSTANT MATERIAL WITH ENHANCED MECHANICAL PROPERTIES  
An ultra low dielectric constant material is disclosed. The ultra-low dielectric constant material comprises a three dimensional random network porous dielectric comprising atoms of Si, C, O, and...
US20060017171 Formation method and structure of conductive bumps  
A formation method and structure of conductive bump are provided. A conductive bump is formed on a wafer through an under bump metallurgy layer. A nickel-based wetting layer in the under bump...
US20090085201 DIRECT DEVICE ATTACHMENT ON DUAL-MODE WIREBOND DIE  
A dual-mode integrated circuit comprises wirebondable and solderable electrical connectors.
US20070045833 Copper bump barrier cap to reduce electrical resistance  
A controlled collapse chip connection (C4) comprises a copper metal C4 bump formed on an integrated circuit substrate, where the C4 bump includes a metal barrier cap to prevent electromigration of...
US20140306331 CHIP AND CHIP ARRANGEMENT  
Various embodiments provide a chip. The chip may include a body having two main surfaces and a plurality of side surfaces; a first power electrode extending over at least one main surface and at...
US20080116572 Semiconductor memory modules, methods of arranging terminals therein, and methods of using thereof  
Example embodiments may provide a semiconductor memory module having shorter length of terminal stubs, a method of arranging terminals to reduce or minimize length of each stub, and methods of...