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US20150014836 Electronic Module Assembly With Patterned Adhesive Array  
An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is...
US20150076680 HEAT SPREADER FOR INTEGRATED CIRCUIT DEVICE  
A BGA type packaged integrated circuit (IC) die has an exposed coronal heat spreader. The die, which is attached to a substrate, is encapsulated in a central segment of molding compound. The...
US20130270688 POWER MODULE  
A power module according to the present invention is a power module configured such that a power device chip is arranged within an outer casing and an electrode of the power device chip is...
US20050104187 Redistribution of substrate interconnects  
A first die/substrate is provided with a backside interconnect. A redistribution layer is provided between the first die/substrate and a second die/substrate that is stacked thereon, which...
US20090302446 SEMICONDUCTOR PACKAGE FABRICATED BY CUTTING AND MOLDING IN SMALL WINDOWS  
A method for cutting and molding in small windows of a window-type semiconductor package and the semiconductor package fabricated from the same are revealed. According to the method, a substrate...
US20090261432 Interconnection system on a plane adjacent to a solid-state device structure  
An interconnection system is provided for a solid-state device. The solid-state that includes, a first layer, multiple devices and a first face. A second layer is bonded to the first face at a...
US20120152302 Diode-Included Connector, Photovoltaic Laminate and Photovoltaic Assembly Using Same  
One embodiment relates to a connector that includes a diode. The diode has an anode and a cathode. The connector further includes a first electrical connection which connects to the anode, a...
US20060220187 HEATSINK MOLDLOCKS  
A system of mold locks (28, 30) is formed on a heatsink (2) of a packaged semiconductor to prevent/mitigate delamination . The mold locks (4, 12) anchor a plastic mold compound (34) that forms the...
US20080258291 Semiconductor Packaging With Internal Wiring Bus  
A packaged semiconductor includes inner bond fingers, at least first and second semiconductor dies, and an interposer. The packaged semiconductor further includes wiring between the first and...
US20100301470 STUD BUMPS AS LOCAL HEAT SINKS DURING TRANSIENT POWER OPERATIONS  
A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of...
US20080179745 LOCALIZED ALLOYING FOR IMPROVED BOND RELIABILITY  
In some embodiments a method of forming a gold-aluminum electrical interconnect is described. The method may include interposing a diffusion retardant layer between the gold and the aluminum...
US20140070393 HORIZONTALLY AND VERTICALLY ALIGNED GRAPHITE NANOFIBERS THERMAL INTERFACE MATERIAL FOR USE IN CHIP STACKS  
The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip...
US20100244266 METALLIC BONDING STRUCTURE FOR COPPER AND SOLDER  
The present invention discloses a metallic bonding structure for copper and solder, which applies to connect at least one electronic element. The metallic bonding structure comprises at least one...
US20110175179 PACKAGE STRUCTURE HAVING MEMS ELEMENT  
A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and...
US20140035119 ELECTRONIC SEMI - CONDUCTOR DEVICE INTENDED FOR MOUNTING IN A PRESSED STACK ASSEMBLY, AND A PRESSED STACK ASSEMBLY COMPRISING SUCH DEVICE  
A semi-conductor electronic device for mounting in a pressed stack assembly. The device comprises a box comprising a lower plate, an upper plate and a lateral wall mechanically connecting the...
US20150187679 Lid Design for Heat Dissipation Enhancement of Die Package  
Embodiments of a lid covering a device die improving heat dissipation for a die package are described. Trenches are formed on the bottom side of a lid to increase surface area for heat...
US20110147914 Clad Solder Thermal Interface Material  
A clad solder thermal interface material is described. In one example the material has a a first layer of solder having a melting temperature lower than a temperature of a particular solder reflow...
US20090212430 CARBON NANOTUBE-BASED CONDUCTIVE CONNECTIONS FOR INTEGRATED CIRCUIT DEVICES  
Electrical connection in an integrated circuit arrangement is facilitated with carbon nanotubes. According to various example embodiments, a carbon nanotube material (120, 135) is associated with...
US20090302447 SEMICONDUCTOR ARRANGEMENT HAVING SPECIALLY FASHIONED BOND WIRES AND METHOD FOR FABRICATING SUCH AN ARRANGEMENT  
A semiconductor arrangement includes first and second integrated circuits (dies), an electrically conductive intermediate element, and one or more bond conductors. The first and the second...
US20120146207 STACKED STRUCTURE AND STACKED METHOD FOR THREE-DIMENSIONAL CHIP  
A stacked structure and a stacked method for a three-dimensional integrated circuit are provided. The provided stacked method includes separating a logic chip into a function chip and an I/O chip;...
US20080157337 Semiconductor packaging substrate improving capability of electrostatic dissipation  
A semiconductor packaging substrate with improved capability of electrostatic dissipation comprises a dielectric layer, a plurality of leads, a plurality of first electrostatic guiding traces, a...
US20140239474 CHIP ARRANGEMENT AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT  
In various embodiments a chip arrangement is provided, wherein the chip arrangement may include a chip and at least one foil attached to at least one side of the chip.
US20080179731 Anti-Impact memory module  
An anti-impact memory module mainly comprises a multi-layer PWB (Printed Wiring Board), a plurality of memory packages and a plurality of first anti-impact bars. The PWB has two longer sides and...
US20060186529 Lead frame, sensor including lead frame and method of forming sensor including lead frame  
A lead frame includes a frame body defining an internal region, a plurality of leads extending from the frame body, and first and second stages that are disposed in the internal region. The first...
US20100090329 HIGH-POWER DEVICE HAVING THERMOCOUPLE EMBEDDED THEREIN AND METHOD FOR MANUFACTURING THE SAME  
Provided is a high-power device having a thermocouple (thermoelectric couple) for measuring the temperature of a transistor constituting a high-power device. The high-power device includes a...
US20090250804 LEADFRAME-BASED IC-PACKAGE WITH SUPPLY-REFERENCE COMB  
An IC package includes a leadframe-diepad (112) and a supply-reference comb (114) for interconnecting a die (110) and the package I/O pins (124) in a manner that facilitates substantially ideal...
US20130001764 POWER DEVICE HAVING REDUCED THICKNESS  
An electronic device includes at least one chip and an insulating body embedding the chip. The electronic device further includes a heat-sink in contact with the chip. The heat-sink includes a...
US20060001149 Packaged substrate having variable width conductors and a variably spaced reference plane  
A package substrate for a microelectronic die is described. The package substrate has first terminals in a small area and second terminals in a larger area with conductors connecting the first and...
US20130134571 POWER MODULE PACKAGE  
Disclosed herein is a power module package including: a first heat dissipation plate including a first flow path, a second flow path, and a third flow path which are sequentially formed, the first...
US20100258883 Metal-Ceramic Multilayer Structure  
A metal-ceramic multilayer structure is provided. The underlying layers of the metal/ceramic multilayer structure have sloped sidewalls such that cracking of the metal-ceramic multilayer structure...
US20090236710 COL SEMICONDUCTOR PACKAGE  
A Chip-On-Lead (COL) semiconductor package is revealed, primarily comprising a plurality of leadframe's leads each having a carrying bar, a finger and a connecting portion connecting the carrying...
US20060125074 Method of connecting internal silver traces to external gold to produce a gold external side metal for an LTCC package  
A method of connecting internal silver traces to external gold to produce a gold external side metal for a low-temperature co-fired ceramic package includes the deposition of a ruthenium dioxide...
US20090067135 Semiconductor Package Having Socket Function, Semiconductor Module, Electronic Circuit Module and Circuit Board with Socket  
Disclosed is a semiconductor package 3 including a socket 1 which is formed on the top surface 3a for enabling electrical conductivity and a connecting terminal 2 which is formed on the bottom...
US20140217570 TRANSISTOR OUTLINE HOUSING AND METHOD FOR PRODUCING SAME  
A transistor outline housing is provided that has bonding wires on an upper surface. The bonding wires are reduced in length and have connection leads with an excess length at an end opposite the...
US20060043565 Laser removal of plating tails for high speed packages  
A method wherein a substrate with plating tails is formed or otherwise provided, such as by performing a conventional electroplating process. Subsequently, a laser is used to remove some or all of...
US20100067207 SEMICONDUCTOR PACKAGE AND METHOD USING ISOLATED VSS PLANE TO ACCOMMADATE HIGH SPEED CIRCUITRY GROUND ISOLATION  
Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a...
US20080157334 Memory module for improving impact resistance  
A memory module for improving impact resistance mainly comprises a multi-layer PWB (Printed Wiring Board) and a plurality of memory packages. The multi-layer PWB is rectangular and has two longer...
US20130087902 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL STRUCTURES AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system includes: forming a thermal attach cluster includes: forming a heat collector having a heat dissipation surface, forming a cluster...
US20100084665 SOLID STATE LIGHT SHEET AND ENCAPSULATED BARE DIE SEMICONDUCTOR CIRCUITS  
An electronically active sheet includes a bottom substrate having a bottom electrically conductive surface. A top substrate having a top electrically conductive surface is disposed facing the...
US20110147913 MICROELECTRONIC PACKAGE AND METHOD FOR A COMPRESSION-BASED MID-LEVEL INTERCONNECT  
A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of...
US20090283883 Semiconductor device using lead frame  
A semiconductor device includes: a semiconductor chip configured to process a signal in a radio frequency band; two conductive antenna connection pins connected with two external antenna...
US20100084756 DUAL OR MULTIPLE ROW PACKAGE  
A dual or multiple row package (300) is provided which comprises a first plurality of terminals (303, 304, 305) and a second plurality of terminals (306, 307), which first and second plurality of...
US20090174055 Leadless Semiconductor Packages  
An encapsulation technique for leadless semiconductor packages entails: (a) attaching a plurality of dice (411) to die pads in cavities (41-45, 51-55) of a leadframe, the cavities arranged in a...
US20060061974 Solder foil semiconductor device and electronic device  
A solder foil formed from a material comprising particles of Cu, etc. as metal particles and Sn particles as solder particles by rolling is suitable for solder bonding at a high temperature side...
US20070108585 Semiconductor package including a semiconductor die having redistributed pads  
A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.
US20100314734 Processes and structures for IC fabrication  
The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the...
US20090224394 SOLID-STATE IMAGE SENSING APPARATUS AND PACKAGE OF SAME  
Warpage and twist of a solid-state image sensing apparatus is controlled, thereby preventing displacement occurring to the solid-state image sensing apparatus when it is mounted on a printed...
US20070241440 Overmolded semiconductor package with a wirebond cage for EMI shielding  
According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. The overmolded package further includes an overmold situated over the component and the...
US20070145564 Sequential fabrication of vertical conductive interconnects in capped chips  
A method is provided of forming a capped chip which includes a conductive interconnect exposed through an opening in the cap. A cap having openings extending between outer and inner surfaces is...
US20090236726 PACKAGE-ON-PACKAGE SEMICONDUCTOR STRUCTURE  
A semiconductor package that includes a substrate having first and second major surfaces is presented. The package includes a plurality of landing pads and a semiconductor die disposed on the...