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US20140167228 ETCH PROCESS WITH PRE-ETCH TRANSIENT CONDITIONING  
A method for etching features with different aspect ratios in an etch layer is provided. A plurality of cycles is provided wherein each cycle comprises a pre-etch transient conditioning of the...
US20130087892 Electrical Connection for Chip Scale Packaging  
A system and method for providing a post-passivation opening and undercontact metallization is provided. An embodiment comprises an opening through the post-passivation which has a first dimension...
US20130113086 SELF-LEVELING PLANARIZATION MATERIALS FOR MICROELECTRONIC TOPOGRAPHY  
Planarization methods and microelectronic structures formed therefrom are disclosed. The methods and structures use planarization materials comprising fluorinated compounds or acetoacetylated...
US20120223418 SOLUTION PROCESSIBLE HARDMASKS FOR HIGH RESOLUTION LITHOGRAPHY  
Solution processible hardmasks are described that can be formed from aqueous precursor solutions comprising polyoxometal clusters and anions, such as polyatomic anions. The solution processible...
US20070018214 Magnesium titanium oxide films  
Embodiments of a magnesium titanium oxide structure on a substrate provide a dielectric for use in a variety of electronic devices. Embodiments of methods of fabricating such a dielectric include...
US20130341769 ALUMINIUM OXIDE-BASED METALLISATION BARRIER  
The present invention relates to aluminium oxide-based passivation layers which simultaneously act as diffusion barrier for underlying wafer layers against aluminium and other metals. Furthermore,...
US20080048271 STRUCTURE AND METHOD TO USE LOW k STRESS LINER TO REDUCE PARASITIC CAPACITANCE  
A low k stress liner, which replaces conventional stress liners in CMOS devices, is provided. In one embodiment, a compressive, low k stress liner is provided which can improve the hole mobility...
US20100301461 RELIABLE INTERCONNECTION  
Embodiments relate to a method for forming reliable interconnects by the use of a device layer that can serve as a barrier or an etch stop layer, among other applications. The device layer is UV...
US20060226516 Silicon-doped carbon dielectrics  
A silicone-doped carbon interlayer dielectric (ILD) and its method of formation are disclosed. The ILD's dielectric constant and/or its mechanical strength can be tailored by varying the ratio of...
US20120205785 Technique for Etching Monolayer and Multilayer Materials  
A process is disclosed for sectioning by etching of monolayers and multilayers using an RIE technique with fluorine-based chemistry. In one embodiment, the process uses Reactive Ion Etching (RIE)...
US20090079040 Semiconductor structure with coincident lattice interlayer  
A semiconductor structure consistent with certain implementations has a crystalline substrate oriented with a {111} plane surface that is within 10 degrees of surface normal. An epitaxially grown...
US20140319660 SOLID-STATE ELECTRONIC DEVICE  
A solid-state electronic device according to the present invention includes: an oxide layer (possibly containing inevitable impurities) that is formed by heating, in an atmosphere containing...
US20070090494 Insulation-coated conductor and manufacturing method thereof  
There is provided an insulation-coated conductor including a conductive member that has a comer potion and a non-comer portion, and an insulating resin coated around the conductive member. The...
US20090243048 METALLIC NANOCRYSTAL ENCAPSULATION  
A method of forming a device includes forming protective shells about metallic nanocrystals supported by a substrate. The metallic nanocrystals having protective shells are encapsulated with a...
US20130069207 METHOD FOR PRODUCING A DEPOSIT AND A DEPOSIT ON A SURFACE OF A SILICON SUBSTRATE  
A deposit and a method for producing a deposit on a surface of a silicon substrate. The deposit comprises aluminum oxide, and the method comprises in any order the alternating steps of a)...
US20110254139 CMP-FIRST DAMASCENE PROCESS SCHEME  
An improved metal interconnect is formed with reduced metal voids and dendrites. An embodiment includes forming a mask layer on a dielectric layer, forming openings in the mask and dielectric...
US20120074487 APPARATUS CONTAINING COBALT TITANIUM OXIDE  
Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be...
US20100052115 Volatile Precursors for Deposition of C-Linked SiCOH Dielectrics  
Disclosed herein are precursors and methods for their use in the manufacture of semiconductor, photovoltaic, TFT-LCD, or flat panel type devices.
US20060194453 Silicon dioxide film and process for preparation of the same  
A transparent amorphous silicon dioxide film containing many fine voids, characterized in that the refractive index (for light at λ=500 nm) is in the range of 1.01 to 1.40 and that 80 vol. % or...
US20130134561 BACKSIDE THERMAL PATTERNING OF BURIED OXIDE (BOX)  
The dominant source of thermal resistance for silicon photonic devices patterned on SOI wafers is the buried oxide layer. To ensure efficient thermally driven silicon devices there is a need for a...
US20060102987 Marking method and sheet for both protective film forming and dicing  
The invention provides a marking method in which marking is performed on a protective film formed on a work with a high accuracy while suppressing a warpage and, also, a sheet for both protective...
US20090085082 CONTROLLED INTERMIXING OF HFO2 AND ZRO2 DIELECTRICS ENABLING HIGHER DIELECTRIC CONSTANT AND REDUCED GATE LEAKAGE  
Controlled deposition of HfO2 and ZrO2 dielectrics is generally described. In one example, a microelectronic apparatus includes a substrate and a dielectric film coupled with the substrate, the...
US20080217746 INSULATING FILM  
An insulating film for semiconductor devices is obtained by curing, on a substrate, a high molecular compound obtained by polymerizing a cage-type silsesquioxane compound having two or more...
US20110079884 Hydrogen Passivation of Integrated Circuits  
An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an...
US20090220782 Method of Forming Gallium Arsenide-On-Insulator  
A method of forming gallium arsenide (GaAs)-on-insulator includes providing a substrate and forming a diffusion barrier layer of a compound of formula AlxGa1-xAs on the substrate. A layer of GaAs...
US20100059834 INTEGRATED ELECTRONIC CIRCUIT INCLUDING A THIN FILM PORTION BASED ON HAFNIUM OXIDE  
An integrated electronic circuit has a thin layer portion based on hafnium oxide. This portion additionally contains magnesium atoms, so that the portion is in the form of a hafnium-and-magnesium...
US20060292885 Layout modification to eliminate line bending caused by line material shrinkage  
A semiconductor device and a method for fabricating a semiconductor device with reduced line bending is provided. The method can include forming a first layer and depositing a photoresist layer on...
US20130099357 STRAIN COMPENSATED REO BUFFER FOR III-N ON SILICON  
A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate...
US20090200553 HIGH TEMPERATURE THIN FILM TRANSISTOR ON SODA LIME GLASS  
The present invention generally comprises a low cost TFT and a method of manufacturing a TFT. For TFTs, soda lime glass would be an attractive alternative to non-alkali glass, but a soda lime...
US20120228748 PASSIVATION LAYER SURFACE TOPOGRAPHY MODIFICATIONS FOR IMPROVED INTEGRITY IN PACKAGED ASSEMBLIES  
A structure and method for producing the same is disclosed. The structure includes an organic passivation layer with solids suspended therein. Preferential etch to remove a portion of the organic...
US20100314724 Selective UV-Ozone Dry Etching of Anti-Stiction Coatings for MEMS Device Fabrication  
Organic anti-stiction coatings such as, for example, hydrocarbon and fluorocarbon based self-assembled organosilanes and siloxanes applied either in solvent or via chemical vapor deposition, are...
US20050280067 Atomic layer deposited zirconium titanium oxide films  
Dielectric layers having an atomic layer deposited oxide containing titanium and zirconium and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an...
US20100301344 DIELECTRIC LAYER FOR AN ELECTRONIC DEVICE  
A dielectric layer for an electronic device, such as a thin-film transistor, is provided. The dielectric layer comprises a molecular glass. The resulting dielectric layer is very thin, pure, and...
US20150129027 Silicon Wafer Coated With A Passivation Layer  
Production of a silicon wafer coated with a passivation layer. The coated silicon wafer may be suitable for use in photovoltaic cells which convert energy from light impinging on the front face of...
US20110204491 DIELECTRIC LAYER STRUCTURE  
A dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile film. The ILD layer further includes a low-k...
US20110062562 DIELECTRIC LAYER STRUCTURE  
A dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile hydrophobic film. The ILD layer further includes a...
US20130001754 IN-SITU PHOTORESIST STRIP DURING PLASMA ETCHING OF ACTIVE HARD MASK  
A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is...
US20130075872 Metal Pad Structures in Dies  
A die includes a substrate, a metal pad over the substrate, and a passivation layer that has a portion over the metal pad. A dummy pattern is disposed adjacent to the metal pad. The dummy pattern...
US20110048527 SILVER THICK FILM PASTE COMPOSITIONS AND THEIR USE IN CONDUCTORS FOR PHOTOVOLTAIC CELLS  
This invention provides a silver thick film paste composition comprising a silver powder comprising silver particles, each said silver particle comprising silver components 100-2000 nm long,...
US20110227070 GETTERING MEMBERS, METHODS OF FORMING THE SAME, AND METHODS OF PERFORMING IMMERSION LITHOGRAPHY USING THE SAME  
Provided herein are gettering members that include a monitor substrate and a conditioning layer thereon. Also provided herein are methods of forming gettering layers and methods of performing...
US20140246758 NITROGEN-CONTAINING OXIDE FILM AND METHOD OF FORMING THE SAME  
A method of forming a nitrogen-containing oxide film is disclosed. The method comprises (a) exposing a substrate to a first gas pulse having one of an oxygen-containing gas and a metal-containing...
US20150029638 POLYIMIDES AS DIELECTRICS  
Polyimides derived from a primary aromatic diamine and aromatic dianhydride mono-mer moieties, wherein one or more of said moieties contain at least one substituent on the aromatic ring selected...
US20100200964 METHOD OF PRODUCING A POROUS DIELECTRIC ELEMENT AND CORRESPONDING DIELECTRIC ELEMENT  
A porous dielectric element is produced by forming a first dielectric and a second dielectric. The second dielectric is dispersed in the first dielectric. The second dielectric is then removed...
US20090224373 Integrated circuit and method for manufacturing same  
When an integrated circuit having an interlayer insulation film built up on top of a wiring layer is subjected to a heat treatment, it is unlikely that a void formed in the interlayer insulation...
US20080265381 SiCOH DIELECTRIC  
A porous composite material useful in semiconductor device manufacturing, in which the diameter (or characteristic dimension) of the pores and the pore size distribution (PSD) is controlled in a...
US20140204967 Thermal Shunt  
A thermal shunt is to transfer heat from a sidewall of a device to a silicon substrate. The device is associated with a Silicon-On-Insulator (SOI) including a buried oxide layer. The thermal shunt...
US20100032813 IC FORMED WITH DENSIFIED CHEMICAL OXIDE LAYER  
A semiconductor device, such as an integrated circuit, has an oxide chemically grown on a silicon surface, and densified by annealing at, e.g., 950° C. for 4 to 5 seconds in an N2 ambient, or at...
US20090206453 Method for Preparing Modified Porous Silica Films, Modified Porous Silica Films Prepared According to This Method and Semiconductor Devices Fabricated Using the Modified Porous Silica Films  
A hydrophobic compound having at least one each of hydrophobic group (an alkyl group having 1 to 6 carbon atoms or a —C6H5 group) and polymerizable group (a hydrogen atom, a hydroxyl group or a...
US20130264625 COBALT TITANIUM OXIDE DIELECTRIC FILMS  
Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be...
US20140151856 Chip Module, an Insulation Material and a Method for Fabricating a Chip Module  
The chip module includes a carrier, a semiconductor chip arranged on or embedded inside the carrier, and an insulation layer that at least partly covers a face of the carrier. The dielectric...

Matches 1 - 50 out of 384 1 2 3 4 5 6 7 8 >