Matches 1 - 50 out of 269 1 2 3 4 5 6 >


Match Document Document Title
US20130277758 Method for Keyhole Repair in Replacement Metal Gate Integration Through the Use of a Printable Dielectric  
A method of fabricating a FET device is provided that includes the following steps. A wafer is provided. At least one active area is formed in the wafer. A plurality of dummy gates is formed over...
US20120153400 TUNNELING TRANSISTORS  
A transistor including a source; a drain; a gate region, the gate region including a gate; an island; and a gate oxide, wherein the gate oxide is positioned between the gate and the island; and...
US20150249076 HIGH PERFORMANCE STANDARD CELL  
A transistor cell is provided that includes a dummy gate overlaying a continuous oxide definition (OD) region. A first portion of the OD region adjacent a first side of the dummy forms the drain....
US20090174008 METHOD AND STRUCTURE TO PROTECT FETs FROM PLASMA DAMAGE DURING FEOL PROCESSING  
Protecting a FET from plasma damage during FEOL processing by forming a FET-like structure in conjunction with and adjacent to an FET, in a same well as the FET, but having a body doped opposite...
US20150243651 VERY PLANAR GATE CUT POST REPLACEMENT GATE PROCESS  
A semiconductor structure with improved gate planarity and method of fabrication are provided. In a replacement gate scheme, an array of sacrificial gate structures of substantially uniform pitch...
US20150171898 LINEARITY PERFORMANCE FOR RADIO-FREQUENCY SWITCHES  
Improved linearity performance for radio-frequency (RF) switches. In some embodiments, a switching device can include a first terminal and a second terminal, and a plurality of switching elements...
US20140239410 Integrated Circuit with Standard Cells  
A die includes a plurality of rows of standard cells. Each of all standard cells in the plurality of rows of standard cells includes a transistor and a source edge, wherein a source region of the...
US20150200010 Memory Cell  
Cell layouts for a memory cell, such as for ternary content addressable memory (TCAM), are disclosed. Some cell layouts include a well strap structure. A cell layout may include a p-doped well, an...
US20140353764 LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY  
A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during...
US20130313653 MOS Transistor with Multi-finger Gate Electrode  
A field effect transistor is described. In accordance with the one example, the transistor includes a semiconductor substrate, a gate pad for receiving a gate signal, a number of transistor cells...
US20110147765 DUMMY STRUCTURE FOR ISOLATING DEVICES IN INTEGRATED CIRCUITS  
The present disclosure provides an integrated circuit. The integrated circuit includes a first operational device having a first transistor of a first composition; a second operational device...
US20080067610 Mask rom and fabricating method thereof  
A mask ROM and fabrication method thereof are disclosed, in which a bit line is formed of a conductive material such as polysilicon, by which a device size can be minimized, and by which...
US20080122009 Dummy active area implementation  
Areas of a semiconductor substrate where semiconductor devices are not to be formed are filled in with dummy active areas. Whole dummy active areas are formed in areas of the semiconductor...
US20080315323 METHOD FOR FORMING LINE PATTERN ARRAY, PHOTOMASK HAVING THE SAME AND SEMICONDUCTOR DEVICE FABRICATED THEREBY  
A method of forming a line pattern array comprises the steps of setting a layout which includes first continuous line patterns arranged to have a first line width and a second continuous line...
US20080157221 STRUCTURE OF SEMICONDUCTOR DEVICE FOR DECREASING CHIP AREA AND MANUFACTURING METHOD THEREOF  
A method of manufacturing a semiconductor device for decreasing a chip area by changing a connecting structure of pull up transistors and pull down transistors are disclosed. The semiconductor...
US20150171109 DEVICES AND METHODS RELATED TO RADIO-FREQUENCY SWITCHES HAVING IMPROVED ON-RESISTANCE PERFORMANCE  
Devices and methods related to radio-frequency (RF) switches having improved on-resistance performance. In some embodiments, a switching device can include a first terminal and a second terminal,...
US20110024841 MOSFET WITH ASYMMETRICAL EXTENSION IMPLANT  
A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a...
US20090072322 SEMICONDUCTOR DEVICES INCLUDING LINE PATTERNS SEPARATED BY CUTTING REGIONS  
Semiconductor devices are provided. A semiconductor device can include a substrate and a plurality of dummy line patterns on the substrate that extend in a first direction parallel with one...
US20140008732 MACRO-TRANSISTOR DEVICES  
Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for...
US20080087938 Mask ROM, mask ROM embedded EEPROM and method of fabricating the same  
Example embodiments are directed to a mask ROM, a mask ROM embedded EEPROM and a method of fabricating the same. The mask ROM may include a select gate pattern and a memory gate pattern disposed...
US20130154027 Memory Cell  
A memory cell and array and a method of forming a memory cell and array are disclosed. An embodiment is a memory cell comprising first and second pull-up transistors, first and second pull-down...
US20150171108 RADIO-FREQUENCY SWITCHING DEVICES HAVING IMPROVED VOLTAGE HANDLING CAPABILITY  
Radio-frequency (RF) switching devices having improved voltage handling capability. In some embodiments, a switching device can include a first terminal and a second terminal, and a plurality of...
US20100164013 RANDOM PERSONALIZATION OF CHIPS DURING FABRICATION  
Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The...
US20090166756 MOS Transistor and Semiconductor Integrated Circuit  
A MOS transistor includes plural transistor cell blocks arranged adjacently in parallel to one another, wherein the plural transistor cell blocks are configured to have plural transistor cells,...
US20110186935 SEMICONDUCTOR DEVICE  
A MOS transistor includes a gate electrode formed in a grid pattern, source regions and drain regions each surrounded by the gate electrode, and a source metal wiring connected to the source...
US20140175559 INTEGRATED DEVICE HAVING MOSFET CELL ARRAY EMBEDDED WITH BARRIER SCHOTTKY DIODE  
Provided is an integrated device having a MOSFET cell array embedded with a junction barrier Schottky (JBS) diode. The integrated device comprises a plurality of areas, each of which includes a...
US20150236043 ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY PANEL  
An array substrate, a manufacturing method thereof and a display panel are provided. The array substrate includes: a substrate; and first pixel groups and second pixel groups which are disposed on...
US20060261418 MEMORY CELL WITH DOUBLE BB IMPLANT  
A buried bitline (BB) may be formed in at least two separate implantation steps, in addition to a pocket implant step. The pocket implant has a first width (W1) and a first depth (D1); the first...
US20100084715 PHOTO ALIGNMENT MARK FOR A GATE LAST PROCESS  
A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, the first and second regions being isolated from each other, a plurality of...
US20110204445 Selective Floating Body SRAM Cell  
A memory cell has N≧16 transistors, in which two are access transistors, at least one pair [say (N-2)/2] are pull-up transistors, and at least another pair [say (N-2)/2] are pull-down transistors....
US20110012202 Selective Floating Body SRAM Cell  
A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors....
US20050073010 Mask read only memory containing diodes and method of manufacturing the same  
A mask read only memory containing diodes and method of manufacturing the same. The mask read only memory is a high-density three dimensional array formed by stacking a plurality of diode layers...
US20150200096 CUT LAST SELF-ALIGNED LITHO-ETCH PATTERNING  
The present disclosure relates to a method of performing a self-aligned litho-etch (SALE) process. In some embodiments, the method is performed by forming a spacer material over a substrate having...
US20150200095 CUT FIRST SELF-ALIGNED LITHO-ETCH PATTERNING  
The present disclosure relates to a method for performing a self-aligned litho-etch (SALE) process. In some embodiments, the method is performed by forming a first cut layer over a substrate...
US20150187747 CIRCUIT WITH INTER-LAYER VIAS AND INTRA-LAYER COUPLED TRANSISTORS  
A circuit comprises a first layer comprising a first voltage line, a first transistor coupled with the first voltage line, a second transistor coupled with the first voltage line, and a first line...
US20090121296 Semiconductor device including dummy gate part and method of fabricating the same  
In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as...
US20090146188 SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF  
A semiconductor storage device includes a plurality of integrated memory cells. Each cell includes a first inverter having a first driver transistor and a first load transistor which are formed on...
US20140117458 HIGH-VOLTAGE TRANSISTOR HAVING SHIELDING GATE  
A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a...
US20130264627 HIGH-VOLTAGE TRANSISTOR HAVING SHIELDING GATE  
A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a...
US20110193152 HIGH-VOLTAGE TRANSISTOR HAVING SHIELDING GATE  
A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a...
US20080277717 MINORITY CARRIER SINK FOR A MEMORY CELL ARRAY COMPRISING NONVOLATILE SEMICONDUCTOR MEMORY CELLS  
A memory cell array of nonvolatile semiconductor memory cells is specified in which a minority carrier sink is formed within a semiconductor body in the region of the memory cell array, the...
US20080054372 Small-Pitch Three-Dimensional Mask-Programmable Memory  
The present invention discloses a small-pitch three-dimensional mask-programmable memory (SP-3DmM). It is an ultra-low-cost and ultra-high-density semiconductor memory. SP-3DmM comprises a...
US20140071731 One-Time Programmable Memory Cell  
A programmable memory cell including a thick oxide spacer transistor, a programmable thin oxide anti-fuse disposed adjacent to the thick oxide spacer transistor, and first and second thick oxide...
US20120099058 ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, LIQUID CRYSTAL DISPLAY  
Embodiments of the disclosed technology relates to an array substrate, a manufacturing method thereof and a liquid crystal display. The method comprises: forming a gate metal film, applying...
US20150241902 Integrated Circuit With Transistor Array And Layout Method Thereof  
An integrated circuit includes a plurality of transistors. The transistors are electrically connected in series and with their respective gates tied together. The transistors are implemented...
US20090200603 High density vertical structure nitride flash memory  
A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron...
US20050145923 NAND flash memory with enhanced program and erase performance, and fabrication process  
NAND flash memory cell array and fabrication process in which control gates and floating gates are stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion,...
US20070273476 Thin Semiconductor Device And Operation Method Of Thin Semiconductor Device  
The present invention provides a thin semiconductor device in which its security such as prevention of counterfeit or information leakage is to be enhanced. One feature of the present invention is...
US20120299116 DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME  
A display panel, in which a plurality of drive units in a transistor array substrate include a faulty drive unit, and a plurality of pixel electrodes include a first pixel electrode corresponding...
US20060186482 Shared contacts for MOSFET devices  
In one aspect, the present invention provides electronic devices that comprise a doped semiconductor shared contact between (a) a gate conductor region of at least one transistor and (b) a...

Matches 1 - 50 out of 269 1 2 3 4 5 6 >