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US20130341720 IMPLEMENTING GATE WITHIN A GATE UTILIZING REPLACEMENT METAL GATE PROCESS  
A method and circuit for implementing field effect transistors (FETs) having a gate within a gate utilizing a replacement metal gate process (RMGP), and a design structure on which the subject...
US20140339639 MULTI-DIRECTION WIRING FOR REPLACEMENT GATE LINES  
A post-planarization recess etch process is employed in combination with a replacement gate scheme to enable formation of multi-directional wiring in gate electrode lines. After formation of...
US20110241116 FET with FUSI Gate and Reduced Source/Drain Contact Resistance  
A method for forming a field effect transistor (FET) includes forming a gate stack on a silicon layer, the gate stack comprising a gate polysilicon on top of a gate oxide layer; forming a fully...
US20130256797 Asymmetric FET Formed Through Use of Variable Pitch Gate for Use as Logic Device and Test Structure  
Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a FET device is provided. The FET device includes a wafer; a plurality of...
US20140048882 TECHNIQUES FOR GATE WORKFUNCTION ENGINEERING TO REDUCE SHORT CHANNEL EFFECTS IN PLANAR CMOS DEVICES  
In one aspect, a CMOS device is provided. The CMOS device includes a SOI wafer having a SOI layer over a BOX; one or more active areas formed in the SOI layer in which one or more FET devices are...
US20140327076 ROBUST REPLACEMENT GATE INTEGRATION  
A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an...
US20110248343 Schottky FET With All Metal Gate  
A method for forming a Schottky field effect transistor (FET) includes forming a gate stack on a silicon substrate, the gate stack comprising a gate polysilicon on top of a gate metal layer;...
US20120007051 Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric  
Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is...
US20120299102 FET with FUSI Gate and Reduced Source/Drain Contact Resistance  
A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the...
US20130277743 STRATIFIED GATE DIELECTRIC STACK FOR GATE DIELECTRIC LEAKAGE REDUCTION  
A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a...
US20110222337 FLOATING-BODY/GATE DRAM CELL  
Memory cell structures and biasing schemes are provided. Certain embodiments pertain to a modified floating-body gate cell, which can provide improved retention times. In one embodiment, a gated...
US20070096208 Manufacturing method for flat panel display  
A dummy glass substrate supporting a plastic insulation substrate for a display apparatus wherein the dummy glass substrate includes a stress relaxation portion having grooves that reduce thermal...
US20150035059 METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS  
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region...
US20150214318 ALIGNED GATE-ALL-AROUND STRUCTURE  
A semiconductor device includes a gate disposed over a substrate. The gate has a first gate portion of the gate including a gate dielectric and a gate electrode disposed above a first channel...
US20150243651 VERY PLANAR GATE CUT POST REPLACEMENT GATE PROCESS  
A semiconductor structure with improved gate planarity and method of fabrication are provided. In a replacement gate scheme, an array of sacrificial gate structures of substantially uniform pitch...
US20080157200 STRESS LINER SURROUNDED FACETLESS EMBEDDED STRESSOR MOSFET  
The present invention provides an STI bounded transistor structure having enhanced performance which is not diminished due to embedded stressor facets that can be present at the edge of the...
US20080012073 TEST STRUCTURE FOR DETERMINING CHARACTERISTICS OF SEMICONDUCTOR ALLOYS IN SOI TRANSISTORS BY X-RAY DIFFRACTION  
By providing test features of increased thickness in a test structure for performing an x-ray diffraction measurement for evaluating the crystalline characteristics, such as the contents of...
US20100019320 Direct Contact to Area Efficient Body Tie Process Flow  
A process flow for fabricating shallow trench isolation (STI) devices with direct body tie contacts is provided. The process flow follows steps similar to standard STI fabrication methods except...
US20150171898 LINEARITY PERFORMANCE FOR RADIO-FREQUENCY SWITCHES  
Improved linearity performance for radio-frequency (RF) switches. In some embodiments, a switching device can include a first terminal and a second terminal, and a plurality of switching elements...
US20130153972 V-Groove Source/Drain Mosfet and Process For Fabricating Same  
A structure includes a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate and a silicided source/drain region formed in a V-shaped groove...
US20120205741 STRUCTURE AND METHOD FOR BURIED INDUCTORS FOR ULTRA-HIGH RESISTIVITY WAFERS FOR SOI/RF SIGE APPLICATIONS  
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high resistivity substrate and a buried inductor...
US20090057780 FINFET STRUCTURE INCLUDING MULTIPLE SEMICONDUCTOR FIN CHANNEL HEIGHTS  
A semiconductor structure and a method for fabricating the semiconductor structure include a first semiconductor fin and a second semiconductor fin of the same overall height over a substrate. Due...
US20150263726 NOVEL METHODOLOGY TO AVOID GATE STRESS FOR LOW VOLTAGE DEVICES IN FDSOI TECHNOLOGY  
An inverter is implemented in an FDSOI integrated circuit die. The inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to...
US20150129965 DEVICES AND METHODS RELATED TO RADIO-FREQUENCY SWITCHES HAVING REDUCED-RESISTANCE METAL LAYOUT  
Devices and methods related to radio-frequency (RF) switches having reduced-resistance metal layout. In some embodiments, a field-effect transistor (FET) based RF switch device can include a...
US20120168864 SELF-ALIGNED WELL IMPLANT FOR IMPROVING SHORT CHANNEL EFFECTS CONTROL, PARASITIC CAPACITANCE, AND JUNCTION LEAKAGE  
A transistor device includes a patterned gate structure formed over a substrate, the patterned gate structure including a gate conductor, a gate dielectric layer and sidewall spacers; and a doped...
US20110006367 GATE PATTERNING OF NANO-CHANNEL DEVICES  
Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In...
US20130043535 ISOLATION REGION FABRICATION FOR REPLACEMENT GATE PROCESSING  
A method for isolation region fabrication for replacement gate integrated circuit (IC) processing includes forming a plurality of dummy gates on a substrate; forming a block mask over the...
US20140183637 STRUCTURE FOR SELF-ALIGNED SILICIDE CONTACTS TO AN UPSIDE-DOWN FET BY EPITAXIAL SOURCE AND DRAIN  
An upside-down p-FET is provided on a donor substrate. The upside-down p-FET includes: self-terminating e-SiGe source and drain regions; a cap of self-aligning silicide/germanide over the e-SiGe...
US20090032872 MULTIPLE OXIDE THICKNESS FOR A SEMICONDUCTOR DEVICE  
Techniques associated with providing multiple gate insulator thickness for a semiconductor device are generally described. In one example, an apparatus includes a semiconductor fin having an...
US20130140636 STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS  
A stressed channel field effect transistor (FET) includes a substrate; a gate stack located on the substrate; a channel region located in the substrate under the gate stack; source/drain stressor...
US20140210004 SELF-ADJUSTING GATE HARD MASK  
A method provides an intermediate semiconductor device structure and includes providing a water having first dummy gate plugs and second dummy gate plugs embedded in a first layer having a non...
US20050280088 Backside body contact  
A back side body contact for a transistor that extends through an opening in an insulating layer located adjacent to the backside of the body. The backside contact is coupled to an interconnect on...
US20070001223 Ultrathin-body schottky contact MOSFET  
An ultra thin SOI MOSFET device structure and method of fabrication is presented. The device has a terminal composed of silicide, which terminal is forming a Schottky contact with the channel. A...
US20070267696 Mobile transforming plug  
A mobile transforming plug includes an insulating main body, a shell cover, a linking element and a linker. At the front side of the insulating main body, a connecting part is formed. A carrying...
US20100314684 FINFET WITH SEPARATE GATES AND METHOD FOR FABRICATING A FINFET WITH SEPARATE GATES  
The present invention relates to a FinFET with separate gates and to a method for fabricating the same. A dielectric gate-separation layer between first and second gate electrodes has an extension...
US20120306015 CONTACTS FOR FET DEVICES  
A device characterized as being an FET device structure with enlarged contact areas is disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both...
US20110180811 WIRELESS CHIP AND ELECTRONIC DEVICE HAVING WIRELESS CHIP  
It is an object to provide a wireless chip which can increase a mechanical strength, and a wireless chip with a high durability. A wireless chip includes a transistor including a field-effect...
US20070102760 Inhibiting radiation hardness of integrated circuits  
A system and method for inhibiting radiation hardness of Silicon on Insulator (SOI) integrated circuits is described. An electrical connection is used to connect a substrate below a buried oxide...
US20090166738 RAM CELL INCLUDING A TRANSISTOR WITH FLOATING BODY FOR INFORMATION STORAGE HAVING ASYMMETRIC DRAIN/SOURCE EXTENSIONS  
In a floating body storage transistor, the dopant concentration at the emitter side of the parasitic bipolar transistor may be significantly increased on the basis of a tilted implantation...
US20140217504 FINFET STRUCTURE AND METHOD TO ADJUST THRESHOLD VOLTAGE IN A FINFET STRUCTURE  
FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt...
US20130099313 FINFET STRUCTURE AND METHOD TO ADJUST THRESHOLD VOLTAGE IN A FINFET STRUCTURE  
FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt...
US20150129967 DUAL GATE FD-SOI TRANSISTOR  
Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the...
US20100038714 DEVICE AND PROCESS INVOLVING PINHOLE UNDERCUT AREA  
An electronic device fabrication method including: (a) providing a dielectric region and a lower electrically conductive region, wherein the dielectric region includes a plurality of pinholes each...
US20080150026 METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH AN ASYMMETRIC SILICIDE  
A MOSFET formed using asymmetric silicidation between source and drain induces higher leakage between the body and the source than between the body and the drain. Implementation of such a MOSFET...
US20070259500 Structure Having Isolation Structure Including Deuterium Within A Substrate And Related Method  
Structures having an isolation structure including deuterium and a related method are disclosed. The deuterium is preferably substantially uniformly distributed, and has a concentration (based on...
US20110024842 PROCEDURE FOR THE USE OF NATURAL CELLULOSIC MATERIAL, SYNTHETIC MATERIAL OR MIXED NATURAL AND SYNTHETIC MATERIAL, SIMULTANEOUSLY AS PHYSICAL AND DIELECTRIC SUPPORT IN SELF-SUSTAINABLE FIELD EFFECT ELECTRONIC AND OPTOELECTRONIC DEVICES  
The present invention refers to the use and creation of natural cellulosic material, synthetic or mixed material and corresponding production process to be used simultaneously as physical and...
US20110133280 DIFFERENT THICKNESS OXIDE SILICON NANOWIRE FIELD EFFECT TRANSISTORS  
A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method...
US20140353754 SELF-ALIGNED BOTTOM-GATED GRAPHENE DEVICES  
A carbon-based semiconductor structure includes a substrate and a gate stack. The gate stack includes a carbon-based gate electrode formed on the substrate. The gate stack also includes a gate...
US20140353750 SELF-ALIGNED BOTTOM-GATED GRAPHENE DEVICES  
A carbon-based semiconductor structure includes a substrate and a gate stack. The gate stack includes a carbon-based gate electrode formed on the substrate. The gate stack also includes a gate...
US20070200174 SOI substrate, mask blank for charged particle beam exposure, and mask for charged particle beam exposure  
The invention provides an SOI substrate 10 comprising on one major surface of a silicon single crystal 13 a silicon thin-film layer 11 via a buried silicon oxide film 12, characterized in that a...