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US20090194796 |
Vertical Gallium Nitride Semiconductor Device and Epitaxial Substrate
Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be... |
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US20140103422 |
STRUCTURE FOR MEMS TRANSISTORS ON FAR BACK END OF LINE
A MEMS transistor for a FBEOL level of a CMOS integrated circuit is disclosed. The MEMS transistor includes a cavity within the integrated circuit. A MEMS cantilever switch having two ends is... |
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US20120187473 |
Edge Termination With Improved Breakdown Voltage
A MOSFET switch which has a low surface electric field at an edge termination area, and also has increased breakdown voltage. The MOSFET switch has a new edge termination structure employing an... |
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US20140042524 |
Device with a Vertical Gate Structure
A device includes a wafer substrate, a conical frustum structure formed in the wafer substrate, and a gate all-around (GAA) structure circumscribing the middle portion of the conical frustum... |
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US20130299896 |
SUPERJUNCTION DEVICE
A superjunction device in which corner portions of each annular-shaped second trench are composed of a plurality of alternately arranged first sides and second sides. The first sides are parallel... |
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US20130320433 |
VERTICAL CHANNEL TRANSISTOR WITH SELF-ALIGNED GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME
A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on... |
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US20150115324 |
Switching Circuit
In an embodiment, a switching circuit includes input drain, source and gate nodes, a high voltage depletion mode transistor including a current path coupled in series with a current path of a low... |
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US20090302374 |
Differential Nitride Pullback to Create Differential NFET to PFET Divots for Improved Performance Versus Leakage
Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide... |
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US20130240842 |
ACTIVE MATRIX DILUTE SOURCE ENABLED VERTICAL ORGANIC LIGHT EMITTING TRANSISTOR
Various embodiments are provided for dilute source enabled vertical organic light emitting transistors. In various embodiments, a display panel includes an array of pixels. In one embodiment,... |
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US20100078710 |
Semiconductor component with a drift zone and a drift control zone
A semiconductor component has a drift zone and a drift control zone, a drift control zone dielectric, which is arranged in sections between the drift zone and the drift control zone, and has a... |
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US20150097226 |
FIELD EFFECT DEVICE WITH ENHANCED GATE DIELECTRIC STRUCTURE
A vertically oriented field effect device has a body and an enhance gate structure. The body includes a JFET (junction field effect transistor) region disposed between junction implants that... |
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US20130062675 |
PILLARS FOR VERTICAL TRANSISTORS
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide... |
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US20140191309 |
VERTICAL POWER MOSFET
When forming a super junction by the embedded epitaxial method, adjusting a taper angle of dry etching to form an inclined column is generally performed in trench forming etching, in order to... |
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US20100078711 |
METHOD OF MANUFACTURING INTEGRATED CIRCUITS INCLUDING A FET WITH A GATE SPACER
A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing... |
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US20080197406 |
Sensing FET integrated with a high-voltage vertical transistor
In one embodiment, a semiconductor device includes a main vertical field-effect transistor (FET) and a sensing FET. The main vertical FET and the sense FET are both formed on a pillar of... |
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US20110227147 |
SUPER JUNCTION DEVICE WITH DEEP TRENCH AND IMPLANT
RESURF effect devices with both relatively deep trenches and relatively deep implants are described herein. Also, methods of fabricating such devices are described herein. A RESURF effect device... |
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US20130193502 |
MEDIUM VOLTAGE MOSFET DEVICE
A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of... |
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US20130175606 |
INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME
A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain... |
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US20140021532 |
VERTICAL TUNNEL FIELD EFFECT TRANSISTOR (FET)
Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical... |
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US20120126311 |
POWER TRANSISTOR WITH METAL SOURCE AND METHOD OF MANUFACTURE
A metal source power transistor device and method of manufacture is provided, wherein the metal source power transistor having a source which is comprised of metal and which forms a Schottky... |
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US20120043602 |
Power MOSFET and Its Edge Termination
Improved MOSFET structures and processes, where multiple polysilicon embedded regions are introduced into the n+ source contact area. A top poly Field Plate is used to shield the electric field... |
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US20150162430 |
PLANAR VERTICAL DMOS TRANSISTOR WITH A CONDUCTIVE SPACER STRUCTURE AS GATE
A planar vertical DMOS transistor uses a conductive spacer structure formed on the sides of a dielectric structure as the gate of the transistor. The planar vertical DMOS transistor with a... |
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US20140001543 |
Integrated circuit device with metal gates including diffusion barrier layers and fabricating methods thereof
An integrated circuit device with metal gates including diffusion barrier layers and fabricating methods thereof are provided. The device may include a gate insulating film, a first conductivity... |
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US20100025757 |
Conductive structure and vertical-type pillar transistor
In a conductive structure, method of forming the conductive structure, a vertical-type pillar transistor and a method of manufacturing the vertical-type pillar transistor, the conductive structure... |
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US20150097225 |
TRENCH GATE TRENCH FIELD PLATE SEMI-VERTICAL SEMI-LATERAL MOSFET
A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the... |
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US20100065903 |
High-voltage vertical transistor with a varied width silicon pillar
In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and... |
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US20140110779 |
VERTICAL POWER MOSFET
Vertical power MOSFETs having a super junction are devices capable of having a lower on resistance than other vertical power MOSFETs. Although they have the advantage of high-speed switching due... |
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US20150008511 |
BOND PAD STACK FOR TRANSISTORS
A method for forming bond pads on a semiconductor die includes forming a dielectric stack including a bottom and top dielectric layer having a contact hole therethrough over a bond pad. An outer... |
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US20120056261 |
BI-DIRECTIONAL, REVERSE BLOCKING BATTERY SWITCH
Embodiments of the present invention relate to an improved package for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side,... |
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US20100320531 |
STANDING CHIP SCALE PACKAGE
A standing chip scale package is disclosed. The standing chip scale package provides electrical connection to bumped device contacts on both sides of the chip. The package is coupleable to a... |
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US20080142811 |
MOSFET devices and methods of fabrication
A vertical MOSFET is disclosed. The MOSFET includes a gate dielectric region, a drift region having a drift region dopant concentration profile of a first conductivity type, and a JFET region... |
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US20100276741 |
INTEGRATED CIRCUIT WITH BURIED DIGIT LINE
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is... |
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US20090057755 |
SPACER UNDERCUT FILLER, METHOD OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME
Disclosed herein is a semiconducting device comprising a gate stack formed on a surface of a semiconductor substrate; a vertical nitride spacer element formed on each vertical sidewall of the gate... |
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US20140239385 |
FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
A Field Effect Transistor (FET) and a method of manufacturing the same are provided. The FET may include a substrate; a source and a drain, one of which is formed on a bulge formed on a top... |
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US20070252195 |
VERTICAL AND TRENCH TYPE INSULATED GATE MOS SEMICONDUCTOR DEVICE
A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate... |
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US20100295023 |
FIELD EFFECT TRANSISTOR FABRICATION FROM CARBON NANOTUBES
Methods and apparatus for an electronic device such as a field effect transistor. One embodiment includes fabrication of an FET utilizing single walled carbon nanotubes as the semiconducting... |
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US20110180867 |
METAL TRANSISTOR DEVICE
The present invention is related to a depletion or enhancement mode metal transistor in which the channel regions of a transistor device comprises a thin film metal or metal composite layer formed... |
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US20140239383 |
WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE
Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of... |
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US20090140328 |
Bridged Gate FinFet
In a fin-type field effect transistor (FinFET) structure, a gate strap is positioned on the top of a gate conductor and runs along the gate conductor. The top of the gate strap is positioned a... |
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US20140284703 |
VERTICAL DOUBLE-DIFFUSION MOS AND MANUFACTURING TECHNIQUE FOR THE SAME
In one embodiment, a method of making a VDMOS transistor can include: (i) etching an oxide layer formed on a surface of an epitaxial structure to define an active region of the VDMOS; (ii)... |
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US20130140629 |
INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL
A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate... |
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US20110101449 |
ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD
Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain... |
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US20110316073 |
SOI CMOS DEVICE HAVING VERTICAL GATE STRUCTURE
The present invention discloses an SOI CMOS device having a vertical gate structure, comprising: an SOI substrate, and an NMOS region and a PMOS region grown on the SOI substrate, wherein the NMOS... |
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US20070296029 |
INTEGRATRED CIRCUIT INCLUDING A TRENCH TRANSISTOR HAVING TWO CONTROL ELECTRODES
An integrated circuit including a field effect controllable trench transistor having two-control electrodes is disclosed. One embodiment provides a trench having a first control electrode and a... |
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US20050133857 |
Power semiconductor component having a gentle turn-off behavior
A vertical semiconductor component having a semiconductor body, which has an inner region and an edge region that is arranged between the inner region and an edge of the semiconductor body. At... |
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US20140264557 |
SELF-ALIGNED APPROACH FOR DRAIN DIFFUSION IN FIELD EFFECT TRANSISTORS
A method for doping terminals of a field-effect transistor (FET), the FET including a drain region, a source region, and a surround gate surrounding a channel region, the method including... |
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US20140231902 |
Vertical Tunneling Field-Effect Transistor Cell
A tunneling field-effect transistor (TFET) device is disclosed. The TFET device includes a source contact on the source region, a plurality of gate contacts at a planar portion of a gate stack and... |
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US20140284705 |
METHOD OF MANUFACTURING VERTICAL PLANAR POWER MOSFET AND METHOD OF MANUFACTURING TRENCH-GATE POWER MOSFET
In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and... |
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US20140183623 |
TRANSISTOR STRUCTURE HAVING A TRENCH DRAIN
A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device.... |
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US20140203352 |
Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same
A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on... |