Matches 1 - 50 out of 325 1 2 3 4 5 6 7 >


Match Document Document Title
US20150194537 MULTI-LAYER INTER-GATE DIELECTRIC STRUCTURE  
A semiconductor device having a first gate stack on a substrate is disclosed. The first gate stack may include a first gate conductor over a first gate dielectric structure. A dielectric structure...
US20140291747 Tungsten Salicide Gate Source For Vertical NAND String To Control On Current And Cell Pillar Fabrication  
A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. During fabrication of the memory device, a tungsten salicide is utilized as an etch-stop layer...
US20140170843 Charge Trapping Split Gate Device and Method of Fabricating Same  
Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split...
US20150255468 CONTACT STRUCTURE AND FORMING METHOD  
Vias are formed within a stack of alternating active and insulating layers by forming a first sub stack, a second sub stack over the first sub stack, a first buffer layer therebetween and a second...
US20150187891 Formation of Gate Sidewall Structure  
A semiconductor device having a gate stack on a substrate is disclosed. The gate stack may include a mask layer disposed over a first gate conductor layer. The first gate conductor layer may be...
US20150091079 NON-VOLATILE MEMORY (NVM) AND HIGH-K AND METAL GATE INTEGRATION USING GATE-FIRST METHODOLOGY  
A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM portion and a first protection layer over a logic portion. A control gate and a storage layer...
US20150236035 Methods For Forming Contact Landing Regions In Split-Gate Non-Volatile Memory (NVM) Cell Arrays  
Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select...
US20090179256 MEMORY HAVING SEPARATED CHARGE TRAP SPACERS AND METHOD OF FORMING THE SAME  
A silicon-oxide-nitride-oxide-silicon (SONOS) memory and the corresponding forming method are disclosed. The memory includes a plurality of select gate structures arranged in an array, a plurality...
US20150008509 METHOD FOR MANUFACTURING A DOUBLE-GATE ELECTRONIC MEMORY CELL AND ASSOCIATED MEMORY CELL  
A method of manufacturing a double-gate electronic memory cell is presented. The cell includes a substrate; a first gate structure, with the first gate structure having a lateral flank; a stack...
US20140319597 Methods And Systems For Gate Dimension Control In Multi-Gate Structures For Semiconductor Devices  
Methods and systems are disclosed for gate dimension control in multi-gate structures for integrated circuit devices. Processing steps for formation of one or more subsequent gate structures are...
US20120217573 NON-VOLATILE MEMORY (NVM) CELL FOR ENDURANCE AND METHOD OF MAKING  
A first dielectric is formed over a semiconductor layer, a first gate layer over the first dielectric, a second dielectric over the first gate layer, and a third dielectric over the second...
US20080296664 INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES  
A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic...
US20090251972 NONVOLATILE MEMORY ARRAYS WITH CHARGE TRAPPING DIELECTRIC AND WITH NON-DIELECTRIC NANODOTS  
Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to...
US20110198686 NITRIDE READ ONLY MEMORY DEVICE WITH BURIED DIFFUSION SPACERS AND METHOD FOR MAKING THE SAME  
A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate...
US20090146207 Nonvolatile Memory Devices Including Common Source  
Provided is a nonvolatile memory device including a common source. The device includes a first active region crossing a second active region, a common source disposed in the second active region,...
US20090200603 High density vertical structure nitride flash memory  
A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron...
US20090194810 SEMICONDUCTOR DEVICE USING ELEMENT ISOLATION REGION OF TRENCH ISOLATION STRUCTURE AND MANUFACTURING METHOD THEREOF  
A stacked film including a gate dielectric film and electrode film of each memory cell of a flash memory is formed on a semiconductor substrate. The stacked film is patterned by reactive ion...
US20150179660 Three Dimensional NAND Device with Channel Located on Three Sides of Lower Select Gate and Method of Making Thereof  
A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side,...
US20100067301 COLUMNAR NON-VOLATILE MEMORY DEVICES WITH AUXILIARY TRANSISTORS AND METHODS OF OPERATING THE SAME  
A non-volatile memory device includes at least one semiconductor column having a first sidewall and a second sidewall. The device also includes at least one gate electrode is disposed on the first...
US20140167142 Use Disposable Gate Cap to Form Transistors, and Split Gate Charge Trapping Memory Cells  
A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer...
US20090321816 Vertical-type non-volatile memory device  
In a vertical-type non-volatile memory device, first and second single-crystalline semiconductor pillars are arranged to face each other on a substrate. Each of the first and second...
US20140264533 CELL PILLAR STRUCTURES AND INTEGRATED FLOWS  
Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a...
US20080283904 TWO-BIT FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME  
A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a gate stacked on the gate oxide layer. A charge storage spacer stack is disposed at either side of...
US20080106948 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, MANUFACTURING METHOD THEREOF AND METHOD OF PROGRAMMING INFORMATION INTO THE MEMORY DEVICE  
A nonvolatile semiconductor memory device capable of improving injection efficiency and simplifying manufacturing process is provided. The device comprises a memory cell having second conductive...
US20100052043 HIGH DENSITY FLASH MEMORY DEVICE AND FABRICATING METHOD THEREOF  
The present invention provides a flash memory device having a high degree of integration and high performance. The flash memory device has a double/triple gate structure where a channel is formed...
US20140353739 Semiconductor device and fabrication method thereof  
A semiconductor device including a first gate structure and a second gate structure immediately adjacent to each other with a spacer therebetween. Line width of the top of the second gate...
US20090065845 Embedded semiconductor device and method of manufacturing an embedded semiconductor device  
Provided are an embedded semiconductor device and a method of manufacturing an embedded semiconductor device. In a method of manufacturing the embedded semiconductor device, layers of at least one...
US20080067583 Nonvolatile semiconductor memory device and manufacturing method thereof  
A nonvolatile semiconductor memory device includes a substrate, and a plurality of memory strings, the memory string including a first selection transistor including a first pillar shaped...
US20080128793 NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY CELL HAVING ASYMMETRICAL DOPED STRUCTURE  
A non-volatile memory cell comprising a substrate, a charge-trapping layer, a control gate, a first conductive state of source and drain, a lightly doped region and a second conductive state of...
US20140133244 Twin MONOS Array for High Speed Application  
A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in...
US20090242970 SEMICONDUCTOR DEVICE, CAPACITOR, AND FIELD EFFECT TRANSISTOR  
It is made possible to provide a semiconductor device that has the effective work function of the connected metal optimized at the interface between a semiconductor and the metal. A semiconductor...
US20110215395 MULTI-TRANSISTOR MEMORY CELL  
The invention relates to a multi-transistor, e.g. two-transistor memory cell arranged on a semiconductor substrate 1 comprising an access transistor 5 and a memory transistor 6, the access...
US20050139905 Dummy layer in semiconductor device and fabricating method thereof  
A semiconductor device and fabricating method. The semiconductor device includes a semiconductor substrate, a device isolation layer on the semiconductor substrate in a logic area of the...
US20100072539 MEMORY CELL OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A memory cell of a nonvolatile semiconductor memory device according to an embodiment of the invention has a MONOS structure. The charge storage layer of the memory cell includes insulating...
US20090114977 NONVOLATILE MEMORY DEVICE HAVING CHARGE TRAPPING LAYER AND METHOD FOR FABRICATING THE SAME  
Disclosed herein is a nonvolatile memory device having a charge trapping layer and a method of making the same. The nonvolatile memory device includes a substrate, a tunneling layer disposed on...
US20100044779 Memory devices capable of reducing lateral movement of charges  
Memory devices is provided, the memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking...
US20080128794 Non-Volatile Memory Including Insulated Gate Bipolar Transistors And Charge Trapping Layer Containing Silicon and Nitrogen  
A memory block of a semiconductor memory array where the semiconductor memory array is a NOR array, a NAND array, or an AND array includes a bit line, memory cells where each memory cell has a...
US20150145022 CMP FABRICATION SOLUTION FOR SPLIT GATE MEMORY EMBEDDED IN HK-MG PROCESS  
A semiconductor device includes a substrate, at least one logic device and a split gate memory device. The at least one logic device is located on the substrate. The split gate memory device is...
US20130264634 LOGIC TRANSISTOR AND NON-VOLATILE MEMORY CELL INTEGRATION  
A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate....
US20130264633 LOGIC TRANSISTOR AND NON-VOLATILE MEMORY CELL INTEGRATION  
A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate....
US20110248334 MULTI-LEVEL CHARGE STORAGE TRANSISTORS AND ASSOCIATED METHODS  
Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and...
US20100038704 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE SUPPRESSING FLUCTUATION IN THRESHOLD VOLTAGE  
First and second memory cell transistors are isolated by an element isolation insulating film. A barrier insulating film covers the element isolation insulating film. The first memory cell...
US20090108334 Charge Trap Device and Method for Fabricating the Same  
A charge trapping device includes a plurality of isolation layers, a plurality of charge trapping layers, a blocking layer, and a control gate electrode. The isolation layers define active...
US20090121275 Non-Volatile Memory Devices Including Blocking and Interface Patterns Between Charge Storage Patterns and Control Electrodes and Related Methods  
A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor...
US20090184364 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME  
A non-volatile semiconductor storage device includes device regions and device isolation regions that are formed on a semiconductor substrate, with a first direction defined as their longitudinal...
US20090039417 Nonvolatile Flash Memory Device and Method for Producing Dielectric Oxide Nanodots on Silicon Dioxide  
A method of producing dielectric oxide nanodots (104) embedded in silicon dioxide as well as a nonvolatile flash memory device comprising a trapping layer (224), the trapping layer (224)...
US20100025755 SEMICONDUCTOR DEVICE  
In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate 1 a first...
US20090207667 NAND FLASH MEMORY ARRAY WITH CUT-OFF GATE LINE AND METHODS FOR OPERATING AND FABRICATING THE SAME  
A NAND flash memory array, an operating method and a fabricating method of the same are provided. The NAND flash memory array has a cut-off gate line under a control gate in order to operate two...
US20080179659 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
A nonvolatile semiconductor memory device relating to one embodiment of this invention includes a substrate, a plurality of memory strings formed on said substrate, said memory string having a...
US20100006925 NON-VOLATILE TWO TRANSISTOR MEMORY CELL AND METHOD FOR PRODUCING THE SAME  
The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory...

Matches 1 - 50 out of 325 1 2 3 4 5 6 7 >