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US20090032861 NONVOLATILE MEMORIES WITH CHARGE TRAPPING LAYERS CONTAINING SILICON NITRIDE WITH GERMANIUM OR PHOSPHORUS  
A nonvolatile memory has a charge trapping layer which includes a layer (130) made of silicon nitride doped with germanium or phosphorus (210). The germanium or phosphorus contains a large...
US20130082318 INTEGRATION OF eNVM, RMG, AND HKMG MODULES  
A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two...
US20140048866 GATE STRUCTURE AND METHOD OF MANUFACTURING THEREOF  
An improved gate structure is provided whereby the gate structure is defined by a trench, the trench having a first oxide layer and a second oxide layer. The invention also provides methods for...
US20150060989 Split Gate Nanocrystal Memory Integration  
A process integration is disclosed for fabricating non-volatile memory (NVM) cells having spacer control gates (108) along with a high-k-metal-poly select gate (121, 123, 127) and one or more...
US20100052037 Charge-trapping engineered flash non-volatile memory  
This invention proposes a charge-trapping-engineered flash (CTEF) non-volatile memory (NVM) of electrode-[blocking oxide]-[trapping—1-trapping—2]-[tunneling oxide]-semiconductor. Dual trapping...
US20090175089 Retention in NVM with top or bottom injection  
Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM,...
US20110037117 LANTHANUM-METAL OXIDE DIELECTRIC APPARATUS, METHODS, AND SYSTEMS  
Lanthanum-metal oxide dielectrics and methods of fabricating such dielectrics provide an insulating layer in a variety of structures for use in a wide range of electronic devices and systems. In...
US20080121982 Semiconductor structure, semiconductor memory device and method of manufacturing the same  
A semiconductor structure includes first and second conductive lines which cross each other. The second conductive lines are electrically insulated from the first conductive lines via an...
US20120074487 APPARATUS CONTAINING COBALT TITANIUM OXIDE  
Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be...
US20080025084 High aspect ration bitline oxides  
A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area, an oxide-nitride-oxide (ONO) layer within the word line areas and at least...
US20100271878 INJECTION METHOD WITH SCHOTTKY SOURCE/DRAIN  
An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon....
US20080142873 INTEGRATED CIRCUIT SYSTEM WITH METAL AND SEMI-CONDUCTING GATE  
A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting...
US20090303794 Structure and Method of A Field-Enhanced Charge Trapping-DRAM  
A field-enhanced (FE) charge trapping-DRAM (TDRAM) device is described which is suitable for DRAM applications, and for additional applications with lower power requirements. In some embodiments,...
US20090173991 METHODS FOR FORMING RHODIUM-BASED CHARGE TRAPS AND APPARATUS INCLUDING RHODIUM-BASED CHARGE TRAPS  
Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge traps in electronic structures for use in a wide range of...
US20140332876 HIGH VOLTAGE GATE FORMATION  
Embodiments described herein generally relate to methods of manufacturing charge-trapping memory by patterning the high voltage gates before other gates are formed. One advantage of such an...
US20140167137 High Voltage Gate Formation  
Embodiments described herein generally relate to methods of manufacturing charge-trapping memory by patterning the high voltage gates before other gates are formed. One advantage of such an...
US20090059675 Radiation hardened multi-bit sonos non-volatile memory  
In one aspect, a radiation hardened transistor includes a buried source, buried drain and a poly-silicon gate separated from the buried source and the buried drain by a buried oxide. A recessed P+...
US20120306000 Formation of Field Effect Transistor Devices  
A method includes defining active regions on a substrate, forming a dummy gate stack material over exposed portions of the active regions of the substrate and non-active regions of the substrate,...
US20140239371 FIELD EFFECT TRANSISTOR WITH SELF-ADJUSTING THRESHOLD VOLTAGE  
Methods for forming field effect transistors (FETs) with improved ON/OFF current ratios in addition to short charging times and the resulting devices are disclosed. Embodiments include forming a...
US20090101963 SPLIT CHARGE STORAGE NODE INNER SPACER PROCESS  
Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic...
US20130009233 Transistor Constructions and Processing Methods  
A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A...
US20110260236 Transistor Constructions and Processing Methods  
A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A...
US20080290400 SONOS ONO stack scaling  
Scaling a nonvolatile trapped-charge memory device and the article made thereby. In an embodiment, scaling includes multiple oxidation and nitridation operations to provide a tunneling layer with...
US20140264542 MEMORY INCLUDING BLOCKING DIELECTRIC IN ETCH STOP TIER  
Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over...
US20090039414 CHARGE TRAPPING MEMORY CELL WITH HIGH SPEED ERASE  
A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a metal or metal compound gate, such as a platinum gate, by a blocking layer of...
US20080150005 MEMORY SYSTEM WITH DEPLETION GATE  
A memory system includes a substrate, forming a first insulator layer over the substrate, forming a charge-storage layer over the first insulator layer, forming a second insulator layer over the...
US20080079061 Flash memory cell structure for increased program speed and erase speed  
According to one exemplary embodiment, a structure, for example a flash memory cell, comprises a transistor gate dielectric stack situated on a semiconductor substrate. The transistor gate...
US20080217680 NON-VOLATILE SEMICONDUCTOR MEMORY USING CHARGE-ACCUMULATION INSULATING FILM  
There is provided a non-volatile semiconductor memory having a charge accumulation layer of a configuration where a metal oxide with a dielectric constant sufficiently higher than a silicon...
US20090040829 LATERAL POCKET IMPLANT CHARGE TRAPPING DEVICES  
A charge trapping memory cell is described, having pocket implants along the sides of the channel and having the same conductivity type as the channel, and which implants have a concentration of...
US20050087793 Embedded non-volatile memory and a method for fabricating the same  
A low density and cost effective embedded non-volatile memory cell includes a semiconductor substrate of a first conductivity type and having device isolation regions and active regions defined...
US20090294831 Semiconductor Constructions, Methods Of Forming Transistor Gates, And Methods Of Forming NAND Cell Units  
Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different...
US20100096687 NON-VOLATILE MEMORY HAVING SILICON NITRIDE CHARGE TRAP LAYER  
A flash memory device and methods of forming a flash memory device are provided. The flash memory device includes a doped silicon nitride layer having a dopant comprising carbon, boron or oxygen....
US20090201741 Non-volatile memory cell with injector  
In a nonvolatile memory (NVM) cell, an injector having one or more layers of material with a lower potential barrier for holes is disposed between a charge storage stack and a source of holes (the...
US20100067310 MOS TRANSISTOR WITH A SETTABLE THRESHOLD  
A MOS transistor comprising a conductive extension of its source region, insulated from its substrate, and partially extending under its channel.
US20060226473 Gate electrode stack and use of a gate electrode stack  
A gate electrode stack is disposed on a substrate in a semiconductor device. A gate conductor includes at least one layer of polysilicon and at least one layer of poly-Si1−x,Gex material. The...
US20090108330 SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS  
Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split...
US20100096688 NON-VOLATILE MEMORY HAVING CHARGE TRAP LAYER WITH COMPOSITIONAL GRADIENT  
A flash memory device and method of forming a flash memory device are provided. The flash memory device includes a silicon nitride layer having a compositional gradient in which the ratio of...
US20080083946 MEMORY CELL SYSTEM WITH CHARGE TRAP  
A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma...
US20070272974 TWIN-GATE NON-VOLATILE MEMORY CELL AND METHOD OF OPERATING THE SAME  
A non-volatile memory cell with twin gates formed on an N-well is provided. The non-volatile memory cell includes at least a first gate, a second gate, a pair of NO (Nitride/Oxide) spacer layers,...
US20100025752 CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME  
There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed...
US20080061359 Dual charge storage node with undercut gate oxide for deep sub-micron memory cell  
An embodiment of the present invention is directed to a memory cell. The memory cell includes a stack formed over a substrate. The stack includes a gate oxide layer and an overlying...
US20110095357 Semiconductor Constructions, Methods Of Forming Transistor Gates, And Methods Of Forming NAND Cell Units  
Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different...
US20110156128 DIELECTRIC FILM MANUFACTURING METHOD  
The present invention provides a manufacturing method of a dielectric film which reduces a leak current value while suppressing the reduction of a relative permittivity, suppresses the reduction...
US20100034023 NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR OPERATING NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT  
According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a...
US20150091076 ISOLATION FORMATION FIRST PROCESS SIMPLIFICATION  
A method for manufacturing a memory device includes providing a substrate having a plurality of active layers, forming a plurality of holes through the plurality of active layers including a first...
US20070221979 Method for production of memory devices and semiconductor memory device  
At least one memory layer is provided on a substrate surface. A plurality of parallel conductor strips is formed from electrically conductive material above the memory layer. Sidewalls of the...
US20080150002 Simultaneous Formation of a Top Oxide Layer in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Transistor and a Gate Oxide in a Metal Oxide Semiconductor (MOS)  
A method for semiconductor fabrication. The method includes providing a silicon substrate and forming a tunnel oxide layer the silicon substrate. Thereafter, a nitride layer is formed over the...
US20130248976 NON-VOLATILE MEMORY  
A non-volatile memory includes a substrate, a gate dielectric layer, a gate conductive layer, a nitride layer, a spacer, a first oxide layer, and a second oxide layer. The gate conductive layer,...
US20080142875 Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes  
Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an...
US20140209994 Embedded Cost-Efficient SONOS Non-Volatile Memory  
A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using...