Match Document Document Title
US20120074483 EEPROM CELL  
A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area....
US20150001605 Gate Constructions Of Recessed Access Devices And Methods Of Forming Gate Constructions Of Recessed Access Devices  
A method of forming a gate construction of a recessed access device includes forming a pair of sidewall spacers laterally over opposing sidewalls of a gate dielectric and elevationally over first...
US20120074480 METHOD OF FORMING LUTETIUM AND LANTHANUM DIELECTRIC STRUCTURES  
Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the...
US20140151775 CONTROL GATE  
A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and...
US20110115009 CONTROL GATE  
A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and...
US20120074482 EEPROM CELL  
A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first...
US20130119451 INTERLAYER POLYSILICON DIELECTRIC CAP AND METHOD OF FORMING THEREOF  
In some embodiments, an interlayer polysilicon dielectric cap disposed atop a substrate having a first floating gate, a second floating gate and an isolation layer disposed between the first...
US20120319185 NAND STRUCTURE AND METHOD OF MANUFACTURING THE SAME  
The present invention provides a NAND gate structure, comprising: a substrate; a gate insulation layer formed on the substrate; a source/drain region formed in the substrate; a middle gate formed...
US20090256187 SEMICONDUCTOR DEVICE HAVING VERTICAL PILLAR TRANSISTORS AND METHOD FOR MANUFACTURING THE SAME  
A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a...
US20120074481 SECURITIES, CHIP MOUNTING PRODUCT, AND MANUFACTURING METHOD THEREOF  
The invention provides an ID chip with reduced cost, increased impact resistance and attractive design, as well as products and the like mounting the ID chip and a manufacturing method thereof. In...
US20080035980 MASK FOR FORMING CONTACT HOLE  
Embodiments relate to a mask in which a mask pattern used for forming a contact hole may be designed such that any one of a horizontal-axis length and a vertical-axis length may be greater than...
US20140167128 Memory Gate Landing Pad Made From Dummy Features  
Embodiments described herein generally relate to landing gate pads for contacts and manufacturing methods therefor. A bridge is formed between two features to allow a contact to be disposed, at...
US20150054046 3D Non-Volatile Memory With Metal Silicide Interconnect  
A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array....
US20130126957 3D Non-Volatile Memory With Metal Silicide Interconnect  
A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array....
US20070205454 Dual storage node memory  
An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second...
US20060049447 Antimony precursor, phase-change memory device using the antimony precursor, and method of manufacturing the phase-change memory device  
An antimony precursor including antimony, nitrogen and silicon, a phase-change memory device using the same, and a method of making the phase-change memory device. The phase-change memory device...
US20070205455 Flash memory cells having trenched storage elements  
An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor...
US20100078701 THREE-DIMENSIONAL MICROELECTRONIC DEVICES INCLUDING REPEATING LAYER PATTERNS OF DIFFERENT THICKNESSES  
A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a...
US20110101439 INTERCONNECTION STRUCTURES FOR SEMICONDCUTOR DEVICES  
An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level...
US20080042183 Nonvolatile Memories with Shaped Floating Gates  
In a nonvolatile memory using floating gates to store charge, individual floating gates are L-shaped. Orientations of L-shaped floating gates may alternate in the bit line direction and may also...
US20150054044 Method to Form a Polysilicon Nanocrystal Thin Film Storage Bitcell within a High K Metal Gate Platform Technology Using a Gate Last Process to Form Transistor Gates  
A process integration is disclosed for fabricating non-volatile memory (NVM) cells (105-109, 113-115) on a first flash cell substrate area (111) which are encapsulated in one or more planar...
US20060091444 Double word line memory structure and manufacturing method thereof  
A memory structure comprises two bit lines, a first gate dielectric, a second gate dielectric, at least one first gate, a second gate and a third gate, a first dielectric spacer and a second...
US20100027355 PLANAR DOUBLE GATE TRANSISTOR STORAGE CELL  
A semiconductor device suitable for use as a storage cell includes a semiconductor body having a top surface and a bottom surface, a top gate dielectric overlying the semiconductor body top...
US20050087793 Embedded non-volatile memory and a method for fabricating the same  
A low density and cost effective embedded non-volatile memory cell includes a semiconductor substrate of a first conductivity type and having device isolation regions and active regions defined...
US20150194439 Embedded NVM in a HKMG Process  
A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells (110) prior to the formation of high-k metal gate electrodes for CMOS transistors (212, 213)...
US20140225176 Embedded NVM in a HKMG Process  
A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells (110) prior to the formation of high-k metal gate electrodes for CMOS transistors (212, 213)...
US20090014769 SUSPENDED-GATE MOS TRANSISTOR WITH NON-VOLATILE OPERATION  
A transistor device with a mobile suspended gate, the device comprising means for piezoelectric actuation of the gate, and a method for producing such a device.
US20150084108 TRANSISTOR STRUCTURE AND METHOD WITH AN EPITAXIAL LAYER OVER MULTIPLE HALO IMPLANTS  
A transistor structure having an epitaxial layer deposited over an implanted substrate in order to reduce process variability. The epitaxial layer is able to be deposited doped, un-doped or...
US20080149984 Floating body memory cell having gates favoring different conductivity type regions  
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back...
US20060027853 Semiconductor storage device and method of manufacturing same  
Disclosed is a semiconductor storage device having a trench around a bit-line diffusion region in an area of a p-well, which constitutes a memory cell area, that is not covered by a word line and...
US20120280298 NONVOLATILE MEMORY DEVICE  
A nonvolatile memory device includes a first channel comprising a pair of first pillars vertically extending from a substrate and a first coupling portion positioned under the pair of first...
US20150041875 Nonvolatile Memory Bitcell With Inlaid High K Metal Select Gate  
A process integration is disclosed for fabricating non-volatile memory (NVM) cells having recessed control gates (118, 128) on a first substrate area (111) which are encapsulated in one or more...
US20070164341 Nonvolatile Semiconductor Memory Device Comprising Shield Electrode On Source and Method For Manufacturing the Same  
A nonvolatile semiconductor memory device includes floating gates, source areas, drain areas, word lines, diffusion layers, source lines and shield wires. The source area is shared by the floating...
US20080280409 Memory Arrays, Semiconductor Constructions And Electronic Systems; And Methods Of Forming Memory Arrays, Semiconductor Constructions And Electronic Systems  
Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some...
US20090184346 Nonvolatile memory and three-state FETs using cladded quantum dot gate structure  
The present invention discloses structures and method of fabricating cladded quantum dot gate nonvolatile memory and three-state field-effect transistor devices that can be scaled down to sub-22...
US20090065840 FLASH MEMORY AND MANUFACTURING METHOD OF THE SAME  
A flash memory and a manufacturing method of the same includes a shallow trench isolation and an active region formed at a substrate, a plurality of stacked gates formed on and/or over the active...
US20050023594 Pr2O3-based la-oxide gate dielectrics  
A dielectric film having a layer of Pr2O3 and a layer of another lanthanide oxide, and a method of fabricating such a dielectric film produce a reliable gate dielectric with a equivalent oxide...
US20070158732 Flash memory device having vertical split gate structure and method for manufacturing the same  
Disclosed are a flash memory device having a vertical split gate structure and a method for manufacturing the same. The flash memory device includes a first trench formed in an active region of a...
US20100065899 SEMICONDUCTOR DEVICES INCLUDING AUXILIARY GATE ELECTRODES AND METHODS OF FABRICATING THE SAME  
A semiconductor device may include first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode may be...
US20070235795 Ferroelectric storage device and manufacturing method thereof  
According to an aspect of the embodiment, there is provided a ferroelectric storage device including: a plurality of memory cells repeatedly arranged in a predetermined direction, each memory cell...
US20070221979 Method for production of memory devices and semiconductor memory device  
At least one memory layer is provided on a substrate surface. A plurality of parallel conductor strips is formed from electrically conductive material above the memory layer. Sidewalls of the...
US20070155098 Method of manufacturing NAND flash memory device  
A method of manufacturing a NAND flash memory device is disclosed. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed...
US20060076605 IMPROVED FLASH FORWARD TUNNELING VOLTAGE (FTV) FLASH MEMORY DEVICE  
A FLASH memory device comprising a substrate having a gate conductor formed thereover is provided. The gate conductor comprises a gate with a floating gate oxide layer formed thereon, the floating...
US20140209989 ANTI-FUSE MEMORY CELL  
An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide is formed by depositing a first oxide over a channel region of the anti-fuse memory cell,...
US20140339620 Integrated Circuitry and Methods of Forming Transistors  
Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second...
US20080017912 Non-volatile memory cell with embedded antifuse  
A nonvolatile memory device includes at least one memory cell which comprises a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode...
US20150200195 SPLIT PAGE 3D MEMORY ARRAY  
A semiconductor device includes active strips. Active strip stack selection structures electrically couple to the active strip stacks at positions between the first and second ends, and select...
US20080308855 Memory devices with isolation structures and methods of forming and programming the same  
Memory devices and methods of programming and forming the same are disclosed. In one embodiment, a memory device has memory cells contained within dielectric isolation structures to isolate them...
US20130009230 OPTIMIZATION OF CRITICAL DIMENSIONS AND PITCH OF PATTERNED FEATURES IN AND ABOVE A SUBSTRATE  
A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention...
US20060054963 Non-volatile and non-uniform trapped-charge memory cell structure and method of fabrication  
A memory cell having a charge-trapping structure in the form of a layer of conductive clusters disposed between upper and lower insulator layers is disclosed. The memory cell can otherwise be...