Match Document Document Title
US20120112259 INTEGRATED CIRCUIT WITH PROTECTION FROM COPPER EXTRUSION  
An integrated circuit may include an element placed in an insulating region adjacent to a copper metallization level and including a barrier layer in contact with a metallization level. The...
US20150021676 HIGH VOLTAGE METAL-OXIDE-METAL (HV-MOM) DEVICE, HV-MOM LAYOUT AND METHOD OF MAKING THE HV-MOM DEVICE  
A high voltage metal-oxide-metal (HV-MOM) device includes a substrate, a deep well in the substrate and at least one high voltage well in the substrate over the deep well. The HV-MOM device...
US20140015005 SINGLE CHIP IGNITER AND INTERNAL COMBUSTION ENGINE IGNITION DEVICE  
Aspects of the invention are directed to a single chip igniter such that it is possible to realize a reduction in operating voltage, an increase in noise tolerance, a reduction in size, and a...
US20130277723 DRAM Cells and Methods of Forming Silicon Dioxide  
Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000° C., and in...
US20120092068 Fringe Capacitor Using Bootstrapped Non-Metal Layer  
A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the...
US20080128771 NANO-FUSE STRUCTURAL ARRANGEMENTS HAVING BLOW PROTECTION BARRIER SPACED FROM AND SURROUNDING FUSE LINK  
A nano-fuse structural arrangement, includes, for example, a semiconductor substrate having an electrically conductive region formed thereon; an electrically conductive elongated nano-structure...
US20120161216 ESD Protection Circuit  
One embodiment of the disclosure provides an electrostatic discharge protection circuit, including a first resistor, a p-type field effect transistor, a capacitance device and an n-type field...
US20150137202 CELL-BASED IC LAYOUT SYSTEM AND CELL-BASED IC LAYOUT METHOD  
A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal layers. The decoupling capacitor cell is...
US20120286341 Adding Decoupling Function for TAP Cells  
A tap cell includes a well region and a well pickup region on the well region; a VDD power rail; and a VSS power rail. A MOS capacitor includes a gate electrode line acting as a first capacitor...
US20120326218 6F2 DRAM Cell  
A 6F2 DRAM cell with paired cells is described. In one embodiment the cell pairs are separated by n-type isolation transistors having gates defining dummy word lines. The dummy word lines are...
US20130200447 Adjustable Meander Line Resistor  
An adjustable meander line resistor comprises a plurality of series circuits. Each series circuit comprises a first resistor formed on a first doped region of a transistor, a second resistor...
US20110198677 SYSTEMS AND METHODS FOR A CONTINUOUS-WELL DECOUPLING CAPACITOR  
A decoupling capacitor includes a pair of MOS capacitors formed in wells of opposite plurality. Each MOS capacitor has a set of well-ties and a high-dose implant, allowing high frequency...
US20150097221 POWER FET WITH A RESONANT TRANSISTOR GATE  
A semiconductor FET provides a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies.
US20130200448 Meander Line Resistor Structure  
A meander line resistor structure comprises a first resistor formed on a first active region, wherein the first resistor is formed by a plurality of first vias connected in series, a second...
US20110006353 DRAM DEVICES  
A DRAM device includes a plug on a substrate, a conductive plate electrically connected to the plug and overlapping the substrate, at least one capacitor on the substrate and spaced apart from the...
US20130221420 STRUCTURE COMPRISING A RUTHENIUM METAL MATERIAL  
A method for forming a ruthenium metal layer comprises combining a ruthenium precursor with a measured amount of oxygen to form a ruthenium oxide layer. The ruthenium oxide is annealed in the...
US20130062675 PILLARS FOR VERTICAL TRANSISTORS  
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide...
US20130248957 DECOUPLING CAPACITOR CELL, CELL-BASED IC, CELL-BASED IC LAYOUT SYSTEM AND METHOD, AND PORTABLE DEVICE  
A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal layers. The decoupling capacitor cell is...
US20140066834 MEDICAL INSTRUMENT  
A medical instrument includes a multilayer wiring board having first, second and third wirings, a fourth wiring formed in a first wiring layer, and a fifth wiring formed in a second wiring layer....
US20060270145 CAPACITIVE ARRAY  
A capacitive array comprising at least two capacitive entities, comprising a substrate layer. The substrate layer comprises a comb comprising at least four substantially identical teeth, and, for...
US20120161215 RECTANGULAR CAPACITORS FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) AND DUAL-PASS LITHOGRAPHY METHODS TO FORM THE SAME  
A rectangular capacitor for dynamic random access memory (DRAM) and a dual-pass lithography method to form the same are described. For example, a capacitor includes a trench disposed in a first...
US20100301331 BODY CONTACT STRUCTURE FOR IN-LINE VOLTAGE CONTRAST DETECTION OF PFET SILICIDE ENCROACHMENT  
Test structures for in-line voltage contrast detection of PFET silicide encroachment defects are disclosed. Embodiments of the present invention provide for improved PFET test structures for...
US20120098045 Zero Temperature Coefficient Capacitor  
A zero temperature coefficient (ZTC) capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. An integrated circuit...
US20130140616 Integrated Circuit Including a Power Transistor and an Auxiliary Transistor  
In one embodiment of an integrated circuit, the integrated circuit includes a power transistor with a power control terminal, a first power load terminal and a second power load terminal. The...
US20110018044 ETCH STOP LAYERS AND METHODS OF FORMING THE SAME  
A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress...
US20110298026 LOGIC-BASED eDRAM USING LOCAL INTERCONNECTS TO REDUCE IMPACT OF EXTENSION CONTACT PARASITICS  
An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization...
US20090166699 Semiconductor Constructions  
In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anistropically etched spacers. The spacers are...
US20150130556 Transistor and Tunable Inductance  
According to a first aspect embodiments provide a transistor including at least one gate region between at least one drain region and at least one source region, wherein a ratio between a width of...
US20120242395 LOW LOSS SWITCHED CAPACITOR  
An integrated circuit including a capacitor bank is disclosed. The capacitor bank includes one or more cells. Each cell may include two capacitors in series and a transistor in parallel with one...
US20100090263 MEMORY DEVICES INCLUDING SEMICONDUCTOR PILLARS  
One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column...
US20080173914 SEMICONDUCTOR DEVICE AND STORAGE MEDIUM  
A power source noise of a semiconductor device having a core cell configuring a logic circuit is reduced. Above the core cell configuring the logic circuit provided on a main surface of a...
US20120091516 Lateral Floating Coupled Capacitor Device Termination Structures  
Voltage termination structures include one or more capacitively coupled trenches, which can be similar to the trenches in the drift regions of the active transistor. The capacitively coupled...
US20130126955 Methods and Apparatus for Hybrid MOS Capacitors in Replacement Gate Process  
Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon...
US20130001663 DRAM Layout with Vertical FETS and Method of Formation  
DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide...
US20110254067 DRAM Layout with Vertical FETS and Method of Formation  
DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide...
US20120241829 Low Leakage Capacitor for Analog Floating-Gate Integrated Circuits  
An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is...
US20080087929 Static random access memory with thin oxide capacitor  
An SRAM includes an SRAM cell with a semiconductor substrate material, and a capacitor. The capacitor includes a first electrode adjacent the substrate material, a thin oxide adjacent the first...
US20120061740 SUBRESOLUTION SILICON FEATURES AND METHODS FOR FORMING THE SAME  
Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an...
US20120292678 BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR  
A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of...
US20110108900 BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR  
A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of...
US20130307042 Floating Body Cell Structures, Devices Including Same, and Methods for Forming Same  
Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The...
US20150069482 DRAM Arrays, Semiconductor Constructions and DRAM Array Layouts  
Some embodiments include a DRAM array layout. Wordlines extend along a first direction, and bitlines extend along a second direction that crosses the first direction. Cell active material...
US20130146953 Method and Structure For Forming ETSOI Capacitors, Diodes, Resistors and Back Gate Contacts  
An ETSOI transistor and a combination of capacitors, junction diodes, bank end contacts and resistors are respectively formed in a transistor and capacitor region thereof by etching through an...
US20100117130 HIGH PERFORMANCE CAPACITORS IN PLANAR BACK GATES CMOS  
A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically...
US20120132969 COMPENSATION NETWORK FOR RF TRANSISTOR  
A compensation network for a radiofrequency transistor is disclosed. The compensation network comprises first and second bonding bars for coupling to a first terminal of the RF transistor and a...
US20130193498 Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor  
A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of...
US20080142861 SYMMETRIC CAPACITOR STRUCTURE  
A structure comprising a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises...
US20120043595 CAPACITOR DEVICE AND METHOD OF FABRICATING THE SAME  
A capacitor device includes a substrate including a first well having a first conductivity type and a first voltage applied thereto and a second well having a second conductivity type and a second...
US20080169118 Wire structure and semiconductor device comprising the the wire structure  
Provided are a wire structure and a semiconductor device having the wire structure. The wire structure includes a first wire that has a first region having a width of several to tens of nanometers...
US20140015027 SEMICONDUCTOR DEVICE HAVING GATE ELECTRODE EMBEDDED IN GATE TRENCH  
Disclosed herein is a device that includes: a substrate having a gate trench; a gate electrode embedded in the gate trench with an intervention of a gate insulation film; and an embedded...