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US20090001416 Growth of indium gallium nitride (InGaN) on porous gallium nitride (GaN) template by metal-organic chemical vapor deposition (MOCVD)  
Si-doped porous GaN is fabricated by UV-enhanced Pt-assisted electrochemical etching and together with a low-temperature grown buffer layer are utilized as the template for InGaN growth. The...
US20140264440 V-SHAPED SIGE RECESS VOLUME TRIM FOR IMPROVED DEVICE PERFORMANCE AND LAYOUT DEPENDENCE  
Some embodiments of the present disclosure relates to a method and a device to achieve a strained channel. A volume of a source or drain recess is controlled by a performing an etch of a substrate...
US20150129911 STRAIN TUNABLE LIGHT EMITTING DIODES WITH GERMANIUM P-I-N HETEROJUNCTIONS  
Tunable p-i-n diodes comprising Ge heterojunction structures are provided. Also provided are methods for making and using the tunable p-i-n diodes. Tunability is provided by adjusting the tensile...
US20080128746 Dual-SiGe epitaxy for MOS devices  
A semiconductor includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor having at least a portion in the semiconductor substrate and adjacent to the gate...
US20090146181 INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONS  
An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from...
US20090108295 DOPANT PROFILE TUNING FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION  
By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly...
US20140070274 POST-GATE SHALLOW TRENCH ISOLATION STRUCTURE FORMATION  
Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The...
US20130099281 POST-GATE SHALLOW TRENCH ISOLATION STRUCTURE FORMATION  
Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The...
US20150076560 INTEGRATED CIRCUITS INCLUDING EPITAXIALLY GROWN STRAIN-INDUCING FILLS DOPED WITH BORON FOR IMPROVED ROBUSTNESS FROM DELIMINATION AND METHODS FOR FABRICATING THE SAME  
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a cavity in a semiconductor region...
US20150014745 Strained InGaAs Quantum Wells for Complementary Transistors  
An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant...
US20120168770 HEAT DISSIPATION STRUCTURE OF CHIP  
A heat dissipation structure of a chip in the field of microelectronics is provided. The heat dissipation structure includes a P-type superlattice layer and an N-type superlattice layer formed...
US20110186910 METHODS OF PREPARING FLEXIBLE PHOTOVOLTAIC DEVICES USING EPITAXIAL LIFTOFF, AND PRESERVING THE INTEGRITY OF GROWTH SUBSTRATES USED IN EPITAXIAL GROWTH  
There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing...
US20080135873 Inducement of Strain in a Semiconductor Layer  
Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces.
US20120280276 Single Crystal Ge On Si  
A single crystal germanium-on-silicon structure includes a single crystal silicon substrate. A single crystal layer of gadolinium oxide is epitaxially grown on the substrate. The gadolinium oxide...
US20150145000 INTEGRATED CIRCUITS WITH SHALLOW TRENCH ISOLATIONS, AND METHODS FOR PRODUCING THE SAME  
Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate,...
US20140054647 HIGH ELECTRON MOBILITY BIPOLAR TRANSISTOR  
A high electron mobility bipolar transistor including a substrate, a pseudomorphic high electron mobility transistor (pHEMT) sub structure, a sub collector/separating layer and a heterojunction...
US20050110040 TEXTURE FOR LOCALIZING AND MINIMIZING EFFECTS OF LATTICE CONSTANTS MISMATCH  
Lattice mismatch is a critical issue for semiconductor devices including nitride LED. Texturing a substrate, texturing an epitaxial layer, and a method are disclosed in the present invention for...
US20050012113 [UV PHOTODETECTOR]  
An UV photo-detector having a GaN-based interlayer is provided. Because of the excellent insulating property of the GaN-based interlayer and an excellent Schottky contact between the GaN-based...
US20120256191 EPITAXIAL GROWTH METHOD AND DEVICES  
Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial...
US20080237634 CRYSTALLOGRAPHIC RECESS ETCH FOR EMBEDDED SEMICONDUCTOR REGION  
Source and drain regions of an FET are etched by a crystallographic anisotropic etch to form a cavity surrounded by crystallographic facets. The exposure of the sidewalls of shallow trench...
US20080029783 Method of fabricating single crystal gallium nitride semiconductor substrate, nitride gallium semiconductor substrate and nitride semiconductor epitaxial substrate  
A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more single crystal...
US20130032858 RARE EARTH OXY-NITRIDE BUFFERED III-N ON SILICON  
Rare earth oxy-nitride buffered III-N on silicon includes a silicon substrate with a rare earth oxide (REO) structure, including several REO layers, is deposited on the silicon substrate. A layer...
US20090072271 EPITAXIAL GROWTH OF THIN SMOOTH GERMANIUM (Ge) ON SILICON (Si) UTILIZING AN INTERFACIAL SILICON GERMANIUM (SiGe) PULSE GROWTH METHOD  
Disclosed is a method of growing thin and smooth germanium (Ge) on a strained or relaxed silicon (Si) layer comprising the steps of: (a) treating surface of the strained or relaxed Si layer to...
US20140167057 REO/ALO/AlN TEMPLATE FOR III-N MATERIAL GROWTH ON SILICON  
A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes epitaxially depositing a layer of rare earth oxide on the...
US20140246679 III-N MATERIAL GROWN ON ErAlN BUFFER ON Si SUBSTRATE  
III-N material grown on a buffer on a silicon substrate includes a single crystal electrically insulating buffer positioned on a silicon substrate. The single crystal buffer includes rare earth...
US20080099785 Defect Reduction Using Aspect Ratio Trapping  
Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.
US20090184341 Elimination of STI recess and facet growth in embedded silicon-germanium (eSiGe) module  
A method (and semiconductor device) of fabricating a semiconductor device eliminates shallow trench isolation (STI) recess in embedded SiGe p-type field effect transistor (pFET) structures. This...
US20120098033 HETEROSTRUCTURES COMPRISING CRYSTALLINE STRAIN RELAXATION LAYERS  
The invention relates to a process for fabricating a heterostructure. This process is noteworthy in that it comprises the following steps: a) a strained crystalline thin film is deposited on, or...
US20090236632 FET HAVING HIGH-K, VT MODIFYING CHANNEL AND GATE EXTENSION DEVOID OF HIGH-K AND/OR VT MODIFYING MATERIAL, AND DESIGN STRUCTURE  
A field effect transistor (FET) including a high dielectric constant (high-k), threshold voltage (Vt) modifying channel and a gate extension devoid of the high-k and/or Vt modifying material, and...
US20080246056 SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFET  
Methods of forming a suicide in an embedded silicon germanium (eSiGe) source/drain region using a suicide prevention spacer overlapping an interface between the eSiGe and the silicon channel, and...
US20120280277 SHORT CHANNEL TRANSISTOR WITH REDUCED LENGTH VARIATION BY USING AMORPHOUS ELECTRODE MATERIAL DURING IMPLANTATION  
In sophisticated transistor elements, enhanced profile uniformity along the transistor width direction may be accomplished by using a gate material in an amorphous state, thereby reducing...
US20090152589 Systems And Methods To Increase Uniaxial Compressive Stress In Tri-Gate Transistors  
A transistor structure that increases uniaxial compressive stress on the channel region of a tri-gate transistor comprises at least two semiconductor bodies formed on a substrate, each...
US20090114949 HIGH-MOBILITY TRENCH MOSFETS  
High-mobility vertical trench DMOSFETs and methods for manufacturing are disclosed. A source region, a drain region or a channel region of a high-mobility vertical trench DMOSFET may comprise...
US20080001169 Lattice-mismatched semiconductor structures and related methods for device fabrication  
Lattice-mismatched materials having configurations that trap defects within sidewall-containing structures.
US20120286329 SOI FET with embedded stressor block  
A method and a structure are disclosed relating to strained body UTSOI FET devices. The method includes forming voids in the source/drain regions that penetrate down into the substrate below the...
US20140191284 GROUP III NITRIDES ON NANOPATTERNED SUBSTRATES  
A patterned substrate is provided having at least two mesa surface portions, and a recessed surface located beneath and positioned between the at least two mesa surface portions. A Group III...
US20140191283 GROUP III NITRIDES ON NANOPATTERNED SUBSTRATES  
A patterned substrate is provided having at least two mesa surface portions, and a recessed surface located beneath and positioned between the at least two mesa surface portions. A Group III...
US20090039361 LATTICE-MISMATCHED SEMICONDUCTOR STRUCTURES WITH REDUCED DISLOCATION DEFECT DENSITIES AND RELATED METHODS FOR DEVICE FABRICATION  
A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline...
US20080093626 NITRIDE SEMICONDUCTOR DEVICE  
A nitride semiconductor device includes: a first nitride semiconductor layer formed of non-doped AlxGa1-XN (0≦X<1); a second nitride semiconductor layer formed on the first nitride semiconductor...
US20080315253 FRONT AND BACKSIDE PROCESSED THIN FILM ELECTRONIC DEVICES  
This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be...
US20130270572 GROUP III-N HFET WITH A GRADED BARRIER LAYER  
A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of...
US20100025728 RELAXATION AND TRANSFER OF STRAINED LAYERS  
The invention relates to a process for fabricating a heterostructure. This process is noteworthy in that it comprises the following steps: a) a strained crystalline thin film is deposited on, or...
US20140159113 IMPLANT DAMAGE CONTROL BY IN-SITU C DOPING DURING SIGE EPITAXY FOR DEVICE APPLICATIONS  
Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode,...
US20100012976 POLISHING OF SMALL COMPOSITE SEMICONDUCTOR MATERIALS  
A device includes a crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with...
US20100046567 PROPAGATION OF MISFIT DISLOCATIONS FROM BUFFER/SI INTERFACE INTO SI  
Misfit dislocations are redirected from the buffer/Si interface and propagated to the Si substrate due to the formation of bubbles in the substrate. The buffer layer growth process is generally a...
US20120199876 Defect Reduction Using Aspect Ratio Trapping  
Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.
US20140084341 STRUCTURES AND DEVICES INCLUDING A TENSILE-STRESSED SILICON ARSENIC LAYER AND METHODS OF FORMING SAME  
Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are disclosed. Exemplary tensile-stressed silicon...
US20120146092 STRUCTURE AND METHOD FOR MOBILITY ENHANCED MOSFETS WITH UNALLOYED SILICIDE  
While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed...
US20080265280 HYBRID FIN FIELD-EFFECT TRANSISTOR STRUCTURES AND RELATED METHODS  
Abstract Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins...
US20110101418 Method for improving transistor performance through reducing the salicide interface resistance  
An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned...