Title:
Display apparatus
United States Patent 3906290


Abstract:
A display apparatus capable of displaying a picture with half-brightness (gray scale) by use of a display panel such as a plasma display panel, comprising a plurality of picture elements or luminescent dots which assume either a luminescent condition or a nonluminescent condition. A halftone picture display can be achieved according to two methods, the first being that the mean brightness of the picture element or luminescent dot be made porportional to the turn-on period. The second method is that the mean brightness of the picture element or luminescent dot for the turn-on period be made proportional to the frequency of the sustaining voltage. Several embodiments are disclosed which incorporate one or both of the foregoing principles to achieve a halftone display.



Inventors:
Kurahashi, Koichiro (Amagasaki, JA)
Tottori, Hiroshi (Amagasaki, JA)
Application Number:
05/398791
Publication Date:
09/16/1975
Filing Date:
09/19/1973
Assignee:
MITSUBISHI DENKI KABUSHIKI KAISHA
Primary Class:
Other Classes:
345/63, 348/800
International Classes:
G09G3/20; G09G3/294; G09G3/296; G09G3/297; (IPC1-7): H05B37/00
Field of Search:
315/169R,169TV 340
View Patent Images:



Primary Examiner:
Lynch, Michael J.
Assistant Examiner:
Davis B. P.
Attorney, Agent or Firm:
Oblon, Fisher, Spivak, McClelland & Maier
Claims:
What is claimed as new and desired to be secured by letters Patent of the United States is

1. A display apparatus comprising a display panel having a plurality of luminescent dots each assuming either a luminescent state or a nonluminescent state, at least one of said luminescent dots constituting each of a plurality of picture elements disposed on said display panel; and a control device for controlling the luminous state of each of said picture elements according to the video signal to be displayed on said display panel; wherein said control device is operated so that each of said picture elements is turned on with a mean brightness proportional to the instantaneous value of said video signal; the control device being operated so that the instantaneous value V of said video signal corresponding to each of said picture elements is coded by the use of n weights w1, w2, w3 ..., wn, according to the formula

2. The display apparatus in accordance with claim 1, further comprising a coder operated so that said instantaneous value V of said video signal corresponding to each of said picture elements is coded by the use of n weights w1, w2, w3, ..., wn, according to said formula.

3. The display apparatus in accordance with claim 1, wherein each of said picture elements comprises a plurality of luminescent dots adjacent to each other.

4. The display apparatus in accordance with claim 1, wherein said control device controls the turn-on period of each of said luminescent dots so that each of said picture elements is turned on with a mean brightness proportional to the weight wk corresponding to the condition ak = 1 (k = 1, 2, 3, ..., n).

5. A display apparatus comprising: a display panel having picture elements each having a turn-on state and a turn-off state; a coder for coding the instantaneous value V of the video signal corresponding to each of said picture elements for display on said display panel by use of n weights w1, w2, w3, ..., wn, according to the formula

6. The display apparatus in accordance with claim 5, further comprising a display panel with picture elements two-dimensionally disposed in both the horizontal and vertical directions, each of said picture elements assuming a bistable state as it is turned on by a turn-on pulse and turned off by a turn-off pulse; a turn-on scanning circuit having shift registers for vertical scanning and for controlling the generation of said turn-on pulse; a turn-off scanning circuit with shift registers to which the first stage thereof the output of a specific state of said turn-on scanning circuit is supplied and thus controls the generation of said turn-off pulse; and a gate circuit for switching, frame by frame, the output stage of said turn-on scanning circuit for the input to the first stage of said turn-off scanning circuit.

7. A display apparatus comprising: a display panel having picture elements each capable of assuming two states, a turn-on state and a turn-off state; a coder for coding the instantaneous value V of the video signal corresponding to each of said picture elements for display on said display panel by the use of weights w1, w2, w3, ..., wn, according to the formula

8. A display apparatus comprising: a display panel having picture elements each assuming two states, a turn-on state and a turn-off state; a coder for coding the instantaneous value V of the video signal corresponding to each of said picture elements for display on said display panel, by the use of weights w1, w2, w3, ..., wn according to the formula

9. A display apparatus comprising: a display panel having picture elements each assuming two states, a turn-on state and a turn-off state; a coder for coding the instantaneous value V of the video signal corresponding to each of said picture elements for display on said display panel, by the use of weights w1, w2, w3, ..., wn, according to the formula

10. The display apparatus in accordance with claim 8, wherein said picture elements are turned on and off in the ascending order or in the descending order of said weights wk.

11. The display apparatus in accordance with claim 8, further comprising: a plurality of X electrode lines and a plurality of Y electrode lines two-dimensionally disposed on said display panel and having said picture elements located at the intersections of said X and Y electrode lines; first, second, third, ..., n-th and (n + 1)-th scanning circuits each having shift registers for scanning said Y electrode lines; and a control device operated so that the output of a specific stage of the N-th scanning circuit (N = 1, 2, 3,000, n) or of the first scanning circuit is supplied to the first stage of the (N + 1)-th scanning circuit, and so that the application of a turn-on pulse to said Y electrode lines is controlled by the output of said N-th scanning circuit, and the supply of a turn-off pulse to said Y electrode lines is controlled by the output of said (N + 1)-th scanning circuit.

12. The display apparatus in accordance with claim 8, further comprising at least (n - 1) delay circuits, each having a time delay equal to ##EQU5## Ti (l = 2, 3, 4, ..., n) and which delay said video signal or the output of said coder which codes said video signal.

13. The display apparatus in accordance with claim 8, further comprising an analog image memory provided with at least one write head for writing therein the video signal or a signal corresponding to the video signal, and at least (n - 1) first, second, third, ..., (n - 1)-th read heads for reading the written signal therefrom; wherein the time delay interval between the signal read by the (N - 1)-th read head (N = 1, 2, 3, ..., (n-1)) and that read by the N-th read head is equal to the time Tk proportional to said weight wk.

14. The display apparatus in accordance with claim 8 further comprising an analog image memory provided with at least one write head for writing therein the video signal or a signal corresponding to the video signal, and at least n first, second, third.,... n-th read heads with a total delay time equal to said frame period; wherein the delay time interval between the signal read by the N-th read head (N = 1,2,3,...,n) and that read by the (n + 1)-th read head is equal to the time Tk proportional to said weight wk.

15. The display apparatus in accordance with claim 8, further comprising: at least n first, second, third,..., n-th coders each capable of making a coded output and a residual analog output available when the analog input is above a given level, or making the analog input or an output corresponding to the analog input available when the analog input is below the given level; and an analog image memory provided with at least (n - 1) pairs or write and read heads for writing the residual output signal of the N-th coder (N = 1, 2, 3, ..., (n - 1)) or a signal corresponding to the residual output signal and for reading the written signal with a delay Tk proportional to said weight wk wherein the output of the (n - 1)-th read head is supplied to the n-th coder.

16. A display apparatus comprising: a display panel with a plurality of luminescent dots each assuming two states, a luminescent state effected by a turn-on pulse and a non-luminescent state effected by a turn-off pulse, and each picture element comprising n of said luminescent dots α1, α2, α3, ...,αn ; a coder for coding the instantaneous value V of the video signal corresponding to each of said picture elements for display panel, by the use of weights w1, w2, w3, ..., wn, according to the formula

17. A display apparatus in accordance with claim 16, further comprising: a plurality of X electrode lines and a plurality of Y electrode lines two-dimensionally disposed on said display panel having said picture elements located at the intersections of said X and Y electrode lines; first, second, third, ..., n-th and (n + 1)-th scanning circuits each having shift registers for scanning said Y electrode lines; and a control device operated so that the output of a specific state of the N-th scanning circuit (N = 1, 2, 3, ..., n) or the first scanning circuit is supplied to the first stage of the (N + 1)-th scanning circuit, and so that the application of a turn-on pulse to said Y electrode lines is controlled by the output of said first scanning circuit, and the application of a turn-off pulse to said Y electrode lines is controlled by the output of said N-th scanning circuit.

18. A display apparatus comprising a plurality of picture elements each capable of being luminous with a luminescent output substantially proportional to the frequency of a sustaining AC voltage during the turn-on period, said picture elements caused to undergo repeating frame scanning wherein n consecutive frames constitute one period, and wherein the video signal V is coded by the use of n weights w1, w2, w3, ..., wn, according to the formula

19. The display apparatus in accordance with claim 18, wherein said plurality of picture elements comprise a plurality of X electrode lines and a plurality of Y electrode lines, and further comprising a sustaining voltage whose frequency is constantly f1 which is applied to said X electrode lines by the half cycle at a specific polarity; a sustaining AC voltage whose frequency is f1, f2, ..., fn from one frame to another which is progressively applied to said Y electrode lines by the half cycle at the reverse polarity; whereby the effective frequency of the sustaining AC voltage applied to the picture element which is given a turn-on period in each frame is controlled to be f1, f2, f3, ..., fn in sequence.

20. The display apparatus in accordance with claim 19, further comprising: a timing circuit which generates a timing signal for providing said reverse half cycle sustaining AC voltage at frequencies f1, f2, ..., fn ; a gate circuit for gating said timing signal and generating a timing signal a fk and fk-1 in the k-th frame; a Y electrode line scanning circuit having shift registers; and a drive circuit for selecting the output fk or fk-1 of said gate circuit and for applying a sustaining voltage to said Y electrode lines; wherein the sustaining voltage whose frequency is fk is applied to the electrode lines scanned before the present scanning line, and the sustaining voltage whose frequency is fk-1 is applied to the electrode lines which are to be scanned.

21. A display apparatus comprising a plurality of picture elements each capable of being luminous with a luminescent output substantially proportional to the frequency of a sustaining AC voltage during the turn-on period, said picture elements being caused to undergo repeating frame scanning wherein n consecutive frames constitute one period, and wherein the video signal V is coded by the use of (m + n) weights u1, u2, ... um, and w1, w2, ..., wn, according to the formula V = K (a11 u1 + a12 u2 ... + a1 mum)w1 + ( a21 u1 + a22 u2 + ... + a2 mum)w2 + ... + ... + ( an1 u1 + an2 u2 + ... + anmum)wn

22. The display apparatus in accordance with claim 21 wherein said plurality of picture elements comprise a plurality of X electrode lines and a plurality of Y electrode lines, and further comprising a sustaining AC voltage whose frequency is constantly f1 which is applied to said X electrode lines by the half cycle at a specific polarity, a sustaining AC voltage whose frequency is f1, f2, ..., fn from one frame to another which is progressively applied to said Y electrode lines by the half cycle at the reverse polarity for the picture element given a turn-on period on the j-th frame (j = 1, 2, ..., n), whereby the effective frequency of the sustaining AC voltage applied to the picture element which is given a turn-on period in each frame is made to be f1, f2, ..., fn in succession.

23. The display apparatus in accordance with claim 22 further comprising: a timing circuit which generates a timing signal for providing said reverse half-cycle sustaining AC voltage at frequencies f1, f2, ..., fn ; a gate circuit for gating said timing signal and generating a timing signal at fk and fk-1 in the k-th frame; a Y electrode line scanning circuit having a shift registers; and a drive circuit for selecting the output fk or fk-1 of said gate circuit and for applying a sustaining voltage to said Y electrode lines; wherein the sustaining voltage whose frequency is fk is applied to the electrode lines scanned before the present scanning line, and the sustaining voltage whose frequency is fk-1 is applied to the electrode lines which are to be scanned.

24. A display apparatus comprising a plurality of luminescent dots each capable of being luminous with a luminescent output substantially proportional to the frequency of a sustaining AC voltage during the turn-on period, a plurality of picture elements each comprising a group of m luminescent dots 1, 2, ..., m, wherein consecutive frames constitute one period, and wherein the video signal V is coded by the use of (m + n) weights u1, u2, ..., um and w1, w2, ..., wn, according to the formula

25. A display apparatus in accordance with claim 24, wherein said plurality of luminescent dots comprise a plurality of X electrode lines and a plurality of Y electrode lines, and further comprising a sustaining AC voltage whose frequency is constantly f1 which is applied to said X electrode lines by the half cycle at a specific polarity; a sustaining AC voltage whose frequency is f1, f2, ..., fn from one frame to another which is progressively applied to said Y electrode lines by the half cycle at the reverse polarity for the luminescent dot given a turn-on period in the j-th frame (j = 1, 2, ..., n), whereby the effective frequency of the sustaining AC voltage applied to the luminescent dot which is given a turn-on period in each frame is made to be f1, f2, ..., fn in succession.

26. A display apparatus in accordance with claim 25 further comprising: a timing circuit which generates a timing signal for providing said reverse half-cycle sustaining AC voltage at frequencies f1, f2, ..., fn ; a gate circuit for gating said timing signal and generating a timing signal a fk and fk-1 in the k-th frame; a Y electrode line scanning circuit having shift registers; and a drive circuit for selecting the output fk or fk-1 of said gate circuit and for applying a sustaining voltage to said Y electrode lines; wherein the sustaining voltage whose frequency is fk is applied to the electrode lines scanned before the present scanning line, and the sustaining voltage whose frequency is fk-1 is applied to the electrode lines which are to be scanned.

Description:
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to display apparatus of the type capable of displaying a picture by the use of a display panel having a plurality of picture elements. The invention relates more specifically to a display apparatus capable of displaying a picture in a halftone by the use of a display panel having a plurality of picture elements whose luminous intensity can hardly be controlled during luminescence.

2. Description of the Prior Art

A cathode-ray tube is generally used in a television receiver. Such a cathode-ray tube normally comprises a plurality of picture elements, i.e., fluorescent dots, arranged in a mosaic form on the inner wall (screen) of the front glass. These dots are scanned in succession by an electron beam deflected in the horizontal and vertical directions. As a result, the fluorescent dots are bombarded with electrons whereby a picture is reproduced on the screen. The energy of the electron beam is modulated according to the brightness of the picture to be displayed. A bombarded dot emits light with a luminous intensity proportional to the energy of the electron beam. In this type of display apparatus, therefore, the luminous intensity of each picture element can be changed by changing the energy of the electron beam. This enables the apparatus to display a picture with half-brightness (gray scale) or in a halftone between the minimum and maximum brightness.

This type of display apparatus usually requires the use of a large vacuum tube, i.e., a cathode-ray tube, which has hampered any attempted substantial reduction in the overall size of the receiver.

With the foregoing in mind, various display panels have been proposed, one of which comprises picture elements whose luminous intensity can hardly be controlled during luminescence. This has made it impossible to obtain a halftone picture on the panel. A plasma display panel is known as an example of such a display panel.

The plasma display panel, utilizing the luminescence caused by a certain discharge phenomenon, has a memory function. In this type of display panel, an AC voltage, called the sustaining voltage, is continuously applied to all the picture elements. Then, in order to turn on or turn off a specific one of the picture elements, a narrow pulse, called the turn-on pulse or turn-off pulse, is applied to the specific element super-imposed on the sustaining voltage. The element, once turned on, maintains intermittent luminescence at the frequency of the sustaining voltage until it is turned off by the turn-off pulse. This is known in the art as the memory function of the plasma panel, which characterizes such a plasma display panel.

Fundamentally, such a plasma display panel has two states, a luminescent state and a nonluminescent state, which has entailed difficulties in controlling the luminous intensity of each picture element during luminescence. This follows from the fact that the luminosity of the picture element is caused by a discharge phenomenon. It is the foregoing problem that has made it impossible to attain a halftone picture. Hence, such a plasma display panel of the prior art has been thought to be inadequate for the purpose of displaying a picture such as a television picture with a halftone.

SUMMARY OF THE INVENTION

It is a general object of this invention to provide a display apparatus capable of displaying a picture with a halftone by the use of a display panel such as a plasma display panel having a plurality of picture elements whose luminous intensity can hardly be controlled.

The foregoing and other objects are attained in accordance with one aspect of the present invention wherein a halftone picture display can be achieved according to two methods, the first being that the mean brightness of the picture element or luminescent dot be made proportional to the turn-on period. The second method is that the mean brightness of the picture element or luminescent dot for the turn-on period be made proportional to the frequency of the sustaining voltage. One display apparatus associating the concept of a plasma display panel according to this invention is characterized in that all the picture elements or luminescent dots are repeatedly scanned and the turn-on period and/or the frequency is changed by the use of the first and/or the second methods above to enable the picture elements to become luminous with a range of brightness which includes halftone.

BRIEF DESCRIPTION OF THE DRAWINGS

Various objects, features and attendant advantages of the present invention will be more fully appreciated as the same becomes better understood from the following detailed description of the present invention when considered in connection with the accompanying drawings, in which:

FIG. 1 is a frontal view showing a display panel such as a plasma display panel, used for the purposes of this invention;

FIG. 2 is a sectional view taken along line II--II in FIG. 1;

FIG. 3 is a diagram of waveforms useful for illustrating general display operations of a plasma display panel;

FIG. 4 is a diagram illustrating the principle of a first system of the present invention in connection with the luminescent period changing format;

FIG. 5 is a block diagram showing one embodiment in accordance with the first system of the present invention;

FIG. 6 is a block diagram showing an essential part of another embodiment in accordance with the first system of the present invention;

FIG. 7 is a diagram illustrating the principle of a second system of the present invention in connection with the luminescent period changing format;

FIG. 8 is a block diagram showing one embodiment in accordance with the second system of the present invention;

FIG. 9 is a diagram of waveforms useful for illustrating the operation of the first embodiment in accordance with the second system of the present invention;

FIG. 10 is a block diagram showing another embodiment in accordance with the second system of the present invention;

FIG. 11 is a diagram illustrating the principle of the second embodiment in accordance with the second system of the present invention;

FIGS. 12 - 15 are block diagrams showing essential parts of other embodiments in accordance with the second system of the present invention;

FIG. 16 is a graph showing characteristics of the encoder used in the embodiment of FIG. 15;

FIG. 17 is a diagram showing another embodiment in accordance with the second system of the present invention;

FIG. 18 is a block diagram showing one embodiment in accordance with a third system of the present invention in connection with the luminescent period changing format;

FIG. 19 is a diagram of waveforms useful for illustrating the operation of the first embodiment in accordance with the third system of the present invention;

FIG. 20 is a diagram showing the principle of the first embodiment in accordance with the third system of the present invention;

FIG. 21 is a block diagram showing another embodiment in accordance with the third system of the present invention;

FIG. 22 is a diagram of waveforms useful for illustrating the operation of the second embodiment in accordance with the third system of the present invention;

FIG. 23 is a block diagram showing a third embodiment in accordance with the third system of the present invention;

FIG. 24 is a diagram of waveforms useful for illustrating the operation of the third embodiment in accordance with the third system of the present invention;

FIG. 25 is a diagram showing the principle of the frequency changing format used for the purpose of the present invention;

FIG. 26 is a block diagram showing one embodiment in accordance with the frequency changing format of the present invention;

FIG. 27 is a diagram of waveforms useful for illustrating the operation of the first embodiment as shown in FIG. 26;

FIGS. 28 and 29 are diagrams showing essential parts of the first embodiment as shown in FIG. 26;

FIG. 30 is a block diagram showing an essential part of another embodiment in accordance with the frequency changing format of the present invention;

FIG. 31 is a diagram illustrating the principle of the first system of a hybrid format in accordance with the present invention;

FIG. 32 is a block diagram showing an embodiment in accordance with the first system of the hybrid format of the present invention;

FIG. 33 is a diagram of waveforms useful for illustrating the operation of the embodiment of the first system of the hybrid format as shown in FIG. 32;

FIGS. 34 and 35 are diagrams illustrating the essential part of the embodiment of the first system of the hybrid format of the present invention;

FIG. 36 is a diagram illustrating the principle of a second system of the hybrid format in accordance with the present invention;

FIG. 37 is a block diagram showing one embodiment of the second system as shown in FIG. 36;

FIG. 38 is a diagram of waveforms useful for illustrating the operation of the embodiment as shown in FIG. 37; and

FIGS. 39 and 40 are diagrams showing essential parts of the embodiment as shown in FIG. 37.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, and more particularly to FIGS. 1 and 2 thereof, the constructional features of a plasma display panel suitable for the application of this invention will first be described. FIG. 1 is a plan view of the display panel, and FIG. 2 a sectional view taken along line II--II of FIG. 1.

The reference numeral 1 denotes the display panel as a whole, which comprises a lower member 10, an upper member 20, and a partition member 30. The lower member 10 has a rectangular substrate 12 comprised of a transparent material such as glass. A first drive line group Y, consisting of a plurality of thin electrode lines Y1, Y2 ... Yy, is disposed on one surface of the substrate 12. As shown in FIG. 1, these drive lines are arranged linearly and in parallel with each other, at nearly equal intervals, in the longitudinal direction with respect to the substrate 12. As seen in FIG. 2, the first drive line group Y has its central area covered with a transparent insulating plate 16, its both end portions being open. The plate 16 is made, for example, of glass. A plurality of grooves are formed on the surface of the plate 16 in contact with the substrate 12, and the individual drive lines Y1, Y2 ... Yy are fitted in these grooves. The other surface 16A of the substrate 12 is flat.

Similar to the lower member 10, the upper member 20 has a rectangular substrate 22 comprised of a transparent insulating material such as glass. A second drive line group X, consisting of a plurality of thin electrode lines X1, X2 ... Xx is disposed on one surface of the substrate 22. As shown in FIG. 1, these drive lines are arranged linearly and in parallel with each other, at nearly equal intervals, in the longitudinal direction with respect to the substrate 22. This drive line group X also has its central area covered with a transparent insulating plate 25 made for example, of glass, both end portions being open. A plurality of grooves are formed on the surface of the substrate 22 in contact with the insulating plate 26, and the individual drive lines X1, X2, ... Xx are fitted in these grooves. The surface 26A on the other surface of plate 26 is flat.

The partition member 30 is sandwiched between the two members 10 and 20 so that the substrates 12 and 22 are longitudinally perpendicular to each other, and such that the first group of drive lines are perpendicular to the second group of drive lines. The partition member 30 is a frame, being nearly a regular square in shape. This member 30 is disposed in contact with the outer edges of the surfaces 16A and 26A, thereby forming a hermetically closed cavity 32 between the plates 16 and 26. Within any part of the cavity 32 the distance between the surfaces 16A and 26A is substantially the same. The cavity 32 is evacuated of air and then filled with an inactive gas such as neon or argon. In this cavity a plurality of picture elements or luminescent dots are formed. These picture elements are located at the positions where the drive lines Y1, Y2 ..., Yy intersect the drive lins X1, X2, ... Xx. Hereinafter, the first drive line group Y will be referred to as the y drive line group and the second drive line group X as the x drive line group. The y drive lines are for vertical scanning.

The following description of the operation of the plasma display panel includes the preliminary and basic operation which will be useful for a better understanding of the apparatus of the present invention.

Referring now to FIG. 3, there are shown waveforms wherein waveform a is a voltage VX to be applied to the x drive line group. This voltage comprises the sustaining voltage VCX, indicated by the solid line, and a voltage VPX, indicated by the dotted line. The sustaining voltage VCX is continuously applied to all the drive lines of the x group. The voltage VPX is the turn-on pulse applied to one of the x drive lines which corresponds to the picture element or the luminescent dot to be energized.

The sustaining voltage VCX on the x side appears in the form of a pulse train comprising a plurality of pulses 35. The pulse 35 is square with a duration time t1, and repeats at time intervals t2. Its pulse height is determined to be smaller than the discharge start voltlage │Vf │ of each picture element. In this example, the time interval t2 is three times the pulse width t1, or t2 = 3t1. In other words, the repetition period t of the pulse 35 is 4t1. This period t can be, for example, 100μ sec.

In FIG. 3, waveform b indicates a voltage VY to be applied to the drive line group. This voltage comprises a sustaining voltage VCY, indicated by the solid line, and voltages VPY and VQ, indicated by the dotted lines. The voltage VPY is the turn-on pulse applied to one of the y drive lines which corresponds to the picture element to be energized. The voltage VQ is the turn-off pulse. The sustaining voltage VCY on the y side is a pulse train comprising a plurality of pulses 36. This voltage is the same as the sustaining voltage VCX on the x side, except for the timing thereof. The pulse 36 appears in the midst of two adjacent pulses 35. Hence, the time interval between the two pulses 35 and 36 is 2t1 or 1/2t.

Waveform c of FIG. 3 shows the voltage applied to the picture element or the luminescent dot. This voltage comprises a sustaining voltage VC, indicated by the solid line, a turn-on pulse VP and a turn-off pulse VQ, indicated by the dotted lines. The sustaining voltage VC, being the sum of the sustaining voltages VCX and VCY, is applied continuously to all the picture elements. The sustaining voltages VCX and VCY are applied thereto so that their pulses 35 and 36 are positive at the x drive line group and y drive line group, respectively. However, as seen from the picture elements, the pulses 35 and 36 are reversed in polarity. For example, as seen in waveform c, the pulse 35 is positive, and the pulse 36 is negative.

The turn-on pulse VP is the sum of the pulses VPX and VPY. The pulses VPX and VPY are applied simultaneously to the picture element which is to be turned on. Since these pulses stand at mutually reversed polarities as shown by waveforms a and b, the turn-on pulse VP combines the two polarities. The turn-on pulse VP is applied while the pulse 35 or 36 is applied for the pulse duration t1. As a result, the turn-on pulse VP and the pulse 35 or 36 are added together. The resultant total pulse height exceeds the discharge start voltage │Vf │ of the picture element to cause that picture element to discharge, i.e., to become luminous. For example, the picture element under the control of drive lines Yi and Xj will emit light when this picture element receives the turn-on pulse VP.

In the picture element which becomes luminous as a result of such a discharge, a wall voltage VW develops due to the positive ions and electrons produced by the discharge. This wall voltage is indicated by waveform d of FIG. 3. When the picture element under the control of drive lines Yi and Xj receives the turn-on pulse VP according to the timing of waveform c when the positive pulse 35 (with respect to the x drive line group) is applied thereto, the electrons and ions produced in this particular picture element will be accelerated towards the drive lines Xj and Yi, respectively. As a result, electrons remain on the surface 26A of the insulating plate 26, and ions remain on the surface 16A of the insulating plate 16, whereby a wall voltage is produced. This wall voltage increases with the same polarity as that of the pulse 35 as the discharge starts. When the wall voltage reaches a given value, the picture element discharge ceases. Thereafter, the wall voltage remains at that given value. Then, when the next pulse 36 is applied, the wall voltage and the pulse 36 are added together. Again the total voltage exceeds the discharge start voltage -Vf needed to cause the picture element to discharge. The wall voltage increases with the same polarity as that of the pulse 36 until it reaches a given value, thereby causing the picture element to cease its discharge again. In this manner, the picture element, once discharge by the turn-on pulse VP, repeats its discharge by virtue of the wall voltage each time the pulses 35 and 36 are applied without the need for any additional turn-on pulse VP. This is the memory function, discussed above, which characterizes the plasma display. Waveform e of FIG. 3 shows a luminescent waveform with a repetition period tp being equal to 2t1 or 1/2t.

The turn-off pulse VQ is applied so that the wall voltage will be substantially terminated. In this example, the turn-off pulse VQ is applied prior to the pulse 35, after the pulse 36 has ceased. This turn-off pulse, in conjunction with the wall voltage, causes the picture element to discharge. However, the turn-off pulse is narrow in width, which results in a substantial cancellation of the wall voltage. In other words, once the turn-off pulse is applied, the discharge will not occur unless the turn-on pulse VP is duly applied thereto. Hereinafter, the period beginning with the turn-on pulse VP and ending with the turn-off pulse VQ will be referred to as the luminescent period or turn-on period Tp. During this period, the picture element repeats luminescence at intervals tp, i.e., 1/2t. It is to be noted that this period tp is dependent upon the period t of the sustaining AC voltage VC of waveform c of FIG. 3 or upon its frequency f.

According to the present invention, a halftone picture display can be achieved according to two principles, referred to hereinafter as the first principle and the second principle. The first principle is that the mean brightness of the picture element or luminescent dot be proportional to the turn-on period TP. The second principle is that the mean brightness of the picture element or luminescent dot for the turn-on period TP is proportional to the frequency f of the sustaining voltage VC. One display apparatus associating the concept of a plasma display panel according to this invention is characterized in that all the picture elements or luminescent dots are repeatedly scanned and the turn-on period TP and/or the frequency f is changed by the use of the first principle and/or the second principle to enable the picture elements to become luminous with a range of brightness which includes halftone.

Further details of the invention will be described hereinafter by way of example using the first principle applied to the format of changing the turn-on period, or briefly the turn-on period changing format.

Referring now to FIG. 4, there is shown a diagram useful for illustrating the fundamental of the first system of the turn-on period changing format, wherein waveform A designates an input video signal, waveform B is a turn-on control pulse applied to a picture element on the K-th scanning line in the video signal, waveform C represents a turn-off control pulse applied to all the picture elements on the K-th scanning line in the video signal, and waveform D represents the luminescent state of a certain specific picture element on the K-th scanning line. In FIG. 4, the i-th picture element on the K-th scanning line will be discussed with one group of frames F1, F2, and F3 used for the video signal.

For explanatory simplicity, it will be assumed in principle that the scanning is made without interlace. If any interlaced scanning is adopted, the invention will be described on the basis of one field corresponding to one frame.

The instantaneous value v of the video signal corresponding to the i-th picture element is coded as

v = K(a1 w1 + a2 w2 + a3 w3)

where a1, a2 and a3 represents a 1 or 0. For the sake of simplicity the pure binary coded system will be considered. Thus, w1 = 1, w2 = 1/2, and w3 = 1/4, while K represents a conversion constant. As shown in FIG. 4B, the turn-on pulse is generated by the use of a coded signal when a1 in the first frame F1, a2 in the second frame F2, and a3 in the third frame F3 are 1. A turn-off pulse, as shown in FIG. 3C, is generated regardless of which value the binary numbers a1, a2 and a3 assume, T-seconds after the occurrence of the turn-on pulse in the first frame, T/2 seconds after the occurrence of the turn-on pulse in the second frame, and T/4 seconds after the occurrence of the turn-on pulse in the third frame, respectively. (T denotes an arbitrary period shorter than the frame period TF.) In this manner, the picture element will be luminescent with the states as shown in FIG. 4D, with the total turn-on period being a1 T + a2 T/2 + a3 T/4. Accordingly, the mean brightness over the three frames is

B = k'(a1 T + a2 T/2 + a3 T4) = K"(a1 + a2 . 1/2 + a3 . 1/4) = K'"(a1 W1 + a2 w2 + a3 w3)

This mean brightness is proportional to the video signal coded with 3 bits and thus a brightness gradient in 8 levels can be obtained. This is the principle of the first system of this invention. According to this principle, the invention makes it possible to realize a halftone display on the panel which has only two states, a luminescent and nonluminescent state.

Generally speaking, this first system is such that the instantaneous value v of the video signal corresponding to each picture element is converted as follows by using n weights w1, w2, ..., wn on the basis of one period consisting of consecutive frames.

v = K(a1 w1 + a2 w2 + a3 w3 + ... +an wn)

where a1, a2, a3 ..., an are either 1 or 0, and K is a conversion constant. In the kth frame (k = 1, 2, 3, ..., n), the picture element satisfying the condition ak = 1 is selected, and the turn-on period or the turn-off period of the selected picture element is proportioned to the corresponding weight wk.

One embodiment of the first system of the invention will be described more specifically by referring to FIG. 5. In FIG. 5, the video signal input v to the terminal 100 is sampled at each clock 61 and coded by the coder 62 which is controlled by the clock source 60. Coder 62 provides a 3-bit binary number (a1, a2, a3). The clock frequency fc of the clock source 60 is selected to be fc = NH fH /(1 =α) whereby all the picture area required can be displayed (NH = the number of picture elements to be displayed on one horizontal scanning line; fH = the horizontal scanning frequency and α= the blanking period rate). A vertical synchronous signal Sv is applied from the terminal 102 to the frame counter 63, and frame switching signals F1, F2 and F3 are generated in succession at each vertical synchronous signal. This vertical synchronous signal is one which is separated from the television signal. The output of the coder 62 is sampled by a gate circuit 65 which is controlled by the output of the frame counter 63. The gate circuit 65 consists essentially of three AND circuits 65-1, 65-2 and 65-3, and one OR circuit 65-4. The AND circuit 65-1 generates the first bit a1 when the signal F1 is received. The AND circuit 65-2 generates the second bit a2 when the signal F2 is received. The AND circuit 65-3 generates the third bit a3 when the signal F3 is received. The outputs of these AND circuits are supplied to an X memory register 40 through the OR circuit 65-4. Therefore the first bit a1 of the coded output in the first frame where the signal F1 is produced, the second bit a2 of the coded output in the second frame where the signal F2 is produced, and the third bit a3 of the coded output in the third frame where the signal F3 is produced are all shifted to the X memory register 40. Memory register 40 consists of shift registers with bits equal in number to the number of picture elements NH on the horizontal scanning line. The output of the coder 62 is fed to the memory register 40 through the gate circuit 65 at each clock 61 from the clock source 60. At the end of the horizontal scanning period, all the picture element signals on the horizontal scanning line are stored in the X memory register 40. These stored signals are transferred to an X drive register 41 by the horizontal synchronous signal SH supplied from the terminal 101. This horizontal synchronous signal SH also is separated from the video signal. Then the picture element signals on the succeeding scanning line are progressively stored in the X memory register 40. The X drive circuit 42 consists essentially of NH - numbers of switching circuits which gate the turn-on signal 71 from a turn-on pulse generator circuit 70 by the output of the X drive register 41. The turn-on pulse is then applied in parallel to the x drive line group on the panel 1, the drive lines of which correspond to the picture elements with a1 being in the 1 state. The turn-on pulse is applied to the y drive lines selected corresponding to the horizontal scanning line of the video signal. This operation is made under the control of a Y drive circuit 51 as will be described later. For example, in the first X drive register 41 through the X memory register 40, the picture elements with a1 being 1 are turned on in parallel. In other words, when the y drive lines are progressively scanned by a turn-on scanning circuit 50, which will be described later, at each horizontal synchronous signal, all the picture elements are turned on in response to the generation of a1. Similarly, in the second and third frames, the picture elements are turned on in response to the generation of a2 and a3.

In the example shown in FIG. 5, the turn-on scanning circuit 50 as well as the turn-off scanning circuit 52, consists essentially of shift registers having bits equal in number to the number of scanning lines Nv, for shifting the horizontal synchronous signal SH. The Y drive circuit 51 consists essentially of Nv switching circuits, with Nv output stages. The n-th output stage gates the turn-on signal 71 from the turn-on pulse generator circuit 70 by the n-th stage output of the turn-on scanning circuit 50, thereby generating a turn-on pulse. At the same time, the n-th output' signal 76 from the turn-off pulse generator circuit 75 by the n-th stage output of the turn-off scanning circuit 52, thereby generating a turn-off pulse. In FIG. 5, 1 is set into the first bit of the turn-on scanning circuit 50 at each vertical synchronous signal Sv. Then the 1 signal is shifted stage by stage each time the horizontal synchronous signal SH is received. Consequently, the Y drive circuit 51, which is controlled by the turn-on scanning circuit 50, selects y drive lines on the panel 1 one by one at each horizontal synchronous signal SH and applies the turn-on pulse to the individual drive lines selected. Also, the turn-on scanning circuit 50 generates outputs from its m-th, m/2-th, and m/4-th stages. These outputs are supplied to the second gate circuit 66 which is controlled by the outputs F1, F2, F3 of the frame counter 63.

The gate circuit 66 consists essentially of three AND circuits 66-1, 66-2, 66-3, and one OR circuit 66-4. The AND circuit 66-1 generates the m-th stage output of the turn-on scanning circuit 50 when the signal F1 is received. The AND circuit 66-2 generates the m/2-th stage output of the turn-on scanning circuit 50 when the signal F2 is received. The AND circuit 66-3 generates the m/4-th stage output of the turn-on scanning circuit 50 when the signal F3 is received. These outputs are supplied to the turn-off scanning circuit 52 through the OR circuit 66-4. The m-th stage output in the first frame where the signal F1 is produced, the m/2-th stage output in the second frame where the signal F2 is produced, and the m/4-th stage output in the third frame where the F3 signal is produced, are all selected and supplied to the first stage of the turn-off scanning circuit 52. The symbol m denotes a value in terms of m = TfH. The turn-off scanning circuit 52 shifts its registers one after another at each arrival of the horizontal signal SH. As a result, the signal of the n-th stage of the turn-off scanning circuit 52 is delayed behind the signal of the n-th stage of the turn-on scanning circuit 50, by m-bits (i.e., T-seconds) in the first frame, and m/2-bits (i.e., T/2 seconds) in the second frame, and m/4-bits (i.e., T/4 seconds) in the third frame, respectively. In other words, the Y drive circuit 51 which is controlled by the turn-off scanning circuit 52, generates a turn-off pulse to the y drive line T-seconds after the generation of a turn-on pulse in the first frame, T/2-seconds in the second frame, and T/4-seconds in the third frame, respectively. The amplitude of the turn-off pulse applied to the y drive line group is selected so that all the picture elements which are luminescent on the y drive line may be turned off. This is done irrespective of the video signal.

As described above, the i-th picture element on the k-th scanning line is turned on when the coder output a1 (k . i) is 1 and turned off T-seconds thereafter, in the first frame, or turned on when the coder output a2 (k . i) is 1 and turned off T/2-seconds thereafter, in the second rrame, or turned on when the coder output a3 (k . i) is 1 and turned off T/4-seconds thereafter, in the third frame. As a result, the mean brightness over the first to third frames is proportional to the brightness level of the video signal coded in 3 bits.

In the foregoing example, one frame is assigned to each field for display of a picture such as by interlaced scanning in a television system. According to the invention, a halftone display can be realized for all scanning lines under the control of interlaced scanning. Another embodiment of the first system of the invention for interlaced scanning is shown in FIG. 6.

Referring now to FIG. 6, a scanning circuit comprising a turn-on scanning circuit 50, a turn-off scanning circuit 52, and a gate circuit 66 similar to the example shown in FIG. 5 is used. The turn-on scanning circuit 50A, turn-off scanning circuit 52A, and gate circuit 66A are for the odd field, while the turn-on scanning circuit 50B, turn-off scanning circuit 52B, and gate circuit 66B are for the even field. The number of stages of each scanning circuit is equal to the number of scanning lines which constitute one field. In FIG. 6, a circuit 67 separates the vertical synchronous signal into a synchronous signal SVA for the odd field, and a synchronous signal SVB for the even field. By so separating the odd field scanning circuit comprising the circuits 50A, 52A and 66A, and the even field scanning circuit comprising the circuits 50B, 52B and 66B may be operated independently of each other to enable the turn-on and turn-off pulses to be applied to the y drive lines by way of the Y drive circuit 51 having outputs equal in number to the number of frame scanning lines. The outputs of the frame counter 63 are switched in succession such as F1 -F2 -F3 -F1 ... field by field by the vertical synchronous signal SV. Thus, the time intervals between the turn-on pulse and the turn-off pulse, and the coded signal given to the X memory register 40 are determined as indicated in Table 1 below. Therefore, according to this invention, halftone display can be realized in each field.

TABLE 1 ______________________________________ Frame 1 2 3 4 5 6 7 Field odd even odd even odd even odd Frame Counter F1 F2 F3 F1 F2 F3 F1 Output Turn-on and Turn-off pulse 1 1/2 1/4 1 1/2 1/4 1 Interval X Memory a1 a2 a3 a1 a2 a3 a1 Register Input ______________________________________

The invention has been described in connection with a plasma display panel which has a memory function. The invention is not, however, limited to the foregoing; the principles of the invention are readily applicable to other display panels of the type operable in two stable states. In the foregoing example, a pure binary system has been illustrated for coding purposes. Instead, other coding methods with weighted codes such as the 1-2-2-4 code may be employed.

Further, in the foregoing example, the display of a positive picture has been shown. Instead, according to the invention, a negative picture may be displayed when it is arranged such that the individual picture elements are first turned on and then turned off at the timing of the initial turn-on, and again the picture elements are turned on at the timing of the turn-off.

In FIG. 5, it may be so arranged that the clock source 60, coder 62, frame counter 63 and gate circuit 65 are disposed on the transmission side, and the panel 1, X memory register 40, X drive register 41, X drive circuit 42, turn-on scanning circuit 50, Y drive cricuit 51, turn-off scanning circuit 52 and gate circuit 66 are disposed on the display side, and the transmission side and the display side are connected through a suitable transmission line.

A second system of the turn-on period changing format which may realized according to the present invention will now be described. This second system makes it possible to achieve a halftone display within the frame period TF.

Referring now to FIG. 7, there is shown a diagram for illustrating the fundamentals of the second system of the invention, wherein the waveform A denotes an input video signal, B1 is a turn-on control pulse for displaying the first bit signal obtained by coding the video signal (B1 also indicates a turn-off control pulse used for the turn-off thereof), B2 represents a turn-on control pulse for displaying, with a delay of T-seconds, the second bit signal obtained by coding the video signal (B2 also indicates its turn-off control pulse), B3 represents a turn-on control pulse for displaying, with a delay of 3T/2-seconds, the third bit signal obtained by coding the video signal (B3 also signifies its turn-off control pulse), and C indicates the luminous state of a specific picture element.

In FIG. 7, the video signal v corresponding to the specific picture element is binary-coded as

v = K(a1 w1 + a2 w2 + a3 w3)

where a1, a2 and a3 have a value 1 or 0, and K is a conversion constant.

For the sake of simplicity, this binary code is weighted to be w1 = 1, w2 = 1/2, and w3 = 1/4. By using these coded signals a1 , a2 and a3, the turn-on pulse is generated when the signal a1 is 1 for the first turn-on pulse VP1, a2 is 1 for the second turn-on control pulse VP2, and a3 is 1 for the third turn-on control pulse VP3. This function is the first feature of this second system. The time at which the turn-on control pulses VP2 and VP3 are generated are off the timing of the signal v. Therefore, it is necessary to delay the signals a2 and a3 by the use of a suitable delay device, as will be described hereinafter.

The picture elements which have been turned on by the turn-on control pulses VP1, VP2 and VP3, respectively are turned off by the turn-off control pulse VQ1 T-seconds, after the turn-on, the turn-off control pulse VQ2 T/2-seconds after the turn-on, and the turn-off control pulse VQ3 T/4-seconds after the turn-on, respectively. This is the second feature of the second system. In this operation, the period T is determined so that the period, (1 + 1/2 + 1/4)T - 7/4T, is shorter than the frame period TF.

Thus, as indicated by waveform C of FIG. 7 which is the luminescent state of the specific picture element, the mean brightness Br in the frame period TF is

Br = K'(a1 T + a2 T/2 + a3 T/4)

= k"(a1 w1 + a2 w2 + a3 w3) In other words, the mean brightness in the frame period is proportional to the video signal which is coded in 3 bits whereby the brightness gradient in 8 levels can be obtained. This is the halftone display system according to the second system of the invention, which permits attainment of a half-tone display by the use of a display panel of the type which primarily has two stable states, the luminescent state and the nonluminescent state. More particularly, this second system is characterized in that a halftone picture can be obtained on the panel within one frame.

Generally speaking, the second system of the invention is such that the instantaneous value v of the video signal corresponding to each picture element is coded as follows by the use of n-numbers of weights w1, w2, w3, ..., wn.

v = K(a1 w1 + a2 w2 + a3 w3 + ... + an wn)

where a1, a2, a3, ..., an are the value 1 or 0, and K is a conversion constant. Then the codes a1, a2, a3, ..., an are assigned to at least one frame, and the picture elements which come under the condition, ak = 1 (where k - 1, 2, 3, ..., n) in the individual frames are turned on for the turn-on periods proportional to the weights wk.

The invention will now be described in more detail with references to FIGS. 8 and 9 which are diagrams illustrating one example of a half-tone display according to the second system. First, the operation of a timing circuit 110 will be described by referring to FIG. 8. The display system of this example is a line-at-a-time system, as it is so-called, wherein all the picture elements on a certain horizontal scanning line are simultaneously selected and turned on. As will be apparent from FIG. 7, a plurality of y drive lines should be selected simultaneously. More specifically, for example, the k-th y drive line is selected to turn on the picture element shown in FIG. 7 by the second bit a2. With this timing, the (k + m)-th y drive line should also be selected so that the picture element on the (k + m)-th scanning line comprised in the scanning lines which are to be scanned one after another from its k-th one at each 1/fH second be turned on by the first bit a1 of this signal. (Note: m is a value defined as m = fH T where fH is the horizontal scanning frequency and T signifies a value determined so that fH T/4 is an integer). To materialize this halftone display system any suitable arrangement should be provided for the concurrent selection of a plurality of y drive lines.

The timing circuit 110 in FIG. 8 is, for example, a monostable multivibrator system which is triggered by the horizontal synchronous signal SH, and generates a series of command pulse trains as shown in FIG. 9B. S1 and S2 are signals for providing the sustaining drive voltage VC, while q1, q2 and q3 are turn-off command signals, and p1, p2 and p3 are turn-on command signals. These signals are generated from the individual terminals of the timing circuit 110 as indicated in FIG. 8. In FIG. 9, waveform A represents the horizontal synchronous signal SH. The turn-on and turn-off pulses shown in FIG. 9 are applied in such a manner that these pulses are effected during one cycle of the sustaining drive voltage. It has been experimentally determined that in a plasma display, the reliability of the display operation will not be lowered even if a plurality of turn-on and turn-off pulses are applied within one cycle of the sustaining drive voltage VC. Thus, without necessarily increasing the frequency f of the sustaining drive voltage VC, the picture element may be turned on or turned off in a relatively short period of time. It is arranged so that the turn-on control pulses VP1 (Y1), VP2 (Y2) and VP3 (Y3) are applied to the y drive lines Y1, Y2 and Y3, respectively at the time p1, p2 and p3, and also the turn-off control pulses VQ1, VQ2 and VQ3 are applied thereto at the times q 1, q2 and q3 respectively. The x drive lines X1 through X3 are controlled so that turn-on control pulses are generated therein at the time p1 for the signal to be displayed on the y drive line Y1 at the time p2 for the signal to be displayed on the y drive line Y2 and at the time p3 for the signal to be displayed on the y drive line Y3, whereby correct turn-on operation is maintained. In this example, as shown in FIG. 9, the states of the picture elements on the drive line Y3 are VP3 (X1) = 0, VP3 (X2) = 1, and VP3 (X3) = 1 at the time p3. (Note: The turn-on control pulse VP3 (X1) is applied to the x drive line X1 at the time p3.) Therefore, the turn-on pulses VP3 as indicated by waveforms C1 through C3 in FIG. 9; are applied to the picture elements (X2, Y3) and (X3, Y3) to turn on only these picture elements. At other times, the picture elements on the y drive line Y3 will not be turned on. In the line-at-a time system, all the picture elements on a y drive line may be turned off simultaneously. For example, all the picture elements on the drive line Y3 can be turned off by applying the turn-off pulse VQ3 (waveforms C1 through C3 in FIG. 9) to the y drive line Y3. Also, all the picture elements on the drive line Y1 can be turned off in parallel by applying the turn-off pulse VQ1 (waveform C4 in FIG. 9) to the drive line Y1. By the use of such a turn-on and turn-off system, the picture elements on a plurality of y drive lines can be independently turned on or off in one horizontal scanning period. In the turn-off operation, the pulses may be generated simultaneously at the times q1, q2 and q3, as contrasted with the above example wherein the turn-off pulses are generated at different times in harmony with the turn-on operation.

In FIG. 8, the video signal v is sampled by a binary 3-bit coder 162 at a clock 161 provided from a clock source 160. The video signal is thereby coded as follows

v = K(a1 + a2 /s + a3 /4)

where a1, a2 and a3 are a value 1 or 0, and K is a conversion constant. A picture can be displayed on the necessary area when the clock frequency fC is determined to be fC = fH . NH /(1 - ), where NH is the number of picture elements to be displayed on one horizontal scanning line, fH is the horizontal scanning frequency, and is the blanking period rate. The coder 162 generates the bits a1, a2 and a3 in parallel, of which the second and third bits a2 and a3 are supplied to delay circuits 112B and 112C, respectively, with delay times of T-seconds and 3T/2-seconds, respectively. These delay circuits in turn generate signals a'2 and a'3. For such a delay circuit, shift registers with mxNH bits and 3mNH /2 bits are used. The signal a'2 is delayed from the signal a2 by T-seconds, and the signal a'3 from the signal a3 by 3T/2 seconds. These coded signals a 1, a'2 and a'3 are supplied to X memory registers 140A, 140B and 140C, respectively, each comprising shift registers with bits equal in number to NH and being shifted by the clock 161. The signals a1, a'2 and a'3 stored in the memory registers are transferred in parallel to X drive registers 141A, 141B and 141C, respectively, by the horizontal synchronous signal SH at the end of the horizontal scanning period. Therefore, at the time tk at which the k-th horizontal scanning is completed, the first bit a1 of the picture element on the k-th scanning line (or briefly, scanning line k) is set in the X drive register 141A, and the second bit a2 of the picture element on the (k - m)-th scanning line (or briefly, scanning line (k - m)) is set in the X drive register 141B, and also the third bit a3 of the picture element on the (k - 3m/2)-th scanning line (or briefly, the scanning line (k - 3m/2)) is set in the X drive register 141C.

With respect to the signal of the picture element on the scanning line k, the first bit a1 is set in the X drive register 141A at the time tk, the second bit a2 is set in the X drive register 141B at the time tk+m, and the third bit a3 is set in the X drive register 141C at the time t+k+3m/2.

The gate circuit 142A gates the turn-on command signals p1, p2 and p3 from the timing circuit 110 by the outputs of the drive registers 141A, 141B and 141C. The gated signal is applied as a turn-on signal to the X drive circuit 142B. As a consequence, in view of all the picture element signals on the scanning line k, the X drive circuit 142B generates a turn-on pulse when a1 is 1 at the time p1 at tk or a2 is 1 at the time p2 at tk+m, or a3 is 1 at the time p3 at tk+3m/2.

With respect to the k-th drive line Yk, the Y drive circuit 151B generates a turn-on pulse at the time p1 at tk by the scanning circuit 150A or at the time p2 at tk+m by the scanning circuit 150B, or at the time p3 at tk+3m/2 by the scanning circuit 150C. Similarly, for this drive line Yk, the Y drive circuit 151B generates a turn-off pulse at the time q1 at tk+m by the scanning circuit 150B, or at the time q2 at tk+3m/2 by the scanning circuit 150C, or at the time q3 at tk+7m/3 by the scanning circuit 150D. Therefore, the specific picture element is turned on at the time p1 at tk when a1 = 1, turned off at the time q1 at tk+m and turned on at the time p2 when a2 = 1, turned off at the time q2 at tk+3m/2 and turned on at the time p3 when a3 = 1, and then turned off at the time q3 at tk+7m/4.

Thus, by the foregoing turn-on and turn-off control, the turn-on time as illustrated in FIG. 7 is controlled whereby a halftone display is realized within one frame.

The operation of the vertical scanning circuit will be described by referring to FIG. 8. This vertical scanning circuit consists essentially of four scanning circuits 150A, 150B, 150C and 150D with shift registers having bits equal in number to the number of horizontal scanning lines and being shifted by the shift clock (horizontal synchronous signal SH). The first scanning circuit 150A is reset at each vertical synchronous signal SV and, at the same time, 1 is set in its first bit. Accordingly, the drive lines can be scanned in succession under the condition that the outputs of the first scanning circuit 150A are 0 except for the k-th line being 1 at tk. The second scanning circuit 150B is reset when the m-th output of the first scanning circuit is 1 and, at the same time, 1 is set in the first bit thereof. By this operation, the k-th output of the second scanning circuit 150B is 1 only at tk+m and otherwise 0. In other words, the output of the second scanning circuit 150B becomes 1 with the delay T = m/fH from the output of the first scanning circuit 150A. Similarly, the third and fourth scanning circuits 150C and 150D are reset when the m/2-th and m/4-th outputs of the second and third scanning circuits 150B and 150C are 1, respectively, and 1 is set in their first bits. The output of the third scanning circuit 150C is delayed from the output of the first scanning circuit 150A by 3T/2-seconds, and the output of the fourth scanning circuit 150D is delayed behind the output of the first scanning circuit 150A by 7T/4-seconds. The outputs of the scanning circuits 150A through 150D are supplied to the corresponding stages of the gate circuit 151A. This gate circuit gates the turn-on timing signal p1 from the timing circuit 110 by the output of the first scanning circuit 150A, the turn-on timing signal p2 and the turn-off timing signal q1 by the output of the second scanning circuit 150B, the turn-on timing signal p3 and the turn-off timing signal q2 by the output of the third scanning circuit 150C, and the turn-off timing signal q3 by the output of the fourth scanning circuit 150D. The gated output is supplied as the turn-on signal and turn-off signal to the input circuit on the turn-on and turn-off sides of the Y drive circuit. As a result, the Y drive circuit 151B is allowed to generate turn-on and turn-off pulses at any timing required.

As described in detail, the display apparatus as in FIG. 8, is capable of displaying a halftone picture in 3-bit coding or in 8 levels within one frame period.

The invention will further be described in connection with a second embodiment of the second system by referring to FIGS. 10 and 11. In the first embodiment as in FIG. 8, the first bit a1 which is to be displayed for T-seconds is supplied directly to the memory register 140A through the coder 162. To this end, the second bit a2 and the third bit a3 should be delayed T-seconds and 3T/2-seconds, respectively, after the first bit a1. These delays may be obtained by the use of shift registers. Then, to delay the third bit a3, the shift register should have as great a number of bits as 3×250×100/2 = 37.5×103, on condition that NH = 250 and m = 100. To remove this problem according to the second embodiment, the display order is changed; the third bit a3 is displayed T/4-seconds, and the second bit a2 is displayed T/2-seconds, and then the first bit a1 is displayed T-seconds. In this manner, the data to be displayed remains unchanged and it is possible to make the delay time maximum, i.e., 3T/4-seconds. This is half the maximum delay time necessary for the first embodiment. This is one noteworthy feature of the second embodiment. In this example, the number of bits used is 18.75×103. The example shown in FIG. 10 is similar to that in FIG. 8, except for the output circuit of the coder 162, and the scanning circuit for vertical scanning. In FIG. 10, the first bit a1 of the output of the coder 162 is supplied to the first memory register 140A through the delay circuit 112A with the delay time 3T/4-seconds, the second bit a2 to the second memory register 140B through the delay circuit 112D with the delay time T/4-seconds, and the third bit a3 to the memory register 140C directly. Other operations are similar to those shown in FIG. 8. As a result of the above operation, the coded signals a1, a2 and a3 are set in the X drive registers 141A, 141B and 141C, respectively, at tk+3m/4, tk+m/4 and tk. By these signals, turn-on pulses are generated at the time p1, p2 and p3.

For vertical scanning, four scanning circuits comprising shift registers with NV bits are arranged so that the first scanning circuit 150E is reset by the vertical synchronous signal SV and, at the same time, 1 is set in its first bit. By the resultant output, the turn-on time p3 is gated. The secono scanning circuit 150F is reset when the m/4-th output of the first scanning circuit 150E is 1. At the same time, 1 is set in the first bit thereof. By the resultant output, the turn-on time p2 and the turn-off time q3 are gated. Similarly, the third and fourth scanning circuits 150G and 150H are reset when the m/2-th and m-th outputs of the second and third scanning circuits 150F and 150G are 1. At the same time, 1 is set in their first bits. By the output of the third scanning circuit 150G, the turn-on time p1 and turn-off time q2 are gated. Also, by the output of the fourth scanning circuit 150H, the turn-off time q1 is gated. Thus, similar to the example shown in FIG. 8, there are generated in the k-th y drive line a turn-on pulse at the time p3 at tk, a turn-on pulse at the time p2 and a turn-off pulse at the time q3 at tk+m/4, a turn-on pulse at the time p1 and a turn-off pulse at the time q2 at tk+3m/4, and a turn-off pulse at the time q1 at tk+7m/4. Therefore, in harmony with the foregoing operation of the X drive circuit, the picture element on the k-th y drive line is turned on when the signal a3 is 1 at the time p3 at tk, turned off at the time q3 at tk+m/4 and turned on when the signal a2 is 1 at the time p2 and turned off at the time q2 at tk+3m/4 and turned on when the signal a1 is 1 at the time p1, and further, turned off at the time q1 at tk+7m/4. Under the foregoing operating conditions, the specific picture elements assumes a luminescent state as shown in FIG. 11C. The means brightness of this picture element in terms of time is

Br - K'(a1 + a2 /2 + a3 /4)

In other words, the mean brightness Br is proportional to the input video signal quantized in 8 levels.

A third embodiment of the second system of the invention will be described by referring to FIG. 12. In the foregoing first and second embodiments of the second system, the necessary delay is established by delaying coded binary signals. According to latest techniques, a video signal can be recorded or reproduced in analog form either directly or after suitable modulation. A typical example of this is the magnetic disk or magnetic drum. An example of this type of memory device used as a delay device is shown in FIG. 12. In FIG. 12, the video signal is frequency-modulated by a modulator 171 and written into a disk or drum type delay linear memory 170 by means of a write head 172. This signal is read out by read heads 173B and 173C located a positions on the recording track of the memory 170 where the signal is delayed T-seconds and 3T/2-seconds respectively. The read signals are demodulated by demodulators 174B and 174C and then selected in succession by a switch circuit 175A and supplied to a coder 180. The coder 180 encodes the signal into signals a1, a2 and a3 in parallel, which are supplied to the first, second and third output lines by way of a second switch circuit 175B which is synchronous with the switch circuit 175A on the input side. The clock frequency at which the signals of the coder 180 are sampled is determined to be exactly three times the clock frequency fC used in the first embodiment of the second system. The switch circuits 175A and 175B are arranged to recycle at the frequency fC. Thus, the coded first bit a1 of the signal without passing through the delay device is supplied to the first memory register 140A which is to receive the signal of the first output line of the second switch circuit 175B. The coded second bit a'2 of the signal delayed T-seconds by the delay device is supplied to the second memory register 140B which is to receive the signal of the second output line. Similarly, the coded third bit a' 3 of the signal delayed T/2-seconds by the delay device is supplied to the third memory register 140C which is to receive the signal of the third output line. Therefore, as in the example of FIG. 8, a half-tone display can be obtained in 8 levels within one frame period. According to this embodiment, a long delay time can be obtained by the use of a comparatively simple delay device such as an analog type magnetic disk or drum. Hence, this embodiment is quite useful, particularly when the delay T is desired to be as long as about half of one frame period.

Recently, a new display system has been proposed in which only one frame of a stationary or still picture is transmitted to the receiver side where this video signal is recorded for display over a certain period when it is needed. In such a video system, the display apparatus on the receiving side should essentially have the function of recording the transmitted picture signal for one frame. To meet this requirement, a third embodiment of the invention is provided which is characterized in that the delay device is used in common as a one-frame memory useful in a still picture system. As shown in FIG. 13, the total delay time of the delay device is made equal to the frame period TF, and read heads 173A, 173B and 173C are disposed on the memory track with delay periods T-seconds and 3T/2-seconds provided between the heads 173A and 173B and between heads 173B and 173C, respectively. If no memory of one frame capacity is needed, the delay time may be determined as 3T/4 seconds, as in the second embodiment shown in FIG. 10.

In the embodiments of FIGS. 12 and 13, the video signal is coded by one coder. Instead, more coders may be used depending on the conversion speed required. FIG. 14 shows an example wherein three coders are used in parallel. In FIG. 14, the video signal is supplied directly to a first coder 180A, and the resultant signal, delayed by 3T/2 seconds is supplied to a second coder 180B and a third coder 180C. Of three bits obtained from these coders, only the first bit a1 from the first coder 180A is supplied to the first memory register 140A, only the second bit a2 from the second coder 180B is fed to the second memory register 140B, and only the third bit a3 from the third coder 180C is fed to the third memory register 140C. In this manner, the coding speed may be one-third of that of the example shown in FIG. 11.

A simplified coder arrangement is shown in FIG. 15, and its characteristics are shown in FIG. 16. In FIG. 15, three coders 181A, 181B and 181C are one-bit coders with characteristics as shown in FIG. 16. Assuming the input video signal is normalized, the first coder 181A having a code output terminal C (181-1) and a residual output terminal R (181-2) where the code output and residual output will appear depends upon the following conditions:

the code output a1 is zero when V 1,

the code output ai is 1 when V 1, and

the residual output v'= 2 x (v - a1).

The same arrangement is made for the coders 181B and 181C. When such coders are serially connected in three stages so that the residual output of the previous stage is supplied to the following stage, the input signal to the first stage is coded in three bits. The input signal v is expressed as

v = a1 + a2 /2 + a3 /4

Thus, the coded signals a1, a2 and a3 are obtained as the outputs of the first, second and third stages. In the embodiments in FIG. 15, an analog delay circuit 170 comprising, for example, a magnetic disk is inserted between the stages of coders. The residual output of the first coder 181A is written into the memory 170 by the write head 172A through the modulator 171A. This signal is reproduced by the read head 173B through the modulator 174B and then is supplied to the second coder 181B with a T-second delay. Similarly, the residual output of the second coder 181B is supplied to the third coder 181C with a T/2-second delay. Hence, with respect to a specific picture element, the first bit a1 is obtained as a result of coding the output of the coder 181A, the second bit a'2 is obtained as a result of coding the output of the second coder 181B with a T-second delay, and the third bit a'3 is obtained as a result of coding the output of the coder 181C with a T/2-second delay. These binary signals a1, a2 and a'3 are supplied to the memory registers 140A, 140B and 140C of FIG. 7 whereby a halftone display is obtained.

This arrangement may be applicable to the foregoing still video system in such a manner that a modulator 171D, a write head 172D, a read head 173D, a demodulator 174D, and a one frame memory constituted of a memory 170B using a track arrangement comprising a memory 170 are used whereby the output 100C of the demodulator 174D is supplied to the decoder 181A. Also, the delay time may be made 3T/4-seconds by the arrangement illustrated in FIG. 10.

In the foregoing embodiments, it is assumed that one picture constitutes two frames, each corresponding to one field, in the event the video signal is subjected to interlaced scanning. When the number of scanning lines is halved to substantially construct the same picture with two frames each field is supposed to constitute one frame for the display.

FIG. 17 is a graph illustrating another example of the second system of the invention wherein a plurality of serial frames are used to display one picture. More specifically, the first and second frames are used whereby, of the coded video signals a1, a2, a3 and a4, the signals a1 and a3 are displayed on the picture element r1 of the first frame, and the signals a2 and a4 are displayed on the picture element r2 of the second frame. For this operation, the foregoing first to third embodiments of the second system can be used.

The invention will be described more particularly in connection with the third system based on the turn-on period changing format. The aim of this third system is to realize a halftone display by the arrangement that one picture element comprises a plurality of luminescent dots.

FIG. 18 is a block diagram showing one construction of one embodiment of the third system, and FIG. 19 is a diagram of waveforms for illustrating the operation of the embodiment of FIG. 18. In this example, one picture element comprises three luminescent dots located at intersections of the x drive line group and the y drive line group on a plasma display panel 1. One specific picture element, e.g., the i-th picture element on the k-th scanning line (briefly, the scanning line k) will be considered. This picture element consists of three luminescent dots α1, α2 and α3 located at the points where the i-th x drive line Xi intersects three y drive lines yk1, yk2 and yk3, as shown in FIG. 18. The video scanning is made on three luminescent dots as one unit, and binary signals a1, a2 and a3 which are obtained by binary-coding the video signal are displayed on the luminescent dots α1, α2, α3, respectively.

Generally, this third system is such that each of a plurality of picture elements comprises luminescent dots α1, α2, α3, ..., αn, and the instantaneous value v of the video signal corresponding to each picture element is coded as follows by the use of weights w1, w2, ..., wn.

v = K(a1 w1 + a2 w2 + a3 w3 + ... + an wn)

where a1, a2 and a3 are of a value 1 or 0, and K is a conversion constant. Then, of n luminescent dots which constitute a specific picture element, the luminescent dotαk which corresponds to the condition ak = 1 (where k= 1, 2, 3, ..., n) is made luminous for the turn-on period proportional to the corresponding weight wk and shorter than the frame period of the video signal.

In FIG. 18, a timing circuit 210 is triggered by the horizontal synchronous signal SH and generates turn-on and turn-off timing signals p1, p2, p3 and q (see FIG. 19B) at the individual output terminals. The references Sx and Sy in FIG. 19B denote timing signals for generating the sustaining drive voltage VC. Turn-on pulses are generated for a plurality of y drive lines by the turn-on timing signals p1, p2 and p3 within one cycle of the sustaining drive voltage. In FIG. 19, waveform A stands for the horizontal synchronous signal SH.

The input video signal v is sampled by a coder 262 at a clock 261 provided from a clock generator circuit 260. This signal v is binary-coded as follows, with weights w1, w2, ..., wn.

v = K(a1 w1 + a2 w2 +... + an wn)

where v is the amplitude of the video signal, a1, a2, ..., an are of a value 1 or 0, and K is a conversion constant. For the sake of simplicity 3-bit pure binary coding will be considered. Thus, v = K(a1 + a2 /2+ a3 /4).

The construction of such a coder is well-known and therefore its description is omitted. The coder 262 generates binary-coded signals a1, a2 and a 3 in parallel, which are supplied to the first, second and third X memory registers 240A, 240B and 240C, respectively. Each of these X memory registers comprises a shift register with bits provided equal in number to the number of picture elements displayed on one scanning line, or equal to the number NH of x drive lines, the shift register being capable of shift-clocking the clock 261. When the clock frequency fC is set to be fC = fH NH /(1 - α) where fH is the horizontal scanning frequency, and α is the blanking period rate, the video signals for NH picture elements can be coded by the coder 262 within the horizontal scanning period. At the end of the horizontal scanning period, the NH numbers of coded signals a1, a2, a3, ... are stored in the X memory registers 240A, 240B and 240C, respectively. Then these signals are transferred to the X drive registers 241A, 241B and 241C, respectively, by the horizontal synchronous signals SH. Each of these X drive registers has bits equal in number to NH. Therefore, at the end of the k-th horizontal scanning, or at the time tk, the coded signals a1, a2 and a3 for the NH picture elements on the line k are set in the X drive registers 241A, 241B and 241C. The outputs of these X drive registers are supplied to the X gate circuit 242. This gate circuit gates the turn-on timing signals p1, p2 and p3 from the timing circuit 210 by the outputs of the drive registers 241A, 241B and 241C. The gated outputs are supplied as the turn-on signal to the X drive circuit 243.

The X drive circuit 243 comprises switch circuits 243-1 provided NH in number, and generates a turn-on pulse upon receiving a turn-on signal. The X drive circuit 243 generates a turn-on pulse for the x drive line on which a1 = 1 at the time p1, for the x drive line on which a2 = 1 at the time p2, and for the x drive line on which a3 = 1 at the time p3, respectively, as indicated by Vpx in FIG. 19C. A turn-on pulse V'px in FIG. 19C occurs for the picture element on the scanning line (k + m). These operations are performed in parallel at the time tk for NH picture elements for display on the scanning line k.

The y drive line group on the panel 1 will be scanned and driven in the following manner. In FIG. 18, the vertical scanning circuit comprises four scanning circuits 250A, 250B, 250C and 250D, a Y gate circuit 252, and a Y drive circuit 253 having 3NH switch circuits equal to the number of y drive lines. Each of the scanning circuits 250A, 250B and 250C and 250D has NV bits being the same number as the y drive lines for picture displayed, and comprises a shift register shifted by the horizontal synchronous signal SH as its shift clock. The switch circuits are grouped by threes, e.g., 253-1A, 253-1B and 253-1C are selected to drive the y drive lines yk3, yk3, and yk3. As shown in FIG. 18, each switch circuit has two input terminals W and E, and generates a turn-on pulse VPY when an input is present at W, or a turn-off pulse VQ when an input is present at E.

The first scanning circuit 250A is reset at each arrival of the vertical synchronous signal SV, and 1 is set in its first bit. Accordingly, this scanning circuit 250A generates a 0 output at the time tk, except for the k-th line where it is 1. This 1 position is shifted at each horizontal synchronous signal SH to allow the y drive lines to be scanned. The second scanning line 250B is reset when the m-th output of the first scanning circuit 250A is 1 and, at the same time 1 is set in its first bit. Thus the k-th output of the second scanning circuit 250B becomes 1 only at tk+m and otherwise is 0. (Note: m = fH T, where T is a period shorter than the frame period TF) In this manner, therefore, the outputs of the individual stages of the second scanning circuit 250B become 1 with a delay T = m/fH from the outputs of the corresponding stages of the first scanning circuit 250A. Similarly, the third and fourth scanning circuits 250C and 250D are reset when the m/2-th and m/4-th outputs of the first scanning circuit 250A are 1 and, at the same time, 1 is set in their first bits. Consequently, the outputs of the individual stages of the third and fourth scanning circuits 250C and 250D become 1 with delays of T/2 and T/4, respectively, from the outputs of the corresponding stages of the first scanning circuit 250A.

The outputs of these scanning circuits are supplied to the corresponding stages of the Y gate circuit 252. This gate circuit gates the foregoing timing signals p1, p2, p3, and q by the outputs of the first to fourth scanning circuits 250A, 250B, 250C and 250D, thereby generating the turn-on pulse VPY and turn-off pulse VQ by way of the drive circuit 253 in the following manner. On the scanning line k, for example, any turn-on pulse VPYK is gated by the k-th output of the first scanning circuit 250A. Then, at tk the following turn-on pulses are generated:

The switch circuit 253-1A generates a turn-on pulse VPYK1 for the drive line yk1 at the time p1.

The switch circuit 253-1B generates a turn-on pulse VPYK2 for the drive line yk2 at the time p2.

The switch circuit 253-1C generates a turn-on pulse VPYK3 for the drive line yk3 at the time p3. These pulses are indicated by D1, D2 and D3 in FIG. 19.

Also, on the scanning line k, the following turn-off pulses are generated:

The switch circuit 253-1A generates a turn-off pulse VQK1 for the drive line yk1 at the time q of tk+m which depends on the second scanning circuit 250B.

The switch circuit 253-1B generates a turn-off pulse VQK2 for the drive line yk2 at the time q of tk+m/2.

The switch circuit 253-1C generates a turn-off pulse VQK3 for the drive line yk3 at the time q of tk+m/4.

The waveform D1 indicates the turn-off pulse VQK1 generated at the time tk+m. The value of this turn-off pulse is determined so that all the luminescent dots on a specific y drive line may be turned off by such a turn-off pulse applied to this drive line. In other words, with these turn-off pulses applied, all the picture elements which have been turned on at the time tk on the drive lines yk1, yk2 and yk3 are turned off with time intervals T, T/2 and T/4, respectively, after the occurrence of the turn-on pulse at tk.

As described above, the turn-on pulse VPX as indicated by waveform C in FIG. 19 is applied to the x drive line X1, and the turn-on pulses VPYK1, VPYK2, and VPYK3 as indicated by waveforms D1, D2 and D3, respectively, are applied to the y drive lines yk1, yk2 and yk3. As a result, the turn-on pulses as shown by waveforms E1, E2 and E3 in FIG. 19 are applied to the luminescent dots α1, α2 and α3 which are located at the intersections of these drive lines. Consequently, luminescence occurs at tk in the following manner:

The luminescent dot α1 on the drive line yk1 is turned on at the time p1 when a1 = 1.

The luminescent dot α2 on the drive line yk2 is turned on at the time p2 when a2 = 1.

The luminescent dot α3 on the drive line yk3 is turned on at time p3 when a3 = 1.

These luminescent dots are turned off with time intervals T, T/2 and T/4, respectively, after tk. FIG. 20 shows their luminescent states, wherein waveforms B1, B2 and B3 stand for the luminescent states of α1, α2 and α3, respectively, and A denotes the video signal received.

Assume that the luminescent dots α1, α2 and α3 are closely adjacent to each other and that the frame period TF is suitably short relative to the afterimage period of the human eyes. If so, the spatially and timewise averaged luminescent output of α1, α2 and α3 is visually observed as the brightness of the picture element (k, i) consisting of these luminescent dots. As evidenced in FIG. 20, the mean brightness of one picture element (k, i) consisting of α1, α2 and α3 is

B = K'(a1 T + a2 T/2+ a3 T/4) = K"(a1 + a2 /2+ a3 /4)

This shows that the brightness B is proportional to the input video signal quantized in 3 bits, i.e., in 8 levels. This is the halftone display on the panel 1 according to the third system of the invention.

The second embodiment of the third system of the present invention as seen in FIG. 21 will be described with the help of the signal waveforms shown in FIG. 22. As contrasted with the foregoing first embodiment wherein one picture element comprises three luminescent dots aligned in the Y-direction on one x drive line, this second embodiment is such that one picture element comprises three luminescent dots aligned in the X-direction on one y drive line.

In FIG. 21, a timing circuit 210A generates turn-on and turn-off timing pulses p1, p2, p3 and q1, q2, q3 as shown in FIG. 22. The video signal v is coded by a coder 262, and the resultant coded signals a1, a2 and a3 are supplied to X memory registers 240A, 240B and 240C and then set in X drive registers 241A, 241B and 241C, respectively, by the horizontal synchronous signal SH. An X drive circuit 243A has 3NH switch circuits equal to the number of x drive lines. The x drive lines, grouped by threes, e.g., Xi1, Xi2 and Xi3, are driven by the switch circuits 243-1A, 243-1B and 243-1C. A gate circuit 242A gates the above-mentioned timing signals by the outputs of the X drive registers 241A, 241B and 241C to cause the switch circuits to generate turn-on pulses as follows:

The switch circuit 243-1A generates a turn-on pulse VPX1 for the drive line Xi1 at the time p1 and a1 = 1.

The switch circuit 243-1B generates a turn-on pulse VPX2 for the drive line Xi2 at the time p2 and a2 = 1.

The switch circuit 243-1C generates a turn-on pulse VPX3 for the drive line Xi3 at the time p3 and a3 = 1.

Similarly, the gate circuit 242A causes the switch circuits to generate turn-off pulses as follows:

The switch circuit 243-1A generates a turn-off pulse VQX1 for the drive line Xi1 at the time q1.

The switch circuit 243-1B generates a turn-off pulse VQX2 for the drive line Xi2 at the time q2.

The switch circuit 243-1C generates a turn-off pulse VQX3 for the drive line Xi3 at the time q3.

Fig. 22 shows these turn-on and turn-off pulses as indicated by waveforms C1, C2 and C3.

The Y drive circuit 253A has NV switch circuits equal to the number of y drive lines. The gate circuit 252A gates the timing signals p1, p2, p3 and q1, q2, q3 by the outputs of four scanning circuits 250A, 250B, 250C and 250D comprising shift registers as in the first embodiment, and causes turn-on and turn-off pulses to be generated for the y drive line yk in the following manner:

Turn-on pulses VPYK1, VPYK2, and VPYK3 are generated at the time p1, p2 and p3 at tk which depends on the output of the first scanning circuit 250A.

A turn-off pulse VQYK1 is generated at the time q1, at tk+m which depends on the output of the second scanning circuit 250B.

A turn-off pulse VQYK2 is generated at the time q2, at tk+m/2 which depends on the output of the third scanning circuit 250C.

A turn-off pulse VQYK3 is generated at the time q3, at tk+m/4 which depends on the output of the fourth scanning circuit 250D.

In FIG. 22, the waveform D indicates this turn-off pulse.

In this embodiment, unlike the first embodiment, the amplitude of the turn-off pulse is determined so that the luminescent dot at a specific intersection of y and x drive lines is turned off only when such turn-off pulse is applied simultaneously to the specific y and x drive lines.

Thus, the turn-on pulses VP1, VP2, VP3 and turn-off pulses VQK1 (and VQK2, VQK3, though not shown) as indicated by waveforms E1, E2 and E3 in FIG. 22 are applied to the luminescent dots α1, α2 and α3 located at the intersections of the y drive line yk and x drive lines Xi1, Xi2 Xi3. Consequently, the luminescent lot α1 is turned on at tk when a1 = 1 and is turned off at tk+m ; the luminescent dot α2 is turned on at tk when a2 = 1 and is turned off at tk+m/2 ; and the luminescent dot α3 is turned on at tk when a3 = 1 and is turned off at tk+m/ 4.

Under these conditions, the periods for which the luminescent dots α1, α2 and α3 remain luminous are T, T/2 and T/4, respectively. In this manner, the video signal is quantized in 8 levels to enable halftone pictures to be displayed on the panel as in the first embodiment of the third system.

Referring now to FIG. 23, there is shown a block diagram of a third embodiment realized according to the third system of the invention. The features and advantages of the invention will further be described from another aspect in connection with the waveform diagram shown in FIG. 24. This example is such that one picture element comprises four luminescent dots determined by two y drive lines and two x drive lines.

A timing circuit 210B generates turn-on timing signals p1, p2, p3, p4 and turn-off timing signals q1, q2, q3, q4 in the waveforms shown in FIG. 24.

In FIG. 23, a 4-bit coder 262A generates coded outputs a1, a2, a3 and a4 in parallel, in which are supplied to four memory registers 240A, 240B, 240C and 240D, respectively. These register outputs are set in X drive registers 241A, 241B, 241C and 241D, respectively, by the horizontal synchronous signal SH.

The X drive circuit 243B comprises 2NH switch circuits equal to the number of x drive lines used. A pair of x drive lines Xi1 and Xi2 are driven by the outputs of the switch circuits 243-1A and 243-1B respectively. The gate circuit 242B gates the timing signals p1 through p4 by the outputs of X drive registers 241A through 241D, and causes turn-on pulses to be generated in the following manner:

The switch circuit 243-1A generates a turn-on pulse VPX1 for the x drive line Xi1 at the time p1 when a1 = 1, or a turn-on pulse VPX2 at the time p2 when a2 = 1.

The switch circuit 243-1B generates a turn-on pulse VPX3 for the drive line Xi2 at the time p3 when a3 = 1, or a turn-on pulse VPX4 at the time p4 when a4 = 1.

Also, the gate circuit 242B gates the turn-off timing signals q1 through q4 and causes turn-off pulses to be generated in the following manner:

The switch circuit 243-1A generates turn-on pulses VQX1 and VQX2 for the x drive line Xi1 at the time q1 and q2.

The switch circuit 243-1B generates turn-off pulses VQY3 andVQY4 for the x drive line Xi2 at the times q3 and q4.

The Y drive circuit 253B comprises 2NV switch circuits being the same number as the number of y drive lines. A pair of y drive lines yk1 and yk2, for example, which organize the k-th line, are driven by the switch circuits 253-1A and 253-1B, respectively. The gate circuit 252B gates the timing signals p1 through p4 and q1 through q4 by the outputs of five scanning circuits 250E, 250F, 250G, 250H and 250I, and causes turn-on and turn-off pulses to be generated in the following manner. Turn-on pulses are generated when, for example, the output of the k-th stage of the first scanning circuit 250E is 1, i.e., at tk, as follows:

The switch circuit 253-1A generates turn-on pulses VPYK1 and VPYK3 for the y drive line yk1 at the time p1 and p2.

The switch circuit 253-1B generates turn-on pulses VPYK2 and VPYK4 for the y drive line yk2 at the time p2 and p4.

The switch circuit 253-1A generates a turn-off pulse VQYK1 for the y drive line yk1 when the output of the k-th stage of the second scanning circuit 250F is 1, or at the time q1 of tk+m, or a turn-off pulse VQYK3 when the output of the k-th stage of the fourth scanning circuit 250H is 1, or at the time a3 of tk+m/4.

The switch circuit 253-1B generates a turn-off pulse VQYK2 for the y drive line yk2 when the output of the k-th stage of the third scanning circuit 250G, is 1, or at the time q2 of tk+m/2, or a turn-off pulse VQYK4 when the output of the k-th stage of the fifth scanning circuit 250I is 1, or at the time q4 of tk+m/8. In this example, the fifth scanning circuit 250I is reset when the output of the m/8-th stage of the first scanning circuit 250E is 1, and, at the same time, 1 is set in its first bit position.

Thus, in the system shown in FIG. 23, the luminescent dots α1, α2, α3 and α4 at the intersections of drive lines yk1, yk2 and Xi1, Xi2 are turned on/off in the following manner:

The dot α1 is turned on at tk and turned off at tk+m, on condition that a2 = 1.

The dot α2 is turned on at tk and turned off at tk+m/2, on condition that a2 = 1.

The dot α3 is turned on at tk and turned off at tk+m/4, on condition that a3 = 1.

The dot α4 is turned on at tk and turned off at tk+m/8, on condition that a4 = 1. Therefore, it is evident that the invention permits one picture element which comprises α1, α2, α3 and α4 to become luminous in a halftone.

Several principles of the invention have been illustrated above by way of example in connection with a television signal which is supposed to be reproduced either by interlaced scanning wherein each field is to construct one frame and thus one complete picture is built with two frames, or by scanning wherein two fields are to construct substantially the same picture with half the number of scanning lines.

The invention will now be described from another important aspect comprised in a "frequency changing format" for changing the frequency of the sustaining AC voltage by the use of the phenomenon related to the second system of the invention wherein the mean brightness of a picture element for its turn-on period TP is proportional to the frequency of the sustaining AC voltage VC.

FIG. 25 is a graphic representation useful for illustrating the principle of the frequency changing format. In FIG. 25, the abscissa represents time, and the ordinate the positions of horizontal scanning line. Also, the straight lines L1, L2 and L3 indicate vertical scanning lines for one period consisting of three frames. For the sake of simplicity, the video signal is assumed to be scanned on a one-field/one-frame basis, with or without interlace.

In FIG. 25, the regions I, II and III are driven by the sustaining voltages f1, f2 and f3 in a manner as will be described hereinafter. This is one feature of this format. The video signal of a picture element, for example, on the line k is binary coded as

V = K(a1 w1 + a2 w2 + ... + an wn)

where a1, a2, ... an are of a value 1 or 0, V is the amplitude of the video signal, K a conversion constant, and w1, w2, ..., wn are weights for the coding. For explanatory simplicity, a 3-bit pure binary coding with weights w1 = 1, w2 = 1/2 and w3 = 1/4 will be considered. Then the following display is performed by using the coded signals a1, a2 and a3. At times tk1, tk2 and tk3 when the scanning of the line k comes to an end in the individual frames, the picture element in the previously luminous state is turned off. Then, in the first frame F1, the picture element is turned on when a1 = 1. In the second frame F2, it is turned on when a2 = 1. In the third frame F3, it is turned on when a3 = 1. This is another feature of this format of the invention. The picture element, once turned on, remains luminous over the full frame period.

The brightness of the picture element turned on by the coded signal in the above manner is proportional to the frequency f of the sustaining voltage in the corresponding frame. Hence, the mean brightness B over the three frames is

B = K'(a1 f1 + a2 f2 + a3 f3)

where K' is a constant. If f2 = f1 /2, and f3 = f1 /4,

B = K"(a1 + a2 /2 + a3 /4)

where K" is a constant. In other words, the mean brightness throughout the three frames is proportional to the amplitude of the video signal quantized in three bits. Thus, the halftone display of a picture in 8 levels can be realized. This display method uses three frames for one cycle as described above, which, however, will cause no flicker if the frame period is short enough.

Table 2 below shows how often the picture element is made luminous in 8 levels of tone by quantized 3-bit pure binary coded signals on the conditions that f2 = 1/2f1 and f3 = 1/4f1. In other words, the amount of luminescence brought about in the three frames by the video signal is summarized according to the signal levels. In the table, f1 denotes the frequency of the sustaining voltage VC, and f1a denotes the number of turn-on in each frame period TF

TABLE 2 ______________________________________ Video First Second Third Number of Signal Frame Frame Frame Turn-Ons Level ( f1) (f2 =1/2f1) (f3 =1/4f1) in 3 Frames ______________________________________ 111 H H H 7/4 f1a 110 H H L 6/4 f1a 101 H L H 5/4 f1a 100 H L L 4/4 f1a 011 L H H 3/4 f1a 010 L H L 2/4 f1a 001 L L H 1/4 f1a 000 L L L 0 ______________________________________

In Table 2, H indicates that luminescence occurs in the specific frame, and L signifies that no luminescence occurs. Of 8 levels of tone, the level 111 is the highest where 7/4f1a turn-ons occur, and 000 is the lowest where no turn-ons occur. As shown, there is a luminescence gradient in terms of the number of turn-ons in the order of signal level. It is readily apparent that a halftone display can be obtained since the luminescent brightness is directly dependent upon the number of turn-ons.

In general, this frequency changing format is such that the instantaneous value v of the video signal corresponding to each picture element is coded as follows with n weights w1, w2, w3, ..., wn for one cycle consisting of n consecutive frames.

V = K(a1 w1 + a2 w2 + a3 w3 + ... + an wn)

where a1, a2, a3, ..., an are of a value 1 or 0, and K is a conversion constant. Thus, in the k-th frame (k = 1, 2, 3, ..., n), the picture element in the state ak = 1 is kept luminous, and the frequency of the AC voltage sustaining such luminescence is proportional to the corresponding weight wk.

A specific example of the frequency changing format of the first system will now be described by referring to FIGS. 26 through 29.

In FIG. 26, a timing circuit 310 receives through its terminal 101 the horizontal synchronous signal SH of a television signal. As a result, the timimg circuit 310 generates timing signals Sx, Sy1, Sy2, Sy3, p and q at its output terminals. The signal Sx determines the timing and width of the sustaining voltage VCX which is applied to the x drive line group on the panel 1. The signals Sy1, Sy2 and Sy3 determine the timing of the sustaining voltage VCY applied to the y drive line group. The signals p and q are the timing pulses for the turn-on pulse VP and turn-off pulse VQ. In FIG. 27, the waveform A indicates the horizontal synchronous signal SH. The timing signals Sx, Sy1, Sy2, Sy3, p and q may be provided, for example, by the use of monostable multivibrators in combination with counters in a well-known manner. The timing signal Sx is applied to the S terminal of an X drive circuit 343 having NH X switch circuits equal to the number of picture elements to be displayed on one horizontal scanning line. As a result, the X drive circuit 343 is generating a sustaining voltage with a waveform Sx applied to all the x drive lines. The construction of the X switch circuit will be described hereinafter with reference to FIG. 28.

In parallel with the above operation, a sustaining voltage controlled by the timing signals Sy1, Sy2, and Sy3 is applied to the y drive line group in each of the regions, I, II and III of FIG. 25. A frame counter 363 is a senary counter which receives through its terminal 102 the vertical synchronous signal SV of a television signal, and generates frame signals F1, F2, F3, F'1, F'2 and F'3 selected at each arrival of the vertical synchronous signal. A first gate circuit 351 gates the timing signals Sy1, Sy2 and Sy3 by these frame signals, according to the logic shown in Table 3 and generates outputs g1 and g2

TABLE 3 ______________________________________ Frame F1 F2 F3 F'1 F'2 F'3 g1 S y1 S y1 S y3 S y3 S y2 S y2 g2 S y3 S y2 S y2 S y1 S y1 S y3 Input to Memory a1 a2 a3 a1 a1 a3 Register Output of Y 0 1 0 1 0 1 0 Scanning Cir- (III) (I) (II) (III) (I) (II) (III) cuit (Region) ______________________________________

For example, in the frame F1, the output g1 is Sy1, and g2 is Sy3. Of the frame signals produced by the frame counter 363, the signals F1, F3, F'2 have (NV + 1) bits, respectively, and are supplied to the Y scanning circuit 330, which comprises shift registers which shift by using the horizontal synchronous signal SH as the shift clock. (Note: NV is the number of y drive lines, i.e., the number of scanning lines to be displayed.) In the frames F1, F3 and F'2, 1 is set in the outputs of the individual stages of the Y scanning circuit in ascending order, while in the frames F2, F'1 and F'3, 0 is set therein progressively. For example, the outputs of the first, second, ..., k-th stages are 1 and those of the (k+1)-th, ..., (NV + 1 )-th stages are 0 at the same tk when the scanning of line k in the first frame is completed. One of the regions shown in FIG. 25 can be designated by the output of the scanning circuit 330. The Y gate circuit 332 gates the timing signals g1 and g2 by the output of the Y scanning circuit 330. The resultant sustaining timing signal is supplied to each of the S terminals of the Y switch circuits which organize the Y drive circuit 333. An example of this Y gate circuit 332, together with the Y switch circuit, will later be described in detail by referring to FIG. 29. Briefly, the Y gate circuit 332 generates g1 when the output of the corresponding stage of the Y scanning circuit 330 is 1, or g2 when it is 0. These signals g1 and g2 are applied to the Y switch circuit 333. As described above, the signals g1 and g2 are switched according to frames as shown in Table 3. Hence the sustaining voltage VCY applied to the y drive line group from the Y drive circuit 333 will assume waveforms Sy1, Sy2 and Sy3 in the regions I, II, and III, respectively. For example, at tk in the first frames F1 and F'1, the y drive lines Y1 and Y2, ..., Yk belong to region I and are driven by the sustaining voltage with waveform Sy1, and the y drive lines Yk+1, Yk+2, ..., Yy belong to region II and are driven by the sustaining voltage with waveform Sy2. In other words, the individual picture elements are driven by different Y sustaining voltages according to the region to which the picture element belongs. Thus, in region I, the picture element is driven in the waveforms Sx and Sy1. In region II, it is driven in the waveforms Sx and Sy 3. The net sustaining voltages applied to the individual picture elements are represented by waveforms indicated by C1, C2 and C3, respectively, in FIG. 27. Of the sustaining voltages applied to the picture elements in the individual regions, a pair of positive and negative ones which contribute to luminescence during one horizontal scanning period are as follows:

The pair of Sx and Sy1 contribute to luminescence for 4 cycles in the region I.

The pair Sx and Sy2 contribute to luminescence for 2 cycles in region II.

The pair Sx and Sy3 contribute to luminescence for 1 cycle in region III. In this manner, it becomes apparent that the three scanning regions I, II and III are driven by sustaining voltages with frequencies in the ratio of 1, 1/2 and 1/4, as has been described with respect to FIG. 25.

The frequency changing format will further be described in connection with signal coding and turn-on means operable according to the coded signals. In FIG. 26, the video signal V from a terminal 100 is sampled at each clock 361 provided from a clock source 360 and coded into binary signals a1, a2 and a3, which are supplied in parallel to an X memory register 340 in the following manner, through a second gate circuit 352 which is controlled by the output of a frame counter 363:

The signal a1 is supplied to the X memory register in the first frames F1 and F'1.

The signal a2 is supplied to the X memory register in the second frames F2 and F'2.

The signal a3 is supplied to the X memory register in the third frames F3 and F'3.

The X memory register 340 has NH bits and comprises a shift register for shifting by a clock 361. Assume that fC = fH NH /(1 - ) where fC is the frequency of the clock 361, fH is the horizontal scanning frequency, and is the horizontal blanking period rate. Under these conditions, the signal of the picture element to be displayed on each line is stored in the X memory register 340 at the end of the horizontal scanning period. The stored signal is transferred to the X drive register 341 with NH bits when the horizontal synchronous signal SH is received. The X gate circuit 342 gates the turn-on timing signal P by the output of the X drive register 341. The resultant turn-on signal is supplied to the W terminal of an X switch circuit of the X drive circuit 343. As a result of this operation, the X drive circuit 343 generates a turn-on pulse VPX superimposed on the X sustaining voltage and applied to the individual drive lines in parallel in the following manner:

The turn-on pulse VPX is applied to the x drive line where a1 = 1, in the first frames F1 and F'1

The turn-on pulse VPX is applied to the x drive line where a2 = 1, in the second frames F2 and F'2.

The turn-on pulse VPX is applied to the x drive line where a3 = 1, in the third frames F3 and F'3.

The Y scanning circuit 330 is operated so that the outputs of the first to k-th stages are 1 and those of the (k+1)-th to (NV + 1)-th stages are 0 at tk in the first frame F1. A Y gate circuit 332 detects the boundary between 1 and 0, and gates the turn-off and turn-on timing signals q and p in the k-th stage which is the boundary therebetween. The gated signal is supplied to the E and W terminals of the Y switch circuit of the Y drive circuit 333. At tk, the Y drive circuit 333 applies a turn-off pulse VQ to the k-th y drive line Yk at the time q, and a turn-on pulse VPY to the same drive line at the time p. The value of the turn-off pulse VQ is determined so that all the picture elements on a specific y drive line are turned off solely by this pulse VQ. Also, at tk, the signal of line k is set in the X drive register 341, and a turn-on pulse VPX corresponding to this signal is supplied to the x drive line at the same time p. Accordingly, the picture elements on the k-th drive line are turned off at the time q. While at the time p, the picture element where a1 = 1 is turned on in the first frame, the picture element where a2 = 1 is turned on in the second frame, and the picture element where a3 = 1 is turned on in the third frame.

The picture element, once turned on, becomes luminous repeatedly for a period f1 in the first frame, f1 /2 in the second frame, and f1 /4 in the third frame. Thus, a halftone display in three bits i.e., in 8 levels, is realized.

The switch circuits which constitute the drive circuits 333 and 343 will now be described with reference to FIG. 28 which is a circuit diagram showing the X switch circuit and X gate circuit which constitute the X drive circuit 343, and FIG. 29 which is a circuit diagram showing the Y switch circuit and Y gate circuit which constitute the Y drive circuit 333. In FIG. 28, the symbols S and W denote input terminals of the sustaining signal and turn-on timing signals, respectively. The symbol D signifies an output terminal connected to the drive lines on the panel 1. Power terminals ES and EWX are connected to the power sources supplying voltages whose amplitudes are nearly the same as those of the sustaining voltage VCX and the turn-on pulse VPX, respectively. When the input signal SX to the terminal S is 0 (i.e., a low input), it is inverted by an inverter 343-1 to turn on a transistor 343-2 and turn off a transistor 343-4. As a consequence, the output D is kept at a potential of nearly zero by a transistor 343-2 through a diode 343-5. When the input SX to the terminal S is 1 (i.e., a high input), the transistor 343-2 turns off, and the transistor 343-4 which is driven by way of the transformer 343-3 turns on. As a result, the output D increases positively to a value near ES. In other words, a sustaining voltage of an amplitude ES is produced at the terminal D when an input is applied to the terminal S. When the input to the terminal W is 1, a transistor 343-8 turns on through a buffer 343-6 and a transformer 343-7, with the result that the output D increases negatively to a value near EWX. When the input to the terminal W is 0, the transistors 343-4 and 343-8 cannot be simultaneously turned on because the inputs to the terminals S and W are not simultaneously 1. As shown in FIG. 28, the X gate circuit belonging to the X switch circuit generates a turn-on timing signal to be applied to the W terminal when the output of the corresponding stage of the X drive register 341 is 1. Therefore the turn-on pulses can be controlled by the coded video signals a1, a2 and a3.

In FIG. 29, the symbols S, W and E denote input terminals of sustaining, turn-on and turn-off timing signals, D denotes an output terminal connected to the y drive lines on the panel 1, and ES, EW and EE denote terminals connected to power sources capable of supplying voltages whose amplitudes are equal to those of the sustaining voltage, turn-on pulse and turn-off pulse, respectively. When the input to the terminal S is 1, a transistor 333-3A turns on by way of a buffer 333-1A and a transformer 333-2A, and at the same time, a transistor 333-6 turns off by way of an OR circuit 333-4 and an inverter 333-5. Accordingly, the output D increases positively to a value near ES. This also occurs when the input to the terminal W or E is 1. The reference numerals 333-1B and 333-1C represent buffers similar to 333-1A. The reference numerals 333-2B and 333-2C denote transformers similar to 333-2A. Also, the reference numerals 333-3B and 333-3C denote transistors. When the inputs to the terminals S, W and E are all 0, the transistor 333-6 turns on, and the output D is kept at a potential near zero. In the above manner, the circuit as shown in FIG. 29, provides sustaining voltage VCY, turn-on pulse VPY and turn-off pulse VQ at its output terminal D by the sustaining voltage, turn-on and turn-off timing signals applied to the input terminals S, W and E.

FIG. 29 includes the Y gate circuit belonging to the Y switch circuit, which is operated in the following manner. With respect to the k-th switch circuit, the Y gate circuit gates the sustaining timing signals through gates 332-1A, 332-1B and 332-1C, thereby generating an output g1 when the output of the k-th stage of the Y scanning circuit 330 is 1, or g2 when it is 0. This output is supplied to the terminal S of the switch circuit. Also, the Y gate circuit generates a turn-on timing signal p and a turn-off timing signal q through a binary OR circuit 332-2, gates 332-3A and 332-3B when the output of the k-th stage of the Y scanning circuit 330 differs from that of the (k + 1)-th stage thereof. These timing signals are supplied to the terminals W and E of the switch circuit. In this manner, the sustaining voltage is assigned to each scanning region, and the turn-on and turn-off pulses are scanned.

Another embodiment permitting interlaced scanning will now be described by referring to FIG. 30. This embodiment uses a Y scanning circuit 330A and a Y gate circuit 332A for the odd field, and a Y scanning circuit 330B and a Y gate circuit 332B for the even field. These scanning and gate circuits are similar to the Y scanning circuit 330 and the Y gate circuit 332 shown in FIG. 26. The number of stages of each scanning circuit is the same as the number of scanning lines which constitute one field. The outputs of the gate circuits 332A and 332B are applied to the corresponding stages of the drive circuit 333 having as many stages as the scanning lines. The scanning circuit 330A for the odd field is set with 1 progressively in the frames F1, F3 and F'2 and the scanning circuit 330B for the even field is set with 1 progressively in the frames F2, F'1 and F'3 in this order. The signal g1 is supplied as the sustaining timing signal to the gate circuit 332A, and g2 is supplied to the gate circuit 332B. Then, when the output of the scanning circuit 330A is 1, the gate circuit 332A applies signal g1 to the corresponding stage of the Y drive circuit 333. When the output of the scanning circuit 330B is 1, the gate circuit 332B applies signal g2 to the corresponding stage of the Y drive circuit 333. The turn-on and turn-off pulses are controlled in the same manner as in the example shown in FIG. 26. The sustaining voltage and the coded signals appearing in the recurring fields will assume values as shown below, in Table 4. Thus, it is feasible to realize a halftone picture display by interlaced scanning.

In the foregoing example, it is noted that the video signal is supposed to be reproduced either by interlaced scanning wherein each field is to construct one frame and thus one complete picture is built with two frames, or by scanning wherein two fields are to construct substantially the same picture with half the number of scanning lines. Also, one cycle of the sustaining voltage is effected at its lowest frequency during the horizontal scanning period for turn-on and turn-off control. Instead, several cycles thereof may be used at its lowest frequency, which will not detract from any advantages of the system of the present invention.

TABLE 4 ______________________________________ odd F1 F3 F'2 Field even F2 F'1 F'3 odd a1 a3 a2 Data Displayed even a2 a1 a3 odd S y1 S y3 S y2 Frequency of = -- = -- = Sustaining f1 f3 f2 Voltage even S y2 S y1 S y3 = = = f2 f1 f3 ______________________________________

Several other embodiments of the invention will hereinafter be described in connection with a hybrid format which incorporates the foregoing first and second systems in combination.

Referring now to FIG. 31, there is shown a graphic representation for illustrating the principle of the hybrid format of the first system, wherein the abscissa represents time, the ordinate represents the horizontal scanning line position, and the straight lines L1, L2 and L3 represent the states of vertical scanning in the first, second and third frames, assuming that three frames constitute one cycle. For the sake of simplicity, the display is performed on a one-field/one-frame basis, with or without interlace.

In FIG. 31, regions I, II and III are driven by the sustaining voltage of a frequency f, f/2 and f/4, respectively, in a mananer as will be described hereinafter. This is the first feature of the first hybrid system.

In FIG. 31, B denotes turn-on periods of a picture element driven by the coded signals a1 through a6. The turn-on period is Ta for the signals a1, a2 and a3, and is Ta/8 for the signals a4, a5 and a6. This is the second feature of the first hybrid system.

For convenience, the picture element on the like k will be considered. The video signal of this picture element is binary coded as

V = K(a1 w1 + a2 w2 + ... +an wn)

where a1, a2, ...,an are of a value 1 or 0, V is the amplitude of the video signal, K is a conversion constant, and w1, w2, ..., wn are coding weights. In this example, 6-bit pure binary coding will be considered. Thus

V = K(a1 + a2 /2 + a3 /4 + a4 /8 + a5 /16 + a6 /32)

The amplitude V is quantized into 64 levels as

b1 = a1 + a4 /8

b2 = a2 + a5 /8

b3 = a3 + a6 /8 Then, by quaternary coded signals b1, b2 and b3,

V = K(b1 + b2 /2 + b3 /4)

This code conversion is the third feature of the first hybrid system.

Assume that, as shown in FIG. 31B, a1 and a4 are displayed for time intervals Ta and Ta/8, respectively, with respect to the coded signal b1. The timewise mean brightness is

B1 = K1 (a1 Ta + a4 /Ta/8) = K'1 (a1 + a4 /8)

where K1 and K'1 are constants. This brightness is proportional to the quaternary value b1. The same code conversion is made for b2 and b3.

The coded signals b1, b2 and b3 which are modulated in terms of time width and displayed in four levels are displayed by applying sustaining voltages at frequencies f, f/2 and f/4, respectively. In this display, the timewise mean brightness B is:

B = K2 (b1 f + b2 f/2 + b3 f/4) = K'2 (b1 + b2 /2 + b3 /4)

where K2 and K'2 are constants.

From Eqs. (1) through (3) it is evident that the brightness of the specific picture element is proportional to the video signal which is binary coded in 6 bits, and that a halftone display in 64 levels can be obtained. This is the fundamental principle of the first hybrid system. According to this invention, no flicker will appear in the display on a 3-frame one cycle basis if the frame period is sufficiently short.

Table 5 below shows how often luminescence occurs for a halftone display in 64 levels quantized by 6-bit pure binary coding. The reference Ta indicates a turn-on period, A denotes the number of turn-ons when a sustaining voltage VC of frequency f is applied, H denotes the occurrence of luminescence and L denotes no occurrence of luminescence. ##EQU1## 111111 H H H H H H 63/32A 111110 H H H H L H 62/32A 111101 H H L H H H 61/32A 111100 H H L H L H 60/32A 111011 L H H H H H 59/32A . . . 000100 H L L L L L 4/32A 000011 L L H L H L 3/32A 000010 L L H L L L 2/32A 000001 L L L L H L 1/32A 000000 L L L L L L 0 __________________________________________________________________________

In general, according to the first system, the video signal V is coded as follows over one cycle comprising n frames, by using (m + n) weights u1, u2 , ..., um and w1, w2, ..., wn.

______________________________________ V = K (a11 u1 + a12 u2 + ... + a1 mum)w. sub.1 + ( a21 u1 + a22 u2 + ... + a2 mum)w2 + ... + ... + ( am1 u1 + an2 u2 + ... + an mum)wm ______________________________________

where a11, a12, ..., anm are of a value 1 or 0, and K is a conversion constant. Thus, in the j-th frame (j = 1, 2, ..., n), the picture element where ajk = 1 is given a turn-on period proportional to the weight uk (k = 1, 2, ..., m) whereby the frequency fj of the sustaining voltage applied for this period becomes proportional to the weight wj.

A specific example of this first system will now be described by referring to FIG. 32. First, a means for generating the sustaining voltage VC will be described.

In FIG. 32, the reference numeral 410 indicates a timing circuit which receives through its terminal 101 the horizontal synchronous signal SH of a known television signal. Triggered by this horizontal synchronous signal, the timing circuit 410 generates timing signals Sx, Sy1, Sy2, Sy3, p1, p2 and q of the waveforms indicated by B1 through B6 in FIG. 33. The signal Sx determines the timing and the width of the sustaining voltage Vcx which is applied to the x drive line group on the panel 1. The signals Sy1, Sy2 and Sy3 determine the timing of the sustaining voltage Vcy which is applied to the y drive line group. The signals p1 and p2 determine the timing of turn-on pulses Vpx and Vpy, respectively, and the signal q is the timing signal for the turn-off pulse VQ. In FIG. 33, waveform A denotes the horizontal synchronous signal SH which may be provided by the use of monostable multivibrators in combination with counters of known types. The timing signal Sx is applied in parallel to the terminal S of an X drive circuit 443 comprising NH X switch circuits equal to the number of picture elements displayed on one horizontal scanning line. As a result, the X drive circuit 443 generates the sustaining voltage Vcx with the waveform shown by Sx, which is applied to all the x drive lines. The construction of the X switch circuit will be further described hereinafter by referring to FIG. 34.

Another sustaining voltage controlled by the signals Sy1, Sy2 and Sy3 is applied to the y drive line group in the regions I, II and III, respectively, of FIG. 31. The frame counter 463 used in this example is a senary counter which receives its terminal 102 the vertical synchronous signal SV of a usual television signal and generates frame signals F1, F2, F3, F'1, F'2 and F'3 switched at each vertical synchronous signal SV. The first gate circuit 451 gates the timing signals Sy1, Sy2 and Sy3 by the frame signals according to the logic shown below in Table 6, and generates outputs g1 and g2.

TABLE 6 ______________________________________ Frame F1 F2 F3 F'1 F'2 F'3 Input to 440A a1 a2 a3 a1 a2 a3 Memory Register 440B a4 a5 a6 a4 a5 a6 (Gate 452) Input to Y g1 S y1 S y1 S y3 S y3 S y2 S y2 Drive Gate (Gate 451) g2 S y3 S y2 S y2 S y1 S y1 S y3 Output of Y 0 1 0 1 0 1 0 Scanning (III) (I) (II) (III) (I) (II) (III) Circuit (Region) ______________________________________

For example, in the frame F1, the signal g1 is Sy1 and g2 is Sy3. The frame signals F1, F3, and F'2 produced in the frame counter 463 are supplied to the first Y scanning circuit 430A comprising a shift register with (NV + 1) bits (NV = the number of y drive lines of the y drive line group, i.e., the number of scanning lines to be displayed) and shifted by the horizontal synchronous signal SH which serves as the shift clock. Accordingly, 1 is set in the outputs of the individual stages of the Y scanning circuit in ascending order in the frames F1, F3 and F'2, and 0 is set therein in the frames F2, F'1 and F'3. For example, at tk, i.e., at the end of the scanning of the line k in the first frame F1, the outputs of the first, second, ..., k-th stages are 1 and those of the (k + 1)-th stages are 0. Therefore, by the outputs of the scanning circuit 430A, the regions (see FIG. 31) can be designated.

The Y gate circuit 432 gates the timing signals g1 and g2 by the outputs of the Y scanning circuit 430A. The resultant sustaining timing signal is applied to each of the terminals S of NV Y switch circuits which constitute the Y drive circuit 433. An example of this Y gate circuit, together with the Y switch circuit, will later be described in detail by referring to FIG. 35. Briefly, the Y gate circuit generates the signal g1 when the output of the corresponding stage of the Y scanning circuit is 1, or g2 when it is 0. These signals g1 and g2 are applied to the Y switch circuit. As described above, the signals g1 and g2 are switched according to the frame as shown in Table 6. Hence, the sustaining voltage Vcy applied to the y drive line group from the Y drive circuit 433 will assume waveforms Sy1, Sy2 and Sy3 in the regions I, II and III, respectively. For example, at tk in the first frames F1 and F'1, the y drive lines Y1, Y2, ..., Yk belong to the region I and are driven by the sustaining voltage with waveform Sy1, and the y drive lines Yk+1, Yk+2, ..., Yy belong to the region II and are driven by the sustaining voltage with waveform Sy2. In other words, the individual picture elements are driven by different Y sustaining voltages according to the regions to which the picture elements belong. Thus, in the region I, the picture element is driven in the waveforms Sx and Sy1. In the region II, it is driven in the waveforms Sx and Sy2. In the region III, it is driven in the waveforms Sx and Sy3. The net sustaining voltages applied to the individual picture elements are of waveforms indicated by C1, C2 and C3, respectively, in FIG. 33. Of the sustaining voltages applied to the picture elements in the individual regions, a pair of positive and negative voltages which contribute to luminescence during one horizontal scanning period are as follows:

The pair Sx and Sy1 contributes to luminescence for 4 cycles in region I.

The pair of Sx and Sy2 contributes to luminescence for 2 cycles in region II.

The pair Sx and Sy3 contributes to luminescence for 1 cycle in region III.

In this manner, it is apparent that the three scanning regions I, II and III are driven by sustaining voltages with frequencies in the ratio of 1, 1/2 and 1/4, as has been presumed with reference to FIG. 31.

The signal coding and the turn-on means using the coded signals will now be described. In FIG. 32, the video signal V from a terminal 100 is sampled at each clock 461 provided from a clock source 460 and coded into 6-bit binary signals a1 through a6, which are delivered in parallel in the following manner, through a second gate circuit 452 which is controlled by the output of a frame counter 463 as shown in Table 6.

The signals a1 and a4 are selected in the first frames F1 and F'1.

The signals a2 and a5 are selected in the second frames F2 and F'2.

The signals a3 and a6 are selected from the third frames F3 and F'3.

These circuits may be formed of known logic circuits and the description thereof need not be given herein.

The coded signals a1, a2 and a3 selected by the gate circuit 452 are supplied to the X memory registers 440A and 440B by way of a delay circuit 456 with the delay time Ta/8. The other signals a4, a5 and a6 are supplied directly to the X memory registers 440A and 440B. These X memory registers comprise shift registers each having NH bits and operated by a shift clock 461. When the clock frequency fC is set to be fC = fH NH /(1 -α) where fH is the horizontal scanning frequency, and α is the rate of horizontal blanking period, then the signal of the picture element to be displayed on a specific line is stored in the X memory registers. The signals stored therein are transferred to X drive registers 441A and 441B each having NH bits, upon arrival of the horizontal synchronous signal SH. Therefore, at the time tk, i.e., at the end of the scanning of the line k in the first frame F1, the signal a1 of the line (k - m/8) is set in the register 441A, and a4 of the line k is set in the register 441B. In view of the signal of the picture element on the line k, the signal a1 is set in the drive register 441A at tk+m/8, and a4 in the drive register 441B at tk. (Note: The symbol m denotes a value satisfying the condition m = fH Ta, where Ta is the display period.)

The X gate circuit 442 gates the foregoing timing signals p1 and p2 by the outputs of the X drive registers 441A and 441B. The gated signal or the turn-on signal, is supplied to the terminal W of each of the X switch circuits which constitute the X drive circuit 443. More details of the X gate circuit and X switch circuit will be described hereinafter by referring to FIG. 34. The turn-on pulse Vpx from the X drive circuit 443 is superimposed on the X sustaining voltage and applied to the corresponding x drive line for the picture element on the line k in the following manner:

In the first frames F1 and F'1, it is applied at the time p1 of tk+m/8, when a1 = 1, or at the time p2 of tk, when a4 = 1.

In the second frames F2 and F'2, it is applied at the time p1 of tk+m/8, when a2 = 1, or at the time p2 of tk, when a5 = 1.

In the third frames F3 and F'3, it is applied at the time p1 of tk+m/8, when a3 = 1, or at the time p2 of tk when a6 = 1.

The scanning of y drive lines is performed in the following manner. As previously described, the Y scanning circuit 430A is operated so that, for example, the outputs of the first to k-th stages are 1 and those of the (k + 1)-th to (NN + 1)-th stages are 0 at tk in the first frame F1. The Y gate circuit 432 detects the boundary between 1 and 0 and gates the timing signal p2 in the boundary stage k and sends the first turn-on pulse to the Y drive circuit 433 in a manner as will be described hereinafter by referring to FIG. 35. This first turn-on signal is generated at tk The second and third Y scanning circuits 430B and 430C are made up of shift registers each having NV bits and operated for shifting by the horizontal synchronous signal SH. By the gate circuit 435, the second Y scanning circuit 430B has its first bit as 1 when the first Y scanning circuit 430B has its first bit as 1 when the first Y scanning circuit 430A has proceeded to the m-th stage. In other words, the outputs of the individual stages of the second Y scanning circuit becomes 1 with a delay Ta/8 (= m/8fH) after those of the corresponding stages of the first Y scanning circuit 430A. Similarly, the outputs of the individual stages of the third Y scanning circuit 430C become 1 with a delay Ta (= m/fH) after those of the corresponding stages of the second Y scanning circuit 430B. The outputs of these Y scanning circuits are supplied to the Y gate circuit 432. As will be described later, the Y gate circuit gates the timing signals q and p1 by the output of the second Y scanning circuit 430B. The gated signals are the first turn-off signal and the second turn-on signal, respectively, which are applied to the Y drive circuit. Similarly, the Y gate circuit gates the timing signal q by the output of the third Y scanning circuit 430C. This gated signal is the second turn-off signal applied to the Y drive circuit. Thus, the Y drive circuit 433 generates turn-on and turn-off pulses superimposed on the Y sustaining voltage VCY and applies these pulses for example, to the k-th y drive line as follows:

The first turn-on pulse VPY at the time p2 of tk.

The first turn-off pulse VQ at the time q of tk+m/8.

The second turn-on pulse VPY at the time p1 of tk+m/8.

The second turn-off pulse VQ at the time q of tk+9m/8. The value of the turn-off pulse is determined so that all the luminescent dots on a specific y drive line may be turned off solely by such a turn-off pulse applied to this specific drive line.

Since the x drive lines are driven as described previously, the picture elements on the line k are turned on or turned off in the following manner:

In the first frames F1 and F'1 :

the picture element where a4 = 1 is turned on at time p2 of tk ;

this picture element is turned off at the time q of tk+m/8 and, at the same time, the picture element where a1 = 1 is turned on at the time p1 ; this picture element is then turned off at the time q of tk+9m/8. Under the foregoing conditions, the coded signal b1 + a4 /8 of 4 levels is displayed by the sustaining voltage of frequency f in the first frame. Similarly, in the second and the third frames, the coded signals b2 and b3 are displayed at the frequencies f/2 and f/4, respectively. This proves the fact that a halftone display in 64 levels can be realized according to the fundamentals of the system illustrated by referring to FIG. 31.

The Operation of the switch circuits which constitute the drive circuit will now be described by referring to FIG. 34 which is a circuit diagram showing an X drive circuit 443 comprising X switch circuits and an X gate circuit, and to FIG. 35 which is a circuit diagram showing a Y drive circuit comprising Y switch circuits and a Y gate circuit. In FIG. 34, the symbols S and W represent sustaining and turn-on timing signal input terminals, respectively, D represents an output terminal connected to the x drive lines on the panel, and ES and EWX represent power terminals connected to the power sources capable of supplying voltages whose amplitudes are nearly the same as those of the sustaining voltage VCX and turn-on phase VPX, respectively. When the input signal Sx is the terminal S is 0 (i.e., a low input), the input is inverted by an inverter 443-1 to cause a transistor 443-2 to be turned on and a transistor 443-4 to be turned off. As a result, the output D is kept near zero by the transistor 443-2 via a diode 443-5. When the input signal Sx to the terminal S is 1 (i.e., a high input), the transistor 443-2 is turned off, and a transistor 443-4 which is driven through a transformer 443-3 is turned on. As a result, the output D increases positively to a value near ES. This shows that a sustaining voltage whose amplitude ES can be generated at the output terminal D by the input to the terminal S. When the input to the terminal W is 1, a transistor 443-8 is turned on through a biffer 443-6 and a transformer 443-7. As a result, the output D increases negatively to a value near EWX. When the input to the terminal W is 0, the transistor 443-8 is off. In other words, a turn-on pulse VPX can be generated by being superimposed on the sustaining voltage by the input to the terminal W. Because the inputs to the two terminals S and W cannot be 1 simultaneously, the transistors 443-4 and 443-8 will not be turned on simultaneously. The X gate circuit belonging to the X swtich circuit applies a turn-on timing signal to the terminal W of the switch circuit when the outputs of the corresponding stages of the X drive registers 441A and 441B are 1, whereby the turn-on pulse is controlled according to the foregoing coded video signals a1 through a6.

In the Y switch circuit shown in FIG. 35, the symbols S, W and E denote sustaining, turn-on and turn-off timing signal input terminals, respectively, D denotes an output terminal connected to the y drive lines on the panel, and ES, EW and EE denote power terminals connected to power sources capable of supplying voltages whose amplitudes are the same as those of the sustaining voltage VCY, turn-on pulse VPY and turn-off pulse VQ.

When the input to the terminal S is 1, a transistor 433-3A is turned on through a buffer 433-1A and a transformer 433-2A, and a transistor 433-6 is turned off through an OR circuit 433-4 and an inverter 433-5. As a result, the output D increases positively to a value near ES. This occurs when the input to the terminal W or E is 1. The reference numerals 433-1B and 433-1C represent buffers similar to 433-1A. Also, 433-2B and 433-2C denote transformers similar to 433-2A. Transistors 433-3B and 433-3C are similar to the transistor 433-3A. When the inputs to the terminals S, W and E are all 0, the transistor 433-6 is turned on whereby the output at the terminal D is kept near zero. According to the invention, therefore, the sustaining voltage vCY, turn-on pulse VPY and turn-off pulse VQ can be generated at the output terminal D by applying a sustaining timing signal, a turn-on timing signal, and a turn-off timing signal to the terminals S, W and E, respectively.

In the Y gate circuit belonging to the Y switch circuit shown in FIG. 35, the gate circuits 432-1A, 432-1B and 432-1C operate to supply the signal g1 to the corresponding switch circuit through its terminal S when the output of the k-th stage of the Y scanning circuit 430A is 1, or the signal g2 to the corresponding switch circuit when the output thereof is 0. (Note: This operation relates to the k-th switch circuit.)

The timing signal p1 is gated through a binary OR circuit 432-2 and a gate circuit 432-3A when the output of the k-th stage of the scanning circuit 430A differs from that of the (k + 1)-th stage thereof. At the same time, the timing signal p2 is gated through a gate circuit 432-3B when the output of the k-th stage of the scanning circuit 430B is 1 whereby a turn-on signal is generated to be applied to the terminal W of the switch circuit. Also, the timing signal q is gated through gate circuits 432-4A, 432-4B and 432-4C when the outputs of the k-th stages of the scanning circuits 430B and 430C are 1 whereby a turn-off signal is generated to be applied to the terminal E of the switch circuit. This causes the Y drive circuit 433 to generate a sustaining voltage, as well as turn-on and turn-off pulses at the necessary times, which are applied to the y drive lines.

In the foregoing example, the invention is applied to a plasma display panel presently in wide use. It is apparent that the invention is readily applicable to other display panels having bistable states. Additionally, in the above example, pure binary coding is employed. Instead, other suitable binary coding may be used, such as 1-2-2-4 with weights.

Furthermore, the system of the invention has been described in relation to the operation wherein one cycle of the sustaining voltage is effected at its lowest frequency during the horizontal scanning period for turn-on and turn-off control. Instead, several cycles thereof may be used at its lowest frequency, which will not detract from any advantages of the system of the present invention.

In the foregoing example, 2-bit time width modulation is made within one frame, and the display in 3 bits is performed through frequency modulation for each frame. Instead, the number of bits for display within one frame may be arbitrarily selected. Also, the combination of bits in each frame may be suitably determined.

Additionally, in the above example, the scanning is made frame by frame without interlace. If interlace is associated, the display is effected on a one-field/one-frame basis. It is evident that the invention can duly be applied to a display controlled under interlaced scanning. It is noted that the video signal is supposed to be reproduced either by interlaced scanning wherein each field is to construct one frame and thus one complete picture is built with two frames, or by scanning wherein two fields are to construct substantially the same picture with half the number of scanning lines.

Another hybrid format of the second system of the invention will hereinafter be described with reference to FIG. 36 which is a diagram useful for illustrating the principle of the second system, wherein the abscissa represents time, the ordinate represents the horizontal scanning line position, and the straight lines L1 and L2 and L3 represent the states of vertical scanning in the first, second and third frames, assuming that three frames constitute one cycle. For the sake of simplicity, display is performed on a one-field/one-frame basis, with or without interlace.

In FIG. 36, the regions I, II and III are driven by the sustaining voltage of frequencies of f, f/2 and f/4, respectively, in a manner as will be described hereinafter. This is the first feature of this second hybrid system.

In FIG. 36, B denotes turn-on state of luminescent dots α1, α2 which constitute one picture element driven by coded signals a1 through a6. The coded signals a1, a2 and a3 are displayed at the luminescent dot α1 for the period Ta, and the coded signal a4, a5 and a6 are displayed at the luminescent dot α2 for the period Ta/8. This is the second feature of the second hybrid system.

For simplicity, the picture element on the line k will be considered. Then the video signal of this picture element is binary coded as

V = K(a1 w1 + a2 w2 + ... + an wn)

where a1, a2, ..., an are of a value 1 or 0, V is the amplitude of the video signal, K is a conversion constant, and w1, w2, ..., wn are coding weights. In this example, 6-bit pure binary coding will be considered. Thus,

V = K(a1 + a2 /2 + a3 /4 + a4 /8 + a5 /16 + a6 /32)

The amplitude V is quantized into 64 levels as

b1 = a1 + a4/ 8

b2 = a2 + a5 8

b3 = a3 + a6 /8

Then, by quaternary coded signals b1, b2 and b3,

V = K(b1 + b2 + b3 /4)

This code conversion is the third feature of this second hybrid system.

Assume that, as shown in FIG. 36B, the coded signal b1 is displayed so that a1 becomes luminous at the first luminescent dot α1 for the time period Ta, and a4 becomes luminous at the second luminescent dot α2 for the period Ta/8, within one frame. The mean brightness, in terms of time, is given as

B1 = K1 (a1 Ta + a4 Ta/8) = K'1 (a1 + a4 /8)

where K1 and K'1 are constants. This is the brightness proportional to the quaternary value b1. The same code conversion is made for b2 and b3.

The code signals b1, b2 and b3 which are modulated in terms of time width and displayed in four levels are displayed by applying sustaining voltages at frequencies f, f/2 and f/4, respectively. In this display, the timewise mean brightness B is

B = K2 (b1 f + b2 f/2 + b3 /4) = K'2 (b1 + b2 /2 + b3 /4)

where K2 and K'2 are constants.

From Eqs. (1a) through (3a) it is evident that the brightness of the specific picture element is proportional to the video signal which is binary coded in 6 bits, and that a halftone display in 64 levels can be obtained. This is the fundamental principle of the second hybrid system. According to the invention, no flicker will appear in the display on a 3-frame one cycle basis if the frame period is sufficiently short.

Table 7 below shows how often luminescence occurs for a halftone display in 64 levels quantized by 6-bit pure binary coding. The reference Ta indicates a turn-on period, A is the number of turn-ons when a sustaining voltage VC of frequency f is applied, H is the occurrence of luminescence and L represents no luminescence. ##EQU2##

α1 H H H 111111 63/32 A α2 H H H α1 H H H 111110 62/32A α2 H H L α1 H H H 111101 61/32 A α2 H L H α1 H H H 111100 60/32 A α2 H L L . α1 L L L 000011 3/32 A α2 L H H α1 L L L 000010 2/32 A α2 L H L α1 L L L 000001 1/32 A α2 L L H α1 L L L 000000 0 α2 L L L __________________________________________________________________________

Generally, according to this second system, one picture element comprises a group of m luminescent dots 1, 2,..., m, and the video signal V is coded as follows over one cycle comprising consecutive frames, by using (m + n) weights u1, u2, ..., um and w1, w2, ..., wn.

______________________________________ V = K (a11 u1 + a12 u2 + ... + a1 mum)w. sub.1 + ( a21 u1 + a22 u2 + ... + a2 mum)w2 + ... + ( am1 u1 + an2 u2 + ... + an mum)wm ______________________________________

where a11, a12, ..., anm are of a value 1 or 0, and K is a conversion constant. Thus, in the j-th frame (j = 1, 2, ..., n), the picture element where ajk = 1 is given a turn-on period proportional to the weight uk (k = 1,2, ..., m) whereby the frequency fj of the sustaining voltage applied for this period is proportional to the weight wj.

A specific example of ths second system will now be described by referring to FIG. 37. First, a means for generating the sustaining voltage VC will be described.

In FIG. 37, the reference numeral 510 indicates a timing circuit which receives through terminal 101 the horizontal synchronous signal SH of a known television signal. Triggered by this horizontal synchronous signal, the timing circuit 510 generates timing signals Sx, Sy1, Sy2, Sy3, p1, p2 and q of the waveforms indicted by B1 through B6 in FIG. 38. The signal Sx determines the timing and the width of the sustaining voltage Vcx which is applied to the x drive line group on the panel 1. The signals Sy1, Sy2 and Sy3 determine the timing of the sustaining voltage Vcy which is applied to the y drive line group. The signals p1 and p2 determine the timing of turn-on pulses Vpx and Vpy, respectively, and the signal q is the timing signal for the turn-off pulse VQ. In FIG. 38, waveform A denotes the horizontal synchronous signal SH, which may be provided by the use of a monostable multivibrator in combination with counters of known types. The timing signal Sx is applied in parallel to the terminal S of the X drive circuit 543 comprising NH X switch circuits equal to the number of picture elements displayed on one horizontal scanning liine. As a result, the X drive circuit 543 generates the sustaining voltage Vcx with the waveform shown by Sx, which is applied to all the x drive lines. The construction of the X switch circuit wlll be described in more detail hereinafter in conjunction with FIG. 39.

The panel 1 has 2NV y drive lines and NH x drive lines wherein one picture element comprises two luminescent dots located at the intersections formed by a pair of y drive lines and one x drive line. For example, the i-th picture element on the line k will be considered. This pciture element comprises two luminescent dots 1 and 2 located at the intersections of a pair of y drive lines yk1 and yk2 with one x drive line Xi. Hence, the y drive lines are to be scanned pair by pair.

A sustaining voltage controlled by the signals Sy1, Sy2 and Sy3 is applied to the y drive line group in the regions I, II and III, respectively, of FIG. 36. The frame counter 563 used in this example is a senary counter which receives through terminal 102 the vertical synchronous signal SV of a usual television signal and generates frame signals F1, F2, F3, F'1, F'2 and F'3 switched at each vertical synchronous signal SV. The first gate circuit 551 gates the timing signals Sy1, Sy2 and Sy3 by the frame signals according to the logic shown below in Table 8, and generates outputs g1 and g2.

TABLE 8 ______________________________________ Frame F1 F2 F3 F'1 F'2 F'3 Input to Memory 540A a1 a2 a3 a1 a2 a3 Register 540B a4 a5 a6 a4 a5 a6 (Gate 552 Input to Y g1 S y1 S y1 S y3 S y3 S y2 S y2 Drive Gate g2 S y3 S y2 S y2 S y1 S y1 S y3 (Gate 551) Output of Y Scanning 0 1 0 1 0 1 0 Circuit (III) (I) (II) (III) (I) (II) (III) (Region) ______________________________________

For example, in the frame F1, the signal g1 is Sy1 and g2 is Sy3. The frame signals F1, F3 and F'2 produced in the frame counter 563 are supplied to the first Y scanning circuit 530A comprising a shift register with (NV + 1) bits (NV = the number of y drive lines of the y drive line group, i.e., the number of scanning lines to be displayed) and shifted to the horizontal synchronous signal SH which serves as the shift clock. Accordingly, 1 is set in the outputs of the individual stages of the Y scanning circuit in ascending order in the frames F1, F3 and F'2 and 0 is set likewise in the frames F2, F'1 and F'3. For example, at tk, i.e., at the end of the scanning of the line k in the first frame F1, the outputs of the first, second, ..., k-th stages are 1 and those of the (k + 1)-th, ..., (NV + 1)-th stages are 0. Therefore, by the outputs of the scanning circuit 530A, the regions (See FIG. 36) can be designated.

The Y gate circuit 532 gates the timing signals g1 and g2 by the outputs of the Y scanning circuit 530A. The resultant sustaining timing signal is applied to each of the terminals S of NV Y switch circuits which constitute the Y drive circuit 533. An example of this Y gate circuit, together with the Y switch circuit, will later be described in detail by referring to FIG. 40. In short, the Y gate circuit generates the signal g1 when the output of the corresponding stage of the Y scanning circuit is 1, or g2 when it is 0. These signals g1 and g2 are supplied to the Y switch circuit. As described above, the signals g1 and g2 are switched according to the frame as shown in Table 8. Hence the sustaining voltage Vcy applied to the y drive line group from the Y drive circuit 533 will assume waveforms Sy1, Sy2 and Sy3 in the regions I, II and III, respectively. For example, at tk, in the first frames F1 and F'1 m the y drive lines Y1, Y2, ..., Yk belong to region I and are driven by the sustaining voltage of waveform Sy1, and the y drive lines Yk+1, Yk+2, ..., Yy belong to region II and are driven by the sustaining voltage of waveform Sy2. In other words, the individual picture elements are driven by different Y sustaining voltages according to the regions to which the picture elements belong. Thus, in region I, the picture element is driven in the waveforms Sx and Sy1. In the region II, it is driven in the waveforms Sx and Sy2. The net sustaining voltages applied to the individual picture elements are of waveforms indicated by C1, C2 and C3, respectively, in FIG. 38. Of the sustaining voltages applied to the picture elements in the individual regions, a pair of positive and negative voltages which contribute to luminescence during one horizontal scanning period are as follows:

The pair Sx and Sy1 contribute to luminescence for 4 cycles in region I.

The pair Sx and Sy2 contribute to luminescence for 2 cycles in region II.

The pair Sx and Sy3 contribute to luminescence for 1 cycle in region III.

In this manner, it is apparent that the three scanning regions I, II and III are driven by the sustaining voltages with frequencies in the ration of 1, 1/2 and 1/4, as has been described in connection with FIG. 36.

The signal coding and the turn-on means using the coded signals will now be described. In FIG. 37, the video signal V from a terminal 100 is sampled at each clock 561 provided from a clock source 560 and coded into 6 bit binary signals a1 through a6, which are delivered in parallel in the following manner, through a second gate circuit 552 which is controlled by the output of a frame counter 563 as shown in Table 8:

The signals a1 and a4 are selected in the first frames F1 and F'1.

The signals a2 and a5 are selected in the second frames F2 and F'2.

The signals a3 and a6 are selected in the third frames F3 and F'3.

These circuits may be formed of known logic circuits and therefore their description need not be given.

The coded signals a1, a2 and a3 selected by the gate circuit 552 are supplied to the X memory registers 540A and 540B by way of a delay circuit 556 with a delay time Ta/8. The other signals a4, a5 and a6 are supplied directly to the X memory registers 540A and 540B. These X memory registers comprise shift registers each having NH bits and operated by a shift clock 561. When the clock frequency fC is set at FC = fH NH /(1 -α) where fH is the horizontal scanning frequency, and α is the rate of horizontal blanking period, then the signal of the picture element to be displayed on a specific line is stored in the X memory registers. The signals stored therein are transferred to X drive registers 541A and 541B each having NH bits, upon arrival of the horizontal synchronous signal SH. Therefore, at the time tk, i.e., at the end of the scanning of the line k in the first frame F1, the signal a1 is set in the register 541A and the signal a2 is set in the register 541B.

The X gate circuit 542 gates the foregoing timing signals p1 and p2 by the outputs of the X drive registers 541A and 541B. the gated signal or the turn-on signal, is supplied to the terminal W of each of the X switch circuits which constitute the X drive circuit 543. More details of the X gate circuit and X switch circuit will be described hereinafter by referring to FIG. 39. The turn-on pulse Vpx from the X drive circuit 543 will be superimposed on the X sustaining voltage and applied to the corresponding x drive line for the picture element on line k in the following manner:

In the first frames F1 and F'1, it is applied at the time p1 when a1 = 1, or at the time p2 when a4 = 1.

In the second frames F2 and F'2, it is applied at the time p1 when a2 = 1, or at the time p2 when a5 = 1.

The third frames F3 and F'3, it is applied at the time p1 when a3 = 1, or at the time p2 when a6 = 1. These turn-on pulses are applied in parallel to the corresponding x drive lines.

The scanning of y drive lines is performed in the following manner. As previously described, the Y scanning circuit 530A is operated so that, for example, the outputs of the first to k-th stages are 1 and those of the (k + 1)-th to (NV + 1)-th stages are 0 at tk in the first frame F1. The Y gate circuit 532 detects the boundary between 1 and 0 and gates the timing signals p1 and p2 in the boundary stage k and sends the first and second turn-on pulses to the Y drive circuit 533 in a manner as will be described hereinafter by referring to FIG. 40. By these turn-on signals generated to tk, the switch circuits which constitute the drive circuit generate turn-on pulses to be applied to the k-th pair of y drive lines yk1 and yk2 at the time p1 and p2, respectively.

The second and third Y scanning circuits 530B and 530C are made up of shift registers each having NV bits and operated by shifting by the horizontal synchronous signal SH. By the gate circuit 535A, the second Y scanning circuit 530B has its first bit set at 1 when the first Y scanning circuit 530A has proceeded to the m-th stage. The third Y scanning circuit 530C has its first bit set at 1 by the gate circuit 535B when the second scanning circuit 530B has proceeded to the m/8-th stage. (Note: The value m is equal to fH Ta, and m/8 is an integer). In other words, the outputs of the individual stages of the second and third scanning circuits 530B and 530C become 1 with delays of Ta (= m/fH) and Ta/ 8 (=m/8fH), respectively, after those of the corresponding stages of the first Y scanning circuit 530A. The outputs of these Y scanning circuits are supplied to the Y gate circuit 532. As will be described later by reference to FIG. 40, the Y gate circuit gates the timing signal q by the outputs of the scanning circuits 530B and 530C, whereby the first and second turn-off signals are generated. As a result, the switch circuits of the Y drive circuit generate turn-off pulses to be applied to the k-th pair of y drive lines at the time q of tk+m and tk+m/8. The value of the turn-off pulse is so determined that all the luminescent dots on a specific y drive line may be turned off when such a turn-off pulse is applied to the y drive line.

Since the x drive lines are driven as described above, the luminescent dots α1 and α2 which constitute the picture element on the line k are turned on or off in the following manner. At tk :

the luminescent dot α1 is turned on at the time p1 when a1 = 1; and α2 at the time p2 when a4 = 1, in the first frames F1 and F'1 ;

the luminescent dot α1 is turned on at the time p1 when a2 = 1; and α2 at the time p2 when a5 = 1, in the second frames F2 and F'2 ;

the luminescent dot α1 is turned on at the time p1 when a3 = 1; and α2 at the time p2 when a6 = 1, in the third frames F3 and F'3.

Also,

the luminescent dot α1 is turned off at the time q of tk+m in each frame;

the luminescent dot α2 is turned off at the time q of tk+m/8 in each frame.

Because the luminescent dots are driven by the sustaining voltage at different frequencies according to the region as described previously, the 4-level coded signal b1 = a1 + a4 /8 is displayed at the frequency f in the first frame. Similarly, in the second and third frames, the coded signals b2 and b3 are displayed at the frequencies f/2 and f/4, respectively, with the result that a halftone display in 64 levels is realized according to the principle illustrated in FIG. 36.

The operation of the switch circuits which constitute the drive circuit, and the gate circuit which controls these circuits will now be described by referring to FIG. 39 which is a circuit diagrarm showing X drive circuit 543 comprising X switch circuits and an X gate circuit, and to FIG. 40 which is a circuit diagram showing a Y drive circuit comprising Y switch circuits and a Y gate circuit. In FIG. 39, the symbols S and W represent sustaining and turn-on timing signal input terminals, respectively, D represents an output terminal connected to the x drive lines on the panel, and ES and EWX represent power terminals connected to the power sources capable of supplying voltages whose amplitudes are nearly the same as those of the sustaining voltage VCX and turn-on pulses VPX, respectively. When the input signal Sx to the terminal S is 0, (i.e., a low input) the input is inverted by an inverter 543-1 to cause a transistor 543-2 to be turned on and a transistor 543-4 to be turned off. As a result, the output D is kept nearly zero by the transistor 543-2 via a diode 543-5. When the input signal Sx to the terminal S is 1 (i.e., a high input), the transistor 543-2 is turned off, and a transistor 543-4 which is driven through a transformer 543-3 is turned on. As a result, the output D increases positively to a value near ES. This shows that a sustaining voltage whose amplitude ES can be generated at the output terminal D by the input to the terminal S. When the input to the terminal W is 1, a transistor 543-8 is turned on through a buffer 543-6 and a transformer 543-7. Consequently, the output D increases negatively to a value near EWX. When the input to the terminal W is 0, the transistor 543-8 is off. In other words, a turn-on pulse VPX can be generated by being superimposed on the sustaining voltage by the input to the terminal W. Because the inputs to the two terminals S and W cannot be 1 simultaneously, the transistors 543-4 and 543-8 will not be turned on simultaneously. The X gate circuit belonging to the X switch circuit applies a turn-on timing signal to the terminal W of the switch circuit when the outputs of the corresponding stages of the X drive registers 541A and 541B are 1 whereby the turn-on pulse is controlled according to the foregoing coded video signals a1 through a6.

In the Y switch circuit shown in FIG. 40, the symbols S, W and E denote sustaining, turn-on and turn-off timing signal input terminals, respectively, D denotes an output terminal connected to the y drive lines on the panel, and ES, EW and EE denote power terminals connected to power sources capable of supplying voltages whose amplitudes are the same as those of the sustaining voltage VCY, turn-on pulse VPY, and turn-off pulse VQ.

When the input to the terminals S is 1, a transistor 533-3A is turned on through a buffer 533-1A and a transformer 533-2A, and a transistor 533-6 is turned off through an OR circuit 533-4 and an inverter 533-5. As a result, the output D increases positively to a value near ES. This occurs when the input to the terminal W or E is 1. The reference numerals 533-1B and 533-1C represent buffers similar to 533-1A. Also, 533-2B and 533-2C denote transformers similar to 533-2A. Also provided are transistors 533-3B and 533-3C which are similar to the transistor 533-3A. When the inputs to the terminals S, W and E are all 0, the transistor 533-6 is turned on whereby the output at the terminal D is kept near zero. According to the invention, therefore, the sustaining voltage VCY, turn-on pulse VPY and turn-off pulse VQ can be generated at the output terminal D by applying a sustaining timing signal, a turn-on timing signal, and a turn-off timing signal to the terminals S, W and E, respectively.

In the Y gate circuit belonging to the Y switch circuit shown in FIG. 40, the gate circuits 532-1A, 532-1B, and 532-C operate to supply the signal g1 to the corresponding switch circuits k1 and k2 at terminal S when the output of the k-th stage of the Y scanning circuit 530A is 1, or the signal g2 to the corresponding switch circuit when the output thereof is 0.

If the output of k-th stage of the scanning circuit 530A differs from that of the (k + 1)-th stage thereof, the timing signal p1 is gated through a binary OR circuit 532-2 and a gate circuit 532-3A, and the gated signal is applied to the terminal W of the switch circuit k1. At the same time, the timing signal p2 is gated through a gate circuit 532-3B and the gated signal is applied to the terminal W of the switch circuit k2. Also, the timing signal q is gated through gate circuits 532-4A, 532-4B and 532-4C when the outputs of the k-th stages of the scanning circuits 530B and 530C are 1 whereby a turn-off signal is generated to be applied to the switch circuits k1 and k2 at terminal E. This causes the Y drive circuit to generate a sustaining voltage, as well as turn-on and turn-off pulses at the necessary times, which are applied to the y drive lines.

In the foregoing example, the invention is applied to a plasma display panel which is presently in wide use. It is apparent that the invention is readily applicable to other display panels having bistable states. Also, in the above example, the pure binary coding is employed. Instead, other suitable binary coding may be used, such as 1-2-2-4 with weights.

Furthermore, the system of the present invention has been described in relation to the operation wherein one cycle of the sustaining voltage is effected at its lowest frequency during the horizontal scanning period for turn-on and turn-off control. Instead, several cycles thereof may be used at its lowest frequency, which will not detract from any advantages of the system of the invention.

In the foregoing example, a 2-bit time width modulation is made within one frame, and the display within one frame may be arbitrarily selected. Also, the combination of bits in each frame may be suitably determined. An example wherein luminous elements which constitute one picture element are disposed in the Y direction has been described above. Instead of this arrangement, they may be arranted in the X direction, or by the pair in the X and Y directions.

In the above example, the scanning is performed frame by frame without interlace. If interlace is employed, the display is effected on a one-field/one-frame basis. It is evident that the invention can duly be applied to a display controlled under interlaced scanning. It is noted that the video signal is supposed to be reproduced either by interlaced scanning wherein each field is to construct one frame and thus one complete picture is built with two frames, or by scanning wherein two fields are to construct substantially the same picture with half the number of scanning lines.

Although specific embodiments of the invention have been disclosed herein in detail, it is to be understood that this is for the purpose of illustrating the invention, and should not be construed as necessarily limiting the scope of the invention, since it is apparent that many changes can be made to the disclosed examples by those skilled in the art to suit particular applications.

Accordingly, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described herein.