Television character crawl display method and apparatus
United States Patent 3891792

A method and apparatus for superimposing printed characters of any such nature as may be transmitted upon a received television image, at the will of the viewer at the receiver. The character information is incrementally transmitted during the vertical blanking interval of the television scanning format. The receiver is especially constructed to have a dynamic shift register, also means to manually select one or none of plural character programs; such as news, stock market, or weather. The characters may be made to crawl horizontally to present an extended message, which crawl may be halted by the viewer. The mandatory display of emergency messages is possible by a control located at the transmitter.

Application Number:
Publication Date:
Filing Date:
Primary Class:
Other Classes:
315/367, 345/636, 348/467, 348/468, 348/564, 348/E7.033, 348/E7.035
International Classes:
G09G5/34; H04N7/088; (IPC1-7): G08B5/36
Field of Search:
340/324A,324AD 315
View Patent Images:

Primary Examiner:
Trafton, David L.
Attorney, Agent or Firm:
Lubcke, Harry R.
I claim

1. The method of displaying characters upon a television screen in addition to displaying a television image, which includes the steps of;

2. The method of claim 1 which additionally includes;

3. The method of claim 1 in which;

4. The method of claim 1 in which;

5. The method of claim 1, which additionally includes;

6. The method of claim 2, which additionally includes;

7. The method of claim 6 in which said temporarily storing step includes;

8. The method of claim 1, which additionally includes;

9. The method of claim 8 in which;

10. Apparatus for displaying characters upon image display means in addition to displaying a television image thereon, comprising;

11. The apparatus of claim 10, in which said second means includes;

12. The apparatus of claim 10, in which said third means includes;

13. The apparatus of claim 10, in which said fourth means includes;

14. The apparatus of claim 10, in which said fifth means includes;

15. The apparatus of claim 10, in which said sixth means includes;

16. The apparatus of claim 10, in which;

17. The apparatus of claim 10, in which;


This invention relates to multiple images upon a television display tube.

At times the prior art has provided multiple images on a television display tube, usually a traveling line of alpha-numeric type at the bottom of a television image. The purpose has been to present news flashes without interrupting the television program in progress. Such a line of characters has been transmitted as an integral part of the video signal forming the image and has been displayed upon all receivers without choice or recourse by the viewer.

In such systems the receivers are not modified. Additional required apparatus is provided wholly at the transmitter.

In other systems where a choice has been possible by the viewer, the prior art has required a memory at the receiver in which alphanumeric characters are usually stored, to be called-out for display by a code signal received from the transmitter. Oriental languages contain about 2,500 characters instead of the about 60 alpha-numeric characters of the western languages. Thus, the code-memory at the receiver system is impractical for anything other than the storage of under 100 characters.

Certain other apparatus has been provided by the prior art for displaying plural stock market tapes, but without the combination with a television image. This is a simple technique, in that exact correlation between the timing of the television image scanning and the process for superimposing a message is not required.

Still other apparatus has employed delay lines for temporary storage. A code was used to key-out characters from a receiver memory.


This invention provides a selected one of a plurality of elongated area character messages, or none, superimposed upon the image of a television receiver, at the option of the viewer at the receiver. This is accomplished by providing additional apparatus and manual controls at the television receiver. A mandatory display of emergency messages is also possible and this is under the exclusive control of the transmitter.

At the transmitter, digital logic, including a clock generator, plural registers and memories for each character pattern, memories for message, counters, and decoders from the character signals. These are incrementally transmitted during successive vertical blanking intervals of the known television image signal (video). The character signal itself directly provides the information required for the display at the receiver.

At the receiver, in addition to the known television circuits, there is provided digital logic, including a character signal data extractor, buffer registers, character element counters, and a large dynamic shift register. These are interconnected by suitable gates and flip-flops. A video data mixer reinserts the characters signal into the video channel, this signal having been read-out of the shift register at a time to be displayed at a selectable vertical position on the television image display device to be seen by the viewer.

Manual controls at the receiver allow one of a plurality of character messages, or none, to be selected for viewing, also to stop the horizontal crawl of the message, if desired.

The characters displayed are formed by "low" - "high" electrical bit pulses supplied to the television image reproducing device. These are suitably timed to form the characters in synchronism with television scanning. These may be alpha-numeric in any language, Japanese or Chinese characters, or any suitable diagrams or representations.

A flag identifies the initiation of character data transmission and promotes simplified apparatus at the receiver.

Typically, all character data are transmitted, incrementally and successively, upon one line of horizontal television scanning during the vertical blanking interval.

A dynamic shift register temporarily stores thousands of bits that have been incrementally transmitted from the transmitter. These form in themselves the character display at the receiver.

Accordingly, permanent memory storage apparatus is not required at the receiver and the information required for the display is not drawn therefrom by merely a transmitted code. The method of operation of the system is thus widely removed from the conventional mode of operation.


FIG. 1 shows the face of a display tube with a representative display thereon and indications of other positions which the display of the line of characters may occupy.

FIG. 2 shows how the letter E is formed on the television raster by appropriately timed bit signals.

FIG. 3 shows the entire transmitter system block diagram.

FIG. 4 shows a segment diagram of a 91 bit shift register, as a simplified example.

FIG. 5A shows related shift pulse trains to the shift register.

FIG. 5B shows display element addresses on the television raster.

FIG. 6 shows the contents of the shift register shifted by 1 bit.

FIG. 7 shows the horizontal crawl sequence of sample letters A B C.

FIG. 8 is a waveform and channel allocation diagram for the 21 st horizontal line.

FIG. 9 is a schematic diagram of the transmitter character-signal forming logic.

FIG. 10 shows a detailed schematic diagram of u, w and W counters.

FIG. 11 is a block diagram of the receiver character-signal forming logic.

FIG. 12 shows a functional block diagram of a portion of the receiver system.

FIG. 13 shows a raster representation of the receiver functioning.

FIG. 14 is a representation of receiver system timing.

FIG. 15 is a further portion of the functional block diagram of the receiver system.

FIG. 16 is a schematic logic diagram of the receiver character-signal forming logic.

FIG. 17 is a schematic logic diagram of the apparatus for accomplishing "mandatory control".


FIG. 1 shows the television display for this system, including the timing relationship for the known television scanning from left to right and top to bottom, respectively, Numeral 1 shows a field started with a vertical drive signal and completed just before the vertical drive signal of the next field. Numeral 2 shows the frame of the raster and 3 indicates a significant part of the normal televised picture. Numeral 4 indicates a typical sub-raster, dimensioned as 16 lines per field, or a total of 32 lines for the full frame of the display system of this invention. Numeral 5 shows a typical superimposed font of this display system; i.e., the message "Electronic Display is popular".

Other positions, such as 7 and 7', are selectable for positions of the sub-raster.

The display normally crawls in the direction indicated by arrow 6. The letter E of the message starts to crawl from the right end of sub-raster 4 and travels to the left, where it is now shown.

The television image may be reproduced in color by the known television process. No interference between the display waveforms and the waveforms required for color television is experienced.

Numeral 8 shows the transmitted data signal, superimposed on the 21st horizontal line, just above the top of the raster frame 2. The exact nature and composition of this signal varies with the details of the message.

In FIG. 2, the capital E of the above illustrated message is identified by numeral 9. It is divided into a number of vertical columns, such as ten, as shown. Pattern data bits (PD bits) in the first (left) column 10 are 1, 1, 1, 1, 1, - - to a total of 12, from the top down to the bottom of this letter. Thereafter, 0, 0, 0, 0. This is sent in the first television scanning field.

In the same manner, the second column, 11, becomes 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, and this is sent on the second field. Continuing, the third column, 12, is sent on the third field, and so on; to the tenth column identified by numeral 13. These columns of PD bits are an important aspect of the system of this invention.

it will be noted that there are four 0 spaces at the bottom of each column on the E. This sets the bottom of that letter and others like it sufficiently far up in the sub-raster so that lower stems of certain small letters such as the p and y can be executed.


The block diagram of FIG. 3 gives the method and apparatus involved in adding the character display to known television transmitting apparatus.

Character coder 14 is the input originating device for coding a large number of characters, such as 2,500 Chinese characters. By pointing with a known light pen each character can be coded as a 6 bit × two frame, or a 12 bits code. The operator selects the character according to the sentence he is forming for transmission.

Sentence memory 15 is connected to character coder 14, for the storage of the coded data output from coder 14. These data are stored in address sequence. For the sending sequence the stored data in sentence memory 15 is read out in address sequence according to the time lapse for each letter covering the entire sentence.

At the end of the sentence memory 15 is programmed to address back to the beginning of the sentence.

The output of sentence memory 15 enters character pattern memory 16. The latter is a magnetic core memory, having a capacity of 131 K bytes. A total of 2,500 character patterns are stored therein, in a 16 × 16 array for each character. The core memory is segmented as 1,024 lines for the X axis, 64 lines for the Y axis, and 16 bits for the Z axis.

X address register 17 is connected to character pattern memory 16 as is x address counter 18. These select the 1,024 lines having to do with the X axis.

Y address register 19 is also connected to character pattern memory 16. This register selects 64 lines having to do with the Y axis, subsequent to the selection for the X axis.

Six bits × two frames of a character are assigned for the X and Y address registers, and its 16 columns for the x address counter 18.

Sixteen bits for the Z axis correspond to the vertical PD bit of each column.

In the address of the core memory that corresponds to the code of each character, the pattern for the character is previously stored.

Buffer register 20 is connected to the output of character pattern memory 16. The display is normally a horizontally crawling format and the coded characters from the sentence memory are converted into vertical column PD bits, 16 bits, and sent out for every field, V. Accordingly, x address counter 18 is set to zero at the beginning of the character and the PD bits in the left end of the character are read from the Z axis and temporarily stored in the 16 bits capacity buffer register 20. This register holds the data until a selected line, typically in the vertical blanking period of the television raster, such as the 21st television scanning line, 21H, occurs, and then the data are sent out serially on that line. At the same time x counter 18 is stepped up one, and the second vertical column PD bit is read out to be ready to be sent out on the following V 21 st line. In the same manner, one character is completed with 16 vertical PD bits upon 16 V periods having occurred.

The following two V intervals do not have an output from character memory 16, but sentence memory 15 is addressed out one step and the next letter code set in the X and Y registers. This two V interval becomes the space between characters. The above operation is then repeated in order to send out the entire sentence.

Encoder 21 is connected to the output of buffer register 20, and the encoder accomplishes the above process. The output of the encoder is connected to mixer 22.

Mixer 22 also receives an input from program-line 23, upon which typically a full color video signal flows. The output of the mixer is taken by the on-air-line 24 and thence to a television video transmitter, pay television cable, or other apparatus that conveys the full transmitter signal to receivers for viewing.


The previously mentioned column PD bits are extracted in the receiver, stored for accumulating a certain amount of data, processed for display and then displayed.

In order to simply explain the mode of receiver operation, a display area of 13 × 7 bits is chosen. A stored capacity of 91 bits is thus required. This is accomplished by shift register 30, shown in FIG. 4.

The input 31 of shift register 30 is switched to either new pattern data 33, or the output 34 of the shift register through recirculation line 35 by means of appropriate actuation of transfer switch 32.

The various segments 36 of shift register 30 begins at number 0, number 1, etc. from the upper-left output side of the register. They progress to number 90 at the lower-right input side of the register.

The output of the shift register 34 is fed to display means 37, which is shown as the known television cathode-ray tube. When the output of the register is high; i.e., a digital 1, then a white (bright) dot appears on the television screen and an elemental part of the character display is formed. When the output of the register is low; i.e., a digital 0, there is no contribution to the image television signal.

In FIG. 4 the data bits are given a designation corresponding to their position in the shift register. These start at the upper-left, output, end of the register with A1, then B1, C1 etc. to M1 in the top row in the illustrative example of this figure. Similarly, the second row starts with A2 and ends with M2; and so on, until the end of the last row is M7. Each of these designations may be a 1 or a 0, according to the data required to reproduce the characters of the message.

Going further, in FIG. 5A pulse train 38 is generated for the duration of one horizontal line, say the Kth line; kth H. It is fed into the clock pulse input of shift register 30 as the shift pulse.

In the recirculation mode, A1 is seen at the beginning of the kth H line. Shift pulse S1 is then added and B1 is shifted into the No. 0 segment of shift register 30. At the same time B1 is seen on display tube 37. Also, previous data bit A1 is fed back into the No. 90 segment via recirculation line 35 and data transfer switch 32. With the next shift pulse S2, C1 is seen on display tube 37.

In this manner, as shown in FIG. 5B, A1 through M1 are displayed on the kth H line, identified by numeral 39 in that figure, by the train of shift pulses S1 through S13. This occurs in synchronism with television scanning.

Then A2 is shifted with S13 and M1 is stored in segment No. 90, at the lower right in FIG. 4.

On the (k + 1) the H line, identified by numeral 40 in FIG. 5B, the same shift pulse train 38 of FIG. 5A is applied to shift register 30, and the same result occurs as has been explained for the k the H line. Similarly, this result occurs again for each of the lines shown in FIG. 5B, as the (k + 2) th H line - - - to the (k + 6) th H line, in this simplified example.

The contents of the shift register are displayed on the picture tube screen 41 of FIG. 5B. They appear as the desired characters in accordance with the initial data.

Shift register 30 in the recirculation mode can hold back the data to the same location as long as the number of shift pulses equals the shift register length.

In other words, data are displayed once in the scanning duration of the k th H through (k + 6) th H lines on screen 41 of the display device. As long as the data a recirculated back to the original segment location in the shift register 30 itself, the display is seen as a still display, having the formation of data A1 through M7 in FIG. 4.

Normally, when the chain of display of data A1 through M7 has been completed (hereinafter designated as the end of an "event") one additional shift pulse designated q is applied to shift register 30.

The content of data in the shift register shown in FIG. 4 becomes that shown in FIG. 6. It is seen that each datum has been shifted one segment location to the left, except the data segmented on No. 12, No. 25, No. 38, - - - No. 90. With one more pulse operation of the above these data will be displayed.

In the process heretofore outlined the previously displayed datum A1 is recirculated into No. 90 segment through data transfer switch 32, but now, at that particular moment switch 32 is turned to accept a new datum A7' (not A1'). In the same manner, new datum A1' is an input by the time 13 shift pulses have occurred. In this way the last datum is replaced and written by new datum A6'. As a result, the whole display is shifted 1 column bit to the left and the extreme right column of the display is refreshed with new data. By the continuation of this operation the character message is made to crawl from right to left.

Recapitulating, the sequence to accomplish the crawl operation is as follows:

1. display of the event,

2. insertion of the q pulse for each television field,

3. write new data for each field.

The order of the sequence does not affect the operation as a whole.

If the input to display tube 37 is gated off from the output 34 of the shift register the display disappears. However, the process of writing in new data can be accomplished independently of any display of it.

Crawl of the characters can be inhibited at the television transmitter by sending out the control signal of the q pulse insertion, because the q pulse is generated in the receiver. The speed of the crawl can also be decreased by controlling for less frequent insertion of the q pulse than normal. The display may also be "frozen"; i.e., the crawl stopped, by not inserting the q pulse to the shift register at the receiver.

A representation of how the crawl operation appears is given in FIG. 7. It shows a portion of the message characters ABC in the English alphabet. The top row 42 shows the data bits A1, B1, C1, - - - to M7 for all of the A and B and the first stroke of C. In the second row, 43, data bits A1', A2', A3' - - - A7' have been added and the display has moved one data position to the left of what is shown in the first row. The same process is repeated for the successively lower rows, 44, 45 and 46, and it is seen that the A has been reduced to a line and the C is now complete.


The illustrative simple embodiment heretofore employed to set forth the method and the major aspects of the apparatus is modified in ways as follows in order to become a full-scale device.

For characters of the Chinese type an area of 16 × 16 bits is typically employed. For English and other alphabet letters an area of 10 × 16 bits with a 2 bit spacing is considered proper for the display, in view of the size of the characters and the number of characters in one line.

Typical crawl speeds then become as follows. For Chinese characters the width of the area plus a spacing of 2 bits is a total of 18 bits. With 60 television fields per second and a 1 bit shift per field, as indicated in FIG. 7 the crawl speed for Chinese characters becomes 60/18 = 3.33 characters per second, and for alphabet characters becomes 60/12 = 5 characters per second.

A desirable vertical extent of pattern data bits includes 32 horizontal scanning lines over one frame; 16 in each field. Considering the aspect ratio of the character and the speed of television scanning, the clock frequency of the shift pulses may be altered to be twice that of the color sub-carrier, 3.58 megahertz (MHz), thus to be 7.16 MHz.

The formation of the sub-raster may typically require 16 × 250 bits =4096 bits storage capacity in the receiver. This provides the capability of displaying 14 Chinese characters or several words in English on one line.

There are numerous different vertical positions on the television viewing screen for the sub-raster which carries the character message. A net viewing raster typically contains 525 lines minus 2 × 21 lines for the vertical blanking. The sub-raster is 32 lines high in each frame. There are thus (525 - 21 × 2)/32 ≉ 15 bands available.

However, since it is common television practice to mask off all around the edge of the raster from the view of the observer, and since all possible positions for the sub-raster are not aesthetically desirable, about six positions are considered proper.

As will become further evident later, more than one message can be transmitted and utilized at the will of the viewer at the receiver. All messages are available at the receiver, and any one, or none, is selected by the viewer by manual control.

A typical number of separate messages is five; such as weather reports, stock market quotations, news, etc. These are all transceived over the 21st horizontal, H, line. A suitable clock frequency for this transceiving is half the color television sub-carrier frequency, or 1.76 megahertz. This allows a sufficient margin for the television video band-width.

In the widely used manner of regenerating synchronizing signals in a television receiver, often known as a.f.c. horizontal synchronization, these synchronizing signals are not precisely in phase with the synchronizing signals that are transmitted. Thus, the television picture reproduced at the receiver may shift slightly with respect to the cathode ray tube reproducer. It is not; however, distorted.

For transceiving character data, critical accuracy of phasing in this aspect is required. According to this invention an additional pulse known as the "initial flag" (pulse) is generated. It is timed to be, and is, inserted ahead of the series of character data transmission signals. It achieves the critial accuracy required at the receiver, so that the characters of the messages will be clearly formed. The complexity, and so the cost, of the receiver character handling apparatus is considerably simplified through the use of this pulse.


The timing relationships for accomplishing transmission of character data and the scheme involved are shown in FIGS. 8, 9, 10.

In FIG. 8, numeral 50 in a row, indicates the channel assignment of the various messages, such as weather, news, etc. This is on the 21 st horizontal line. This is a preferred line, being at the end of the vertical blanking period and thus devoid of the video signal forming the television image. In general, another horizontal line, or even lines, in the vicinity may be used, with understandable adjustment or minor modification of the apparatus involved in handling this part of the process.

As will be seen, line 50 is divided into seven channels; 0W, 1W, - - - 6W. All have 18 divisions at the period of 0.5587 microseconds, corresponding to the frequency of 1.79 megahertz, except channel 6W. The latter is of residual nature.

Channel 0W starts at the leading edge of the horizontal (H) syncronizing signal and holds until slightly over the termination of the horizontal blanking signal. Therefore, no character data signal can be assigned to channel 0W. However, the last portion of it, identified by numeral 51, is used as the initial flag pulse for the synchronization of the character data signal in the receiver.

Channels 1W through 5W are used for the allocation of the A, B, C, D and E roll character message data.

Channel 6W contains only 5.75 divisions instead of 18. It terminates at the leading edge of the next H synchronizing pulse, and this channel is not used for data transmission.

The diagram identified by numeral 52 shows the control bit region 1Wo, 2Wo, - - etc., which is formed of 2 bits, and the character data bit region 1W1, 2W1, - - - etc., which is formed of 16 bits.

The diagram identified by numeral 53 gives the detail of one channel. Therein, 54 is a spare (unused) bit, 55 is a freeze bit, and the inclusive 56 numeral indicates the pattern data bits.

If the freeze bit 55 is in the 1 state, the insertion of the q pulse on that field is inhibited in the receiver and the character display is frozen (not allowed to crawl) for that scanning field for that channel. When that is the case, data are not to be transmitted in that channel. Both the space bit and the freeze bit may be programmed to control additional modes of operation, besides the basic mode mentioned.

The waveform identified by numeral 57 in FIG. 8 gives details for the line 21st H. Initial flag pulse 58 is the detail of the indication 51 on the numeral 50 row. The variations inclusively indicated at 59 comprise the data of the No. 1 channel. These waveform variations are accomplished in buffer register 20 and encoder 21 of FIG. 3.


FIG. 9 shows the transmitter character-forming logic, notably buffer register 20 and encoder 21.

For simplification of explanation FIG. 9 has been drawn for positive logic, regardless of the conventional integrated circuit (IC) system of logic. That is, flip-flops and counters are enabled or cleared by the positive-going edge of the clock pulse or clear pulse. The outputs of gates are not inverted.

For reducing the influence of the frequency interleaving of the NTSC standards, the color sub-carrier frequency fs is frequency-doubled to 2fs=7.16 megahertz.

This frequency, at 60 in FIG. 9, is fed into u-counter 61, where it id divided 4 times, to fs2,= 1.79 MHz. This frequency, which is the clock frequency for the data transmission, is fed into following w-counter 62 and subsequently W-counter 63. These counters generate various timing pulses, shown at the top of each, as to the outputs.

The u-counter may be a dual J-K master-slave flip-flop, as the T.I. SN7473, and the W-counter and W-counter each a synchronous up-down 4 bit binary counter, as the T.I. SN74191.

As will be noted in FIG. 9, the clear CL terminal of counters 61, 62, 63 are connected to a 21H pulse from decoder 100. Accordingly, the outputs of these counters occur only on the 21st line of television scanning. From w-counter 62 and W-counter 63 the pulse trains indicated by row 52 in FIG. 8 are obtained.

This operation is understood in greater detail by reference to the actual circuit employed in an embodiment shown in FIG. 10.

Firstly, as WA holds in the 0 state, AND gate 64 is enabled by wB. This results in w-counter 62 being allowed to count two, stepped out to W-counter 63 through OR gate 65, and allows the WA output terminal to be high; i.e., a 1.

These two count divisions are timed to be in the control bit regions 0W, 1Wo, 2Wo, - - -, shown in row 52 of FIG. 8.

Secondly, when WA is in the 1 state, the output of AND gate 64 is ignored. Then w-counter 62 is enabled to count the full 16 divisions.

The zero-return pulse is applied to W-counter 63 via OR gate 65. Then WA is returned to 0 and WB is counted up by one.

The 16 bit divisions referred to above correspond to the pattern data bit region shown in row 52 in FIG. 8 and detailed at 56 in row 53. These are denoted as 0W1 1W1, 2W1 - - -. A 2-16 division pulse train combination is formed and WB, WC, WD count to allocate the channel number. Actually, any data is not assigned for channel 0W.

The above structure has been symbolized in a simple manner for w-counter 62 and W-counter 63 in FIG. 9.

In FIG. 9 the five buffer registers 66 through 70 constitute the buffer memory for the pattern data bits being read out of the character pattern memory 16 of FIG. 3. In FIG. 3 only one such buffer register 20 was shown for simplification purposes. FIG. 9 has been drawn for five message channels; thus, the five buffer registers 66 through 70.

The process of data input to the registers is handled by means of a minicomputer or equivalent means so that it occurs at some other time during the scanning cycle of television than during the 21st horizontal line; i.e., 21st H. The data are successively fed to the data input terminals 71 through 75 for the five registers. The clock pulses required to load these data into the registers are fed into the data-in clock terminals 81 through 85 by external means of operation.

On the other hand, "conjugate" clock pulses required to read out ("pop-up") the data on the 21st H line are fed into the same clock terminals of the buffer registers 66 through 70 from decoder 86. This alternate manner of feeding is accomplished through the use of OR gates 76 through 80, respectively. Decoder 86 may be a BCD-to-decimal T.I. SN7442.

The manner in which the data are read out are as follows.

The data in buffer register 66 are read out at the time corresponding to the pattern data region 56 of channel No. 1. This coincides to the 1W1 state of W-counter 63.

The data in buffer register 67 are read out at the time corresponding to the data region of channel No. 2. This coincides to the 2W1 state of W-counter 63.

The same is repeated in sequence for channels 3, 4, 5; the latter involving buffer register 70 at time 5W1 of W-counter 63. Refer to row 52 of FIG. 8.

Recapitulating, decoder 86 feeds five packages of 16 clock pulses to five buffers, respectively. Then the five outputs of the buffer registers are selected in synchronism with W-counter 63 by means of data selector 88, to which they are connected. Data selector 88 may be an 8 bit data selector, such as the T.I. SN74151.

In decoder 86, one out of 8 outputs; 0, 1, 2, - - - 7, is selected at the required time by the binary code connected to terminals A, B, and C. Terminal D acts commonly to turn off all of the outputs. Outputs WB, WC and WD from W-counter 63 are connected to terminals A, B and C of decoder 86 in order to select channels 1 through 5. The clock pulse of 1.79 MHz and output WA from W-counter 63 are fed to the D terminal of decoder 86 through AND gate 87.

Accordingly, output terminal 1 of decoder 86 bursts a group of 16 clock pulses during the 1W1 period of row 52 of FIG. 8.

Next, output terminal 2 of the decoder bursts 16 clock pulses during the 2W1 period; and similarly for the remaining terminals 3, 4 and 5.

Thus, the data signals of each buffer register 66 through 70 are drawn out in sequence.

Data selector 88 operates as follows.

Data input terminals 1 througn 5 are driven by the output of buffer registers 66 through 70, as has been mentioned. The binary select terminals A, B, C of selector 88 and the strobe terminal S are driven by the WB, WC, WD and WA outputs of W-counter 63, respectively. Output terminal Y of selector 88 feeds out the data sequentially. Thus, the read-out contents of the buffer registers are arranged in sequence to match the channel assignment.

It has been previously described that the initial flag pulse 51 of FIG. 8 has been positioned in the last division of 0W1.

In order to generate this pulse the output of 4-input AND gate 89 in FIG. 9 is connected to the outputs wA, wB, wC and wD from w-counter 62. These are then ANDed through the gate, the output of which is connected to data input terminal 0 of data selector 88. The ANDed form of wA, wB, wC, wD, which is (wA. wB. wC. wD), corresponds to the last division of 0W1 and numeral 51 in FIG. 8. It is selected in the data region of 0 channel.

The output Y of data selector 88 includes the initial flag pulse and the whole of the pattern data bits for five channels.

Freeze bit 55 of FIG. 8 is normally in the 0 state for the ordinary crawl operation, but if the display is to be frozen, then the freeze bit is mandated to be stored in the buffer memory prior to the 21st H line.

In FIG. 9 the five flip-flops 90 through 94 are provided for storing the freeze bits for the five channels.

As previously explained with respect to the operation of the data bits, the loading process of the freeze bit is controlled by a minicomputer or similar apparatus. The freeze bit is reset at the No. 6 channel by the output of two-input AND gate 95, by an input of WC and WD.

Each of flip-flops 90 through 94 may be a dual D-type edge-triggered flip-flop, such as the T.I. SN7474.

The freeze bit data selection is accomplished in the same manner as the pattern data bits were selected. In the freeze bit case the data selector involved in 96. The strobe terminal S thereof is fed by the output of two-input AND gate 97, with a WA and wA input. (WA, is, of course, the inverted polarity of the WA pulse). The WA and wA pulses corespond to the freeze bit position.

The Y output of data selector 96 is combined with the output of data selector 88 by two-input OR gate 98 by the necessary interconnection of these devices as shown in FIG. 9. The line output of this OR gate is the signal to be transmitted, having the pattern data bits and the control bits bursting only during the 21st H. line. This output is connected to mixer 22 in FIG. 3, for mixing with video.

The 21st H line is selected by h-counter 99 and decoder 100 that is connected thereto. The counter is cleared by the vertical drive pulse from the television scanning operation. This is indicated at the V.D. terminal in FIG. 9, which connects to the CL terminal of h-counter 99.

However, it is known that the V.D. pulse has a duration extending from the 1st H to the 9th H. Thus, counter 99 is held in the "clear" state for this time and starts to count from the 10th H.

The output terminal 11 of decoder 100 corresponds to 21st H and is used to enable counter 62 and 63. To prevent output terminal 11 being activated after the 21st H repeatedly in the same field, the output signal of terminal 14 of decoder 100 is inverted to inhibit the insertion of H synchronizing signal to h-counter through AND gate 102.

The output signal of terminal 12 of decoder 100 is used for a "done" (completed) signal to a minicomputer and associated apparatus to prepare for the next sequence.


The block diagram of FIG. 11 shows the elements of what may be a known super-heterodyne color televison receiver plus the additional elements to give the character display according to this invention.

Television receiving antenna 120, radio-frequency tuner unit 121 and intermediate frequency amplifier 122 are conventional. Block 123 is similar, and may contain the video detector, sync. signal separator, and color circuits such as the color burst separator and regenerator for providing a continuous color subcarrier that is locked to the incoming color burst from the transmitter. Modern receivers are transistorized and may use integrated circuits (ICs); thus, the exact location of some circuits may not fall within the illustrative blocks that have been shown.

Video amplifier 124: the luminance television signal is amplified and the chrominance signal is also processed. These drive display means 125, typically a color television cathode-ray tube, upon which the television image is reproduced, also the characters, when desired.

Of the other outputs from block 123, that on conductor 126 carries an amplified and sliced luminance signal. That on conductor 127 is a frequency-doubled color subcarrier, having a frequency of 7.16 MHz. That on conductor 128 are the horizontal, H, and vertical, V, synchonizing signals associated with television deflection.

Video amplifier 124 is constituted to accept signals from display gate 190 at its terminal 124' and to combine these with the original picture signal that comes in from block 123.

In Fig. 11 the blocks 130 to 190 (each ending in zero) represent the apparatus to be added to the receiver to provide the character display according to this invention.

In order to accomplish the digital character display the television raster is considered to be addressed both horizontally and vertically. Thus, two address counters are provided, one for the longitudinal and one for the latitudinal directions.

The former is block 130. It is clocked by the 7.16 MHz frequency input 127 and is reset by the horizontal synchronizing signal, H, 128.

The latter is block 140. It is clocked by the H synchronizing signal and is reset by the V synchronizing signal.

Both counters address over the scanned raster and provide the various timing signals corresponding to the addresses.

Channel selector 150 accepts the incoming luminance signal 126 and address signals from blocks 130 and 140. It discriminates initial flag pulse 215 (FIG. 13) from luminance signal 126. It also establishes the precise timing coincidence for the transceiving relationship through the role of the initial flag pulse.

Channel select switch 129 is connected to the channel selector and extracts one of the plural channels which supply digital data upon the 21st horizontal line.

Block 160 accepts the luminance signal 126 as the input. Block 160 is composed of two buffer registers. One is a 16 bit buffer register for the pattern data bits and it is loaded at the selected moment of the channel involved over the 21st H line. At a later time this shift register discharges its contents to a following shift register 180 in synchronism with appropriate shift pulses.

The other buffer register is a flip-flop and is concerned with the q pulse. It functions in essentially the same manner as the 16 bit buffer register, except that it has a smaller bit length.

A 256 shift pulse generator 170 is controlled by address signals from 130 and 140. The output of 170 feeds 256 shift pulses to shift register 180.

Shift register 180, having peripheral items of apparatus, is the large-scale shift register for the receiver. This shift register stores the incoming pattern data, typically 4096 bits. Of these, 16 bits are rewritten for every television field. The contents of this shift register are displayed by recirculation.

Display gate 190 functions to control the position of the character display, as 4, 7, etc. in FIG. 1; also, to display or not-display as controlled by message on-off switch 190'. As previously mentioned, the output of gate 190 is fed to terminal 124' of video amplifier 124 to effect superimposition of the character message upon the television image.


FIGS. 12 and 15 are functional block diagrams of receiver details and FIG. 16 is a schematic logic diagram of the receiver charactersignal forming logic.

In FIG. 12, longitudinal counter 130 is indicated by the dotted rectangle and it is composed of 2 bit u-counter 132, 4 bit w-counter 133 and 4 bit W-counter 134. These are all reset by H synchronizing signal on line 135 into OR gate 136, and also by the trailing edge of initial flag upon line 137 via OR gate 136.

The incoming 7.16 MHz signal, terminal 131, is fed to u-counter 132 and there is divided down to 1.79 MHz. The 1.79 MHz signal is fed from there to w-counter 133 as a clock pulse.

The longitudinal counter 130 may be formed from a dual J-K master-slave flip-flop TI SN7473 for the u-counter, for the w-counter a synchronous up-down 4 bit binary counter TI SN74191, and the same for the W-counter.

The w-counter 133 and W-counter 134 generate seven channel timings with the formation of 2-16 pulse train combination, each at a 1.79 MHz rate, in the same manner as was previously stated in respect to FIG. 10, but in this case both counters are enabled over the whole raster.

The seven channels are denoted as 0W, 1W, - - - and 6W on the W-counter state and the pulse trains in each channel are 0w, 1w, 0w, 1w, - - - 15w on the w-counter and WA state.

Latitudinal counter 140, FIG. 12, if formed of 4 bit counters; h-counter 142, and B-counter 143, as well as decoder 145. These counters are reset by the V synchronizing signal, introduced at 144 to the CL terminals, and they start to count at the trailing edge of the V synchronizing signal. The h-counter 142 is clocked by the H synchronizing signal at 141, and counts 0h, 1h, - - - and 15h in binary.

The connected, following B-counter is clocked by the most significant bit of h-counter 142, and counts 0B, 1B, - - - 15B in binary. These are decoded to decimal by decoder 145. At the output, B stands for band.

As a result, the whole raster is addressed as shown in FIG. 13 and any positions designated on the raster are translated into the code introduced by these counters according to FIG. 13.

Further in FIG. 13, numeral 201 designates the leading edge of H synchronizing signal as reproduced in the receiver, 202 is the horizontal, H, blanking period, 203 is the vertical, V, synchronizing signal, 204 is the vertical, V, blanking period, and 205 is the raster in the actual embodiment.

Horizontal strip 206 identifies the longitudinal address concerned with character dsiplay information and vertical strip 207 identifies the latitudinal address.

The nos. of line 208 locates where the corresponding horizontal lines are located on the raster, so that the relation between the character format and the raster becomes known. The regenerated vertical, V, synchronizing signal is taken as occupying the time and space between 4th H to 7th H. The latitudinal counters are held in the clear state during this 4 H interval.

The h-counter 142 and the B-counter 143 in FIG. 12 start to count at the 8th H horizontal line, but the B-counter is held in the 0 state through 8th H to 23rd H, until the h-counter counts 16 H lines.

Until the next V synchronizing signal appears, B-counter 143 counts over and automatically returns to the 0 state. This zero state is shown at 209 in FIG. 13.

The following calculations are pertinent:

525 lines / 2 - 4 lines = 258.5 lines

258.5 lines - 162 lines = 2.5 lines

Hence the 0 state involves 2H lines or 3H lines, depending upon even or odd fields.

In principle, the duration of the 0 state is calculated from the next relation.

525 lines / 2 - 162 lines = 6.5 lines

but 162 lines involve 16 lines of the 0 state, so

6.5 lines + 16 lines = 22.5 lines

22 lines or 23 lines are obtained for the 0 state regardless of the width of the V sync signal.

Also, the width of the V sync must not be over 6.5 lines.

In the example of FIG. 13 sub-raster 210 lies in latitudinal address 3 B, and starts at horizontal position 2, identified by numeral 211.

Horizontal position 1 is identified by numeral 212 and has to do with window mask 214.

In the upper part of FIG. 13 the detail set forth for channel 3W also applies to channel 1W, etc. Therein, position 2 occupies internal position 12w in channel 1W1 and position 1 occupies internal position 2w in channel 1W1.

Data transmission from buffer register 160 to shift register 180 is accomplished at the time of longitudinal position 2 and latitudinal position 2B. This is shown in FIG. 13 at 213.

A window masking 214 is provided over the upper-left hand portion of the raster. It starts at the starting tip of the leading edge of the horizontal, H, synchronizing signal and ends at position 1, 212. Vertically, it terminates at the end of the 0B band.

This window is used to certify that initial flag pulse 215 is the first incoming white signal within the area of the window, for the whole raster. Consequently, any signals within the vertical blanking interval 204 are ignored unless the signals are lead with the white signal over the window mask area 214. Of course, the known "vertical interval test signal, VITS" is excepted, and functions as usual in the known color television practice.

If a white signal with a certain amplitude level appears within window 214, this verifies that this signal is the initial flag pulse. Then data following this initial flag are those transmitted for this system and that horizontal line containing such data is certain to be the 21st H line.

The initial flag pulse is used to actuate receiver apparatus as follows.

In FIG. 12 dotted rectangle 150 is the channel selector. It is formed of several components. Window signal generator 151, which is enabled over window signal mask area 214, receives inputs corresponding to latitudinal band OB, the H sync horizontal synchronization pulse, and the longitudinally significant position 1 212.

Two-input AND gate 152 receives an input from window signal generator 151 and from luminance signal line 153. The latter is thus checked to determine whether or not it contains the initial flag pulse.

Flip-flop 1, 154, is set at terminal CP by the output of AND gate 152 and is cleared at terminal CL by the V sync vertical synchronization pulse. The output of flip-flop 1 is differentiated by differentiator 155 and is fed therefrom to set flip-flop 2, 156, at the CP terminal. Flip-flop 2 is cleared at terminal CL by the H sync horizontal synchronization pulse.

The output of differentiator 155 is also fed, through conductor 137, to the CL terminals of the three counters 132, 133 and 134 through OR gate 136.

Window signal generator 151, and flip-flops 154 and 156 may be dual J-K master-slave flip-flops, such as the TI SN7473.

In the foregoing configuration of apparatus, if a signal appears at the output of AND gate 152, it is the initial flag pulse. The trailing edge thereof sets flip-flop 1, 154, which causes flip-flop 2, 156, to consequently be set. As flip-flop 1 is cleared by the V sync signal, this flip-flop is frozen until the next V sync signal arrives. This flip-flop thus shuts out the luminance signal after the initial flag pulse is received and sends no signal to flip-flop 2 over the V sync period.

Flip-flop 2, 156, is cleared by every H sync signal, and so is immediately reset by the next H sync signal. It is held in the reset state until the next initial flag pulse arrives. It is thus activated for the period starting by the initial flag pulse and ending at the end of the 21st H horizontal line.

Because of the connection 137 previously described, upon the moment of activation of flip-flop 1, 154, counters 132, 133 and 134 are reset once; but the output of differentiator 155 is momentary and so the counters immediately start to count. However, the composition of the counting on line 21st H is different from that on other horizontal lines.

Referring to FIG. 14, waveform 250 is that for 21st H. Horizontal diagram 251 gives the composition of the 21st H horizontal line for W-counter 134. Horizontal diagram 252 gives further details of this composition. Horizontal diagram 253 gives the ordinary composition for other horizontal lines.

For horizontal lines other than the 21st H, W-counter 134 is cleared by H sync signal 135, through OR gate 136, and commences to count 0W, 1W, - - - 6W, as shown at 253 in FIG. 14.

For horizontal line 21st H, having the initial flag pulse, W-counter 134 is cleared by the H sync signal as usual. It commences to count from 0W as is to be noted at 255 on diagram 251, but near the end of 0W the W-counter is reset again by output upon conductor 137 from differentiator 155. The W-counter then again commences to count at the reset moment another 0W as shown at 256.

The reproduction of the H sync signal in the receiver may be uncertain. This may cause the first 0W sequence 255 not to contain 18 divisions of the 1.79 MHz frequency. Therefore, the role of initial flag pulse 215 handles the situation.

Referring again to FIG. 12, the output of flip-flop 2, element 156, is activated precisely at the beginning of the second 0W 256 and to the end of the 21st H line. This output is fed to the strobe terminal of the connected data selector 157. This may be an 8 bit data selector, such as the TI SN74151.

The data input as 0, 1, 2, 3, and 4, are selected by channel select switch 158. In the same way as with transmitter data selector 88 of FIG. 9, binary data select terminals A, B and C are driven by WB, WC AND WD of W-counter 134.

The output of the data selector, at 159, is selected to be exactly 0W, 1W - - - 4W for the respective channels according to the position of channel select switch 158.

In FIG. 15 there is shown the detail of buffer register 160. Sixteen bit buffer register 161 is for handling the pattern data bits. This register may be embodied by combining two 8 bit shift registers, such as the TI SN7491A, in series.

The input terminal in of the register is connected to incoming luminance signal at 126. The clock pulse terminal CP is driven by the output of OR gate 164.

As described previously, the shift register is enabled to be loaded or to pop-up the data only upon clock pulses being provided. In this case, two kinds of shift pulses are required, one kind is for loading and the other kind is for the "hop-up" of the data.

The clock pulse for loading is formed by three-input AND gate 162. The three inputs are the outputs from data selector 157, from WA of W-counter 134, and from the 1.79 MHz output of u-counter 132. Output 159 from data selector 157 enters the top input 163 and is the selected channel timing. The WA signal extracts the data region of the channel involved. The 1.79 MHz input is the clock pulse.

The output of gate 162 is connected to the clock pulse terminal, CP, of buffer register 161 through OR gate 164. It is a 16 pulse train bursted at the data region of the selected channel over the field.

At that time luminance signal 126, representing the pattern data of that channel is fed to the in input terminal of buffer register 161 and the 16 pattern data bits are loaded into that register.

The clock pulse for the hop-up of the data is PH. 2B, which is the product of the most significant bit of P-counter 172 and the 2B band from decoder 145 of FIG. 12. This clock pulse passes through OR gate 164 to the clock pulse terminal CP of buffer register 161 by the wiring shown in FIG. 15.

The trailing edge of clock pulse PH. 2B is shown as 216 in FIG. 13. At that instant buffer register 161 hops-up its data to feed the same into shift register 182. At the same time the buffer register is loaded with the undesired data of the luminance signal, but these data are swept away at the next normal loading period for the register.

J-K flip-flop 165 may be one unit of a dual J-K master-slave flip flop, such as the TI SN7475. The J input IN is driven by the incoming luminance signal 126. The K input is grounded. The clock pulse terminal CP is driven by the output of three-input AND gate 166.

The three inputs to AND gate 166 are; the output from data selector 157 (via 163), WA from W-counter 134, and wA from w-counter 133, both of FIG. 12.

The data which control the insertion of the q pulse in that field are loaded to J-K flip-flop 165. The output thereof enters AND gate 168 and acts as the control thereof. Timing signal 167 determines the exact time that the q pulse is inserted by being the second input to the AND gate. The output of AND gate 168 is fed to OR gate 185 as the q pulse.

Also in FIG. 15, the detail of 256 shift pulse generator block 170 is given. Flip-flop 3, 171, has the capability of start-stop functioning. It may be one section of a dual J-K master-slave flip-flop, such as the TI SN7473.

P-counter 172 may be two synchronous 4-bit binary counters, such as two TI SN74193 connected in series.

The Q output of flip-flop 3 is fed to the clear terminal CL of the P-counter, with the provision of Q be in the 1 state to clear the P-counter. The carry output thereof is fed back to clear flip-flop 3 at the CL terminal, via conductor 173.

With this configuration, as the clock pulse input of flip-flop 3 is driven at the position 2, shown as 211 in FIG. 13, flip-flop 3 starts at position 2 on every horizontal line. This releases P-counter 172 from the clear state. The P-counter then commences to count with the 7.16 MHz input to terminal CP. Then the carry output mentioned in the paragraph above occurs and resets flip-flop 3. In this duration P-counter may count 256 divisions of clock pulse. This repeatedly holds P-counter 172 in the clear state.

The 256 division duration of the 7.16 MHz clock rate is 35.759 microseconds. Flip-flop 3 starts at position 2 and continues for this duration within each horizontal, H, line. Thus, flip-flop 3 determines the longitudinal dimension of sub-raster 210 in FIG. 13, and this is precisely the duration of 256 shift pulses on every H line.

The timing generation for the new data-in is accomplished by AND gate 174 and flip-flop 4, 175.

A position 2 timing signal ranged within the 2B band is composed by impressing these two inputs upon AND gate 174. The output thereof is fed to the CP input of flip-flop 4. This flip-flop may be one unit of a dual J-K master-slave flip-flop, such as the TI SN7473. Flip-flop 4 starts at the timing of position 2 and then is immediately reset by the least significant bit (LSB) of P-counter 172, denoted as the PA terminal in FIG. 15.

Flip-flop 4 is active on only one division of the position 2 of 2B band. This is shown by numeral 213 in FIG. 13. This output is used to control the transfer switch of the shift register for the entry of new data.

In FIG. 15 the details of shift register and peripherals 180 of FIG. 11 are given.

Numeral 181 identifies a data transfer switch, which is controlled by the output of flip-flop 4. When in the upper contact position, new data is toggled to shift register 182, and when the switch is in the lower contact position the stored data in shift register 182 is recirculated through it.

Shift register 182 has a larger capacity, such as 4096 bits. It may be embodied by using four 1024 bit dynamic recirculation shift registers manufactured by Intel as item 2405. This item includes data transfer switch 181 built-in, in semiconductor form. The shift register may alternately be embodied by using four similar registers manufactured by Texas Instruments as item TI TMS3514, with transfer switch circuit.

For example, it is assumed that the entrance of new data to shift register 182 is accomplished during the 2B vertical band, and the display in the 3B band.

Inputs 2B and 3B are ORed with OR gate 183, and the output fed to AND gate 184. This three-input gate also accepts the Q output of fip-flop 3, 171, and the 7.16 Mhz clock pulse. The resultant output of AND gate 184 generates 256 pulse trains bursted on every horizontal, H, line within the range of the 2B and 3B bands.

This output is connected to the lower clock input terminal of shift register 182 through two-input OR gate 185. The other input to this OR gate is the q pulse output of AND gate 168.

Since the 2B and 3B bands each include 16 horizontal, H, lines; 256 divisions times 16 H lines = 4096 clock pulses, which are applied to shift register 182 during each of these bands. The 4096 bit shift register accomplishes perfect circulation sequences in each of these bands.

In the entry of new data, transfer switch 181 is toggled to the newdata-in side only for the one division moment of position 2, 211, on every H line of the 2B band, shown as 213 in FIG. 13. At that moment the data stored in buffer register 161 are entered into shift register 182 only by the very first pulse of the 256 pulse train group on that particular H line.

On the other hand, PH. 2B is ORed with the output of AND gate 162 and is applied to the clock pulse terminal CP of buffer register 161. This is so that the leading or trailing edge of PH, the most significant bit of P-counter 172, may become the transition for buffer register 161, to prepare the next data leading to the transfer switch in that line. The trailing edges are shown by 216 in FIG. 13. By repeating the same procedure for the 16 horizontal, H, lines of the 2B band, all of the data stored in buffer register 161 are transferred to shift register 182.

In FIG. 15 the details of display gate 190 are given. It is principally a four-input AND gate 191. One input thereof is the output of shift register 182. Another is the Q output from flip-flop 3, which dimensions the longitude of the sub-raster. Another is 3B, which determines the vertical position of the display and is derived from the corresponding output terminal of the decoder connected to the B-counter in FIG. 16. Another is the character message ON-OFF switch 192. This is manually operated by the viewer.

The output of this gate, conductor 193, is the desired resultant of the entire character system. It is fed to the superimpose terminal 124' of video amplifier 124 of FIG. 11.

An embodiment of the actual schematic diagram of the receiver character-signal forming logic is given in FIG. 16.

For purposes of simplification FIG. 16 is illustrated as a positive logic system, regardless of what would be conventional.

The following aspects should be compared with respect to the description already given above for FIGS. 11, 12 and 15.

1. The insertion of the q pulse

2. The clock pulse to shift register 180

3. The selection of the display position

4. The freeze (stopping of crawling.

Items of apparatus having previously been illustrated carry the same identifying numerals as previously used.

Certain aspects are similar to the transmitter character-forming logic, given in FIGS. 9 and 10.

The alternate embodiment for accomplishing "mandatory control" of the character-forming apparatus at the receiver is shown by the modification according to FIG. 17.

As has been previously explained, for this case the control bits include both a space bit and a freeze bit. This allows four states by utilizing the ordinary binary code. For example, these may be programmed so that state 0 is for freezing (causing the character display to remain motionless), state 1 is for crawling (the horizontal traverse of an extended message across the image raster of the television display device 125), state 2 imposes mandatory control, and state 3 is for releasing the mandatory state.

The space bit and the freeze bit are transceived by the same means as data bit, are extracted from the television image information, and are stored in a two bit shift register at the receiver.

These are decoded by decoder 401 in FIG. 17 into 0, 1, 2 and 3 outputs.

Flip-flop FF-5, element 402 in FIG. 17, establishes the mandatory state. It is set by output 2 of decoder 401 and is reset by output 3 of the same.

The Q terminal of FF-5 is fed to one input terminal of OR gate 403. Freeze switch 308, previously described, is fed to the other input terminal of the OR gate. The switch is normally in control, according to the will of the viewer, but while a mandatory control signal is being sent from the transmitter the freeze operation is inhibited and the full mandatory message is displayed. Typically, the mandatory message and anti-freeze state is carried by all of the several message channels that are available according to this invention.

Outputs 1 and 2 of decoder 401 are ORed in OR gate 404, the output of which is connected to one input of AND gate 405 to be the q pulse instead of the usual arrangement for providing this pulse; i.e., the signal ANDed by inverted luminance signal WA, 303, and wA, 304, in AND gate 311 in FIG. 16.

Further, this mandatory control arrangement causes the mandatory message to be displayed even though the display On-Off switch has been set to off by the viewer.

To accomplish this the display On-Off switch is ORed with the Q output of FF-5, 402. A Q output over-rides the effect of the switch. Through OR gate 406 the appropriate state is fed to display gate 307, which is shown with its other connections in FIG. 16 and fragmentarily in this regard in FIG. 17.

While reset terminal of FF-5 is connected to output terminal 3 of decoder 401 in FIG. 17, reset may be accomplished. But in some application, reset may be done by 10th H for example, instead of the output terminal 3 of decoder 401.

Reference has been made to a "minicomputer" herein. This is a known simple control entity, which accomplishes reading from sentence memory 15, FIG. 3, reading from character pattern memory 16 with that data, and sends out the data bits obtained therefrom into buffer register 20. It also accomplishes the data-in operation to sentence memory 15, letter by letter from character coder 14.