Title:
CHARACTER DISPLAY SYSTEM WITH TABBING FUNCTION
United States Patent 3816823


Abstract:
A character display system with tabulation facilities includes a display device such as a cathode-ray tube wherein signal codes representing characters are translated to signals for writing the characters along a line on the face of the cathode-ray tube. The signal codes are sequentially translated and transferred to the cathode-ray tube. During the course of this sequential operation tab indicator signals are generated to interrupt the operation until tab positions indicator signals which are related to particular positions along the display line are sensed.



Inventors:
MANBER S
Application Number:
05/293011
Publication Date:
06/11/1974
Filing Date:
09/28/1972
Assignee:
REDACTRON CORP,US
Primary Class:
Other Classes:
178/15, 345/27, 396/550, 400/279
International Classes:
G09G1/00; G09G5/22; (IPC1-7): G06F3/14
Field of Search:
340/324A,324AD 178
View Patent Images:
US Patent References:
3582736BRUSHLESS SYNCHRONOUS MOTOR CONTROL SYSTEM1971-06-01Kite et al.
3559208N/A1971-01-26DiGuigno et al.
3292154Display apparatus1966-12-13Simmons



Primary Examiner:
Caldwell, John W.
Assistant Examiner:
Curtis, Marshall M.
Attorney, Agent or Firm:
Hane, Baxley & Spiecens
Claims:
What is claimed is

1. A character display system comprising: a display device which displays a line of characters in response to serially received signal codes associated with the characters, said display device including a display medium, a source of a beam which when impinging on the display medium changes its visual state at the point of impingement, means for driving the beam to sweep across the display medium at a uniform speed, and means for intensity modulating the beam during the sweep; and means for controlling the positioning of the characters along the line of the display comprising storing means for storing signal codes representing the characters to be displayed along the line, said storing means being a multiposition storage device for storing signal codes wherein certain of the positions store signal codes representing the characters to be displayed and at least one position stores a signal code representing a tab operation, transmitting means for sequentially transmitting the stored signal codes from said means to said display device in the order in which the characters are to be displayed along the line, tabbing means for generating a tab indicator signal during the transmission of said signal codes to said display device, said tabbing means including means for detecting the transmission of the tab operation signal code from said storing means to then generate a tab indicator signal, position indicating means for generating at least one tab position signal, said position indicating means including a multicell storage device wherein each cell is associated with a particular position on a display line for storing representations of tab position indicating signals and means for sequentially interrogating the cells in synchronism with the sweeps of said record medium by said beam, means for interrupting the transmission of signal codes whenever a tab indicator signal is generated until the subsequent generation of a tab position signal, and means for controlling changing the contents of the cells of said multicell storage device.

2. The system of claim 1 wherein said storing means includes a multiposition shift register means for storing signal codes representing the characters in the order they are to be displayed and at least one signal code representing a tab operation in one of the positions, and means for regularly shifting said shift register means at a uniform speed under the control of said interrupting means.

3. The system of claim 1 wherein said display device includes signal code translating means for translating the signal codes representing characters to signals for controlling the beam according to patterns related to the associated characters.

4. The system of claim 3 wherein said interrupting means controls the operation of said translating means.

5. The system of claim 1 wherein said display device includes a cathode-ray tube.

6. The system of claim 1 wherein said multicell storage device comprises a shift register means, and means for stepping said shift register means in synchronism with the sweeps of said record medium by said beam.

Description:
THE INVENTION

This invention pertains to character display systems and more particularly to such systems which include facilities for automatically performing tabulation operations.

Character display systems are becoming more and more prevalent. As their cost comes down they are being applied to more uses. As the market for these systems expands, the users are demanding more versatile systems.

One particular use concerns displaying stored information to determine its format and content before printing a hard copy. This information can take many forms. If the information is concerned with tables of figures or uniquely positioned characters along lines of text, complex programs and routines must control the flow of characters from the source to the display device. These programs generally pad the character flow with blank or space symbols to accomplish the tabulations. While such a technique works it is complex and puts an added load onto the processor which feeds the display device.

In addition, the interactive systems wherein the viewer is provided with the facility to edit the information stored in the processor after viewing the display, there is always the problem of misregistrations in the subsequent displays and hard copy output unless very complex safeguards are added to the processor programs.

It is accordingly a general object of the invention to provide an improved character display system with simple tabulation facilities.

It is another object of the invention to provide such a system which permits the simple presentation of tabulated information.

It is a further object of the invention to provide such a system wherein versatile tabulations are performed using a minimum of added hardware and software in the system.

Other objects, the features and advantages of the invention will be apparent from the following detailed description when read with the accompanying drawing which shows by way of example and not limitation apparatus for implementing the invention, while the invention is defined in the appended claims.

In the drawing:

FIG. 1 is a block diagram of a character display system according to the invention;

FIG. 2 is a logic diagram of the tab control of the system of FIG. 1; and

FIG. 3 is a logic diagram of the write clock of FIG. 1.

Before describing the display apparatus, the assumed display format will be discussed. The displayed material will be horizontal lines of text on the screen of a cathode-ray tube which is driven in a conventional line-raster scan. Each line of text will start at the same left hand margin, except for controlled indentations or tabulations. Each line will have no more than a fixed number of characters or alphanumerics. Each alphanumeric will be represented by a 5×7 matrix of dots with a space allotment to one side of the alphanumeric. The possible five dots of any given row of the matrix for each alphanumeric of a line to be displayed, will be written during the same horizontal scan. Seven contiguous sequential scans will be required to write all seven rows of the matrix while the equivalent of about the next two possible horizontal scans of the raster will be blank to provide the space between lines of text. While a cathode-ray tube system is being assumed it should be realized that other raster type display systems such as electrostatic ink jet systems or laser systems could be used.

Generally, the bytes (signal codes) representing the alphanumerics of a line of text will be transmitted from a store to an end-around shift register. When the shift register has been loaded, a horizontal sync pulse is generated to start the first horizontal scan for that line of text. An indication associated with this first horizontal scan and the byte of the first alphanumeric at the output of the shift register are used by a translator to select and generate the dot signals of the top row of this alphanumeric which are loaded in parallel into a five-bit shift register.

A write clock then generates five shift pulses at the appropriate time to feed the dot signals of the row to the intensity or "video" input of the cathode-ray tube system. The end-around shift register is then shifted one place to present the next byte for translation. This process continues until the last alphanumeric has been translated for the first time. At this point, the top row of dots of each alphanumeric has been displayed. Another horizontal sync pulse is generated and the process is repeated for the second row. This time the translator receives the bytes and an indication associated with the second horizontal scan. This process continues for a total of seven such horizontal scans so that all seven rows of the dot signals for all the alphanumerics of the first line of text are displayed. Then there is a pause to provide a vertical space before the next line of text is displayed. During this pause the bytes of this next line of text are transferred to the end-around shift register. This second line of text is displayed in the same manner as the first but vertically downward displaced therefrom.

Embedded in the character bytes stored in the shift register are control bytes. For example, when a tabulation or tab is to be performed before the display of a character a tab control byte preceeds the byte of that character. When the control byte is sensed, byte shifting and character display are interrupted until the next possible tab position is reached in the horizontal scan when a signal is generated to restart the byte shifting and display. This signal is generated by a tab position indicator means comprising another shift register which stores indications of the possible tab positions along the scan lines and operates in synchronism with the sweeps of the horizontal raster lines.

Another control byte stored in the first shift register is the start of line control byte to indicate the start of a line of characters.

FIG. 1 shows a system utilizing positive logic for performing these operations. The system includes a store STR which can be a miniprocessor and memory which stores all the bytes representing the text to be displayed as well as the above-mentioned control bytes. Assume the bytes to be coded combinations of seven bits. Store STR transmits these seven bits in parallel to seven line cable C1. In addition, store STR when transmitting a byte will emit a shift pulse on line SP to an input of OR-circuit B1. In parallel therewith, or after such transfer, store STR transmits onto line L1 a series of tab bits representing tab positions along a display line and for each bit emits a shift pulse on line ST or OR-circuit B2. The number of bits transferred equals the number of possible tab positions (say 70) on a display line. High or 1 bits will represent the desired tab positions which are "set", and low or 0 bits represent spaces between tab positions which are not "set". Furthermore, at the start of each "page" of text to be displayed store STR emits a vertical sync pulse onto line V, and at the start of each line of text to be displayed it emits a pulse onto line HS and a clear pulse on line CL. Finally, store STR can receive pulses from line EOL indicating that a line of text has been displayed so that it can initiate the transfer of the information for the next line.

The bytes from store STR are received by byte code shift register BSR which can be seven parallel end-around shift registers, say, 70 bits long, i.e., the maximum number of alphanumerics that can be displayed on a line. The bytes from store STR are received at inputs T1 and transmitted from outputs EX onto seven-line cable C2 as seven bits in parallel. Seven-line cable C3 feeds the bytes back to inputs T2 to provide the end-around shifting facility. Pulses received at shift input SF from the output of OR-circuit B1 cause the shifting of the bytes.

The tab bits from store STR are received by tab shift register TSR which is a single end-around shift register 70 bit positions long. The bits received from line L1 and input T1 are transmitted from output EX onto line L2. Line L3 feeds the bits back to input T2 to provide the end-around shifting facility. Pulses received at shift input SF from the output of OR-circuit B2 cause the shifting of the bits.

Decoder DEC connected to cable C4 generates a signal on line TAB whenever a tab control byte is sensed, and generates a signal on line SOS whenever a start-of-line control byte is sensed. The decoder can comprise two seven-input AND-circuits with some of the inputs including inverters according to the signal codes for the control bytes.

Tab control TCC hereinafter more fully described emits 70 shift pulses onto line TS which are fed to the second input of OR-circuit B2 in response to each signal on line H and then emits a signal on line EOS. Tab control TCC also emits a signal on line SCN starting shortly after the receipt of the signal on line H and ending with the signal on line EOS.

The count of the number of horizontal scans per line of text is performed by row shift register SR1, a seven-bit long shift register which is cleared to a bit only in its first stage upon receipt of a pulse on line HS and is shifted one position each time it receives a pulse at shift input SF from line EOS. During such shifting, shift register SR1 successively transmits signals on lines H0, H1, H2, . . . H6, and EOL. The pulses on lines H0 to H6, connected to translator TRL, are used to select the seven rows of dot signals. The signal on line EOL, connected to store STR, is used to indicate the entire line has been displayed. Note, that although a shift register has been used to count and record the number of horizontal scans associated with a line of text, one could equally use a modulo-7 counter.

Translator TRL can comprise a read only memory. Each register of the memory can comprise five bits of storage, related to a particular row of the matrix of a particular character. A register is selected by means of the byte received from the outputs EX of byte code shift register BSR via seven-line cables C2 and C5 (associated with the alphanumeric to be displayed) and a signal on one of the line H0 to H6 (associated with the particular row of dots then to be displayed), whenever the translator TRL cannot select a register its outputs effectively transmit no signals. The contents of the selected register are read in parallel, via lines R0 to R4 and AND-circuits A0 to A4, respectively, into shift register SR2.

Shift register SR2 can be a conventional five-bit shift register wherein the five stages are loaded in parallel from AND-circuits A0 to A4 while shift pulses received at shift input SF connected to line BS sequentially shift the contents out onto line VID. In order to count the number of shifts and to indicate when five shifts has occurred, there is provided five-bit shift register SR3 whose shift pulse input SF is connected to line BS and whose output is connected to line RE. A pre-setting input is connected to line LR such that upon receipt of a pulse therefrom, the first stage is set to a 1 bit and the four remaining stages set to 0 bits. In this way, after the register has been pre-set and five shift pulses occur, a pulse will be emitted onto line RE. Of course, shift register SR3 can be replaced by a modulo-5 counter which is cleared by a pulse on line LR and emits a pulse onto line RE after counting five pulses from line BS.

The shift pulses on line BS are generated by write clock WC, hereinafter more fully described in detail. For the present, one needs to know that write clock WC controllably emits bursts of five shift pulses generally in response to pulses on line RE, i.e., a pulse on line RE results in a burst of five shift pulses on line BS preceded by pulse on line LR which is preceded by a pulse on line CS.

These pulse groups are generally free running once a horizontal scan is started in response to a signal on line HS from store STR at the start of each line to be displayed or on line EOS from tab control TCC at the end of each horizontal scan. However, whenever a tabulation is called for as indicated by a signal on line TAB from decoder DEC, pulse group generation is stalled until a signal is received via line TBS from tab shift register TSR.

Cathode-ray tube system CRT can be a conventional CRT display having horizontal and vertical circuits connected respectively, to line H and V for generating the horizontal and vertical deflection signals, to control the sweep of the electron beam, and video circuits connected to line VID for intensity modulating the electron beam.

The operation of the system of FIG. 1 will now be described. After the store STR transmits signals on line CL to initialize all registers and flip-flops it transmits a pulse of line V to cathode ray tube system CRT as a vertical sync pulse; it transmits the bytes of the first line of text to be displayed to byte shift register BSR; it transmits the tab position bits to tab shift register TSR; and then transmits a pulse on line HS to write clock WC and to the pre-set input of shift register SR1. The bytes of each line of text are prefixed by a start-of-line control byte and interspaced with control bytes. It will be assumed that this first line of text is the start of a paragraph which must be indented five spaces and that the 20th character is to be displayed in the 50th position on the line. Therefore, a tab control byte follows the start-of-line control byte which is followed by nineteen character bytes. Then comes another tab control byte followed by the 20th and succeeding character bytes for the line. Note the number of succeeding character bytes in the shift register is limited by the number of available display positions. In this case, since there is a maximum of 70 and the succeeding characters start at position 51 there can be only a maximum of nineteen more characters displayed on the line.

In the tab shift register TSR, the sixth and 50th positions will contain 1 bits while all other positions will contain 0 bits. Shift register SR1 is set to its first stage and starts generating a signal on line H0 associated with the first row of dot matrices. White clock WC immediately transmits a pulse on line H which is received by cathode-ray tube system CRT as a horizontal sync pulse, which is received by tab control TCC and which is received at the set input S of flip-flop F1. The setting of flip-flop F1 activates clock CK (a gated oscillator) to emit shift pulses via OR-circuit B1 to the shift pulse input of shift register BSR which starts shifting until the start-of-line control byte is at its outputs EX. This byte is sensed by decoder DEC which transmits a signal on line SOS to the reset input R of flip-flop F1 which resets and shuts off clock CK. In this way, variable length lines of text can start at the same left margin since the shifting occurs during the horizontal retrace time.

The signal on line H received by tab control TCC, after a time delay related to the retrace time starts emitting shift pulses onto line TS to shift the tab bits in tab shift register TSR and transmits a signal on line SCN to allow operation of write clock WC.

The write clock WC transmits a pulse via line CS, AND-circuit A5 and OR-circuit B1 to the shift input of byte code shift register BSR. (In addition the write clock generates pulses on lines LR and BS which will have no significant effect at this time.) When shift register BSR shifts, it will present a tab control byte to its output EX which is sensed by decoder DEC to cause the generation of tab signal on line TAB. This signal when present prevents variable clock WC from generating any pulse signals on lines LR, BS and CS. Now it should be realized that the cathode-ray tube is scanning a line and tab shift register TSR is shifting in response to shift pulses on line TS from tab control TCC. Thus the electron beam is moving to the right. When the tab shift register has shifted five places, the first 1 bit is transmitted from output EX of tab shift register TSR via lines L2 and TBS to write clock WC cancelling the effect of the signal on line TAB so that the write clock WC resumes operation. Thus, write clock WC transmits a pulse via line CS, AND-circuit circuit A5 and OR-circuit B1 to the shift pulse input SF of shift register BSR causing the first alphanumeric byte to be transmitted from its output to translator TRL. This byte cooperates with the signal on line H0 in translator TRL to select the dot signals for the first (top row) of the dot matrix for the alphanumeric associated with this byte. The dot signals are fed in parallel via lines R0 to R4 to inputs of AND-circuits A0 to A4, respectively. Then, write clock WC emits a pulse on line LR which gates the dot signals (bits) into shift register SR2 and sets a 1 into the first stage of shift register SR3. Thereafter, write clock WC transmits five shift pulses to both shift registers. The dot signals are shifted onto line VID and into the cathode-ray tube system CRT to generate the dots for the first row of the matrix for the first symbol of the line. Note because of operation of the signal on lines TAB and TBS these dots are written five character positions to the right of the start of the scan line. Following the fifth shift pulse, shift registers SR2 and SR3 are empty with the bit in register SR3 fed via line RE to write clock WC. After a delay, write clock WC transmits another pulse on line CS resulting in a shift in shift register BSR and the second byte is presented for translation in the same manner as the first byte. The dot signals for the first row of the second byte are gated into the shift register SR2 by another pulse on line LR which also loads the 1 bit into the first stage of shift register SR3. Another five shift pulses are generated and the dots of the first row of the second alphanumeric symbols are displayed. This process continues until decoder DEC detects the second tab control byte after the nineteenth character byte. At that time another signal is generated on line TAB which stalls the write clock WC until the tab shift register TSR has reached its fiftieth shift. At that time it transmits a pulse on line TBS to permit the write clock WC to again free run as described above and the top rows of the remaining characters are written. Finally, after the seventieth shift pulse generated by tab control TCC, the end of the first line scan has been reached. This is indicated by the generation of a signal on line EOS and the termination of the signal on line SCN. The signal on line EOS steps shift register SR1 which starts transmitting a signal on line H1 associated with the second row of the dot matrices. The signal on line EOS is received by write clock WC which responds to it in the same manner as the receipt of a signal on line HS, i.e., by generating the signal on line H. The alignment shifting in end-around shift register BSR is performed. Note, since tab shift register TSR is seventy places long and has been shifted seventy times it is again in registration with the scan line. The signal on line H fed to cathode-ray tube system CRT triggers the horizontal circuits therein into the retrace phase and after a period of time starts the next horizontal scan. In addition, the H signal is fed to tab control TCC which after a period of time related to the duration of the retrace phase again generates a signal on line SCN to permit the operation of the write clock WC which generates a pulse on line CS to start the display of the second rows of dot signals. These second rows of dot signals are transmitted to cathode-ray tube system CRT in the same manner as the first rows, as described above. The third, fourth, fifth, sixth and seventh rows are similarly generated. After the seventh row has been displayed, shift register SR1 transmits a signal on line EOL which is fed to store STR to indicate that the whole line of text has been displayed. In addition, the signal on line EOL blocks AND-gate A5 to prevent any shifting in shift register BSR.

In order to display the second line of text, store STR must load the new line into shift register BSR and transmit a pulse on line HS. Thereafter, the system operates as described above except that because the vertical deflection is still operating and no new vertical sync pulse is generated, the second line is displayed below the first line.

Tab control TCC of FIG. 2 includes a delay one shot D1 (a one shot multivibrator which when triggered generates a negative going pulse having a duration related to the horizontal retrace time of the cathode-ray tube system CRT of FIG. 1) which is triggered by a signal on line H. The output of delay one shot D1 is connected to the set input S of set-reset flip-flop F2 whose 1 output is connected to line SCN. Thus, the trailing edge of the pulse from delay one shot D1 sets flip-flop F2. The line SCN is connected to the input of tab clock TCK which can be gated oscillator which generates pulses having a repetition rate such that seventy pulses are generated during the time of one horizontal scan of the cathode-ray tube raster. The output of tab clock TCK is connected to line TS which is connected to modulo counter MC. Modulo counter MC can be a binary counter array which counts to 70 and then clears itself or can be a 70 bit long end-around shift register. In either case, the output of modulo counter MC is connected to line EOS which is connected to the reset input R of flip-flop F2. In this way tab control TCC emits 70 tab shift pulses each time it receives a signal on line H.

The write clock of FIG. 3 will now be described. Basically the write clock WC generates the shift pulses for byte code shift register BSR and the loading pulses for shift registers SR2 and SR3 as well as their shift pulses. The clock is best described by starting at the output of OR-circuit B3 which is connected to the trigger input of one-shot circuit 1S1 whose output is connected to line CS and to the trigger input of trailing-edge-triggered one-shot circuit 1S2. Thus, when OR-circuit B3 emits a pulse it triggers one-shot 1S1 which transmits a shift pulse on line CS. In addition, the trailing-edge of this pulse triggers one-shot 1S2 whose output is connected to line LR. One-shot 1S2 emits a pulse on line LR which samples AND-circuits A0 to A4 (FIG. 1) to load the dot signals into shift register SR2 and to pre-set shift register SR3. In addition, line LR is connected to the set input S of set-reset flip-flop F3 whose reset input is connected to line RE. The 1 output of flip-flop F3 is connected to the input of gated oscillator G0 whose output is connected to line BS. Oscillator G0 can be a pulse generator which is free-running when its input is high and is cut-off when its input is low (a gated multivibrator).

In general, the pulse on line LR sets flip-flops F3 turning on gated oscillator G0 to provide the shift pulses on line BS for shift register SR2 and SR3 (FIG. 1). After five such pulses a signal is present on line RE connected to the reset input of flip-flop F3 which resets, terminating the shift pulses.

Generally, the pulse on line RE also passes through AND-circuit A6 to an input of OR-circuit B3 to repeat the cycle and make the clock free-running. However, at the end of each horizontal scan, there must be a time delay so that no dots are displayed while the beam is driven to the left margin. This is accomplished by connecting the output of OR-circuit B4 to a second (and inverting input) of AND-circuit A6. Thus, whenever, a signal is present on either of the lines EOS and HS connected to inputs of OR-circuit B4 the H signal is generated to start the retrace. This signal blocks AND-circuit A6 to nullify the effect of a signal on line RE. Then when tab control TCC generates the signal on line SCN during each actual horizontal scan, the SCN signal passes through OR-circuit B5 by trigger one shot 183 acting only as a leading edge differentiator, i.e., it can be a one-shot multivibrator which emits a narrow pulse when triggered by a positive going signal. The output of one shot 183 is connected to the second input of OR-circuit B3.

In addition when tabbing is called for it is necessary to interrupt the free-running operation of the write clock WC. This is accomplished by flip-flop F4 whose 0 output is connected to the third input of AND-circuit A6 and the second input of OR-circuit B5. Thus, at the start of a tab operation when a signal is generated on line TAB connected to the input S of flip-flop F4, the flip-flop sets blocking AND-circuit A6. At the end of the tab operation indicated by the generation of a signal on line TBS connected to the reset input of flip-flop F4, the flip-flop resets with its 0 output going high. AND-circuit A6 opens, and the positive going edge from the 0 output passes through OR-circuit B5 to trigger one shot 183 which emits a pulse to OR-circuit B3 reintiating the free-running action.

While the system has been described with respect to monospaced characters, the invention is equally applicable to proportional spaced characters wherein there can be more or less possible tab positions than the possible number of characters on a line.

There will now be obvious to those skilled in the art, many modifications and variations satisfying many or all of the objects of the invention but which do not depart from the spirit thereof as defined by the appended claims.