Title:
PROPORTIONAL SYMBOL DISPLAY
United States Patent 3754229


Abstract:
A display system wherein intensity modulated dot signals are used to generate visually displayed symbols or matrices of dots on a medium. Proportional spacing of the symbols is obtained by controllably varying the speed at which the dot signals are generated during uniform scans of the medium.



Inventors:
MANBER S
Application Number:
05/267641
Publication Date:
08/21/1973
Filing Date:
06/29/1972
Assignee:
REDACTRON CORP,US
Primary Class:
Other Classes:
396/550
International Classes:
G09G5/24; (IPC1-7): G06F3/14
Field of Search:
95/4
View Patent Images:
US Patent References:



Primary Examiner:
Caldwell, John W.
Assistant Examiner:
Curtis, Marshall M.
Claims:
What is claimed is

1. A system for displaying symbols as matrices of dots comprising: a record medium, a source of a beam which when impinging on said second medium changes the visual state of said record medium at the point of impingement, means for generating a scanning raster whereby the beam repetitively sweeps across said record medium at a uniform speed, means for generating a different plurality of dot signals for each of the symbols to be displayed, means for intensity modulating the beam in accordance with received dot signals, and transmitting means for transmitting the dot signals to said intensity modulating means at a rate corresponding to a plurality of particular symbol being displayed whereby the symbols are displayed with controllable width.

2. The system of claim 1 wherein said record medium is the screen of a cathode-ray tube display, said source of the beam is the electrode gun and associated circuits of said cathode-ray tube display, and said means for generating the scanning raster is the horizontal and vertical deflection circuits of said cathode-ray tube display.

3. The system of claim 1 wherein said means for generating a different plurality of dot signals for each of the symbols comprises a memory having a plurality of addressable registers, each of said registers being associated with a symbol and storing indicia representing the dots of the matrix of the symbol, and selection means for selecting particular registers and converting the indicia therein to dot signals.

4. The system of claim 1 wherein said transmitting means comprises at least one shift register for receiving the generated dot signals, shift pulse generating means for generating a plurality of shift pulses for shifting the dot signals through said shift register, and means for selectively varying the pulse repetition rate of the shift pulses.

5. The system of claim 1 wherein said transmitting means comprises at least one shift register for receiving the dot signals from said memory and selection means in parallel, shift pulse generating means for generating a plurality of shift pulses for shifting the dot signals through said shift register, and means for selectively varying the pulse repetition rate of the shift pulses.

6. The system of claim 5 wherein said record medium is the screen of a cathode-ray tube display, said source of the beam is the electrode gun and associated circuits of said cathode-ray tube display, and said means for generating the scanning raster is the horizontal and vertical deflection circuits of said cathode-ray tube display.

7. The system of claim 1 further comprising a first means for sequentially generating groups of coded combinations of bits wherein each coded combination of bits is associated with a symbol to be displayed, addressed memory means for storing indicia representing all possible symbols which can be displayed, selection means receiving each group of coded combination of bits for selecting from said addresssed memory means the indicia representing the symbol associated with the received group and converting the indicia into a parallel array of dot signals, a shift register for receiving in parallel the array of dot signals and transmitting the dot signals serially to said intensity modulating means, shift pulse generating means for generating a plurality of shift pulses for shifting the dot signals through said shift register, and means for selectively varying the pulse repetition rate of the shift pulses.

8. The system of claim 7 wherein said addressed memory means also stores indicia representing a spacing factor for each symbol, said selection means also including means for selecting the spacing factor indicia and means for utilizing the selected spacing factor indicia to select the pulse repetition rate of the shift pulses.

9. The system of claim 8 wherein said shift pulse generating means comprises a plurality of selectively operable shift pulse generators, and means for energizing the operation of a particular shift pulse generator in accordance with the selected spacing factor indicia.

10. The system of claim 9 wherein said record medium is the screen of a cathode-ray tube display, said source of the beam is the electrode gun and associated circuits of said cathode-ray tube display, and said means for generating the scanning raster is the horizontal and vertical deflection circuits of said cathode-ray tube display.

11. In a display system wherein intensity modulating dot signals are used to generate visually displayed symbols as matrices of dots on a medium, the method of controlling the width of the displayed symbols by controllably varying the rate relative to scan speed at which the intensity modulating dot signals associated with each symbol are generated during scans of the medium at uniform speed.

Description:
This invention pertains to symbol display systems and more particularly to such systems wherein the symbols are displayed as matrices of dots.

A very common method of displaying symbols utilizes a cathode-ray tube system wherein the electron beam sweeps out a raster of horizontal lines which are uniformly displaced from each other in a vertical direction on the screen. In such a raster the horizontal lines are scanned at a uniform rate of speed. During the scan of each horizontal line, the beam is turned on and then off at particular points to "paint" dots on the screen. By choosing the points where the beam is turned on, one can construct symbols. In fact, this technique is so common that for the set of alphanumeric symbols, particular matrices of dots have become standardized. One of the most common is the 5×7 matrix, since it has been found that combinations of these 35 dots arranged in five columns and seven rows can legibly represent at least all 26 alphabetic characters and the 10 numerals. Although other matrices can be used, the following discussion will assume the 5×7 matrix. However, it should be realized the invention also contemplates the other matrices. With a matrix representation each symbol such as an alphanumeric, is allotted five columns. Therefore, presently available symbol display systems, when writing a line of alphanumerics basically divides the horizontal scan into equal increments wherein, in each increment, there is space for writing a five column wide character. Now, it is a fact that the actual widths of the characters vary. For instance, compare the width of the letter "m" or "w" with the width of the letter "i" or "l". Therefore, by allotting the same space per character, it is apparent that a displayed line of text looks different from a conventionally printed line of text. This same problem has also arisen with respect to typewritten text and has been solved with typewriters which perform proportional spacing.

It is accordingly, a general object of the invention to provide a method and apparatus for displaying proportionally spaced symbols on a raster scanning type display device wherein each symbol is represented by a different combination of dots in a fixed two-dimensional matrix.

Briefly, the invention contemplates a system for displaying symbols as matrices of dots comprising a record medium, a source of a beam which when impinging on the record medium, changes the visual state thereof at the point of impingement, means for generating a scanning raster whereby the beam repetitively and at constant speed sweeps across the record medium, means for generating a different plurality of dot signals for each of the symbols to be displayed, means for intensity modulating the beam in accordance with received dot signals, and means for transmitting the dot signals to the intensity modulating means at a speed related to the particular symbol being displayed whereby symbols are displayed with proportional spacing.

Other objects, the features and advantages of the invention will be apparent from the following detailed description when read with the accompanying drawing which shows an exemplary embodiment of the apparatus for realizing the invention.

In the drawing:

FIG. 1 is a block diagram of a display system according to the invention; and

FIG. 2 is a logic diagram of a variable clock incorporated in the system of FIG. 1.

Before describing the display apparatus, the assumed display format will be discussed. The displayed material will be horizontal lines of text on the screen of a cathode-ray tube which is driven in a conventional raster scan. Each line of text will start at the same left hand margin, except for controlled indentations or tabulations. Each line will have no more than a fixed number of alphanumerics. Each alphanumeric will be represented by a 5×7 matrix of dots with a space allotment to one side of the alphanumeric. The possible five dots of any given row of the matrix for each alphanumeric of a line to be displayed, will be written during the same horizontal scan. Seven contiguous sequential scans will be required to write all seven rows of the matrix while the equivalent of about the next two possible horizontal scans of the raster will be blank to provide the space between lines of text. While a cathode-ray tube system is being assumed it should be realized that other raster type display systems such as electrostatic ink jet systems could be used.

Generally, the bytes representing the alphanumerics of a line of text will be transmitted from a store to an end-around shift register. When the shift register has been loaded, a horizontal sync pulse is generated to start the first horizontal scan for that line of text. An indication associated with this first horizontal scan and the byte of the first alphanumeric at the output of the shift register are used by a translator to select and generate the dot signals of the top row of this alphanumeric which are loaded in parallel into a five-bit shift register. In addition, the translator feeds signals to a variable clock to indicate a specific shift pulse repetition rate. For example, if the alphanumeric has an average width such as "b," "c," "q," etc., a given rate is specified, if the alphanumeric is narrow such as "i" or "l" a faster rate is specified, and if the alphanumeric is wide such as "m" or "w," then a slower rate is specified. The variable clock then generates five shift pulses at the appropriate rate to feed the dot signals of the row to the intensity or "video" input of the cathode-ray tube system. The end-around shift register is then shifted one place to present the next alphanumeric for translation. This process continues until the last alphanumeric has been translated for the first time. At this point, the top row of dots of each alphanumeric has been displayed. Another horizontal sync pulse is generated and the process repeated for the second row. This time the translator receives the bytes and an indication associated with the second horizontal scan. This process continues for seven such horizontal scans so that all seven rows of the dot signals for all the alphanumerics of the first line of text are displayed. Then there is a pause to provide a vertical space before the next line of text is displayed. During this pause the bytes of this next line of text are transferred to the end-around shift register. This second line of text is displayed in the same manner as the first but vertically downward displaced therefrom.

FIG. 1 shows a system utilizing positive logic for performing these operations. The system includes a store STR which can be a miniprocessor and memory which stores all the bytes representing the text to be displayed as well as several control bytes such as a start-of-line byte and an end-of-line byte. Assume the bytes to be coded combinations of seven bits. Store STR transmits these seven bits in parallel to seven-line cable C1. In addition, store STR when transmitting a byte will emit a shift pulse on line SP to an input of OR-circuit B1. Furthermore, at the start of each "page" of text to be displayed store STR emits a vertical sync pulse onto line V, and at the start of each line of text to be displayed it emits a pulse onto line HS and a clear pulse on line CL. Finally, store STR can receive pulses from line EOL indicating that a line of text has been displayed so that it can initiate the transfer of the information for the next line.

The bytes from store STR are received by end-around shift register EASR which can be seven parallel end-around shift registers, say, 70 bits long, i.e., the maximum number of alphanumerics that can be displayed on a line. The bytes from store STR are received at inputs T1 and transmitted from outputs EX onto seven-line cable C2 as seven bits in parallel. Seven-line cable C3 feeds the bytes back to inputs T2 to provide the end-around shifting facility. Pulses received at shift input SF from the output of OR-circuit B1 cause the shifting of the bytes.

Decoder DEC, of conventional design, when detecting the start-of-line control byte emits a pulse on line SOS and when detecting the end-of-line control byte emits a pulse of line EOS. The inputs of decoder DEC are connected via seven-line cables C4 and C3 to outputs EX of end-around shift register EASR.

The count of the number of horizontal scans per line of text is performed by shift register SR1, a seven-bit long shift register which is cleared to a bit only in its first stage upon receipt of a pulse on line HS and is shifted one position each time it receives a pulse at shift input SF from line EOS. During such shifting, shift register SR1 successively transmits signals on lines H0, H1, H2, . . . , H6, and EOL. The pulses on lines H0 to H6, connected to translator TRL, are used to select the seven rows of dot signals. The signal on line EOL, connected to store STR, is used to indicate the entire line has been displayed. Note, that although a shift register has been used to count and record the number of horizontal scans associated with a line of text, one could equally use a modulo-7 counter.

Translator TRL can comprise two read only memories ROM1 and ROM2. Each register of memory ROM1 can comprise two bits of storage for storing speed indicating signals. These registers are selected by the bytes received from the outputs EX of end-around shift register EASR, via seven-line cables C2, C5 and C6, and their contents read out onto lines RA and RB. For normal speed the selected register will store the binary combination 10, for low speed 01 and for high speed 11.

Each register of memory ROM2 can comprise five bits of storage, related to a particular row of the matrix of a particular character. A register is selected by means of the byte received from the outputs EX of end-around shift register EASR via seven-line cables C2 and C5 (associated with the alphanumeric to be displayed) and a signal on one of the lines H0 to H6 (associated with the particular row of dots then to be displayed), whenever the translator TRL cannot select a register all its outputs are low. The contents of the selected register are read in parallel, via lines R0 to R4 and AND-circuits A0 to A4, respectively, into shift register SR2. It should be noted that memory ROM1 can be replaced by two more shift register channels in end-around shift register EASR with such channels carrying the two-bit speed information for the alphanumerics. In such a case, register EASR has nine outputs with the bottom two connected to lines RA and RB.

Shift register SR2 can be a conventional five-bit shift register wherein the five stages are loaded in para lel from AND-circuits A0 to A4 while shift pulses received at shift input SF connected to line BS sequentially shift the contents out onto line Z. In order to count the number of shifts and to indicate when five shifts has occurred, there is provided five-bit shift register SR3 whose shift pulse input SF is connected to line BS and whose output is connected to line RE. A pre-setting input is connected to line LR such that upon receipt of a pulse therefrom, the first stage is set to 1 and the four remaining stages set to 0. In this way, after the register has been pre-set and five shift pulses occur, a pulse will be emitted onto line RE. Of course, shift register SR3 can be replaced by a modulo-5 counter which is cleared by a pulse on line LR and emits a pulse onto line RE after counting five pulses from lines BS.

The shift pulses on line BS are generated by variable clock VC, hereinafter, more fully described in detail. For the present, one needs to know that variable clock VC controllably emits bursts of five shift pulses generally in response to pulses on line RE, i.e., a pulse on line RE results in a burst of five shift pulses on line BS preceded by pulse on line LR which is preceded by a pulse on line CS. The repetition rate of the pulses within a burst of five is controlled by signals on lines RA and RB. Whenever the end of a horizontal scan is reached, variable clock VC receives a signal on line E0S from decoder DEC to delay the generation of the pulses on lines CS, LR and BS until the horizontal scan is retraced in response to a signal on line H effectively caused by the signal on line EOS.

Cathode-ray tube system CRT can be a conventional CRT display having horizontal and vertical circuits connected respectively, to lines H and V for generating the horizontal and vertical deflection signals, to control the sweep of the electron beam, and video circuits connected to line Z for intensity modulating the electron beam.

The operation of the system of FIG. 1 will now be described. After the store STR transmits signals (not shown) to initialize all registers and flip-flops it transmits a pulse of line V to cathode-ray tube system CRT as a vertical sync pulse; it transmits the bytes of the first line of text to be displayed to end-around shift register EASR; and then transmits a pulse on line HS to variable clock VC and to the pre-set input of shift register SR1. The bytes of each line of text are prefixed by a start-of-line control byte and suffixed by an end-of-line control byte. Shift register SR1 is set to its first stage and starts generating a signal on line H0 associated with the first row of the dot matrices. Variable clock VC immediately transmits a pulse on line H which is received by cathode-ray tube system CRT as a horizontal sync pulse, and which is received at the set input S of flip-flop F1. The setting of flip-flop F1 activates clock CK (a voltage controlled oscillator) to emit shift pulses via OR-circuit B1 to the shift pulse input of shift register EASR which starts shifting until the start-of-line control byte is at its outputs EX. This byte is sensed by decoder DEC which transmits a signal on line SOS to the reset input R of flip-flop F1 which resets and shuts off clock CK. In this way, variable length lines of text can start at the same left margin since the shifting occurs during the horizontal retrace time. Thereafter, variable clock VC transmits a pulse via line CS, AND-circuit A5 and OR-circuit B1 to the shift pulse input SF of shift register EASR causing the first alphanumeric byte to be transmitted from its output to translator TRL. This byte is translated by memory ROM1 to feed a combination of signals on lines RA and RB to variable clock VC to set the shift pulse speed. In addition, this byte cooperates with the signal on line H0 in memory ROM2 to select the dot signals for the first (top row) of the dot matrix for the alphanumeric associated with this byte. The dot signals are fed in parallel via lines R0 to R4 to inputs of AND-circuits A0 to A4, respectively. Then, variable clock VC emits a pulse on line LR which gates the dot signals (bits) into shift register SR2 and sets a 1 into the first stage of shift register SR3. Thereafter, variable clock VC transmits five shift pulses at the presecribed repetition rate (speed) to both shift registers. The dot signals are shifted onto line Z and into the cathode-ray tube system CRT to generate the dots for the first row of the matrix for the first symbol of the line. Following the fifth shift pulse, shift registers SR2 and SR3 are empty with the bit in register SR3 fed via line RE to variable clock VC. After a delay, variable clock VC transmits another pulse of line CS resulting in a shift in shift register EASR and the second byte is presented for translation in the same manner as the first byte. The dot signals for the first row of the second byte are gated into the shift register SR2 by another pulse on line LR which also loads the 1 bit into the first stage of shift register SR3. Another five shift pulses are generated and the dots of the first row of the second alphanumeric symbol are displayed. This process continues until decoder DEC detects the end-of-line control bit and transmits a signal on line EOS. Note translator TRL cannot translate this byte hence, it will transmit no dot signals. The signal on line EOS steps shift register SR1 which starts transmitting a signal on line H1 associated with the second row of the dot matrices. The signal on line EOS is received by variable clock VC which responds to it in the same manner as the receipt of a signal on line HS, i.e., by generating the signal on line H. The alignment shifting in end-around shift register EASR is performed and thereafter, the second rows of the dot signals are transmitted to cathode-ray tube system CRT in the same manner as the first rows, as described above. The third, fourth, fifth, sixth and seventh rows are similarly generated. After the seventh row has been displayed, shift register SR1 transmits a signal on line EOL which is fed to store STR to indicate that the whole line of text has been displayed. In addition, the signal on line EOL blocks AND-gate A5 to prevent any shifting in shift register EASR.

In order to display the second line of text, store STR must load the new line into shift register EASR and transmit a pulse on line HS. Thereafter, the system operates as described above except that because the vertical deflection is still operating and no new vertical sync pulse is generated, the second line is displayed below the first line.

The variable clock of FIG. 2 will now be described. Basically, the variable clock VC generates the shift pulses for end-around shift register EASR, the loading pulses for shift registers SR2 and SR3 as well as their shift pulses. The clock is best described by starting at the output of OR-circuit B3 which is connected to the trigger input of trailing-edge-triggered one-shot circuit 1S1 whose output is connected to line CS and to the trigger input of trailing-edge-triggered one-shot circuit 1S2. Thus, when OR-circuit B3 emits a pulse its trailing edge triggers one-shot 1S1 which transmits a shift pulse on line CS. In addition, the the trailing-edge of this pulse triggers one-shot 1S2 whose output is connected to line LR and the set input of flip-flop F2. One-shot 1S2 emits a pulse on line LR which samples AND-circuits A0 to A4 (FIG. 1) to load the dot signals into shift register SR2 and to pre-set shift register SR3. In addition, the trailing-edge of the pulse sets flip-flop F2 whose output is connected to an input of each of the AND-circuits A7, A8 and A9. The other inputs of these AND-circuits are connected to lines RA and RB. Thus, one of these AND-circuits will pass a signal (go high), which one being determined by the shifting rate desired as represented by the coded combination of signals on lines RA and RB. The outputs of AND-circuits A7, A8 and A9 are connected to the control inputs of gated oscillators VS, VN and VF, respectively. Each of the oscillators can be a free-running relaxation oscillator which is biased to cut-off until it receives a high signal at its control input. The oscillating frequencies are chosen such that oscillator VS is the slowest, oscillator VN intermediate and oscillator VF the fastest. The outputs of the oscillators are fed via OR-circuit B4 to line BS to provide shift pulses for shift registers SR2 and SR3 (FIG. 1). After five such pulses a signal is present on line RE connected to the reset input of flip-flop F2 which resets, terminating the shift pulses.

Generally, the pulse on line RE also passes through AND-circuit A6 to an input of OR-circuit B3 to repeat the cycle. However, at the end of each horizontal scan, there must be a time delay so that no dots are displayed while the beam is driven to the left margin. This is accomplished by connecting the output of OR-circuit B2 to the second (and inverting input) of AND-circuit A6 and via one-shot 1S3 to the second input of OR-circuits B3. One-shot 1S3 when triggered, emits a negative going pulse for a period of time sufficient to permit a horizontal retrace to occur.

The inputs of OR-circuit B2 are connected to lines EOS and HS. Thus, whenever a signal is present on either one of these lines, a pulse is transmitted to line H, one-shot 1S3 is triggered and AND-circuit A6 is blocked causing the generation of a new horizontal scan which is initiated by a retrace and thereafter, the shift pulse cycle can occur.

There will now be obvious to those skilled in the art, many modifications and variations satisfying many or all of the objects of the invention but which do not depart from the spirit thereof as defined by the appended claims.