Title:
CHARACTER GENERATING APPARATUS FOR TELEVISION TITLING
United States Patent 3740743


Abstract:
An apparatus which receives a sequence of character representative signals and which generates stroke signals that are suitable for controlling a scanned display to present the sequence of characters on the display with proportional spacing. The system includes a timing generator for generating timing signals which are synchronized with the display scan and a recirculating storage for storing the character-representative signals, reading out specified character-representative signals which correspond to a specified character in the sequence and then restoring the specified character signals. The recirculating storage is shifted in response to spacer timing signals generated by a spacer detector which is responsive to the specified character signals and includes means for generating spacer timing signals that are a function of the width of the specified character. A stroke generator which is responsive to the timing signals and the spacer timing signals generates a stroke of the specified character.



Inventors:
BARON S
Application Number:
05/128727
Publication Date:
06/19/1973
Filing Date:
03/29/1971
Assignee:
COLUMBIA BROADCASTING SYS INC,US
Primary Class:
Other Classes:
178/30, 345/16, 396/550
International Classes:
B41B19/01; B41B27/28; G09G5/24; (IPC1-7): G06F3/14
Field of Search:
340/324A 178
View Patent Images:
US Patent References:
3593310DISPLAY SYSTEM1971-07-13Kievit
3165045Data processing system1965-01-12Troll



Primary Examiner:
Caldwell, John W.
Assistant Examiner:
Curtis, Marshall M.
Claims:
I claim

1. Apparatus for receiving a sequence of character-representative signals and for generating video control signals which are suitable for controlling a scanned display to present the sequence of characters on the display, comprising:

2. Apparatus as defined by claim 1 wherein said stroke generator means is also responsive to said spacer timing signals which triggers the readout of said video control signals from said stroke generator means.

3. Apparatus as defined by claim 1 wherein said spacer detector means includes:

4. Apparatus as defined by claim 3 wherein said character timing generator comprises a serial-in-parallel-out shift register.

5. Apparatus as defined by claim 4 wherein said sequence controller comprises a serial-in-parallel-out shift register which is reset by said selected timing pulse.

6. Apparatus as defined by claim 5 wherein one of said spacer timing signals is applied to and is operative to reset said character timing generator.

7. Apparatus as defined by claim 1 wherein said recirculating storage means comprises a plurality of recirculating shift registers, one for each of a predetermined number of rows of characters to be displayed.

8. Apparatus as defined by claim 7 wherein the scanned display exhibits a television raster scan-line pattern having a plurality of substantially parallel synchronized scanlines.

9. Apparatus as defined by claim 8 further comprising automatic line counting means responsive to synchronizing signals from said scanned display and operative to count a predetermined number of lines within each display row.

10. Apparatus as defined by claim 9 wherein said timing generator means includes means for generating a predetermined number of clock pulses during each scanline.

11. Apparatus as defined in claim 10 further comprising automatic position counting means responsive to said spacer timing signals for counting the number of characters occurring during a given scanline.

12. Apparatus as defined by claim 11 further comprising manual position counting means responsive to external signals indicative of the position at which a new character is to be entered on the display.

13. Apparatus as defined by claim 12 further comprising load controlling means responsive to said manual and automatic counting means and operative to generate a load command signal at a time at which a new character is to be entered into said recirculating storage means.

14. Apparatus as defined by claim 13 further comprising manual row counting means responsive to external signals indicative of the row in which said new character is to be entered on the display.

15. Apparatus as defined by claim 14 further comprising cursor video generating means responsive to said manual position counter and said manual row counter and operative to generate cursor control signals suitable for controlling said display to present thereon an indication of the position on the display at which a new character is to be entered.

Description:
BACKGROUND OF THE INVENTION

This invention relates to a television tilting apparatus and, more particularly, to an apparatus that receives digital input signals corresponding to title information and generates video signals for displaying the information in readable form.

There have been previously described various systems which convert digital title information into video signals that are suitable for display in readable form. Systems of this type are employed, for example, to provide title information alone on a display screen, such as is typically done with financial data. Tile information may also be generated for display in conjunction with conventional television picture information. This is generally accomplished by combining the video picture signal and the video title signal using known keying techniques.

A system that receives digitally coded characters and generates character video signals suitable for display using a television raster scanning pattern is disclosed in the U.S. Pat. No. 3,422,420 of R.J. Clark. In the Clark system the received digitally coded input character signals to be displayed in a row are stored in ordered positions in recirculating shift registers. Various timing signals, synchronized with the display scan, are generated in repetitive sequences and effectively divide the display scan into a plurality of "character space areas" of predetermined equal size. A character pattern or outline trace is formed in a character space area on the display device by blanking and unblanking the scanning beam as the beam traverses the display device. Thus, each character is formed on the display as a series of "slices" or "strokes" during successive scanlines. The character signals are read out of the recirculating shift registers one at a time, and a "character generator" subsystem generates the appropriate video stroke signals (blanking and unblanking commands) which are distinctive of the character being read out. The timing signals control the shifting and reading out of the character signals in the recirculating registers such that a new character signal is read out each time the display scan passes into a new character space area. After being read out, each character signals is restored in the recirculating registers to be recalled during the next display scnaline when the next strokes of each character in the display row are generated. The retentivity of vision of the eye is relied upon to build up the impression of a complete character from the separate character strokes that are produced during each scanline.

Prior art systems such as that disclosed in the Clark patent allot character space areas of a given predetermined width to each character being displayed. In such systems the timing signals are conveniently synchronized with the display scan and also with the shifting of the recirculating shift registers, so that each character stroke in a scanline is assigned an equal predetermined width. This means, for example, that the character "i" is afforded the same display width as the character "w." Of necessity, the w takes up most of the avilable width whereas the i takes up only a small part of the width of a character space area. As a result, the displayed titles appear peculiar to the reader's eye and are somewhat difficult to read due to disproportionate spacing between characters. It is the primary object of the present invention to provide a television titling system whcih generates proportionally spaced characters for display.

SUMMARY OF THE INVENTION

The present invention is directed to an apparatus which receives a sequence of character-representative signals and which generates stroke signals that are suitable for controlling a scanned display to present the sequence of characters on the display with proportional spacing. The system includes a timing generator for generating timing signals which are synchronized with the display scan, and a recirculating storage for storing the character-representative signals, reading out specified character-representative signals which correspond to a specified character in the sequence, and then restoring the specified character signals. The recirculating storage is shifted in response to spacer timing signals generated by a spacer detector which is responsive to the specified character signals and includes means for generating spacer timing signals which are a function of the width of the specified character. A stroke generator which is responsive to the timing signals and the spacer timing signals generates a stroke of the specified character.

DESCRIPTION OF THE DRAWINGS

Other objects, features and advantages of the invention will become apparent, and its construction and operation better understood, from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is an illustration of the type of character patterns that can be formed using the present system;

FIG. 2 is a schematic block diagram showing the principal components of the system;

FIG. 3A and 3B togher is a schematic diagram showing the system in greater detail;

FIG. 4 is a schematic diagram showing the line and row calculator of FIG. 3 in greater detail;

FIG. 5 is a schematic diagram showing the spacer detector means of FIG. 3 in greater detail;

FIG. 6 is another illustration of the type of character patterns that can be formed with the present system along with certain timing diagrams which relate to the particular characters shown;

FIG. 7 is a schematic diagram showing the character position calculator of FIG. 3 in greater detail;

FIG. 8 is a schematic diagram illustrating the stream selector circuitry of the system of FIG. 3; and

FIG. 9 is a block diagram illustrating the stroke generator circuitry of FIG. 3 in greater detail.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Character Display

FIG. 1 illustrates the type of character patterns which can be formed with the video stroke signals generated by the present apparatus. The characters are depicted as being displayed on a display device having a television raster type scanning pattern. With such a device the characters are generally displayed at a white or light level, but the characters are shown in FIG. 1 as black on a white background for ease of illustration. The television scanning pattern may be a conventional interlaced raster scan of 525 horizontal scanlines; i.e., 262 1/2 "odd" lines and 262 1/2 "even" lines. The illustrated upper case characters are twenty-eight scanlines high, the individual scanlines being denoted as h1 to h28. Each scanline has a duration of about 64 microseconds. A basic system clock produces a plurality of pulses during each scanline and effectively divides each scanline into a plurality of elemental spaces, shown as the horizontal divisions or elements in FIG. 1. Each element corresponds to a time duration of about 100 nanoseconds, and the first character "W" was arbitrarily chosen as starting at a time t100, or 100 elements (i.e. 10 microseconds) after the beginning of the horizontal scanline reference.

The row of characters shown in FIG. 1 occupies the portion of the screen from t100 to about t190, so it takes the scanning beam about 9 microseconds to traverse the portion shown during each scanline. During the first scanline, labeled h1, the top stroke of the character "W" is displayed by turning the scanning beam "on" for the periods t100 - t104, t113 - t118, and t127 - t131. After a "space" of four elements, the beam is again turned on for the period t135 - t139 to produce the top stroke of the "I" and then from t143 - t159 for the top stroke of the "E," etc. The next horizontal scanline of an interlaced raster scan is h3, which happens to require the same strokes as h1 for the characters shown. For the scanline h5, the beam is turned on for the periods t101 - t105, t110 - t120, and t126 - t129 for the "W," t135 - t139 for the "I;" t143 - t148 for the "E;" and so on. In this manner, and with the help of the retentivity of vision of the eye, the separate character strokes produced during each scanline give the impression of complete characters on the display screen.

It is seen that the characters have differing widths and that each character does not occupy an equal-sized "character space" on the display screen. For example, among the characters shown, the number of elemental widths occupied by each character are as follows: "W"-31; "I"-4; "E"-16; and "L"-16. The characters in a word are proportionally spaced four elements apart, so that words can be comfortably read and are esthetically pleasing.

GENERAL OPERATION

The basic operation of the apparatus will now be described with the aid of FIGS. 2 and 3. In FIG. 2 an input sequence of character-representative digital signals 10 is received by a recirculating storage means 100. These signals are typically in binary form with, for example, a given six-bit coded input signal representing one of 64 (26) letters, numbers and symbols. The input character-representative signals may be derived, for example, from a computer or, as will be further described below, from an input keyboard. For the immediate explanation it will be assumed that a sequence of twenty characters is received and processed for video presentation in a single row.

The storage means 100 includes a six-level shift register having a plurality of stages, the number being determined by the maximum number of characters to be displayed in a row on the display device. The received signals 10 are stored in sequence in twenty stages of the shift register. Upon the appropriate commands, the six bits representative of the character in the last stage of the shift register are read out and then restored to the first stage of the register to be recirculated. The character read out will be referred to as the "specified character" and its representative bits or signals as the "specified character signals."

A timing generator means 200 receives synchronizing signals from the display device; namely the vertical and horizontal sync signals. The timing generator means 200 includes a ten megacycle keyed oscillator which produces basic clock pulses every 100 nanoseconds. The oscillator is keyed by the horizontal sync signals from the display device. The timing genrator also includes various counters which keep track of the number of lines scanned by the display up to a given time. When the display scan is in a row area (only a single row of displayed characters is considered at this point for ease of explanation) the counters produce signals which indicate which line of the row is being scanned.

A stroke generator 300 receives the specified character signals and line information from the timing generator means, and in response thereto generates stroke bits suitable for controlling the display to produce the appropriate stroke of the specified character. The stroke generator means includes a "read-only" memory which is addressed by the received character information and by line information. For example, if the received information indicates that the specified character is a "W" and that the present display scan-line is h5 (FIG. 1), then the memory output stroke bits will be sequential signals instructing the scanning beam to turn "on" for the intervals t101 - t105, t111 - t120 and t126 - t130.

The specified character signals are also received by a spacer detector 300 which determines the width of the specified character and generates a spacer timing signal which depends upon the time when the horizontally scanning beam passes out of the display area needed to produce the specified character. The spacer timing signals are used to shift the recirculating storage means so that the next character in the sequence becomes the new "specified" character in the last stage of the shift register. The appropriate stroke of the new specified character is then generated. The spacer detector also generates a coordinating timing signal, synchronized with the spacer timing signal, for controlling the timing associated with the generation and readout of strike bits.

The operation of the apparatus of FIG. 2 will be better understood by visualizing the letters of FIG. 1 as being the beginning of the sequence of the twenty characters to be displayed in a single row. The sequence of binary coded character-representative signals are read into the recirculating storage 100 and are stored in order with the "W," the "I," the "E," etc., in adjacent stages of the shift register. The sync signals from the display are fed to the timing generator 200, and counters in the timing generator count the number of horizontal scanlines of a display field scansion until, after a predetermined number of lines, the display row area is reached. The scanlines within the display row are then separately counted by the timing generator 200, the first scan-line being h1 (FIG. 1).

The scanline h1 begins its left-to-right scan at a time reference, to, which represents the time at which the horizontal sync signal keys the ten megacycle basic clock oscillator. A predetermined time after t0, the signals representative of the character in the last stage of the shift register (i.e., the specified character "W") are fed to the stroke generator 300 and to the spacer detector 400. The stroke generator generates stroke bits which instruct the scanning beam to turn "on" for the appropriate time intervals (t100 - t104, t113 - t118 and t127 - t131 for character "W," line h1). The spacer detector 400 decodes the character-representative signals and determines the width of the specified character. In the case of the "W," the character is thirty-one elemental divisions wide, or, in other words, it requires a thirty-one clock pulse duration for display. The spacer detector accordingly generates a spacer timing signal at a time reference t131 ; that is, thirty-one clock pulses after the initiation (at t100) of display of the specified character.

The spacer timing signal is fed to the recirculating storage 100 and used to shift the positions of the character-representative signals in the shift register. The "W" is shifted back to the first stage of the shift register and the "I" moves into the last stage to become the new specified character. Similarly each character moves up one position so that the "E" is in the next-to-last stage, the "L" in the second-from-last stage, and so on. A coordinating timing signal, which occurs about 400 nanoseconds (four elemental divisions) after the spacer timing signal, is also generated by the spacer detector. The coordinating timing signal is fed to the stroke generator.

During the time after occurrence of the spacer timing signal, the scanning beam moves along the "space" area beginning with the elemental division t131 (FIG. 1). Also during this time the binary signals representative of the character "I" are fed from the last stage of the shift register to the stroke generator 300 and to the spacer detector 400. The stroke generator 300 generates stroke bits which instruct the scanning beam to turn "on" for a period of four elemental divisions. The coordinating timing signal (from the spacer detector 400) controls the start of the readout of stroke bits to occur at t135, so that the scanning beam turns "on" for the time interval t135 - t139. Meanwhile, the spacer detector decodes the new characterrepresentative signals and determines that the specified character ("I") is four elemental divisions wide. The spacer detector accordingly generates the next spacer timing signal at the time reference t139 ; that is, four clock pulses after the initiation (at t135) of display of the specified character "I."

In a similar manner the remaining top slices of each of the 20 characters are produced during the scanline h1. For the complete scanline, the spacer timing signals circulate the character-representative signals in the shift register by exactly one full cycle, so that at the end of scanline h1 the "W" is again in the last stage of the shift register, the "I" in the next-to-last stage, etc. The next hogizontal scanline of the interlaced raster scan is h3. The horizontal sync signal associated with the beginning of scanline h3 is counted by the timing generator 200 and the resultant new line information is fed to the stroke generator. The appropriate strokes of each of the twenty characters are then generated as previously described, and in this manner the character strokes for each odd-numbered scanline are successively formed. At the end of the vertical field scansion the scanning beam is retraced whereupon it scans the even-numbered scanlines and forms the remaining character strokes.

DETAILED OPERATION

FIG. 3 illustrates in further detail a preferred embodiment of the apparatus shown in the block diagram of FIG. 2. The recirculating storage 100, timing generator 200, stroke generator 300, and spacer detector 400 are each shown in dashed blocks with the components contained within each block labeled with a reference numeral in the appropriate "hundred" series.

In the following description of FIG. 3, it will be assumed that the input character-representative binary signals 50 are generated from a keyboard (not shown) and that the output stroke bits 80 are displayed on a conventional television monitor (not shown). It will become clear, however, that the stroke bits 80 can most usefully be combined with program video and transmitted to remote television receivers. Synchronizing signals 60 from the display monitor are supplied to the timing generator 200. Also supplied to the timing generator are cursor control signals 70 from the keyboard. The cursor control signals regulate the relative position on the display at which a given new input character is to be entered. Cursor video bits 90 control the display on the monitor screen of a "cursor dot" which gives a continuous visual indication of the status of the cursor control signals.

The input character-representative signals 50 are stored in a memory input buffer 110 and are read into the recirculating shift registers 150 in response to signals from the memory input controller 120 and the stream selectors 130. The embodiment of FIG. 3 includes a capability for the display of twelve rows of characters and there are accordingly twelve groups of shift registers 150. Each shift register has six parallel levels of fifty stages so that each display row is potentially capable of displaying 50 characters. (As will later become clear, the actual number of characters which can be displayed on a given row is variable since it depends upon the widths of the individual characters being displayed.) The shift registers 150 are dynamic MOS registers driven by the clock drivers 140 and having their stages coupled back to their first stages through the stream selectors 130. The information in each shift register is directly recirculated by the stream selectors during most of the operating time; i.e., except when new character signals are being loaded into the shift registers. A more detailed description of the loading process will be deferred until later in the specification. It suffices for the present to assume that signals representative of the characters to be displayed have been loaded into the shift registers 150 in appropriate sequence and that the stream selectors directly couple the last and first stages of the registers for a recirculation condition.

The synchronizing signals 60 include the vertical and horizontal sync signals from the display monitor. The horizontal sync pulses occur once every 63.56 microseconds and are used to key the oscillator 210 which produces basic clock pulses at a frequency of ten megacycles. The visible horizontal scanline duration is about 50 microseconds, so there are about 500 clock pulses per visible scanline and about 135 clock pulses during each horizontal blanking period.

The display sync signals 60 are received by the line and row calculator 230 which counts the horizontal scanlines of the display and keeps track of the preselected row in which the scanning beam is positioned at any given instant. This row information is fed to the memory input control 120 and to the memory output multiplexer 160 so that information will be read into and out of the appropriate row in the recirculating storage 100. The calculator 230 also keeps track of the line within a row at which the beam is positioned (viz, the "h" count in FIG. 1); this information is required by the stroke generator.

The line and row calculator 230, illustrated in further detail in FIG. 4, inlcudes counters 231, 232, and 233, each of which may comprise a binary counter. The function of the delayed line counter 231 is to provide a "safe" area at the top of the display scan before the start of the first row. At the beginning of a new display field scansion, the vertical sync signal resets the counters 232 and 233. The counter 231 counts 40 horizontal sync pulses (corresponding to the first 40 horizontal scanlines) and produces a signal which enables the automatic line counter 232. The counter 232 counts the next 17 horizontal sync pulses corresponding to the 14 odd (or even) scanlines of the first character row plus three odd (or even) scanlines constituting a row space between the characters in consecutive rows. Each complete row is thus seen to consist of a total of 34 odd and even scanlines. The line counter 232 produces an output count signal 232a which indicates the instantaneous line count within a row; this signal is sent to the stroke generator 300. After reaching a count of seventeen, the automatic line counter generates a signal which resets inself so that it can start counting lines within the next row. This signal, 232b, also steps the count of the automatic row counter 233. The row counter 233 produces an output count signal 233a indicative of the instantaneous row count which is sent to the memory output multiplexer 160 in the recirculating storage 100. After reaching a count of twelve, the row counter 233 generates a signal 233b which inhibits further row counting until the next vertical sync pulse resets and enables the row counter 233.

Referring again to FIG. 3, the specified character contained in the memory output buffer 160 is received by a character width decoder 310 in the spacer detector 300. The character width decoder 310 comprises a "read-only" memory, for example, a TTL-type matrix, having eight possible output indications. The decoder 310 receives the specified six-bit signal representative of one of the 64 possible characters and produces a logical "1" output on one of eight output lines 310a (shown as a single cable in FIG. 3). Each of the output lines, designated "line 0" through "line 7", indicates one of eight predetermined characters widths. The characters range in width from the four elemental divisions of the "I" to the thirty-one elemental divisions of the "W." Actually, there are seven real width indications for visible characters with one width signal, for example the one on "line 0," being reserved for the case when the specified character is a "null." A null character-representative signal, (which may conveniently be "000000") means that the position being read out of the recirculating shift register 50 is empty. A null should not be confused with a between-word "space," which is another six-bit character-representative signal (for example, "000001") that presents an acutal space of 16 elemental divisions on the display. As will become clear below, there are necessarily some nulls in each row. The widths of some representative characters and their corresponding line numbers are indicated in Table I:

TABLE I

Character Width Line Code (elemental divisions) null 0 line 0 I, ! 4 line 1 E,F,"space" 16 line 2 B,H, 19 line 3 C,R 21 line 4 A,V 23 line 5 M 25 line 6 W 31 line 7

The coded width signals 310a are fed to a spacer timing multiplexer 330, which also receives character timing generator 320. The timing pulses 320a consist of a series of eight timed pulses which occur at intervals that are a function of the elapsed time required to scan each of the eight possible character widths. The multiplexer 330 allows the proper timing pulse, as determined by the coded width signal 310a, to pass to a sequence controller 340. The sequence controller 340 generates signals which shift the recirculating shift registers 50, coordinate the readout of stroke bits from the stroke generator 400, and reset the character timing generator 320.

The operation of the spacer detector 300 can be more clearly understood by referring to FIG. 5. The character timing generator 320 is shown in dashed lines and is seen to include a one-level shift register 321 having thirty-two stages. The shift register 321 is "clocked" by the basic clock pulses from the ten megahertz keyed oscillator 210 (FIG. 3). The shift register 321 is reset at a time reference To to a state as shown in FIG. 5 with a "1" in the first stage and "0"'s in all other stages. Each clock pulse advances the "1" to the next stage of the shift register so that it takes 32 clock pulses for the "1" to enter and move through the entire shift register. As an example, after four clock pulses (400 nanoseconds after To) the "1" is in the stage of the register denoted R4, and after 25 clock pulses (2.5 microseconds after To) the "1" is in the stage of the register denoted R25. Output leads are coupled to eight selected stages of the shift register, namely: Ro, R4, R16, R19, R21, R23, R25 and R31. Pulses appear on these leads as a result of the "1" passing through their associated shift register stages, and these pulses, Tn, are designated by their times of occurrence; i.e., To through T31.

The spacer timing multiplexer includes eight AND gates 331 through 338, each of which receives one of the width signal lines 310a and one of the character timing pulses 320a. The output of each AND gate is fed to the input of an OR gate 339, the output of which is a spacer timing pulse occurring at a time corresponding to the end of the stroke of the specified character.

The spacer timing pulse is fed to the timing controller 340 which comprises a one level, four stage shift register 341 that operates in a manner similar to the shift register 321. The shift register 341 is clocked by the basic clock pulses from the 10 megahertz keyed oscillator. The spacer timing pulse resets the register 341 to the state shown in FIG. 5 with a "1" in the first stage (Rn) and "0" in the other stages (Rn+1 to Rn+4). The next four clock pulses each advance "1" to the next stage of the register. Outputs 340a, 340b and 340c appear sequentially, in the manner previously described, after stages denoted Rn+1, Rn+2, and Rn+4. These outputs occur at the times Tn+1, Tn+2 and Tn+4 ; i.e., one, two, and four clock pulses, respectively, after Tn, where Tn is the time of occurrence of the spacer timing pulse relative to the time reference To. The output 340a is used to clock the recirculation shift registers 50, and the output 340b is fed to a horizontal position counter 220 which will be described hereinbelow. The last output 340c is sent to the stroke memory and triggers the readout of stroke bits from the stroke memory. The output 340c contemporaneously resets the shift register 321 in the character timing generator 320. It should be noted that at the beginning of each scanline a signal is needed to initially set register 321. For this purpose, the signal designated "horizontal synch reset" which is synchronized with horizontal flyback, is applied to the register, the signal being timed to occur a few microseconds afterthe beginning of each horizontal line and determines the relative positions of the first character of each row.

As an illustration of the operation of the spacer detector means 300, and referring to FIGS. 3, 5 and 6, assume that the specified character just read into both the character width decoder 310 and stroke memory is an F, and that the next characters to be read in are an "R" an "I" and a "W" (FIG. 6). An "F" is sixteen elemental divisions wide and will produce a logical "1" on line 2 of the lines 340a (Table I). Line 2 is one of the two inputs to the AND gate 333. The shift register 321 is reset at the time reference disignated To, which corresponds to the time at which the stroke memory is triggered to begin reading out the stroke bits of the "F" for display. (Both of these events are precipitated by the signal 340c which occured at the time reference Tn+4 of whatever character was read out before the "F.") The next clock pulse moves the "1" in shift register 321 into the second stage and also causes the readout of the first stroke bit of the "F" from the stroke generator. As demonstrated above, the pulses T4, T16, T19 etc. occur four, sixteen, nineteen, etc. clock pulses and after To. Only the pulse T16 is passed through its AND gate 333, however, since the other AND gates do not have "1"'s on their line 310a inputs. As a result, the spacer timing pulse T16 appears at the output of the OR gate 339 16 clock pulses after the beginning of the readout of the "F" stroke bits. Also, since the "F" is sixteen elemental divisions wide, it requires a sixteen clock pulse duration for the readout of its stroke bits. Therefore, it follows that the spacer timing pulse occurs simultaneously with the clock pulse during which the last stroke bit of the "F" is read out.

In the case of an "F" the spacer timing pulse Tn is T16 and theshift register 341 is reset at this time. One clock pulse later (at Tn+1), or, 17 clock pulses after To, the signal 340a shifts the recirculating registers and the next character, "R," becomes the new specified character read into the character width decoder and the stroke memory. Four clock pulses after T16 (i.e., at Tn+4) the signal 340c enables the stroke memory to begin reading out the stroke bits of the new specified character, "R." The signal 340c also resets the shift register 321 and establishes a new time reference To for the "R."

An "R" is 21 elemental divisions wide and will produce a logical "1" on line 4 of the lines 310a (Table I), causing the pulse T21 passing through the AND gate 335 to become the spacer timing pulse. The "R," being 21 elemental divisions wide, requires a 21 clock pulse duration for the readout of its stroke bits. Thus, as before, the spacer timing pulse occurs simultaneously with the readout of the last stroke bit of the character being read out of the stroke memory. The same is true for the "I" and the "W" which follow.

The timing of the pulses at 340c, the spacer timing pulses, and the pulses of 340a (FIG. 4) are shown in FIG. 6 in timed relationship to the readout of characters. (The scale directly below the characters indicates the number of elapsed clock pulses from the time reference To of the first character shown, viz., "F.") As seen from the timing diagrams, the timing reference, To, for each character occurs one clock pulse before the first stroke bit of the character is read out. The spacer timing pulses occur during the last stroke bit of the character being read out. Also, the pulses 340a, which serve to shift the recirculating registers (FIG. 3), occur during the next clock pulse after the spacer timing pulse.

It should be noted that for each stroke of a given character (i.e., during successive scanlines), the timing of the spacer timing pulse and the timing of the outputs of the sequence controller 340 are the same. In other words, the particular stroke pattern of a character, which may vary from scanline to scanline, does not affect the relative timing of the spacer timing pulse and its related sequence controller outputs. In FIG. 6, for example, the first scanline of the "F" requires stroke bits which unblank the display beam for the entire sixteen element width of the character. For, the last scanline of the "F," only the first four stroke bits should unblank the display beam while the last twelve stroke bits should blank the display beam. In either case, however, the stroke pattern for the "F" is considered to have a sixteen clock pulse duration and the timing of the spacer timing pulse and its related sequence controller outputs are as shown in FIG. 5.

The loading of new characters into the recirculating shift registers 150 can now be conveniently described in detail. Referring again to FIG. 3, the cursor control signals 70 are received by a character position calculator 220. As was previously indicated, the cursor control signals originate from a keyboard and regulate the relative position on the display at which a given new input character is to be entered. The cursor video signals 90 (the generation of which is to be hereinafter described) control the display on the monitor screen of a cursor dot which gives an operator a continuous visual indication of the status of the cursor control signals.

Referring to FIG. 7, the character position calculator 220 includes counters 221, 222 and 223 and a comparator 224. The cursor control signals 70 include a "row advance pulse" signal 71, and a "position advance pulse" signal 72 which are generated when the operator depresses a key on the keyboard which affects the cursor. Themanual row counter 221 is a binary counter whose output count (a number from "one" to "twelve") indicates the display row in which the next new character is to be entered. In other words, the row counter 221 indicates which row of the shift registers 150 (FIG. 3) is to receive the next new character. The manual horizontal position counter 222 is also a binary counter whose output count (a number from "one" to "fifty") indicates the horizontal display position at which the the next new character is to be entered. In other words, the counter 222 indicates the particular stage of the shift register 150 in which the next new character can be entered. Thus, for example, if the next character to be entered is to go into the tenth stage of the third row of shift registers, the counter 221 would indicate a count of "three" and the counter 222 would indicate a count of "ten". Each of the counters shifts back to a count of "one" when pulsed from its highest possible count.

The operator manipulates the status of the cursor by using the keyboard to generate the signals 71, 72, The cursor status may be changed by the operator without entering new characters to the display by depressing keys on the keyborad (not shown) designated as "cursor position advance" or "cursor row advance." Depressing the "cursor position advance" key generates a pulse 72 which steps the counter 222 by one and also moves the displayed cursor dot by one horizontal position as will be shown. Depressing the "cursor row advance" key generates a pulse 71 which steps the counter 221 by one and accordingly moves the displayed cursor dot to the next row.

The cursor status is also changed automatically when a character is entered on the display by depressing a character key. When a character key is depressed the six-bit input character-representative signals 50 are generated by the keyboard logic an entered into the memory input buffer 110 (FIG. 3). Also, a position advance pulse 72 and a preliminary enable signal 73 (FIG. 7) are generated. The pulse 72 thus steps the counter 222 by "one" when a new character is entered.

Generally, the operator will be entering a sequence of characters to form a word by successively depressing the appropriate character keys. As an example, referring again to FIGS. 3, 6 and 7, assume that the "F," "R" and "I" (FIG. 6) have been entered as the first three characters of the first row of display and occupy the first three positions of the "row 1" shift registor 150 (FIG. 3). In this condition the manual horizontal position counter 222 will contain a count of "four," having been stepped by "one" (from an original count of "one") for each of the three entered characters. Also, the displayed cursor dot would be in the position shown by the dot 601 of FIG. 6 and would indicate to the operator that the next character to be entered will go into a position to the right of the "I" on the display. Now, if the operator depresses the "W" key, the "W" character signals will enter the fourth position of the "row 1" shift register 150 (in a manner to be shown) and the "W" will appear on the display. The pulse 72, generated when the "W" key was depressed, will step the counter 222 to a count of "five" and the displayed cursor dot will appear to jump to the position indicated by the dot 602. The actual generation of the cursor video will be treated in more detail in a later portion of the specification. It suffices for the present to appreciate that the cursor position is defined by the states of the counters 221 and 222.

The automatic horizontal position counter 223 is a binary counter which, like the manual horizontal position counter 222, produces output counts from "one" to "fifty." The counter 223 is reset to "one" at the beginning of each display scanline (by the horizontal sync signal) and counts to "fifty" during each scanline. The counter 223 is stepped by the pulses 340b (FIGS. 3 and 5), which, it will be recalled, occur during the next clock pulse each time the recirculating registers are shifted by the pulse 340a. Thus, the pulses 340b are counted by the automatic horizontal position counter 223 to keep track of which character position of the shift registers 150 is being read out of the last stage of the shift registers and restored to the first stage. As will be seen, this information is needed so that new characters can be entered in the appropriate position of the selected shift register.

The outputs of the counters 222 and 223 are compared by the horizontal position comparator 224 containing logic which produces a "position enable" signal 224a when the count of counter 222 is the same as that of the counter 223. The signal 224a, which occurs once every scanline, is thus timed to occur exactly when the contents of the desired stage of the shift register is being read out.

Depressing a particular character key on the keyboard automatically generates a preliminary enable signal 73 which immediately resets the flip-flop 250 designated as the "load command generator." As soon as the position enable signal 224a occurs, the flip-flop of the command generator 250 is set and produces a load command pulse 250a. The load command pulse is received by the memory input controller 120 (FIG. 3) which directs theload command pulse to the stream selector circuitry of the row into which the new character is to be entered. The memory input controller 120 also receives the manual row count (which is the desired information as to which row in which the new character is to be entered) in binary form. The input controller 120 includes a conventional logic decoder which converts the binary row count to an activated signal on one of twelve lines. The load command pulse 250 is then ANDed with the active line to produce a "Load Row N" (where N is the appropriate row number from one to twelve) signal 120a.

FIG. 8 illustrates the functioning of the stream selector circuits 130 and specifically shows, as representative, the stream selector circuitry for the first, second and sixth levels of shift registers of Row 1. The stream selector circuitry for each level is seen to include an inverter 131, "AND" gates 132 and 133, and an "OR" gate 134. As was indicated above, the memory input controller 120 produces a "Load Row N" signal on one of its twelve outputs at the time at which the new character bits are to be entered in the appropriate stage of the selected shift register 150. During most of the operating time of the equipment, the "Load Row N" signals are off and are therefore at a logical "0" level. This produces a recirculating condition of the shift registers 150 as can be seen, for example, by assuming that the "Load Row 1" signal is at "0" in FIG. 8. Under this condition, the outputs of the AND gates 133 are each "0" (since each has a "0" input), and the output of each "OR" gate 134 therefore "tracks" the output of the AND gate 132 which feeds it. Each of the AND gates 132 receives a "1" input (an inverted "0") from the inverted 131; the output of each AND gate 132 is therefore determined by its other input, viz., the bit 150a fed back back from the last stage of the shift register. It follows that the output 150a of the last stage of the shift register is fed back through the gates 132 and 134 to the first stage of the shift register.

When the "Load Row 1" signal is at a logical "1" level, however, the outputs of the inverters 131 are at "0" and the gates 132 also have "0" outputs. In this case, the AND gates 133 are seen to be active, each having an output which corresponds to its data bit input. The six data bits are thus passed through the OR gates 134 and into position in the shift register in place of the six old bits which had passed out of the last stage of the register.

Referring again to FIG. 3, the outputs 150a of the shift registers are each received by the memory output multiplexer 160. The shift registers 150 are all shifted simultaneously by the clock drivers 140 so that the multiplexer 160 constantly receives twelve groups (one for each row) of new six-bit character-representative signals at once. Only the characters of the row being displayed are read out of the multiplexer 160 (one at a time), however. The multiplexer 160 receives the binary coded row count from the automatic row counter 233 (FIG. 4) in the automatic row calculator 230. The multiplexer 160 includes conventional decoder logic which converts the binary number (from "one" to "twelve") to an output signal on one of twelve output lines. The appropriate row of shift register outputs is then selected by multiplexing circuitry of the type shown in multiplexer 330 (FIG. 5).

FIG. 9 illustrates the functioning of the stroke generator 400 which includes the stroke memory 410 and the cursor video generator 420. The stroke memory 410 includes a read-only memory (ROM) unit 411 which receives the specified character signals and the line information 232a from the automatic line counter 232 (FIG. 4). Read-only memories are described, for example, in an article by F. Kvamme which appeared at page 88 of the Jan. 5, 1970 issue of "Electronics." The ROM 411 generates thirty-one stroke bits which are entered in parallel into the parallel-in-serial-out shift register 412. The stroke bits are clocked out serially using the basic clock pulses from the keyed oscillator 210 (FIG. 3). The readout of stroke bits is indicated by the enabling of the register 412, which is accomplished by the coordinating timing signal 340c from the sequence controller 340.

It should be understood that most characters consist of less than 31 stroke bits. For example, the top stroke line of an "I" consists of the four stroke bits "1111." The remaining bits (5 through 31) read out of the ROM are "0"'s. These "0"'s do not have a chance to be read out, however. After the fourth stroke bit, the signal 340a (FIG. 5) shifts the recirculating registers 150 and a new specified character is read into the ROM. The shift register 412 is then reloaded and does not begin its next readout until enabled again by the coordinating timing signal.

The cursor video generator 420 includes a comparator 421, a gate 422, a small-scale ROM 423, and a four stage parallel-in-serial-out shift register 424. The row comparator 421 receives the outputs of the manual row counter 221 (FIG. 7) and of the automatic row counter 233 (FIG. 4), and generates a signal 421a during the time that these counts are equal. In other words, the signal 421a is generated only during the display row in which the cursor is set. The signal 421a and the position enable signal 224a (FIG. 7) are received at the input of the gate 422. The position enable signal 224a, it will be remembered, occurs when the manual horizontal position counter has a count which is the same as the automatic horizontal position counter 223 (i.e., at the selected cursor position). When the signals 421a and 224a are both present, the gate 422 allows the line information signal 232a to pass to the ROM 423. If the particular scanline is one of the last six scanlines of a character row, the ROM 423 generates four stroke bits consisting of either "0110" or "1111" (see dot configuration of FIG. 6). These bits are entered in parallel into the four-stage parallel-in-serial-out shift register 424. The readout of the bits is then triggered by the coordinating timing signal 340c.

The stroke bits are typically combined with ordinary program video using conventional keying techniques and the composite video can then be transmitted. The cursor stroke bits are additionally keyed into the video which is displayed on the operator's control monitor. The cursor video generally is not transmitted with the composite program video and character stroke bits.

While the invention has been described with reference to a particular embodiment, it will be appreciated that numerous variations can be made within the spirit of the invention. For example, the vertical and horizontal sync signals are shown as derived from a display (e.g., the operator's control monitor). Alternatively, an external source of sync signals can be used to snychronize the program video, the operator's display and the titling apparatus.