Circuit arrangement for processing an input information in a conditionally prescribed order of succession
United States Patent 3079589

877,777. Computing apparatus operating in conditional programmes. PHILIPS ELECTRICAL INDUSTRIES Ltd. June 10, 1959 [June 13, 1958], No. 19877/59. Class 106 (1). The invention aims at obviating apparatus design difficulties arising in a conditional programme when the same data-processing unit is used more than once and the continuation of the programme depends not on the unit but on the preceding steps of the programme, and provides that each unit, B1 to B4 (Fig. 1), gives an output of data and one or more address parts which are written at different locations, K1 to K9, of an address memory AG, each address part containing the address of the unit next used and the location in the address memory of the address part supplied by the unit next used which is to be read out when this unit has completed its processing; further, on an output issuing from a data processing unit a signal is generated causing read-out of one of the address parts from the address memory, this read-out causing a first signal which causes transfer of data from a auxiliary store SG to the unit next used, which in turn causes a second signal which primes the generator of the read-out signal, only the generator that was previously primed producing the subsequent read-out signal. The apparatus of Fig. 1, including data sources A1 to A3 and data processing units B1 to B3 will be described as operating according to the programme symbolized in Fig. 2 which expresses that data from A1 is to be processed in B1 then B4; if output of B4 is of the kind (1) send result to B2, if of the kinds (2) or (3) send result to B3 which terminates the programme, if of the kind (4) send result to B1, and so on. Information from sources Al to A3 is stored in buffer stores BG1 to BG3. Preference switch PS gates information from BG1, the data to an auxiliary store SG and the address part to column KO of address memory AG. As soon as the address part is stored it is decoded due to a delayed signal from PS and results in signals issuing which open gate P1, prime read-out pulse generator Q1 and release information from SG to B1. The output from B1 when data processing is complete is passed, the data to auxiliary store, and the address parts (of which there are three since B1 is used three times in the programme) one each to columns K1 to K3 of address memory AG, whereupon a signal issues on line 22 through delay V2 to the read-out pulse generators Q1 to Q9 of which only that generator which has been primed, viz. Q1, operates. This results in the address part in column K1 being decoded and signals issuing to open gate P4 and prime read-out pulse generator Q1. Thus the address part in the output of unit B4 which is stored in the column K1 of the address memory will be read out to determine which unit is used after B4. The address parts of the outputs of the data processing units necessary to carry out the programme of Fig. 2 are set out in Fig. 3: P2; Q2 means open gate P2, prime the generator Q2. In general a data processing unit will require as many address parts as the number of times it is used in the programme. Preferably the address memory comprises magnetic cores each column comprising cores representing all the Pi or Qi. The cores are set when a data processing unit provides an output according to Fig. 3.

Gerrit, Mol
Jacobus, Schmitz Mattheus
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Other Classes:
712/E9.012, 712/E9.081
International Classes:
G06F9/26; G06F9/32; H03K3/30; H03K3/45; H03K5/02; H03K19/16; H04Q3/54
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