Title:
METHOD OF FABRICATING GATE ELECTRODE USING A TREATED HARD MASK
Kind Code:
A1


Abstract:
A method for fabricating an integrated device is disclosed. In an embodiment, a hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided to the hard mask layer to make the hard mask layer more resistant to a wet etch solution. Then, a patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.



Inventors:
Yeh, Matt (Hsinchu, TW)
Ouyang, Hui (Chuebi City, TW)
Chung, Han-pin (Fongshan City, TW)
Wang, Shiang-bau (Pingzchen City, TW)
Application Number:
12/700862
Publication Date:
08/11/2011
Filing Date:
02/05/2010
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Hsinchu, TW)
Primary Class:
Other Classes:
257/E21.19, 257/E21.334, 257/E21.632, 438/525, 438/585
International Classes:
H01L21/8238; H01L21/265; H01L21/28
View Patent Images:



Primary Examiner:
CHOI, CALVIN Y
Attorney, Agent or Firm:
HAYNES AND BOONE, LLP (IP Section 2323 Victory Avenue Suite 700 Dallas TX 75219)
Claims:
What is claimed is:

1. A method of fabricating an integrated circuit device, the method comprising: providing a substrate; forming a material layer over the substrate; forming a hard mask layer over the material layer; providing a treatment to the hard mask layer to introduce species therein; and patterning the treated hard mask layer and the material layer.

2. The method of claim 1, wherein the hard mask layer is a silicon oxide layer.

3. The method of claim 1, wherein the hard mask layer have a thickness less than or equal to approximately 800 Angstroms.

4. The method of claim 1, further comprising a step of providing a thermal anneal to the hard mask layer.

5. The method of claim 4, wherein a temperature of the thermal anneal is between about 750° C. and about 1100° C.

6. The method of claim 4, wherein a duration of the thermal anneal is between about 0.1 sec and about 1800 sec.

7. The method of claim 1, wherein the species is at least one of boron, carbon, fluorine, or nitrogen.

8. The method of claim 1, wherein the species has an atomic number less than about 50.

9. The method of claim 1, wherein an energy source of the treatment is provided by at least one of ion implantation, plasma, UV, or e-beam.

10. The method of claim 8, wherein the species is introduced by an ion implantation that is performed at an energy higher than or equal to approximately 10 KeV.

11. The method of claim 8, wherein the species is introduced by an ion implantation that is performed with a dose of less than exceeding about 1E14 atoms/cm2.

12. The method of claim 1 wherein the material layer is a polysilicon layer.

13. The method of claim 1, further comprising a step of forming LDD regions in the substrate by an implantation process utilizing a tilt-angle of between about 25° and about 30°.

14. A method for manufacturing a gate structure, the method comprising: forming a gate electrode layer over a substrate; forming a hard mask layer over the gate electrode layer; providing a treatment to the hard mask layer to form a treated hard mask layer, comprising: heating the hard mask layer; and introducing species into the hard mask layer; and patterning the treated hard mask layer and the gate electrode layer.

15. The method of claim 14, wherein a temperature of the step of heating is between about 750° C. and about 1100° C.

16. The method of claim 14, wherein the species is at least one of boron, carbon, fluorine or nitrogen.

17. The method of claim 14, wherein the step of introducing species is formed by an ion implantation at an energy higher than or equal to 10 KeV.

18. The method of claim 17, wherein the ion implantation is performed with a dose of less than about 1E14 atoms/cm2.

19. A method for manufacturing a gate electrode, the method comprising: providing a substrate; forming a gate electrode layer over the substrate; forming a hard mask layer over the gate electrode layer; heating the hard mask layer to form a heated hard mask layer; ion implantating the heated hard mask layer to form a treated hard mask layer; patterning the treated hard mask layer and the gate electrode layer to form a gate structure of a PMOS device and a gate structure of an NMOS device; forming n-type strained source/drain regions in the substrate, wherein the n-type strained source/drain regions are adjacent to the edges of the gate structure of NMOS device; forming p-type strained source/drain regions in the substrate, wherein the p-type strained source/drain regions are adjacent to the edges of the gate structure of PMOS device; forming n-type lightly-doped source/drain regions in the n-type strained source/drain regions by a first tilt-angle ion implantation; and forming p-type lightly-doped source/drain regions in the p-type strained source/drain regions by a second tilt-angle ion implantation.

20. The semiconductor device of claim 19, wherein an etch rate of the treated hard mask layer in a 1/100 diluted by volume of liquid hydrofluoric acid solution at room temperature is less than 40 A/min.

Description:

BACKGROUND

The present disclosure relates generally an integrated circuit (IC) device and, more particularly, to method for forming a gate structure.

As technology nodes shrink, in some IC designs, there has been a desire to replace the typically polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. Providing metal gate structures (e.g., including a metal gate electrode rather than polysilicon) offers one solution. One process of forming a metal gate stack is termed “gate last” process in which the final gate stack is fabricated “last” which allows for a reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate. Additionally, as the dimensions of transistors decrease, the thickness of the gate oxide must be reduced to maintain performance with the decreased gate length. In order to reduce gate leakage, high dielectric constant (high-k) gate insulator layers are also used which allow greater physical thicknesses while maintaining the same effective thickness as would be provided by a typical gate oxide used in larger technology nodes.

There are challenges to implement such features and processes in CMOS fabrication. As technology nodes continue to decrease, particularly to the 22 nm technology node and beyond, the spacing between gate stacks continues to decrease, which affects the pocket/LDD implantation process. The issue becomes worse with a thick hard mask applied on a gate stack to increase the total thickness of the gate stack. A conventional hard mask layer needs to be thick as deposited due to its characteristics of being easily etched away in subsequent wet etch processes. If the hard mask layer is not thick as deposited, the remaining thickness of the hard mask layer after a wet etch process may not be sufficient for protecting the underlying material layer. However, the thick hard mask layer exacerbates the shadowing effects during pocket/LDD implantation process.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a flow chart of a method for fabricating an integrated circuit device according to aspects of the present disclosure; and

FIGS. 2-9 are various cross-sectional views of embodiments of an integrated circuit device during various fabrication stages according to the method of FIG. 1.

DETAILED DESCRIPTION

The present disclosure relates generally to methods for manufacturing integrated circuit devices, and more particularly, to hard mask layers utilized for manufacturing integrated circuit devices.

It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

With reference to FIGS. 1 and 2-9, a method 100 and a semiconductor device 200 are collectively described below. The semiconductor device 200 illustrates an integrated circuit, or portion thereof, that can comprise memory cells and/or logic circuits. The semiconductor device 200 can include passive components such as resistors, capacitors, inductors, and/or fuses; and active components, such as P-channel field effect transistors (PFETs), N-channel field effect transistors (NFETs), metal-oxide-semiconductor field effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOSs), high voltage transistors, and/or high frequency transistors, other suitable components, and/or combinations thereof. It is understood that additional steps can be provided before, during, and/or after the method 100, and some of the steps described below can be replaced or eliminated, for additional embodiments of the method. It is further understood that additional features can be added in the semiconductor device 200, and some of the features described below can be replaced or eliminated, for additional embodiments of the semiconductor device 200.

Referring to FIGS. 1 and 2, the method 100 begins at block 102 wherein a substrate 210 is provided. In the present embodiment, the substrate 210 is a semiconductor substrate comprising silicon. Alternatively, the substrate 210 comprises an elementary semiconductor including silicon and/or germanium in single crystal form; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. The alloy semiconductor substrate may have a gradient SiGe feature in which the Si and Ge composition change from one ratio at one location to another ratio at another location of the gradient SiGe feature. The alloy SiGe may be formed over a silicon substrate. The SiGe substrate may be mechanically strained by materials with which this substrate is in contact. Furthermore, the semiconductor substrate may be a semiconductor on insulator (SOI). In some examples, the semiconductor substrate may include a doped epi layer. In other examples, the silicon substrate may include a multilayer compound semiconductor structure.

The substrate 210 may include various doped regions depending on design requirements as known in the art (e.g., p-type wells or n-type wells). The doped regions may be doped with p-type dopants, such as boron or BF2, and/or n-type dopants, such as phosphorus or arsenic. The doped regions may be formed directly on the substrate 210, in a P-well structure, in a N-well structure, in a dual-well structure, or using a raised structure. The semiconductor substrate 210 may further include various active regions, such as regions configured for an N-type metal-oxide-semiconductor transistor device (referred to as an NMOS) and regions configured for a P-type metal-oxide-semiconductor transistor device (referred to as a PMOS). It is understood that the semiconductor device 200 may be formed by CMOS technology processing, and thus some processes are not described in detail herein.

An exemplary isolation region 212 is formed in the substrate 210 to isolate various regions of the substrate 210, and in the present embodiment, to isolate the NMOS and PMOS device regions. The isolation region 212 utilizes isolation technology, such as local oxidation of silicon (LOCOS) or shallow trench isolation (STI), to define and electrically isolate the various regions. In the present embodiment, the isolation region 212 includes a STI. The isolation region 212 comprises silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. The isolation region 212 is formed by any suitable process. As one example, the formation of an STI includes a photolithography process, etching a trench in the substrate (for example, by using a dry etching and/or wet etching), and filling the trench (for example, by using a chemical vapor deposition process) with one or more dielectric materials. In some examples, the filled trench may have a multi-layer structure such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.

A material layer is formed over the substrate 210. The material layer includes one or more material layers comprising any suitable material and thickness. The material layer can include interfacial layers, capping layers, diffusion/barrier layers, dielectric layers, high-k dielectric layers, conductive layers, gate layers, liner layers, seed layers, adhesion layers, other suitable layers, and/or combinations thereof. The material layer is formed by any suitable process including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), plating, other suitable methods, and/or combinations thereof. The semiconductor device 200 may include one or more antireflective coating layers, such as a top antireflective coating layer and/or a bottom antireflective coating layer.

In one embodiment, the material layer includes a gate dielectric layer 214 and a gate electrode layer 216. The gate dielectric layer 214 is formed over the substrate 210 by any suitable process to any suitable thickness. The gate dielectric layer 214, for example, is silicon oxide, silicon oxynitride, silicon nitride, spin-on glass (SOG), fluorinated silica glass (FSG), carbon doped silicon oxide, BLACK DIAMOND® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parlyene, BCB (bis-benzocyclobutenes), SILK (Dow Chemical, Midland, Mich.), polyimide, other suitable dielectric materials, or combinations thereof. The gate dielectric layer 214 may comprise a high-k dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HfSiO, HfZrO, other suitable high-k dielectric materials, and/or combinations thereof. The gate dielectric layer 214 can further include an interfacial layer, which comprises a grown silicon oxide layer (e.g., thermal oxide or chemical oxide) or silicon oxynitride (SiON).

The gate electrode layer 216 is formed over the gate dielectric layer 214 by any suitable process to any suitable thickness. In the present embodiment, the gate electrode layer 216 is a polysilicon layer. The polysilicon (or poly) layer is formed by CVD or other suitable deposition processes. For example, silane (SiH4) may be used as a chemical gas in the CVD process to form the gate electrode layer 216. The gate electrode layer 216 may have a thickness ranging from about 400 to about 800 angstrom (A). In another embodiment, the gate electrode layer 216 and/or the gate dielectric layer 214 may be sacrificial layers and will be removed by a replacement step after a gate patterning process.

The method 100 continues with block 104 in which a hard mask layer 218 is formed over the gate electrode layer 216 by any suitable process to any suitable thickness. The hard mask layer 218, in one embodiment, includes silicon oxide. The hard mask layer 218, in another embodiment, may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), SiOC, spin-on glass (SOG), a low-k film, tetraethylorthosilicate (TEOS), plasma enhanced CVD oxide (PE-oxide), high-aspect-ratio-process (HARP) formed oxide, amorphous carbon material, tetraethylorthosilicate (TEOS), other suitable materials, and/or combinations thereof. The silicon oxide layer may be formed using methods such as CVD, PVD, or ALD and may have a thickness ranging from about 300 to about 800 angstrom (A).

Referring to FIGS. 1 and 3, the method 100 proceeds to block 106 wherein a treatment 220 is performed on the hard mask layer 218. The treatment 220 is designed to transform the hard mask layer 218 to be more resistant to wet chemicals used in subsequent wet etch processes, such as hydrofluoric acid (HF) solution. In one embodiment, the treatment 220 may introduce additional species in the hard mask layer 218 by an energy source. The energy source of the treatment may be provided by an ion implantation process, or other suitable processes including plasma, e-beam, ultraviolet (UV), or combinations thereof. The ion implantation is preferably performed at a relatively high energy and low dose to prevent the ions from being further penetrating and/or diffusing into the underlying gate electrode layer 216. In one embodiment, the ion implantation process is performed at energy not less than about 10 KeV. In another embodiment, the ion implantation process is performed with a dose not more than about 1E14 atoms/cm2. In another embodiment, the atomic number of the ion species is preferable not more than 49, i.e., less than 50, such as to prevent damage of the hard mask layer 218. The ion implantation process is performed with a tilt angle preferably not greater than 30 degrees. The ion species of the ion implantation process, for example, includes carbon, fluorine, nitrogen, phosphorous, arsenic, indium, or combinations thereof. The treatment 220 may further comprise an annealing process before and/or after the step of introducing additional species. The duration time of the annealing process ranges from 0.1 sec. to 1800 sec. The annealing temperature ranges from 750° C. to 1100° C., and preferably ranging from 900° C. to 1050° C. The annealing may be performed by using a furnace, rapid thermal processing (RTP), hot plate, or other suitable equipment.

After performing the treatment 220, the hard mask layer 218 is transformed to a treated hard mask layer 218′. The treated hard mask layer 218′ can provide more etch resistance when exposed to a wet etch process, such as a hydrofluoric acid (HF) solution. Hence, the treated hard mask layer 218′ has an etch rate lower than the etch rate of the hard mask layer 218 in a wet etch process using HF solution. The subsequent wet etch process may utilize a diluted hydrofluoric acid (DHF) solution for a dipping process and the DHF solution may have any suitable concentration (e.g., 1:100 by volume of liquid) at a suitable temperature (e.g., elevated or room temperature). The etch rates of the hard mask layer 218 and the treated hard mask layer 218′, for example, are around 100 A/min. and less than about 40 A/min, in the DHF solution with 1/100 concentration by volume of liquid at room temperature, respectively. Since less of the treated hard mask layer 218′ is etched away (consumed) by the subsequent HF or DHF solution, the hard mask layer 218 is designed to be thinner than hard mask layer 218. Therefore, the thin hard mask layer does not cause a shadowing side effect during a subsequent pocket implantation and/or lightly doped drain (LDD) implantation. Thus, the overall device performance is improved. Further, the treated hard mask layer 218′ can function well as a hard mask to protect the underlying gate electrode layer 216 and/or define a pattern to be transferred to the gate dielectric layer 214 and the gate electrode layer 216.

Referring to FIG. 4, gate structures comprising a gate dielectric 214, a gate electrode 216, and a treated hard mask 218′ are formed by any suitable process. For example, a layer of photoresist (not shown) is formed over the treated hard mask layer 218′ by a suitable process, such as spin-on coating, and patterned to form a patterned photoresist feature. The pattern of the photoresist can then be transferred by a dry etch process to the underlying gate dielectric layer 214, the gate electrode layer 216, and the treated hard mask layer 218′ to form the gate structures. Additionally, an anti-reflective coating (ARC) layer (not shown) may be formed on the treated hard mask layer 218′ and under the layer of photoresist to enhance a subsequent patterning process as known in the art. The photolithography patterning processes may include soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, and/or combinations thereof. The photolithography exposing process may also be implemented or replaced by other proper methods such as maskless photolithography, electron-beam writing, ion-beam writing, and molecular imprint. Then, an etch process, including dry etch, wet etch, and/or other etch methods (e.g., reactive ion etch) is provided to from a gate structure for the PMOS device 240A and a gate structure for the NMOS device 240B. The photoresist layer may be stripped thereafter. It is understood that the above examples do not limit the processing steps that may be utilized to form the gate structures.

Referring to FIG. 5, offset spacers 224 are formed overlying sidewalls of the PMOS/NMOS devices 240A/240B. In an example, the offset spacers 224 are formed by blanket depositing a dielectric layer over the gate structures of PMOS/NMOS devices 240A/240B and the substrate 210, and then patterning the dielectric layer to form offset spacers 224. The dielectric layer comprises, for example, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, other suitable materials, and/or combinations thereof. The thickness of the dielectric layer is ranging from 100 A to about 300 A. The dielectric layer may be formed by using commonly used techniques, such as plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), atomic layer deposition (ALD), and the like. The patterning may be performed by either a wet etch process, a dry etch process, or combinations thereof. Preferably, the dielectric layer is patterned by a dry etch process. More preferably, the dielectric layer is patterned by an anisotropic dry etch process.

Referring to FIG. 6, recesses 226 may be optionally formed on each side of the gate structure of NMOS device 240B in the substrate 210. Recesses are not formed around the PMOS device 240A at this time because PMOS device 240A is covered by a protector 230, e.g., a photoresist pattern, thereon while the NMOS device 240B is exposed. The recesses 226 may be formed by any suitable process and are substantially aligned with edges of the offset spacers 224 of the gate structure of NMOS device 240B. The recesses 226 may be formed by a selective etch process, which can include one or more wet etch and/or dry etch processes. Then, the protector 230 may be removed by a stripping process as known in the art. Thereafter, N-type strained source/drain (NSSD) regions 228 are formed by any suitable process over the recesses 226 as illustrated in FIG. 7. In one embodiment, the NSSD regions 228 are formed by one or more epitaxial growth processes to any suitable thickness. The thickness of an exemplary NSSD region 228 is approximately 200 Å. The epitaxial process may include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxial process may use gaseous and/or liquid precursors, which may interact with the composition of the substrate 210. The NSSD regions 228 comprise any suitable material, such as epitaxially grown silicon, SiC, and/or combinations thereof. A cleaning process may be subsequently performed, such as cleaning process utilizing a DHF cleaning solution.

Subsequently, various implantation processes are performed on the substrate 210. The various implantation processes may form various doped regions. The doped regions may comprise various doping profiles and may be formed by a plurality of implantation processes. In one embodiment, N-type lightly doped source/drain (NLDD) regions 232 may be formed in or under the NSSD regions 228 by one or more ion implantation processes. The NLDD regions 232 are substantially aligned with edges of the offset spacers 224 of the gate structure of NMOS device 240B. In another embodiment, P-type pocket regions 234 may be formed adjacent to the NSSD regions 228 and under the offset spacers 224 by one or more ion implantation processes. The implantation for forming the NLDD/P-type pocket regions 232, 234 may employ tilt angle processes by any suitable angles. In one embodiment, approximately 25° to about 30° of the tilt angle is utilized. The tilt-angle implantation may be subject to shadowing side effects if the thickness of the gate structures 240B is too high. As noted above, the treated hard mask layer 218′ has a relatively low etch rate in wet etch processes, therefore, the hard mask layer 218′ can be the relatively thin to prevent from the shadowing effects during tilt angle implantation processes for forming the NLDD/P-type pocket regions.

Referring to FIG. 8, recesses 236 are formed on each side of the gate structure of PMOS device 240A in the substrate 210. A protector 238, e.g., photoresist pattern, may be formed overlying the NMOS device 240B while the PMOS device 240A is exposed. The recesses 236 are formed on each side of the gate structure of PMOS device 240A by any suitable process, and are substantially aligned with edges of the offset spacers 224 of the gate structure of PMOS device 240A. The recesses 236 may be formed by a selective etch process, which can include one or more wet etch and/or dry etch processes. Then, the protector 238 is removed by a stripping process as know in the art. The P-type strained source/drain drain (PSSD) regions 240 are formed by any suitable process over the recesses 234 as illustrated in FIG. 9. In one embodiment, the PSSD regions 240 are formed by one or more epitaxial growth processes to any suitable thickness. The thickness of an exemplary PSSD region 240 thickness is approximately 200 Å. The epitaxial process may include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxial process may use gaseous and/or liquid precursors, which may interact with the composition of the substrate 210. The PSSD regions 240 comprise any suitable material, such as epitaxially grown SiGe. A cleaning process may be subsequently performed, such as a cleaning process utilizing a DHF cleaning solution.

Subsequently, various implantation processes are performed on the substrate 210. The various implantation processes may form various doped regions. The doped regions may comprise various doping profiles and may be formed by a plurality of implantation processes. In one embodiment, P-type lightly doped source/drain (PLDD) regions 242 may be formed in PSSD regions 240 by one or more ion implant processes. The PLDD regions 242 are substantially aligned with the edges of the offset spacers 224 of the gate structure of PMOS device 240A. In another embodiment, N-type pocket regions 244 may be formed adjacent to the PSSD regions 240 and under the offset spacers 224 by one or more ion implant processes. The implantation for forming the PLDD/N-type pocket regions 242,244 may employ tilt angle processes by any suitable angles. In one embodiment, the angles for forming the PLDD/N-type pocket regions 242,244 are similar to the angles for forming the NLDD/P-type pocket regions 232,234. In one embodiment, approximately about 25° to about 30° of the tilt angle is utilized. The tilt angle implantation may be subject to shadowing side effects if the thickness of the gate structures 240A is too high. As noted above, the treated hard mask layer 218′ has the relatively low etch rate in wet etch processes, therefore, the hard mask layer 218′ is thin enough to prevent shadowing effects during tilt angle implantation processes for forming the PLDD/N-type pocket regions.

Source/drain (S/D) regions (not shown) may be formed in the substrate 210 for the NMOS/PMOS devices 240B, 240A by a conventional implantation process. One or more contact features (not shown), such as silicide regions, may also be formed by any suitable process on the S/D regions.

Subsequent processing may implement a gate replacement process. For example, metal gates may replace the gate electrode 216 (i.e., polysilicon gate layer) of the gate structures of the NMOS/PMOS devices 240B, 240A. A first metal gate having a first work function may be formed in the gate structure of the NMOS devices 240B and a second gate structure having a second work function may be formed in the gate structure of the PMOS devices 240A. The metal gates may comprise any suitable material including aluminum, copper, tungsten, titanium, tantulum, tantalum aluminum, tantalum aluminum nitride, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, silver, TaC, TaSiN, TaCN, TiAl, TiAlN, WN, metal alloys, other suitable materials, and/or combinations thereof.

Subsequent processing may form various contacts/vias/lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate 210, configured to connect the various features or structures of the semiconductor device 200. The additional features may provide electrical interconnection to the device. For example, a multilayer interconnection includes vertical interconnects, such as conventional vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may implement various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.