Title:
Determining a message residue
Kind Code:
A1


Abstract:
In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format, and perform a polynomial multiplication of the first number and the at least a portion of the first number.



Inventors:
Gopal, Vinodh (Westborough, MA, US)
Wolrich, Gilbert (Framingham, MA, US)
Feghali, Wajdi (Boston, MA, US)
Ozturk, Erdinc (Worcester, MA, US)
Gueron, Shay (Haifa, IL)
Application Number:
12/291621
Publication Date:
06/18/2009
Filing Date:
11/12/2008
Primary Class:
Other Classes:
708/400, 708/491, 714/E11.033, 708/209
International Classes:
H03M13/09; G06F5/01; G06F7/72; G06F11/10; G06F17/14
View Patent Images:



Primary Examiner:
CHAUDRY, MUJTABA M
Attorney, Agent or Firm:
INTEL CORPORATION (c/o Lisa Hopkinson 4500 S. Dobson Road, MS: OC2-157, Chandler, AZ, 85248, US)
Claims:
What is claimed is:

1. Circuitry for determining a modular remainder with respect to a polynomial of a message comprised of a series of segments, comprising circuitry to: repeatedly: access a strict subset of segments, the strict subset consisting of the most significant segments representing the message; independently multiply each of at least the two most significant segments by respective constants; transform the strict subset of segments into a smaller set of segments based on the independently multiplying each of at least the most significant segments by respective constants; and determine the modular remainder based on a set of segments output by the repeatedly accessing, multiplying, and transforming; and store the determined modular remainder.

2. The circuitry of claim 1, wherein the circuitry comprises circuitry to: simultaneously process at least one second message by repeatedly: accessing a strict subset of segments of the second message, the strict subset consisting of the most significant segments representing the second message; independently multiplying each of at least the two most significant segments of the second message by the respective constants; transforming the strict subset of segments of the second message into a smaller set of segments based on the independently multiplying each of at least the most significant segments of the second message by the respective constants.

3. The circuitry of claim 1, wherein the strict subset of segments consists of four segments and the smaller set of segments consists of two segments.

4. The circuitry of claim 1, wherein the modular remainder comprises a CRC (Cyclic Redundancy Check) value.

5. The circuitry of claim 1, wherein the constants comprise constants derived by segment size and the polynomial.

6. The circuitry of claim 5, wherein the circuitry comprises circuitry to determine a value based on the least significant of the subset of segments and the multiplication of the most significant segments by constants derived from the segment size and the polynomial.

7. The circuitry of claim 6, wherein the circuitry comprises circuitry to: access a set of constants, determined prior to accessing the message, based on at least one of: (a) the polynomial and (b) a size of a segment.

8. The circuitry of claim 1, wherein the message comprises a set of segments, S, of size n where n is an integer; wherein each constant is determined by Kn=2z mod polynomial where z is an integer that differs for different constants and n is an integer identifying a one of the constants; wherein the circuitry comprises circuitry to perform polynomial multiplication of the most significant remaining segment of S by a first one of the constants and the next most significant segment of S by a second one of the constants and xor the results with remaining segments in the strict subset of segments.

9. The circuitry of claim 1, wherein the message comprises a set of segments, S, of size n where n is an integer; wherein each constant is determined by rKn=bitreflect(2z mod polynomial)<<1, where z is an integer that differs for different constants and n is an integer identifying a one of the constants; wherein the circuitry comprises circuitry to perform polynomial multiplication of the most significant remaining segment of S by a first one of the constants and the next most significant segment of S by a second one of the constants and xor the results with remaining segments in the strict subset of segments.

10. Circuitry to: access at least a portion of a first number having a first endian format; determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format; perform a polynomial multiplication of the first number and the at least a portion of the first number.

11. The circuitry of claim 10, wherein the first number comprises a message; and wherein the circuitry comprises circuitry to determine a cyclic redundancy check (CRC) of the message.

12. The circuitry of claim 11, wherein the circuitry is to: repeatedly reduce the message into an equivalent message with respect to the resulting CRC value for the message by repeated folding of at least one most significant message segment into remaining segments.

13. The circuitry of claim 12, wherein the repeating folding comprises folding more than one most significant message segment into a same set of remaining segments.

14. The circuitry of claim 12, wherein the folding comprises multiplying a most significant segment by the second number.

15. The circuitry of claim 14, wherein the folding comprises adding the multiplying of the most significant segment by the second number to at least one remaining message segments.

16. The circuitry of claim 10, wherein the third number equals 2z mod poly where z is an integer and poly represents a polynomial.

17. Computer program instructions disposed an a computer readable storage medium, the instructions, when executed, cause a processor to determine a modular remainder with respect to a polynomial of a message comprised of a series of segments, the instructions comprising instructions to cause the processor to: repeatedly: access a strict subset of segments, the strict subset consisting of the most significant segments representing the message; independently multiply each of at least the two most significant segments by respective constants; transform the strict subset of segments into a smaller set of segments based on the independently multiplying each of at least the most significant segments by respective constants; and determine the modular remainder based on a set of segments output by the repeatedly accessing, multiplying, and transforming; and store the determined modular remainder.

18. The computer program instructions circuitry of claim 17, wherein the instructions comprise instructions to cause the processor to: simultaneously process at least one second message by repeatedly: accessing a strict subset of segments of the second message, the strict subset consisting of the most significant segments representing the second message; independently multiplying each of at least the two most significant segments of the second message by the respective constants; transforming the strict subset of segments of the second message into a smaller set of segments based on the independently multiplying each of at least the most significant segments of the second message by the respective constants.

19. The computer program instructions of claim 18, wherein the instructions cause the processor to: determine a value based on the least significant of the subset of segments and the multiplication of the most significant segments by constants derived from the segment size and the polynomial; wherein each constant is determined by Kn=2z mod polynomial where z is an integer that differs for different constants and n is an integer identifying a one of the constants; wherein the instructions comprise instructions to cause the processor to perform polynomial multiplication of the most significant remaining segment of the message by a first one of the constants and the next most significant segment of the message by a second one of the constants and xor the results with remaining segments in the strict subset of segments.

20. Computer program instructions disposed on a computer readable storage medium, the instructions comprising instructions to cause the processor to: access at least a portion of a first number having a first endian format; determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format; perform a polynomial multiplication of the first number and the at least a portion of the first number.

21. The computer program instructions of claim 20, wherein the first number comprises a message; and wherein the instructions comprises instructions to determine a cyclic redundancy check (CRC) of the message.

22. The computer program instructions of claim 21, wherein the instructions cause the processor to: repeatedly reduce the message into an equivalent message with respect to the resulting CRC value for the message by repeated folding of at least one most significant message segment into remaining segments.

23. A communications system, comprising: at least one PHY to receive signals from a communications medium, at least one MAC (media access controller) coupled to the at least one PHY; and circuitry to repeatedly: access a strict subset of segments, the strict subset consisting of the most significant segments representing the message; independently multiply each of at least the two most significant segments by respective constants; transform the strict subset of segments into a smaller set of segments based on the independently multiplying each of at least the most significant segments by respective constants; and determine the modular remainder based on a set of segments output by the repeatedly accessing, multiplying, and transforming; and store the determined modular remainder.

24. The communications system of claim 23, wherein the circuitry comprises circuitry to: simultaneously process at least one second message by repeatedly: accessing a strict subset of segments of the second message, the strict subset consisting of the most significant segments representing the second message; independently multiplying each of at least the two most significant segments of the second message by the respective constants; transforming the strict subset of segments of the second message into a smaller set of segments based on the independently multiplying each of at least the most significant segments of the second message by the respective constants.

25. The communications system of claim 23, wherein the circuitry comprises circuitry to: determine a value based on the least significant of the subset of segments and the multiplication of the most significant segments by constants derived from the segment size and the polynomial; wherein each constant is determined by Kn=2z mod polynomial where z is an integer that differs for different constants and n is an integer identifying a one of the constants; wherein the circuitry comprises circuitry to perform polynomial multiplication of the most significant remaining segment of the message by a first one of the constants and the next most significant segment of the message by a second one of the constants and xor the results with remaining segments in the strict subset of segments.

Description:

REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part and claims priority to U.S. application Ser. No. 11/959,142, attorney docket P25497, entitled “Determining A Message Residue”, filed on Dec. 28, 2007, by inventors Gilbert Wolrich, Michael Kounavis, and Vinodh Gopal, which is incorporated by reference in its entirety herein.

BACKGROUND

A variety of computer applications operate on messages to create a message residue. The residue can represent message contents much more compactly. Among other uses, message residues are frequently used to determine whether data transmitted over network connections or retrieved from a storage device may have been corrupted. For instance, a noisy transmission line may change a “1” signal to a “0”, or vice versa. To detect corruption, a message is often accompanied by its message residue. A receiver of the data can then independently determine a residue for the message and compare the determined residue with the received residue.

A common message residue is known as a Cyclic Redundancy Check (CRC). A CRC computation is based on interpreting a stream of message bits as coefficients of a polynomial. For example, a message of “1010” corresponds to a polynomial of (1 X3)+(0 x2)+(1 x1)+(0 x0) or, more simply, x3+x1. The message polynomial is divided by another polynomial known as the modulus. For example, the other polynomial may be “11” or x+1. A CRC is the remainder of a division of the message by the polynomial. CRC polynomial division, however, is somewhat different than ordinary division in that it is computed over the finite field GF(2) (i.e., the set of integers modulo 2). More simply put: even number coefficients become zeroes and odd number coefficients become ones.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating repeated reduction of message segments used to represent a message.

FIG. 2 is a flow-chart of a process to determine a message residue.

FIG. 3 is code illustrating reduction of message segments used to represent a message.

FIG. 4 is a sample execution schedule of instructions to reduce message segments used to represent a message.

FIG. 5 is a sample execution schedule of instructions to reduce message segments used to represent a message.

FIG. 6 is a diagram of a sample binary polynomial multiplication circuit.

FIG. 7 is a diagram illustrating a byte shuffle operation to re-order message bits in order of significance.

FIG. 8 is a diagram illustrating segment reduction of a message having bits arranged in little-endian format.

FIG. 9 is a diagram illustrating a relationship between multiplication of operands and multiplication of bit reflected operands.

FIG. 10 is code illustrating reduction of message segments having bits arranged in big-endian format.

DETAILED DESCRIPTION

Message residues are commonly used in many different protocols to protect data integrity. Computing these residues, however, imposes significant computational overhead. The following describes techniques that repeatedly whittle a message into a smaller set of equivalent data using fast, inexpensive operations. The resulting, smaller, set of data can then be processed, for example, in a conventional manner to arrive at a final message residue value. In other words, the more burdensome task of determining an exact value of a message residue is postponed until a message is reduced to a smaller size that retains the mathematical characteristics of the original message with respect to the residue.

In greater detail, FIG. 1 depicts a message S 100. To determine a message residue, the bits of the message S can be handled as the coefficients of a polynomial S(x). For example, a 32-bit CRC of S can be defined as:


CRC=S·232 mod g [1]

where g is a 33-bit polynomial. Different values of g have been defined for a variety of applications. For example, iSCSI (Internet Small Computer System Interface) defines a value of 11EDC6F4116 for g. Other applications have selected different polynomial sizes and values. Typically, the resulting CRC value is stored with the message, S, in the empty 32-least significant bits created by the 232 shift. Alternately, the value may be stored in a packet field or other location. Recomputing the CRC value and comparing with the stored value can indicate whether data was corrupted.

As shown, S can be represented as a series of n-bit segments, labeled S[ ], 100a-100z. The following describes techniques that successively “fold” the most significant segments into remaining segments, repeatedly reducing the amount of data used to represent S. In particular, the determination of the different values (e.g., 102, 104) to fold into the remaining segments (e.g., 100c, 100d), can be independently computed, potentially permitting parallel computation of these values. In comparison with an approach that successively folds a single segment 100a at a time, folding multiple segments 100a, 100b at each iteration can greatly decrease computation time.

In greater detail, FIG. 1 depicts the first two 108a, 108b of a series of repeated folding operations that operate on a subset of segments. In the example shown, each subset features the four most significant remaining segments representing S. For example, the initial folding operation 108a operates on segments 100a, 100b, 100c, 100d. As shown, the operation 108a includes binary polynomial multiplication 102a of the most significant segment 100a by a first pre-computed constant K2 and a binary polynomial multiplication 104 of the next most significant segment 100b by a second pre-computed constant K1. The results of these multiplications 102, 104 are folded into the remaining message segments by XORing the results with the values of the least significant segments of the subset 100c, 100d to yield segments 106a, 106b. The values of these segments 106a, 106b preserve the contribution of the most significant segments 100a, 100b to the final determination of the residue for S. Thereafter, segments 100a, 100b can be discarded or ignored for residue purposes.

As shown, the segments 106a, 106b output from the first set of folding operations 108a can be combined with the next segments of S 100e, 100f to form a new subset of segments 106a, 106b, 100e, 100f. Again, a set of folding operation 108b proceeds, folding the most significant segments 106a, 106b into segments 100e, 100f by a multiplication of segment 106a by constant K2, a multiplication of segment 106b by a constant K1, and XOR-ing the results with segments 100e, 100f to yield segments 110 (labeled S″).

This process of folding can repeat as desired to reduce the data representing S by two segments for each iteration. The reduction may be repeated any number of times. For example, in the sample implementation shown, folding may continue until only two segments remain. The residue of the final two segments (e.g., remaining-segments mod g) can be determined in a variety of ways as described below. The folding operations shown in FIG. 1 use constants K1 and K2 which can be pre-computed prior to accessing any segments of S. These constants may be determined as:


K1=2y mod g


K2=2x mod g

where x and y demarcate the boundary of the most significant segments folded into the remaining segments. For example, as shown in FIG. 1, y represents the ending bit position of segment 100b within the subset of segments 100a-100d and x represents the ending bit position of segment 100a within the subset 100a-100d. The values of x and y may vary in different implementations and architectures. For instance, for an implementation that operates on subsets of 64-bit segments, y may have a value of 128 and x may have a value of 192. However, in another 64-bit segment implementation, y may have a value of 96 and x may have a value of 160. For an implementation using 32-bit segments, x may have a value of 64 and y may have a value of 96.

The contribution of a given segment (e.g., 100a, 100b) to the message residue can, thus, be expressed as S[ ]·Kn. This technique described is well suited to execution on processors that have a Galois-field (carry-less) multiplier, though such hardware is not an implementation requirement.

Since g, x, and y, are constants, a set of K values (e.g., K1, K2, . . . ) can be pre-computed and stored prior to processing of the data values of S. Potentially, different sets of K can be pre-computed and stored for different values of g, x, and/or y. Such an implementation can quickly switch between polynomials by a lookup of a set of K values based on the particular computational setup.

Specific examples described above illustrated determination of a 32-bit CRC polynomial however the techniques described above may be applied to different sized remainders and/or polynomials. The techniques described above work also may work for arbitrary and/or non-uniform segment sizes. Additionally, while the above described folding operations 108a, 108b that operate on 4-segment subsets, other implementations may operate on a different number of segments. For example, instead of 4:2 segment reduction another implementation may feature a different segment reduction ratio. For instance, another implementation may fold more than two segments per iteration 108. Further, while the above describes a CRC message residue, the techniques described above can be used in other operations that determine a message residue or perform a modular reduction of a polynomial.

FIG. 2 illustrates a sample process for computing a message residue. As shown, after computing K values 202, the initial data segments 204 are reduced 206 to a set of fewer but equivalent data segments with respect to the residue by folding multiple segments into the remaining message at a time. If additional segments remain 208, reducing 206 continues with each reducing folding multiple segments into remaining ones. As shown, a final residue value 210 can be determined for the final set of remaining segments.

A variety of approaches can determine the final residue value such as a lookup table or a wide variety of algorithms (e.g., Barrett's reduction) to determine a modular remainder. For example, the final segments can be processed using an approach that implements the division process as multiplication. For instance, a n-bit remainder, rn, can be expressed as:


rn=L(g*·(M(s·q+))

where

L is an operation returning the b-least-significant-bits of data;

g* is the b-least-significant bits of polynomial g,

M is an operation returning the b-most-significant-bits,

q+ is the quotient of (22n/g), and

b is (width of g)−1.

Like the folding techniques described above, this approach can use pre-computed values for g* and q+ to speed computation.

FIG. 3 illustrates a sample implementation 300 of the reduction techniques described above. As shown, the inner loop of code 300 includes a sequence of 7-instructions. In this example, the high order bits of R1 and R2 initially store the value of the first segment, the low order bits of R1 and R2 initially store the value of the second segment, and a register, K, stores both K2 and K1 in the respective high and low order bits of a register.

Two of the operations (operation 3 and 4) use a binary polynomial multiplication instruction (labeled “BMUL”) that performs a polynomial multiplication over GF(2) of specified portions of the operands. That is, the instruction can operate on either the high order and/or low order half of the operands as indicated by the notation “.high” or “.low”. For example, BMUL (R1, K).low multiplies the lower half of R1 by the lower half of the register K (e.g., K1). A sample implementation of circuitry to implement this instruction is described below in conjunction with FIG. 6.

In this particular implementation, each segment is 32-bits and each register (e.g. R0, R1, R2) is 64-bits. For architectures using a 64-bit datapath and/or 64/128-bit register files, the use of 32-bit segments and constant values, K, can reduce the need to shift or mask registers to access segment and constant values during folding operations. Other implementations, however, can feature different sized segments and constants and may be tailored for other architectures.

A given set of instructions using the techniques above can be scheduled in a variety of ways to increase overall throughput. For example, FIG. 4 illustrates an instruction execution schedule 400 that operates on two different messages (“a”, “b”) in parallel. The schedule 400 shown identifies the cycle/processor execution port of the instructions 300 of the sample implementation of FIG. 3. For example, in cycle 1, inner-loop instructions 1 and 2 are executed for message “a” (labeled 1a, 2a), while in cycle 2, instruction 3 is executed for message “a” (labeled 1a) and instructions 1 and 2 are executed for message “b” (labeled 1b, 2b).

The sample schedule 400 shown in FIG. 4 reflects a processor architecture featuring multiple ports of execution, though only a single port (port0) implements or is used to execute the binary polynomial multiplication instruction. The schedule 400 also reflects an architecture where the binary polynomial multiplication instruction is a 1-cycle operation. In this sample schedule 400, each iteration of the folding process consumes 7-cycles for the inner loop and uses 4-registers (R0, R1, R2, and a register to store K1 and K2). As shown, 6 8-byte blocks are processed after 17 cycles, averaging close to 3-cycles per 8-byte block. Continued operation approaches an average of 2.5 cycles per block.

FIG. 5 depicts another schedule 500 where the binary polynomial multiplication instruction is assumed to take 3-cycles instead of 1-cycle. While this may increase the total number of instruction cycles used to perform the reduction and may increase the number of registers used, increasing the number of messages simultaneously processed can mask the increase in instruction execution time and nevertheless attain similar performance to the 1-cycle binary polynomial multiplication instruction. For example, the schedule 500 of FIG. 5 processes 4-messages (“a”, “b”, “c”, and “d”) simultaneously and, again, achieves close to 2.5 cycles per 8-byte block.

Other schedules are possible for different architectures and different instructions used to implement the folding operations than those described above. For example, a processor implementing the binary polynomial multiplication instruction on multiple processor execution ports can initiate execution of instructions 3 and 4 in the same cycle.

FIG. 6 depicts a sample of circuitry that may be used to implement the binary polynomial multiplication instruction. In particular, the instruction operates on two operands, src1 and src2. Based on the values imm1 and imm0, the circuitry selects 604, 606 the specified High (“H”) or Low (“L”) order bits of the operands to supply to the multiplier 616. The circuitry can also perform XOR-ing 616, 614 of the High and Low portions of either operand if imm2 is set. The multiplier 616 stores output to the specified destination register 618.

Expressed as pseudo-code, the circuitry implements logic for an instruction having a syntax of:


dest=BMUL(source1,source2)imm8

where the imm8 modifier is composed of imm2, imm1, imm0 bits. The values of these bits instruct the logic to perform the following operations:

imm2imm1imm0Operations
000Src1_low × src2_low
001Src1_low × src2_high
010Src1_high × src2_low
011Src1_high × src2_high
100(src1_low ⊕ src1_high) × (src2_low ⊕
src2_high)

where, in a 64-bit register implementation, low corresponds to bits [31:0] and high corresponds to bits [63:32]. The circuitry like that shown can reduce shifting and masking used to access segment/constant values. However, a wide variety of other implementation of the binary polynomial multiplication instruction are easily constructed. Additionally, other implementations may feature different circuit components, feature a different syntax, and perform different operations on operands.

Implementations of techniques described above may also vary based on the byte arrangement and endianess of message bytes. For example, FIG. 7 illustrates message bytes 700a ordered from low-order byte (byte-0) to high (byte-15) where the high order byte represents the next sequential byte of a message. However, as shown in the scenario, each byte within the message has a little-endian format 702a. Thus, the sequence of bits within the message 700a are not arranged in a linearly ascending or descending order of significance. This “saw-tooth” arrangement of bits, where the byte arrangement is the opposite of the bit endian-ness within a byte, may make computations more difficult.

To organize the bits into a linear sequence, a byte shuffle operation may be used. For example, as shown in FIG. 7, shuffling bytes of message 700a yields message 700b. Since both the bytes of message 700b and the bits within the bytes of message 700b are arranged in the same sequence of significance (high to low), the bits of message 700a linearly descend from high to low significance. As shown, pseudo-code 704 features shuffle byte (PSHUFB) instructions 706, 708 that reorder bytes of a message portion to create a linear descending arrangement of bits.

FIG. 8 depicts another scenario where the bytes 902 feature a big-endian format and the bytes are arranged from low to high significance. While the bits proceed in a linearly increasing order of significance, from the least significant bit to the most significant, the bit ordering is the exact opposite of the arrangement of message 700b in FIG. 7. Instead of rearranging the bits, however, FIG. 9 illustrates a technique that permits circuitry operating on the “reversed” message to proceed without time consuming bit or byte rearrangement. Briefly, due to the bit-agnostic property of polynomial multiplication (i.e., the columns are independent), the constants used can be computed to properly operate on the reversed message, obviating the need for bit-reflections or byte shuffles.

To illustrate, FIG. 9 shows two four-bit numbers a and b. As shown, polynomial multiplication of the bits of a and b yield the bit-values of byte c. FIG. 9 also depicts polynomial multiplication of bit-reflections of a and b, labeled ar and br, to yield the bit-values of byte d. As shown, the values of c and d, excluding the most-significant 0, mirror each other. That is, c0=d6, c1=d5, c2=d4, and c3=d3. In other words, d[6:0]=bitreflect(c[6:0]). Including the zero value of c7 and d7, d<<1=bitreflect(c). While FIG. 9 features 4-bit numbers, this relationship equally applies to larger numbers.

Circuitry can be constructed based on this relationship to permit processing of the “reverse” bit-ordering shown in FIG. 8 without bit reflections or byte shufflings. In other words, instead of rearranging the bit-sequence of the message, the procedure can operate on the bits, as is, by reflecting the constants, K, and shifting them to the left by one. Thus, as shown in FIG. 10, code 1000 performs a bit-reflection and shift of each K value to yield the rK values. This can be a one-time operation performed before processing of a message. As shown, the procedures 1000 uses the rK values in a polynomial multiplication operation with message segments similar to that shown in FIG. 3, though with constant values that reflect the bit-ordering.

The ability to operate on a reflected message may be used in other modular reduction schemes than that described above. For example, a reflected and shifted constant may be used in a scheme that folds a single segment per iteration instead of multiple segments. Additionally, the more general technique of processing a reflected bit sequence with binary polynomial multiplication of a bitreflected/shifted value may be used in a wide variety of applications.

The techniques described above can be implemented in a wide variety of logic. For example, the techniques may be implemented as circuitry (e.g., a processor element (e.g., a CPU (Central Processing Unit) or processor core) that executed program instructions disposed on a computer readable storage medium. While the logic was illustrated as programmatic instructions executed by processor circuitry, the techniques may be implemented in dedicated digital or analog circuitry (e.g., expressed in a hardware description language such as Verilog™), firmware, and/or as an ASIC (Application Specific Integrated Circuit) or Programmable Gate Array (PGA). Alternately, the circuitry may feature a combination of dedicated hardware and programmable execution (e.g., a processor that implements a program that uses a Galois-field (carry-less) multiplier or multiplier configured to handle carry-less multiplication.

The logic may be integrated within a discrete component such as a NIC (Network Interface Controller), framer, offload engine, storage processor, and so forth. For example, to process a received protocol data unit (PDU), a component may verify a CRC value included with the PDU. Alternately, for egress packets, the component may generate a CRC value for including in the PDU. Such components may include a PHY coupled to a MAC (media access controller) (e.g., an Ethernet MAC). As another example, these techniques may be implemented in blade circuitry for insertion into a chassis backplane.

Other embodiments are within the scope of the following claims.