Title:
MULTI-DIRECTIONAL TRENCHING OF A PLURALITY OF DIES IN MANUFACTURING SUPERJUNCTION DEVICES
Kind Code:
A1


Abstract:
A method of manufacturing a superjunction device includes providing a semiconductor wafer having a plurality of dies. A first plurality of trenches having a first orientation are formed in a first die. A second plurality of trenches having a second orientation are formed in a second die. The second orientation is different from the first orientation.



Inventors:
Ishiguro, Takeshi (Fukushima-ken, JP)
Sugiura, Kenji (Kawasaki-shi, JP)
Griffin, Hugh J. (Newtownabbey, GB)
Application Number:
12/031909
Publication Date:
04/02/2009
Filing Date:
02/15/2008
Assignee:
Icemos Technology Corporation (Tempe, AZ, US)
Primary Class:
Other Classes:
257/E27.07, 438/421, 257/E21.573
International Classes:
H01L21/764; H01L27/10
View Patent Images:



Primary Examiner:
PHAM, THANHHA S
Attorney, Agent or Firm:
PANITCH SCHWARZE BELISARIO & NADEL LLP (ONE COMMERCE SQUARE, 2005 MARKET STREET, SUITE 2200, PHILADELPHIA, PA, 19103, US)
Claims:
1. A method of manufacturing a superjunction device, the method comprising: (a) providing a semiconductor wafer, the semiconductor wafer including a plurality of dies; (b) forming a first plurality of trenches in at least one first die, each of the first plurality of trenches having a first orientation; and (c) forming a second plurality of trenches in at least one second die, each of the second plurality of trenches having a second orientation that is different from the first orientation.

2. The method of claim 1, wherein the a number of first dies containing the first plurality of trenches is equal to a number of second dies containing the second plurality of trenches.

3. The method of claim 2, wherein (i) each of the first plurality of trenches has a length dimension, the length dimension of each of the first plurality of trenches being identical; and (ii) each of the second plurality of trenches has a length dimension, the length dimension of each of the second plurality trenches being identical.

4. The method of claim 1, wherein the steps (a)-(c) are performed sequentially.

5. The method of claim 1, wherein the steps (b) and (c) are performed concurrently.

6. The method of claim 1, wherein prior to commencement of each of the steps (a)-(c), the respective preceding step is substantially completed.

7. The method of claim 1, wherein prior to commencement of each of the steps (a)-(c), the respective preceding step is fully completed.

8. A superjunction device formed by the method of claim 1.

9. A superjunction device comprising: (a) a semiconductor wafer, the semiconductor wafer including a plurality of dies; (b) a first plurality of trenches formed in a first plurality of dies, each of the first plurality of trenches having a first orientation; and (c) a second plurality of trenches formed in a second plurality of dies, each of the second plurality of trenches having a second orientation that is different from the first orientation.

10. The device of claim 9, wherein the first plurality of trenches defines a first area and the second plurality of trenches defines a second area.

11. The device of claim 9, wherein a ratio of the first area to the second area is one-to-one.

12. The device of claim 9, wherein (i) each of the first plurality of trenches has a length dimension, the length dimension of each of the first plurality of trenches being different from at least one other of the first plurality of trenches; and (ii) each of the second plurality of trenches has a length dimension, the length dimension of each of the second plurality of trenches being different from at least one other of the second plurality of trenches.

13. The device of claim 9, wherein (i) each of the first plurality of trenches has a length dimension, the length dimension of each of the first plurality of trenches being identical; and (ii) each of the second plurality of trenches has a length dimension, the length dimension of each of the second plurality of trenches being identical.

14. A semiconductor device comprising: (a) a semiconductor wafer, the semiconductor wafer including a plurality of dies; (b) a first plurality of trenches formed in a first plurality of dies, each of the first plurality of trenches having a first orientation; and (c) a second plurality of trenches formed in a second plurality of dies, each of the second plurality of trenches having a second orientation that is different from the first orientation.

Description:

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority to U.S. Provisional Patent Application No. 60/975,878, filed on Sep. 28, 2007, entitled “Multi-Directional Trenching in Manufacturing Superjunction Devices.”

BACKGROUND OF THE INVENTION

An embodiment of the present invention relates generally to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a superjunction device with a first plurality of trenches having one orientation and a second plurality of trenches having a second orientation different than the first orientation.

Semiconductor wafer manufacture generally refers to the process of making integrated circuits on silicon wafers. A typical semiconductor wafer is generally circular in plan view. Individual electronic circuits or devices are formed across at least one surface of the wafer and then the wafer is typically cut (sawed or diced) into a plurality of individual “dies” for packaging into individual integrated circuits (ICs).

Since the invention of superjunction devices by Dr. Xingbi Chen, as disclosed in U.S. Pat. No. 5,216,275, the contents of which are incorporated by reference herein, there have been many attempts to expand and improve on the superjunction effect of his invention. U.S. Pat. Nos. 6,410,958, 6,300,171 and 6,307,246 are examples of such efforts and are incorporated herein by reference.

Trench type superjunction devices are expected to replace multi-epi superjunction devices because of the potential lower processing cost. FIG. 1A illustrates a top plan view of a wafer 10 used in the manufacturing of a plurality of trench-type superjunction devices or dies 20. FIG. 1B shows a magnified view of two dies 20 representative of the plurality of dies 20 located on the wafer 10. Each die 20 includes a plurality of trenches 22, each of the trenches 22 traversing the die 20 in a generally horizontal orientation. FIG. 1C shows an alternate configuration wherein the plurality of trenches 22 are each oriented generally vertically on the die 20. In each case, all of the trenches 22 on all of the dies 20 of the wafer 10 have the same orientation. FIG. 1D illustrates an enlarged partial cross-sectional view of a die 20 having a plurality of trenches 22 formed in a silicon layer 12 disposed on a substrate 11. A plurality of corresponding mesas 24 are thereby formed, each mesa 24 being capped by a layer of oxide 26. The trenches 22 are typically filled with a refill material 28.

Generally, the cost of semiconductor device manufacturing has been reduced by condensing the design rules (recommended parameters) and enlarging the diameter of the process wafer. The design rules reduction may be applied to trench-type superjunction technology, as described in co-pending {Inser 35UI1 Ap No. when filed}. However, conventional trenching methods tend to cause wafer bowing and warping. Such deformations are especially prevalent when trenching large diameter wafers (e.g., greater than about six inches). Once bowing and warping occurs, a wafer typically can no longer be processed effectively, if at all. Further, even if the wafer remains capable of processing, there is a higher risk of chipping or breakage. The degree of bowing and/or warping is greater when using deep trenching, such as the type of deep trenching used, for example, in the formation of superjunction devices. Thus, the use of conventional trenching methods for manufacturing superjunction devices does not permit the cost reduction achieved by increasing the diameter of the wafer.

It is desirable to provide a method of manufacturing trench-type superjunction devices that minimizes and/or eliminates the effects of bowing and warping. It is further desirable to provide a method of manufacturing trench-type superjunction devices that reduces manufacturing costs by enabling the use of larger wafer diameters.

BRIEF SUMMARY OF THE INVENTION

Briefly stated, embodiments of the present invention comprise a method of manufacturing a superjunction device. One embodiment of the method includes providing a semiconductor wafer having a plurality of dies. The method further includes forming a first plurality of trenches in at least one first die, each of the first plurality of trenches having a first orientation. The method also includes forming a second plurality of trenches in at least one second die, each of the second plurality of trenches having a second orientation that is different from the first orientation.

Embodiments of the present invention also comprise superjunction devices. In one embodiment, the superjunction device includes a semiconductor wafer having a plurality of dies. A first plurality of trenches are formed in a first plurality of dies. Each of the first plurality of trenches has a first orientation. A second plurality of trenches is formed in a second plurality of dies. Each of the second plurality of trenches has a second orientation that is different from the first orientation.

Yet another embodiment of the present invention comprises other types of semiconductor devices formed on or in a semiconductor wafer. The semiconductor wafer includes a plurality of dies. A first plurality of trenches are formed in a first plurality of dies. Each of the first plurality of trenches has a first orientation. A second plurality of trenches is formed in a second plurality of dies. Each of the second plurality of trenches has a second orientation that is different from the first orientation.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing summary, as well as the following detailed description of preferred embodiments of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustration, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.

FIG. 1A is a top plan view of a prior art semiconductor wafer having a plurality of dies formed thereon;

FIG. 1B is a greatly enlarged top plan view of two adjacent dies from the prior art wafer of FIG. 1A;

FIG. 1C is a greatly enlarged top plan view of two alternate adjacent dies from the prior art wafer of FIG. 1A;

FIG. 1D is an enlarged partial cross-sectional elevational view of one of the dies from either of FIGS. 1B or 1C;

FIGS. 2A-2C are greatly enlarged top plan views of dies manufactured in accordance with preferred embodiments of the present invention;

FIGS. 3A and 3B are greatly enlarged top plan views of adjacent dies on a wafer manufactured in accordance with preferred embodiments of the present invention;

FIG. 4A is an enlarged cross-sectional elevational view of a portion of a die after an oxide layer is disposed on a silicon layer in accordance with a preferred embodiment;

FIG. 4B is an enlarged cross-sectional elevational view of a portion of the die of FIG. 4A after trenches are formed thereon in accordance with a preferred embodiment; and

FIG. 4C is an enlarged cross-sectional elevational view of a portion of the die of FIG. 4B after the trenches are filled with a refill material in accordance with a preferred embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Certain terminology is used in the following description for convenience only and is not limiting. The words “right”, “left”, “lower”, and “upper” designate directions in the drawings to which reference is made. The words “inwardly” and “outwardly” refer to directions toward and away from, respectively, the geometric center of the device and designated parts thereof. The terminology includes the above-listed words, derivatives thereof, and words of similar import. Additionally, the words “a” and “an”, as used in the claims and in the corresponding portions of the specification, mean “at least one.”

As used herein, reference to conductivity will be limited to the embodiment described. However, those skilled in the art know that p-type conductivity can be switched with n-type conductivity and the device would still be functionally correct (i.e., a first or a second conductivity type). Therefore, where used herein, reference to n or p can also mean either n or p or p and n can be substituted therefor.

Furthermore, n+ and p+ refer to heavily doped n and p regions, respectively; n++ and p++ refer to very heavily doped n and p regions, respectively; n and p refer to lightly doped n and p regions, respectively; and n−− and p−− refer to very lightly doped n and p regions, respectively. However, such relative doping terms should not be construed as limiting.

Referring to the drawings in detail, wherein like reference numerals indicate like elements throughout, there is shown in FIG. 2A a top plan view of an individual die 220a manufactured in accordance with a preferred embodiment of the present invention. A plurality of trenches 222a are formed on the die 220a, the trenches 222a having a first orientation, depicted in FIG. 2A as being vertical. A further plurality of trenches 223 a are also formed on the die 220a, the trenches 223a having a second orientation, depicted in FIG. 2A as being horizontal. In the embodiment depicted in FIG. 2A, the first and second trench orientations differ by approximately 90°, but the trenches 222a, 223a may be formed at other angles relative to one another, such as, for example, 45°. By utilizing more than one trench direction within the die 220a, stress is reduced on the die 220a and the overall wafer.

Embodiments of the present invention are not limited to the example illustrated in FIG. 2A. There is no restriction on orientations, angles, lengths, widths, and/or shapes of trenches 222a, 223a. There is also no restriction on the number of trenches 222a, 223a or combinations available on the die 220a.

In preferred embodiments, an area occupied by trenches 222a of one orientation should be generally equal in size to an area occupied by trenches 223a of another orientation. Preferably, the trenches 222a, 223a are located on the die 220a generally symmetrically. The configurations of the trenches 222a, 223 a reduce the mechanical stress placed on the die 220a and overall wafer to thereby reduce bowing or warping of the wafer. FIG. 2B illustrates a second embodiment of a die 220b, including vertical trenches 222b and horizontal trenches 223b. Die 220b maintains about a 1:1 area ratio (as described above) of trenches 222b, 223b despite the irregular configuration.

FIG. 2C illustrates a further embodiment of a die 220c, which features a different type of trenching pattern. The die 220c includes a plurality of trenches 222c that are angled at about 45° from the horizontal direction and a plurality of trenches 223c that are angled at about 135° from the horizontal direction. The trenches 222c, 223c are grouped with similarly oriented trenches to form square patterns on the die 220c. FIG. 2C thus illustrates an example where the die 220c may include trenches 222c, 223c of various lengths while continuing to maintain about a 1:1 area ratio convenient for minimizing stress on the wafer.

FIG. 3A illustrates an alternative embodiment of the present invention. The dies 320a, 321a shown are formed adjacent to one another on a wafer, such as the wafer 10 shown in FIG. 1A. In each die 320a are formed a plurality of trenches 323a oriented in a horizontal direction. In each die 321a are formed a plurality of trenches 322a oriented in a vertical direction. Unlike in the previous embodiments of FIGS. 2A-2C, each die 320a, 321a in FIG. 3A includes trenches 323a, 322a formed in only one orientation. The mechanical stress on the overall wafer is thereby reduced by, as shown in FIG. 3A, placing dies 320a, 321a having trenches 323a, 322a oriented in different directions adjacent to one another. Although the length of each of the trenches 322a is greater than the length of each of the trenches 323a, the number of trenches 323a is greater than the number of trenches 322a. As a result, the overall area covered by the trenches 322a and 323a are about the same. Particularly in FIG. 3A, a wafer would include a pattern of dies 320a, 321a wherein every other die 320a, 321a in both horizontal and vertical directions on the wafer would include identical trench orientations.

FIG. 3B depicts a configuration of the dies 320b, 321b as an alternative to that shown in FIG. 3A. Extrapolating the configuration of FIG. 3B over an entire wafer would result in a row (or column) of dies 320b having horizontally oriented trenches 323b, a row (or column) of dies 321b having vertically oriented trenches 322b, and so forth.

It is understood by those skilled in the art that orientations of the trenches 322, 323 in each die 320, 321 are not limited to the embodiments described above. The dies 320, 321 are also not limited to being rectangular in shape and may be designed in any manner convenient for use in superjunction devices, for example, square, rectangular, circular, polygonal, or the like.

Embodiments of the present invention may be employed not only in superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET) devices, but also in Schottky devices or any devices that require deep, refilled trenches, including microelectromechanical systems (MEMS).

Embodiments of the present invention, such as those shown in FIGS. 2A-2C and 3A-3B, allow for the manufacture of larger diameter semiconductor wafers having a bow of less than 100 microns. Preferably, the wafer bow is reduced to below 50 microns on, for example, an eight inch diameter wafer.

Referring to FIGS. 4A-4C, a process for manufacturing a superjunction device in accordance with embodiments of the present invention is described. FIG. 4A shows a partial cross-sectional elevational view of a die 420 as part of a wafer (not shown). The die 420 includes a semiconductor material layer 412 that may be doped as necessary. Preferably, the semiconductor material layer 412 is silicon. But, the semiconductor material layer 412 may be formed of other materials such as silicon carbide, gallium arsenide, germanium, or the like. In the example of FIGS. 4A-4C, the semiconductor material layer 412 is an n-type epitaxial silicon layer that is disposed on a heavily doped substrate layer 411. Although both layers 411, 412 are shown in FIG. 4A as having n-type conductivity, it is understood that one or both layers 411, 412 may instead have p-type conductivity. Other layers not shown may be included in the die 420 as required. A temporary layer used to handle the overall wafer may also be included.

An oxide or other dielectric layer 426 is disposed above the silicon layer 412. The oxide layer 426 is applied using one of thermal growth, low pressure (LP) chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), and deposition or some other process. The oxide layer 426 is preferably formed of an oxide. Alternatively, the oxide layer 426 may be a nitride, silicon-oxynitride, or other known dielectrics.

Known processing techniques such as grinding, polishing and etching may be performed to obtain a desired thicknesses of the substrate 411, silicon layer 412, oxide layer 426, and any additional layers. Generally, semiconductor wafers are coarsely thinned by a grinding machine having a rough grinding wheel or grinding pad such as a diamond or carbide wheel or pad having for example, diamond impregnated resin teeth. Grinding the wafer also allows for thinner, and therefore, smaller IC packages. Generally, polishing is a finer process using a wet silica-particle slurry which is washed across the surface of the wafer at a predetermined flow rate and is referred to as chemical mechanical polishing (CMP). Optionally, surfaces of the wafer are thinned by grinding and then polishing.

Referring to FIG. 4B, trenches 422 are formed in the die 420 through the oxide layer 426 and at least partially through the silicon layer 412, forming mesas 424. In the example of FIG. 4B the trenches 422 extend completely through the silicon layer 412 to the substrate 411, but the trenches 422 may extend to any desired depth. A photoresist patterning layer (not shown) may be disposed above the oxide layer 426 to provide a pattern for etching the trenches 422. Preferably, the trenches 422 are formed by utilizing known techniques such as plasma etching, reactive ion etching (RIE), sputter etching, vapor phase etching, chemical etching, deep RIE, or the like. Deep RIE technology permits deeper trenches 422 with straighter sidewalls. Furthermore, forming deeper trenches 422 that have straighter sidewalls than conventionally etched or formed trenches, in addition to other steps in the process, results in a final superjunction device with enhanced avalanche breakdown voltage (Vb) characteristics as compared to conventional semiconductor-transistor devices.

The sidewalls of each trench 422 can be smoothed, if needed, using, for example, one or more of the following process steps: (i) an isotropic plasma etch may be used to remove a thin layer of silicon (typically 100-1000 Angstroms) from the trench 422 surfaces or (ii) a sacrificial silicon dioxide layer may be grown on the surfaces of the trench 422 and then removed using an etch such as a buffered oxide etch or a diluted hydrofluoric (HF) acid etch. The use of the smoothing techniques can produce smooth trench 422 surfaces with rounded corners while removing residual stress and unwanted contaminates. However, where it is desirable to have vertical sidewalls and square corners, an anisotropic etch process may be used instead of the isotropic etch process discussed above. Anisotropic etching, in contrast to isotropic etching, generally means different etch rates in different directions in the material being etched.

The trenches 422 shown in FIG. 4B are formed in accordance with embodiments of the present invention described above. That is, sets of trenches 422 are formed having differing orientations on an individual die 420, or alternatively, trenches 422 formed on one die 420 have a different orientation than trenches 422 formed on an adjacent die 420.

The sidewalls of the trenches 422 are subsequently implanted or doped with a p-dopant such as boron (P) using any techniques known in the art. However, in some cases n-type doping may be required for the mesas 424 prior to the p-type doping of the trench 422 sidewalls. Preferably, the implants are performed without benefits of a masking step, e.g., at an implantation angle Φ (not shown) determined by the width and the depth of the trenches 422, at a high energy level in the range of about 40 Kilo-electron-volts (KeV) to several Mega-eV. Preferably, the energy level is in the range of about 200 KeV to 1 MeV, but it should be recognized that the energy level should be selected to sufficiently implant the dopant. The use of the predetermined implantation angle Θ ensures that only the sidewalls and not the bottoms of the trenches 422 are implanted.

In the manufacture of prior art devices, the implantation angle Θ is typically between 2° and 12°. The wafer is also oriented at one, or often two “twist angles,” i.e., the relative orientation of the wafer in a plane defined by the wafer with respect to the ion beam. The most common angles are 0° and 180°. In accordance with preferred embodiments however, more twist angles may be required, for example, the wafer may be oriented at 45°, 135°, 225°, and 315° during processing. The twist angles required for ion implantation are often governed by restrictions imposed by the manufacturing apparatus. Therefore, embodiments of the present invention are in no way limited to the values or number of twist angles described above.

Following implanting the p-type implant on the sidewalls of the trenches 422, a drive-in step (i.e., a diffusion) is performed using any known techniques to create p-type doped regions (see FIG. 4C) proximate the sidewalls of the trenches 422. Preferably, a temperature and a time period for the drive-in step are selected to sufficiently drive in the implanted dopant into the mesas 424. For example, for p-type doping, the drive-in step (i.e., a diffusion) may be performed at a temperature of about 1150-1200° Celsius for about 1-2 hours. Alternatively, for n-type doping, the drive in step may be performed at a temperature of up to about 1200° C. for up to about 24 hours.

An optional oxidation step, usually performed in a steam or oxygen ambient, can also be performed with or subsequent to the drive-in step, which forms a silicon dioxide layer (not shown) on the sidewalls and the bottoms of the trenches 422. A thin layer of silicon nitride (not shown) can also be deposited on the sidewalls and the bottoms of the trenches 422. Deposition of silicon nitride on thermally oxidized silicon wafers does not influence the fundamental properties of the Si—SiO2 interface. The existence of silicon nitride makes surface potential stable or unstable according to the structures, partly due to the existence of hydrogen in silicon nitride. Hydrogen can influence electric properties. The layer of silicon nitride also serves the function to isolate and protect the silicon and silicon oxide from a refill material to be deposited in trenches 422.

The lining of the trenches 422 with silicon nitride can be performed in general by CVD (thermal or plasma). The lining of the trenches 422 with silicon dioxide can be performed in general by CVD (thermal, plasma, or spun-on-glass (SOG)). The lining of the trenches 422 with silicon dioxide and/or silicon nitride can preferably be performed using application of tetraethylorthosilicate (TEOS) because of the better conformity achieved by TEOS. Preferably, the silicon nitride is about 100 Å to about 10,000 Å thick (1 μm=10,000 Å).

Referring to FIG. 4C, the trenches 422 are then filled with a temporary or permanent refill material 428 such as a semi-insulating material, an insulating material, or a combination thereof. The refill material 428 can be a polysilicon, a re-crystalized polysilicon, a single crystal silicon, or a semi-insulating polycrystalline silicon (SIPOS). The trenches 422 may be filled using a SOG technique, CVD, surface reflow, or other methods known in the art. For example, the trenches 422 can be refilled with SIPOS. The amount of oxygen content in the SIPOS is selectively chosen to be between 2% and 80% to improve the electrical characteristics in the die 420. Increasing the amount of oxygen content is desirable for electrical characteristics, but varying the oxygen content also results in altered material properties. Higher oxygen content SIPOS will thermally expand and contract differently than the surrounding silicon which may lead to undesirable fracturing or cracking especially near the interface of differing materials. Accordingly, the oxygen content of the SIPOS is optimally selected to achieve the most desirable electrical characteristics without an undesirable impact on mechanical properties.

It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that the invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims.