Title:
Dynamic design of solar cell structures, photovoltaic modules and corresponding processes
Kind Code:
A1


Abstract:
Photovoltaic modules can be formed with a plurality of solar cells having different sized structures to improve module performance. The sized can be determined dynamically based on estimated properties of the semiconductor so that the current outputs of the cells in the module are more similar to each other. The modules can produce higher power relative to modules with similar equal sized cells that do not produce matched currents. Appropriate dynamic processing methods are described that include processing steps that provide adjustments of the processing according to the dynamic adjustments in cell designs.



Inventors:
Hieslmair, Henry (San Francisco, CA, US)
Application Number:
12/070381
Publication Date:
08/28/2008
Filing Date:
02/15/2008
Primary Class:
Other Classes:
136/252, 136/258, 219/121.72, 257/E21.135, 257/E31.011, 438/93
International Classes:
H01L31/028; B23K26/00; H01L21/22; H01L31/042
View Patent Images:



Primary Examiner:
AYAD, TAMIR
Attorney, Agent or Firm:
DARDI & ASSOCIATES, PLLC (220 S. 6TH ST., SUITE 2000, U.S. BANK PLAZA, MINNEAPOLIS, MN, 55402, US)
Claims:
What we claim is:

1. A photovoltaic module comprising a transparent substrate and a plurality of series-connected solar cells attached to the transparent substrate, wherein the area of at least two cells are different from each other and wherein the difference in area of the cells results in a better match of current output of the individual cells relative to cells of equal area with the same respective photo-conversion efficiency as the particular cells of the module.

2. The photovoltaic module of claim 1 wherein the solar cells comprise polycrystalline silicon/germanium.

3. The photovoltaic module of claim 1 wherein the solar cells comprise a silicon/germanium layer having an average thickness form about 5 microns to about 100 microns.

4. The photovoltaic module of claim 1 wherein the plurality of solar cells comprises at least 10 solar cells and wherein the area of at least two of the solar cells differ from each other by at least about 5% relative to the average area.

5. The photovoltaic module of claim 1 wherein the current output of the cells under uniform illumination with sun light differ from each other by no more than about 5 percent.

6. A solar cell comprising a semiconductor sheet having a front surface configured to receive light and a rear surface opposite the front surface, p-dopant regions and n-dopant regions located along the rear surface, and two electrical interconnects providing respectively electrical contact between the p-dopant regions and the n-dopant regions, wherein p-dopant regions and the n-dopant regions are not symmetrically located along the rear surface.

7. The solar cell of claim 6 wherein the semiconductor sheet comprises polycrystalline silicon/germanium.

8. The solar cell of claim 7 wherein the semiconductor sheet has an average thickness from about 5 microns to about 100 microns.

9. The solar cell of claim 7 wherein the dopant regions comprise doped silicon/germanium extending from the rear surface of the sheet.

10. The solar cell of claim 7 wherein the dopant regions comprise dopant extending into the rear surface of the semiconductor sheet at selected locations.

11. The solar cell of claim 6 wherein the dopant regions are on a checker board configuration with alternating n-doped and p-doped regions wherein the squares of the checker board are unequal in size.

12. The solar cell of claim 6 wherein the dopant regions are arranged in rows with p-doped regions within selected rows and n-doped regions in other rows wherein the spacing of the rows, the spacing of regions within a row or both are non-uniform.

13. The solar cell of claim 6 wherein the dopant regions are positioned within windows through a dielectric layer associated with the rear surface and wherein the respective electrical interconnect fills the windows with an electrically conductive material while electrically connecting the appropriate dopant regions.

14. A method for subdividing a semiconductor sheet for use as individual photovoltaic cells within a photovoltaic module, the method comprising cutting the semiconductor sheet into unequal area subsections based on measurements along the semiconductor sheets, wherein the measurements are correlated with expected current generated for an area of the semiconductor material at the measured location.

15. The method of claim 14 wherein the semiconductor sheet comprises polycrystalline silicon/germanium.

16. The method of claim 14 wherein the cutting is performed using a laser.

17. The method of claim 14 wherein the semiconductor sheet has a thickness from about 5 microns to about 100 micron and wherein the cutting is performed with the semiconductor sheet adhered to a support sheet.

18. The method of claim 14 wherein the measurement is performed optically.

19. A method for producing a solar cell comprising depositing dopants in association with a semiconductor layer in an un-symmetric pattern based on performance measurements for semiconductor layer.

20. The method of claim 19 wherein the semiconductor sheet comprises polycrystalline silicon/germanium having an average thickness from about 5 microns to about 100 microns and wherein p-dopants and n-dopants are deposited along a rear surface of the semiconductor sheet through windows in a dielectric layer.

21. The method of claim 19 wherein p-dopants and n-dopants are deposited at selected locations and wherein the dopant regions are on a checker board configuration with alternating n-doped and p-doped regions wherein the squares of the checker board are unequal in size.

22. The method of claim 19 wherein p-dopants and n-dopants are deposited at selected locations and wherein the dopant regions are arranged in rows with p-doped regions within selected rows and n-doped regions in other rows wherein the spacing of the rows, the spacing of regions within a row or both are non-uniform.

23. The method of claim 20 further comprising depositing two current collectors respectively providing electrical connections between p-doped regions and n-doped regions.

Description:

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. provisional patent application Ser. No. 60/902,006 filed Feb. 16, 2007 to Hieslmair, entitled “Photovoltaic Cell Structures, Solar Panels and Corresponding Processes,” incorporated herein by reference.

FIELD OF THE INVENTION

The invention relates to photovoltaic cells, photovoltaic modules and processes for the formation of these devices in which processing parameters are selected dynamically based on semiconductor property measurements. In some embodiments, the invention relates to rear point contacted photovoltaic cells and corresponding modules, which may comprise thin films of silicon/germanium semiconductor material.

BACKGROUND OF THE INVENTION

Various technologies are available for the formation of photovoltaic cells, e.g., solar cells. A majority of commercial photovoltaic cells are based on silicon. With non-renewable energy sources continuing to increase in price, there is continuing interest in alternative energy sources. Increased commercialization of alternative energy sources relies on increasing cost effectiveness through lower costs per energy unit, which can be achieved through improved efficiency of the energy source and/or through cost reduction for materials and processing.

Photovoltaic cells operate through the absorption of light to form electron-hole pairs. A semiconductor material can be conveniently used to absorb the light with a resulting charge separation. Current is harvested at a voltage differential to perform useful work in an external circuit, either directly or following storage with an appropriate energy storage device.

SUMMARY OF THE INVENTION

In a first aspect, the invention pertains to a photovoltaic module comprising a transparent substrate and a plurality of series-connected solar cells attached to the transparent substrate. In some embodiments, the area of at least two cells are different from each other, and the difference in area of the cells results in a better match of current output of the individual cells relative to cells of equal area with the same respective photo-conversion efficiency as the particular cells of the module.

In a further aspect, the invention pertains to a solar cell comprising a semiconductor sheet having a front surface configured to receive light and a rear surface opposite the front surface, p-dopant regions and n-dopant regions located along the rear surface, and two electrical interconnects providing respectively electrical contact between the p-dopant regions and the n-dopant regions. In some embodiments, the p-dopant regions and the n-dopant regions are not symmetrically located along the rear surface.

In another aspect, the invention pertains to a method for subdividing a semiconductor sheet for use as individual photovoltaic cells within a photovoltaic module. The method can comprise cutting the semiconductor sheet into unequal area subsections based on measurements along the semiconductor sheets. The measurements can be correlated with expected current generated for an area of the semiconductor material at the measured location.

In additional aspects, the invention pertains to a method for producing a solar cell comprising depositing dopants in association with a semiconductor layer in an un-symmetric pattern based on performance measurements for semiconductor layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic side perspective view of a photovoltaic module with a portion of the backing layer removed to expose some of the solar cells within the module.

FIG. 2 is a sectional side view of the photovoltaic module of FIG. 1 taken along line 2-2 of FIG. 1.

FIG. 3 is a bottom view of a photovoltaic module with the backing layer removed to expose the solar cells within the module.

FIG. 4 is a bottom perspective view of an individual solar cell.

FIG. 5 is a sectional view of the solar cell of FIG. 5 taken along line 5-5 of FIG. 4.

FIG. 6 is a bottom view of a semiconductor substrate with the current collectors removed to expose dopant domains through holes drilled through a passivation layer.

FIG. 7 is a bottom view of an alternative embodiment of a solar cell.

FIG. 8 is a bottom view of the solar cell of FIG. 7 prior to application with the current collectors removed to expose dopant domains within holes through a passivation layer.

FIG. 9 is a flow diagram indicating the process of module preparation, although the particular steps can have sub-steps that are performed in a different order relative to the overall process of the flow diagram.

FIG. 10A is a bottom view of a semiconductor sheet with a dynamic cell selection indicated.

FIG. 10B is a bottom view of the sheet of FIG. 10A following the cutting of the cells and the drilling of holes for dopant placement.

FIG. 11 is a bottom view of a semiconductor sheet showing cut cell after real time cell selection.

FIG. 12 is a flow diagram indicating steps for solar cell processing, although the order shown in the diagram is not necessarily the processing order.

DETAILED DESCRIPTION OF THE INVENTION

Dynamic processing approaches described herein for forming photovoltaic modules can provide more efficient solar cells and corresponding photovoltaic modules that produce higher power for a relatively fixed amount of materials within the module. In particular, photovoltaic modules can be formed from larger sheets of semiconductor material that can be measured to map out the expected performance characteristics across the sheet. The measurements of anticipated performance properties of the semiconductor material provide a basis for the dynamic processing of the semiconductor. In some embodiments, processing approaches are directed to the formation of electrically connected photovoltaic cells with rear connections. The improved processes are suitable for thin semiconductor film processing, although the approaches can also be used for thicker semiconductor layer processing.

Some of the processing improvements described herein are particularly suitable for module level processing of a plurality of cells simultaneously. Doping approaches described herein are suitable for real time selection of dopant placement. Through the inspection of the semiconductor material and real time dopant deposition, the individual cell size and location can be selected to produce similar currents so that the overall power generation of the module can be improved. These power improvement approaches and corresponding processing steps can generally be used for any type of solar cell using a range of semiconductor materials.

Photovoltaic modules generally comprise a transparent front sheet that is exposed to sunlight during use of the module. The solar cells, i.e., photovoltaic cells, within the photovoltaic module can be placed adjacent to the transparent front sheet such that light transmitted through the transparent front sheet can be absorbed by a semiconductor material in the solar cell. The transparent front sheet can provide support, physical protection as well as protection from environmental contaminants and the like. The photovoltaic cells are generally connected in series to increase the available voltage of the module. A photovoltaic module can comprise sets of connected parallel photovoltaic cells along with the sets of cells connected in series. The active material of a photovoltaic cell is generally a semiconductor. Following absorption of light, photocurrent can be harvested from the conduction band to perform useful work through connection to an external circuit.

Doped contact regions interfacing with the semiconductor material facilitate the harvesting of the photocurrent. In particular, electronic and holes can segregate to the respective n+-doped and p+-doped regions. The doped-contact regions interface with electrical conductors to form current collectors to harvest the photocurrent formed by absorbing light to generate a potential between the two poles of the contacts. Within a single cell, the doped contact regions of like polarity are connected to a common current collector, such that the two current collectors associated with the different polarities of doped contacts form the counter electrodes of the photovoltaic cell.

While the voltages are additive for solar cells connected in series, the current of the series of cells depends on the performance of the individual solar cells. In particular, the current through the series of cells is essentially the current capability of the poorest current delivering solar cell in the series since the weakest solar cell cannot support a higher current at a common illumination level. Power available from higher performance cells is lost trying to push current through the lower performing cells. The power from series connected solar cells is the product of the current times the voltage of the unit. The current of a particular cell can be a function of the carrier lifetime, which is related to the efficiency for harvesting current from populated conduction bands upon absorption of light. Generally, the efficiency of the cell is also related to the design of the cell, for example, with respect to division of the cell into p+-doped and n+-doped regions and placement of the doped regions.

In some embodiments of improved modules described herein, the size of the individual cells can be sized based on measured properties of the semiconductor material that is formed into the photovoltaic cells. Thus, the collection of cells for a module can be selected to have significantly smaller differences in current capabilities relative to corresponding cells cut with equal size. This selection of cell areas can be particularly convenient when the individual cells are divided or cut from a larger sheet so that the area of the sheet can be effectively and appropriately divided. Specifically, a semiconductor sheet can be evaluated to estimate minority carrier lifetimes, which is the primary determinant of performance, at selected locations along the surface of the semiconductor. In general, the measurements of the semiconductor properties can be performed before or after formation of p-doped and/or n-doped contacts, although dopant contact placement can also be performed dynamically if the measurements are performed prior to dopant deposition. These estimates can provide the basis for dividing the total area of the semiconductor material into more even current generating cells with unequal sizes. The size of the cells can be selected based on the real time measurements in a dynamic rather than static process. The cut cells can then be assembled into a single photovoltaic module, a plurality of modules or a portion of a module.

The placement of dopant contact regions within a cell influences performance of a cell. In particular, the spacing of p+-doped regions with respect to n+-doped regions as well as the size of the doped regions can influence cell performance. Similarly, the area attributed to differently doped contact regions, i.e., p+-doped and n+-doped regions, can be balanced based on estimated performance properties across the cell. Thus, the number and/or placement and/or size of n+-doped regions and p+-doped regions can be selected to improve current generation efficiency of an individual cell. The ability to select the number and/or placement and/or size of doped contact regions within an individual cell is based upon the ability to selectively deposit the dopants in real time based on the dynamic evaluation of the desired dopant locations. Using real time evaluation, the individual cells can be designed dynamically rather than statically as an alternative or addition to dynamic selection of overall solar cell sizes. The processing approach generally can also influence the placement and size of the doped regions at least with respect to available ranges.

Generally, the dynamic processing approaches described herein can be applied for photovoltaic structures based on any type of semiconductor material, such single crystalline silicon, polycrystalline silicon, amorphous silicon, cadmium selenide, cadmium telluride, CIS alloys and the like. CIS alloys refer to chalcogenide alloys generally involving Cu, In, Ga, Se and S. The semiconductor sheets generally can be doped to increase charge mobility, although the overall dopant levels across the semiconductor layer are less than the dopant levels of appropriate corresponding doped contacts.

In the following, embodiments of particular interest based on polycrystalline silicon are discussed in more detail, although appropriate portions can be generalized for other semiconductor systems based on the disclosure herein. Furthermore, thin silicon films can be suitable for dynamic processing in which the films have a thickness form about 5 microns to about 100 microns. These thin films make effective use of materials while providing an efficient format for subdividing the films according to the approaches described herein to improve output of cells and modules. The formation of these thin films is made possible as a result of revolutionary process approaches described further below.

In embodiments of particular interest, the photovoltaic module comprises a silicon, germanium or silicon-germanium alloy material that is used for the semiconductor substrate. For simplicity of discussion, the reference in the specification to silicon implicitly refers to silicon, germanium, silicon-germanium alloys and blends thereof, unless indicated otherwise in context. In the claims, silicon/germanium refers to silicon, germanium, silicon-germanium alloys and blends thereof.

Metal or other electrically conducting material connects to the doped semiconductor regions as a current collector within a cell. The current collectors of adjacent cells can be joined with electrical connections to connect the cells in series. The end cells in the series can be connected to an outside circuit to power selected applications or to charge an electrical storage device, such as a rechargeable battery. The photovoltaic module can be mounted on a suitable frame.

In general, a photovoltaic cell comprises a photoconducting semiconductor structure with a front surface designed for receiving light. The front surface may have an antireflective coating and/or a texture or the like. The front surface generally is designed for placement adjacent a transparent layer, such as a silica glass layer, within a photovoltaic module. The rear surface of the cell faces away from the transparent front sheet, and generally provides for at least some of the electrical connections to the cell. The module generally can have a rear seal, which may function together with a front transparent material and/or frame, to protect the solar cells in the photovoltaic module from moisture and other environmental contaminants. Appropriate electrical connections extend from the sealed module.

The semiconductor doped regions can be formed as doped domains along the semiconducting material, in which the doped domains can extend into the semiconductor material and/or extend from the surface of the semiconductor material. Various contact structures have been designed for photovoltaic cells. For example, some cells have one type of doped region on the front surface and a second type of doped region on the rear surface. Generally, any front placed doped regions need to be in electrical contact with a current collector that extends to connect the contact with the opposite pole of an adjacent cell for a series connection or to an external circuit. In some embodiments, each cell has doped regions of opposite polarity both along the rear or back side of the cell. Placement of the doped regions of both polarities on the rear surface can provide convenient processing while less processing is directed to the front surface. For rear connected solar cells, the front surface can be free of structures that may interfere with access to irradiation of the semiconductor material with light.

P+-doped regions generally comprise an electron deficient dopant, such as B, Al, Ga, In or combinations thereof. N+-doped regions generally comprise an electron rich dopant, such as P, As, Sb, or combinations thereof. The p+-doped regions form the cell anode (emitter), and the n+-doped regions form the cell cathode (collector). In some embodiments, the rear side of the cell has a plurality of p+-doped regions and a plurality of n+-doped regions. In some embodiments, the front and/or rear sides of the semiconducting material can comprise a passivation layer that is electrically insulating. Suitable materials to form passivation layers include, for example, stoichiometric and non stoichiometric silicon oxides, silicon nitrides, and silicon oxynitrides, with or without hydrogen additions.

For the dynamic module and cell processing described herein, real time measurements can be used to estimate performance characteristics, such as carrier lifetimes, at different physical locations along the semiconductor material. The measurements can be made, for example, using non-destructive optical techniques, which can provide for rapid evaluation of the semiconductor material in relatively large sheets. The optical measurements can be made at selected resolution, and further extrapolation and interpolation can supplement the direct measurements. The measurements can then be used to select cell sizes and/or dopant placement to improve the efficiency of the resulting cells and modules through improved matching of current performance. However, to take advantage of these measurements, corresponding efficient techniques to cut the semiconductor and/or place dopants along the semiconductor can be implemented in real time adjustable procedures based on the measurements.

In some embodiments, a plurality of solar cells is cut from a larger sheet of semiconductor material. Generally, any reasonable cutting approach can be used. For example, mechanical cutting, fluid jet cutting or radiation based cutting can be used to cut the larger sheet. In some embodiments, radiation-based cutting, such as with a laser, can be effectively used to make sharp divisions to form individual cells. The semiconductor sheet can be supported on a substrate during the cutting process. It can be particularly desirable to support the semiconductor sheet for embodiments in which the semiconductor is a thin foil, such that the cut sections are less likely to suffer damage in handling.

The cut segments may or may not be repositioned with respect to placement within a photovoltaic module. In other words, in some embodiments, the original semiconductor sheet can be selected to provide the semiconductor structure for a photovoltaic module or a selected portion thereof, and the semiconductor sheet is then subdivided into individual cell through the cutting process. For example, the semiconductor sheet or a plurality of semiconductor sheets, can be secured to the transparent front sheet of the module for cutting such that the cut cells structures are appropriately positioned for further processing into the complete module without changing the position of the semiconductor material on the transparent front sheet. In alternative embodiments, the cut semiconductor sections cut form a single sheet can be separately assembled into a plurality of modules, such as one portion of segments being assembled into a first module and another portion of segments being assembled into a second module. In further embodiments, the cut segments can be assembled with segments cut from one or more other semiconductor sheets into a single module, or the cut segments can be combined with cut segments from other semiconductor sheets for assembly into multiple modules.

In general, dopants can be applied in any reasonable process to the semiconductor materials to form doped contacts. For example, a liquid composition comprising a dopant element can be deposited for incorporation into the semiconductor. Alternatively, approaches have been described for obtaining dopants from doped silicon oxide particles to transfer to a silicon substrate. In further embodiments, doped silicon particles can be used to form doped silicon domains associated with the semiconductor sheet. These approaches are discussed further below in the context of printing approaches for the doping of thin silicon/germanium foils.

For the deposition of dopants for photovoltaics, the resolution generally is intermediate in the sense of having a micron scale resolution, but not on the even smaller scale of current integrated circuit components. Thus, inkjet printing, other printing approaches or the like can be convenient to deposit a liquid dopant composition at select locations along the cell, such as along the rear or backside of the cell, to provide dopant atoms to subsequently form the respective n+-doped and p+-doped domains. While conventional inkjet heads can be adapted for this use, redesigned print heads for the specific application can similarly be used to deliver desired volumes of liquid from a reservoir at dynamically selected locations.

An inkjet process introduces a great level of flexibility to the processing of the doped contact regions. Specifically, the doping process can be dynamically adjusted in a straightforward way for a particular semiconductor sheet. Thus, based on measurements for the particular semiconductor sheet, the location of the doped regions can be selected. As noted above, the size of individual cells can be selected based on semiconductor properties across the surface of the semiconductor sheet. If the cell sizes are selected based on semiconductor measurements, based on the selected sizes of the cells, the dopant domains can be correspondingly selected to fit within the particular cell size and shape. Furthermore, dopant placement can be selected based on semiconductor measurements even if the cell size is not dynamically selected, i.e., if the cells are formed to be of equal size. Similarly, the dopant placement as well as the size and/or dopant levels of individual doped contacts can be also selected if desired based on measurements relating to the semiconductor properties. Using the deposition approaches described herein, dopant inks or other dopant formulations can be printed or deposited at the selected locations in real time for rapid and efficient processing.

In general, any composition suitable for delivering dopant atoms in an ink form can be incorporated into the ink. Inks are considered broadly as a liquid composition capable of providing the desired dopant elements. In particular, nanoscale particles dispersed at relatively high concentrations can be used in dopant inks. Dopant inks can comprise particles with selected compositions to deliver desired dopants at desired concentrations. For example, highly doped silica particles and/or silicon particles can provide the dopants without introducing any significant quantities of contaminants with respect to silicon-based semiconductor sheets. In other embodiments, dopant inks can comprise non-particulate dopant compositions.

In appropriate embodiments, the doped particles for forming the inks can be synthesized through any appropriate process. However, highly doped particles can be produced with desirable properties, for example, using laser pyrolysis, which is a convenient and versatile approach for the synthesis of highly uniform submicron particles with a range of selectable dopants. While in principle a range of doped particles are suitable, doped submicron particles or nanoparticles having an average primary particle diameter no more than about 250 nm are desirable due to their ability to form good dispersions. In some embodiments, the doped particles comprise Si, Ge, SiO2, GeO2, combinations thereof, alloys thereof or mixtures thereof. Doped particles may be surface modified with associated compositions to stabilize the particle dispersions.

As noted above, various dopant configurations and cell designs can be used for the solar cell structure, such as dopant contacts along both the front and rear cell surfaces. Similarly, any reasonable combination of processing approaches can be adapted for dopant placement with respect to selected dopant locations on the semiconductor substrate. The final cell structure can include other layers in addition to a transparent front sheet, a semiconductor sheet, current collectors and dopant regions. These additional layers can include, for example, adhesive layers, dielectric layers, antireflective layers, protective layers and the like. General approaches are described further below for general placement of dopant and contact structures. However, a more detailed description is provided for a particular embodiment relating to a silicon foil semiconductor in which dopants are deposited along the rear surface and all contacts are correspondingly placed along the rear surface of the cell.

In some embodiments, for the formation of a rear contact solar cell, efficient processing can be achieved from the deposition of a passivation, dielectric layer onto the semiconductor rear surface prior to introducing the dopant for the semiconductor layer. Then, portions of the passivation layer can be removed to expose the semiconductor surface to allow for contact with the dopant. Openings/holes can be placed through the passivation layer, for example, using a laser or the like, although other approaches, such as mechanical drilling or etching can be alternative or additional approaches. Laser drilling or other approaches can be controlled to expose the semiconductor surface without significantly damaging the semiconductor surface. The size of the holes, the number of holes and/or placement of the holes can be selected to yield desired degrees of doping and cell performance.

In general, there are multiple dopant locations of opposite polarity across a particular cell. If the sizes of the individual cells are dynamically selected, the size of a particular cell can directly influence the number and placement of doped contacts. Also, the corresponding placement of the doped regions can be based on measurements of the semiconductor properties across a particular cell so that the performance associated with n+-doped contacts and p+-doped contacts are balanced such that improved current output of the cell can be realized relative to purely geometric placement of doped-contacts. The dopant locations can be selected to yield high efficiency of current harvesting as long as reasonable approaches are available for forming current collectors. Thus, doped-contact placement should also account for appropriate placement of current collectors based on the selected process for current collector placement. With respect to the coordination of processing steps, placement of holes through a passivation layer can be based upon on the selected pattern of placement of the doped domains along the semiconductor surface.

In some embodiments, patterned layered structures can be used to form desired current collector configurations. The use of lithography, photolithography or the like can be adapted to form the layered current collector structures. However, printing approaches can also be used to form current collectors which are consistent with dynamic selection of the placement of dopant portions of the cell contacts that correspondingly result in the need to dynamically place the electrical interconnects such that the current collectors connect the dopant regions of common polarity. In general, the use of a reasonably large number of dopant domains can be desirable since then the p-doped and n-doped regions can have a shorter distance to an adjacent doped region. If adjacent doped regions are close to each other more efficient harvesting of the photocurrent can take place.

After a dopant ink is deposited at selected positions along the semiconductor surface, the dopants can be further processed to form the doped contact. For dopant compositions and doped silicon oxide particles, the dopants generally are driven into the layer of semiconductor material at the deposited locations, such as through heating of the structure in an oven to mobilize the dopants, which then migrate into the semiconductor material. The diffusion of the dopant atoms depends on the time and diffusion conditions. In general, the oven based approach is relatively slow and tends to drive the dopants relatively deeply into the semiconductor material in order to obtain desired levels of dopant within the semiconductor.

Alternatively or additionally, dopants can be driven into the semiconductor using an intense light source. For example, a laser beam can be pulsed onto the surface to melt a very thin layer along the surface to form a doped region. In particular, a laser can provide an intense pulse over a relatively large area to process the dopant into the surface. Generally, suitable lasers can emit light with wavelengths ranging from infrared to ultraviolet. The pulsing of the laser can be repeated to achieve the desired level of dopant drive into the surface. If silicon oxide particles are used to provide the dopant atoms, after the dopant is driven into the semiconductor, the remnants of the particles from the dopant ink can be removed from the surface through an appropriate etching process. In some embodiments, this can be done without removing the passivation layer.

For embodiments in which silicon particles are used to deliver the dopant atoms to the doped regions, the silicon particles can be fused at the location to directly form the doped regions. Some dopant may or may not diffuse into the underlying silicon sheet during this fusing process. Thus, the resulting doped contact region can be in the form of a thin island on top of the semiconductor sheet and/or within the surface of the semiconductor sheet. In either case, efficient harvesting of the photocurrent can take place since a thin doped contact over the semiconductor sheet can perform similarly to a contact within the semiconductor sheet.

Once the p+-doped regions and n+-doped regions are formed through appropriate doping, the doped regions of like polarity are connected to respective current collectors. In appropriate embodiments, the holes through the passivation layer can be used to form the electrical connection with the doped domains. Various approaches can be used to deposit the current collector material. For example, the current collector can be formed using a silver ink that is deposited at the appropriate locations, such as with an inkjet or screen printing. Suitable commercial silver inks include, for example, DowCorning® Brand highly conductive silver inks and conductive silver ink 2512 from Metech, Elverson, Pa. Alternatively or additionally, physical vapor deposition or the like can be used to deposit the current collector material. Following deposition of the current collector material, the structure can be heated to crosslink, fuse and/or anneal the current collector material if appropriate. In some embodiments, a seed layer can be deposited for the current collector and electrochemical deposition is used to complete the current collector formation.

The current collectors generally should be connected to link adjacent cells in series. To accomplish this objective, the current collector material can be deposited in a configuration that extends to connect the cells over an electrically resistive bridge or the like and/or additional wiring or the like can be used to connect the current collectors of adjacent cells. An adhesive and/or backing material can be placed over the cell rear surface to protect the rear surface and to facilitate handling. Specifically, a backing structure, such as a polymer sheet can be placed over the entire back and/or sides of the module. The cell module can be placed into an appropriate frame either before or after placement of a backing material or the like. Electrical leads for positive and negative poles should be accessible for connection to an external circuit following completion of the module, although leads can be covered or otherwise protected for shipping and/or storage.

The ability to dynamically process solar cells and corresponding modules in real time provides the ability to improve module performance for a given amount of material to improve, i.e., reduce, average cost per unit of power generation. Correspondingly, the uniformity of the modules can be improved since variation within a semiconductor sheet can be accounted for in the cell processing such that a module performs closer to the specification of the average semiconductor sheet. Thus, one aspect of process variation can be reduced. In general, appropriate doping approaches provide for convenient real time programming of dopant placement that allows for adjustment of cell size based on semiconductor measurements to improve further the module performance and potentially the performance of individual cells. In some embodiments, convenient processing approaches comprise a relatively early in the process association of the cells with the transparent front sheet with additional processing taking place along the rear of the cell.

Module and Cell Structures

The photovoltaic modules generally have a transparent front sheet and a protective backing layer with the solar cells between the transparent front sheet and the protective backing layer. A plurality of solar cells generally is connected in series within a photovoltaic module. The semiconductor structure of the photovoltaic cell can be a thin silicon foil, although the processing approaches herein can be applied for other semiconductor materials and formats. Each cell generally has a plurality of doped domains to form the contacts for the two polarity current collectors of the cell. In some embodiments, the solar cells can be rear or back surface contact solar cells, although other contact structures can be adopted in further embodiments. High cell performance can be expected from the structures described herein.

A schematic view of a photovoltaic module is shown in FIG. 1. Photovoltaic module 100 can comprise a transparent front sheet 102, a protective backing layer 104, a protective seal 106, a plurality of photovoltaic cells 108 and terminals 110, 112. A sectional view is shown in FIG. 2. Transparent front sheet 102 can be a sheet of silica glass or other suitable material that is transparent to appropriate sun light wavelengths and provides a reasonable barrier to environmental assaults such as moisture. Suitable materials for the module components are discussed in more detail in the following section. Backing layer 104 can be any suitable material that provides protection and reasonable handling of the module at an appropriate cost. Backing layer 104 does not need to be transparent and in some embodiments can be reflective to reflect the light that transmitted through the semiconductor back through the semiconductor layer where a portion of the reflected light can be adsorbed. Protective seal 106 can form a seal between front protective sheet 102 and protective backing layer 104. In some embodiments, a single material, such as a heat sealable polymer film, can be used to form backing layer 104 and seal 106 as a unitary structure.

Solar cells 108 are placed with their front surface against transparent front sheet 102 so that solar light can reach the semiconductor material of the photovoltaic cells. Solar cells can be connected electrically in series using current collectors 120, conductive wires or the like. End cells in the series can be connected respectively to terminals 110, 112 that provide for connection of the module to an external circuit. In some embodiments, some solar cells can be connected in parallel to increase the current with an offsetting decrease in voltage, and/or sets of series connected photovoltaic cells can be connected to separate terminal associated with a large module if each series of cells generates an appropriate amount of voltage. Furthermore, the average size of each photovoltaic cell can be adjusted to achieve desired module properties. For example, the formation of a module with fewer, larger cells connected in series generate a relatively larger amount of current at a lower voltage relative to a larger number of smaller cells over the same module footprint. The voltage from the series of cells is determined by adding the individual voltages of the individual series connected cells.

A particular intended application generally influences the selection of module size. For example, potential applications range from small individual external lights to solar panels for a residential house to panels for a commercial scale electricity generation facility. Reasonable module sizes may range, for example, from four square centimeters (cm2) or less to several square meters or larger. Once the overall size is selected for a module, the average individual cell sizes can be selected to balance current versus voltage as well as processing considerations and material considerations. The dynamic processing approaches herein can be adapted for any of these selected embodiments with appropriate corresponding equipment design. In some embodiments, the module comprises at least 10 cells, in further embodiments at least 20 cells and in additional embodiments from about 24 cells to about 200 cells. A person of ordinary skill in the art will recognize that additional ranges of cell number within the explicit ranges above are contemplated and are within the present disclosure.

A bottom view of an embodiment of a photovoltaic module 130 is shown in FIG. 3 with the backing layer removed. In this embodiment, photovoltaic cells 132 with different areas are mounted on transparent front sheet 134. In some embodiments, an entire collection of cells in a module is cut from a single large semiconductor sheet, or a set of cells of the module is cut from a single semiconductor sheet. Dynamic cell cutting and doping processes allow for efficient selection of cells with areas better matched for current generation. As shown in FIG. 3, the plurality of cells is cut with approximately the same cell width while the cell lengths are selected to adjust current generation of the cell to a selected value. Other formats of cell division can be used as described further below.

Referring to FIGS. 4 and 5, an embodiment of an individual photovoltaic cell is shown. In some embodiments, photovoltaic cell 150 can comprise a semiconductor layer 152, a front surface passivation layer 154, a rear surface passivation layer 156, negative contact or collector 160, and positive contact or emitter 162. Collector 160 generally is in electrical contact with n+-doped regions 164, as shown in the cross sectional view in FIG. 5. Emitter 162 generally is in electrical contact with p+-doped regions 166, as shown in FIG. 5. Doped regions 164, 166 can be positioned below holes 168 in passivation layer 156, and holes 168 can be filed with current collector material to make electrical contact with doped regions 164, 166.

A bottom view is shown in FIG. 6 of the solar cell with the current collector material removed. In general, doped regions and corresponding holes or openings through the passivation layer can have any reasonable shape that separates the different poles of the cell. For example, the holes/openings through the passivation layer can have generally cylindrical shapes, groove shapes or other desired shapes. Roughly cylindrical holes can be formed conveniently using the processes described herein. For example, the holes can be formed by laser drilling. Similarly, openings shaped as grooves can be formed by appropriately moving a laser beam between pulses. If a greater amount of passivation material is removed, the corresponding size of the doped regions increases. Thus, if more passivation material is removed, contact resistance may decrease but surface recombination of holes and electrons may increase so that a balance between these effects can influence cell design.

In general, the holes can have average diameters, with averages over different holes as well as over non-circular shapes, ranging form 5 microns to about 100 microns and in further embodiments from about 10 microns to about 30 microns. The spacing of the holes can be from about 50 microns to about 500 microns and in further embodiments from about 80 microns to about 240 microns. A person of ordinary skill in the art will recognize that additional ranges of hole dimensions and spacing within the explicit ranges above are contemplated and are within the present disclosure.

Alternating rows are visible of n+-doped regions 164 and p+-doped regions 166 within holes 168 through layer 156. To simplify the diagram, only two rows are labeled with reference numbers 164, 166, but it is clear how these contacts line up with current collector strips in FIG. 4 so that n+-doped regions are in electrical contact with negative current collector 160, and p+-doped regions are in electrical contact with the positive current collector 162. Similarly, only two example holes are labeled in the figure, although each doped region is associated with a hole. While the holes are shown in a rectangular grid in FIG. 4, the hole placement can be performed based on semiconductor property measurements across the surface such that the hole placement is dynamically determined for a particular structure with placement constrained by the ability to form appropriate current collectors.

An alternative embodiment of a solar cell is shown in FIGS. 7 and 8. In this embodiment, photovoltaic cell 178 has n+-doped regions 180 and p+-doped regions 182 that are arranged in a checkerboard fashion, as shown in FIG. 8. Negative contact 184 and positive contact 186 are correspondingly aligned in angled stripes as shown in FIG. 7. Then, negative contact 184 is in electrical contact with n+-doped regions 180, and positive contact 186 is in electrical contact with p+-doped regions 182. While FIGS. 6 and 8 depict geometrically arranged contacts, the dynamic selection of contact placement can involve less symmetric placement of the contacts, as described further below.

The structure in FIG. 7 has the current collector material for the two poles deposited as a common level on the structure. For a rear contact photovoltaic cell, two layer current collector structures with an insulating layer separating the opposite polarity electrodes have been described. See, U.S. Pat. No. 4,927,770 to Swanson, entitled “Method of Fabricating Back Surface Point Contact Solar Cells,” and U.S. Pat. No. 6,423,568 to Verlinden et al., entitled “Method of Fabricating a Silicon Solar Cell,” both of which are incorporated herein by reference. While the two layer current collector structure can be incorporated into the structures described herein, a two layered structure would add processing steps.

Regardless of the configuration of the metal fingers, the metal fingers and associated metal surface can be designed to cover as much area as practical without having the opposite poles touching since the metal also functions as a rear light reflector. Thus, the finger width can be approximately at least about 40 percent of the finger pitch, i.e., spacing between centers of the fingers, and in further embodiments at least about 50 percent of the finger pitch and in additional embodiments from about 60 to about 85 percent of the finger pitch. A person of ordinary skill in the art will recognize that additional ranges of finger pitch within these explicit ranges are contemplated and are within the present disclosure.

The discussion above focuses on thin film semiconductor solar cells with rear contacts. However, the dynamic processing aspects with respect to cell size and dopant placement can be applied for other cell configurations. For example, thin film solar cells with a combination of front and rear contacts are described further in U.S. Pat. No. 6,455,347 to Hiraishi et al., entitled “Method of Fabricating Thin-Film Photovoltaic Module,” incorporated herein by reference. Another representative photovoltaic module structure with front contacts and rear contacts is described in U.S. Pat. No. 5,956,572 to Kidoguchi et al., entitled “Method of Fabricating Integrated Thin Film Solar Cells,” incorporated herein by reference. The dynamic processes described herein can be adapted for processing cells with both front contacts and rear contacts based on the teachings herein. For these embodiments, the dynamic cutting of the cells can be performed prior to the transfer of the semiconductor sheet to the transparent front sheet such that the front surface of the semiconductor layer can be processed with respect to placement of the front surface contacts prior to securing the cells to the transparent front surface. After securing the cells to the transparent substrate, the remainder of the processing can be performed with respect to the rear surface. Suitable solar cell structures with rear contacts are described further in copending U.S. patent application Ser. No. 12/______, filed on the same date as the present application, to Hieslmair et al., entitled “Solar Cell Structures, Photovoltaic Panels and Corresponding Processes,” incorporated herein by reference.

Materials for Photovoltaic Assemblies

Examples of suitable materials for incorporation into the photovoltaic modules are described in the following. The transparent front sheet can be, for example, a silica glass, other inorganic glass material, a transparent polymer material, composites thereof or the like. The transparent front sheet can have an antireflective coating or other optical coating one or both surfaces. Suitable polymeric backing layers include, for example, Tedlar® “S” type, a polyvinyl fluoride film, from DuPont. With respect to reflective materials, the polymer sheet for the backing layer can be coated with a thin metal film, such as metalized Mylar® polyester film. A protective seal joining the transparent front sheet and a backing layer can be formed from an adhesive, a natural or synthetic rubber or other polymer or the like.

In general, any reasonable semiconductor material useful for solar cells can be processed as described herein if the material can be formed into sheets that can be appropriately cut into selected cell sizes. However, polycrystalline silicon provides desired levels of performance while having reasonably cost materials available for forming large area semiconductor sheets that can be cut into individual solar cells. In particular, suitable semiconducting material includes, for example, thin foils of polycrystalline silicon.

Thin foils of silicon or other inorganic semiconductors can be formed on a sacrificial release layer. In some embodiments, the release layer is mechanically weak so that the release layer can be fractured without damage to the silicon layer on top of the release layer. The formation of thin sheets of silicon by Light Reactive Deposition (LRD™) is described further in published U.S. patent application 2007/0212510A to Hieslmair et al., filed on Mar. 13, 2007, entitled “Thin Silicon or Germanium Sheets and Photovoltaics Formed From Thin Sheets,” incorporated herein by reference. Similarly, the thin films of silicon on a release layer can be formed using a chemical vapor deposition (CVD) approach onto a porous release layer at an atmospheric or sub-atmospheric pressure. The CVD process onto a porous release layer is described further in U.S. provisional patent application Ser. No. 61/062,398 to Hieslmair et al., filed on Jan. 25, 2008, entitled “Deposition Onto a Release Layer for Synthesizing Inorganic Foils,” incorporated herein by reference. The properties of the silicon foils can be improved through an efficient zone melt recrystallization process designed for use with thin foils on a release layer as described further in copending U.S. provisional patent application Ser. No. 61/062,420 filed on Jan. 25, 2008 to Hielsmair et al., entitled “Zone Melt Recrystallization for Thin Silicon Films,” incorporated herein by reference.

The use of a thin silicon foil reduces material usage while promising good cell performance. Thin silicon foils generally have thicknesses from about 5 microns to about 100 microns. In some embodiments, the thin silicon sheets can have a thickness of no more than about 100 microns, such as from 5 microns to 100 microns and any subrange within this range. A person of ordinary skill in the art will recognize that additional ranges of foil thickness within the explicit ranges are contemplated and are within the present disclosure. With the use of thin semiconductor foils formed using a sacrificial, release layer, the exposed surface can be cleaned, textured, coated and/or otherwise prepared and then the thin foil can be separated from an underlying substrate directly onto a transparent substrate. In some embodiments, one or more additional layers, such as a passivation layer, can be deposited over and/or under the silicon layer.

The silicon foil can be transferred to the transparent front sheet, for example, using an adhesive composition to adhere the silicon foil or using electrostatic interaction. Suitable adhesives include, for example, silicone adhesives or EVA adhesives. Other reasonable adhesives can be used for other uses in photovoltaic module assembly, such as the adherence of a backing material, attachment to a frame, forming seals within the structure and the like. Other polymers, such as rubbers can be also used in forming seals. Processes and apparatuses for the transfer of thin inorganic foils to receiving surfaces is described further in copending U.S. provisional patent application Ser. No. 61/062,399 filed on Jan. 25, 2008 to Mosso et al., entitled “Layer Transfer for Large Area Inorganic Foils,” incorporated herein by reference.

In some embodiments, the front and rear sides of the semiconducting layer can comprise a passivation layer that is electrically insulating. Suitable materials to form passivation layers include, for example, stoichiometric and non-stoichiometric silicon oxides, silicon nitrides, and silicon oxynitrides, silicon carbides, silicon carbonitrides, combinations thereof and mixtures thereof, with or without hydrogen additions. In some embodiments, passivation layers can comprise, for example, SiNxOy, x≦ 4/3 and y≦2, silicon oxide (SiO2), silicon nitride (Si3N4), silicon rich oxide (SiOx, x<2), or silicon rich nitride (SiNx, x< 4/3). The passivation layers can protect the semiconductor material from environmental degradation, reduce surface recombination of holes and electrons, provide structural design features and/or assist with some processing steps, as well as provide anti-reflecting properties for front surfaces. In some embodiments, front passivation layer can comprise SiNxOy or other transparent dielectric material. The passivation layer generally is also chemically inert so that the cell is more resistant to any environmental contaminants.

Passivation layers can be formed in a similar reactive deposition process that forms the thin crystalline silicon layer, although the passivation layers can be formed from other techniques such as CVD or PVD techniques using, for example, commercial deposition apparatuses, or with Light Reactive Deposition. Light Reactive Deposition (LRD™) is described further in copending U.S. patent application Ser. Nos. 09/715,935 to Bi et al., entitled “Coating Formation By Reactive Deposition,” 10/414,443 to Bi et al., entitled “Coating Formation By Reactive Deposition,” and 11/017,214 to Chiruvolu et al., entitled “Dense Coating Formation By Reactive Deposition,” incorporated herein by reference. The passivation layers can be deposited with plasma CVD or the like. The passivation layers generally can have a thickness generally from about 10 nanometers (nm) to 200 nm and in further embodiments from 30 nm to 180 nm and in further embodiments from 50 nm to 150 nm. A person of ordinary skill in the art will recognize that additional ranges of thicknesses within the explicit ranges above are contemplated and are within the present disclosure.

The front passivation layer and/or rear passivation layer generally can have texture to scatter light into the semiconductor layer, for example, to increase effective light path and corresponding absorption of the light. In some embodiments, the textured material can comprise a rough surface with an average peak to peak distance from about 50 nm to about 100 microns. The texture can be introduced during the deposition process to form the passivation layer and/or the texture can be added subsequent to the deposition step.

As noted above, the processing of the semiconductor material into a solar cell involves the delivery of dopant materials for the formation of doped-contacts. In general, any reasonable ink can be used that is capable of delivering the desired dopant atoms to the exposed silicon. For example, phosphorous or boron containing liquids can be deposited. In particular, suitable inks can comprise, for example, trioctyl phosphate, phosphoric acid in ethylene glycol and/or propylene glycol or boric acid in ethylene glycol and/or propylene glycol. In some embodiments, inks loaded with inorganic particles can be deposited to provide the dopants. For example, the inorganic particles can comprise doped silica or doped silicon. Doped silica glasses have been used to deliver dopants for photovoltaic cells using photolithographic processes. The use of inks with doped particles can provide for printing of the dopants at desired locations, for example using inkjet printing.

In embodiments of particular interest, the doped particles have an average primary particle size of no more than about 250 nm, in other embodiments no more than about 100 nm, in further embodiments no more than about 50 nm and in additional embodiments no more than about 25 nm. A person of ordinary skill in the art will recognize that additional ranges of particle size within the explicit ranges above are contemplated and are within the present disclosure. In general, doped particles generally can be formed from either reactive flow based approaches or solution based approaches. Submicron inorganic particles with various compositions can be produced by pyrolysis, especially laser pyrolysis, alone or with additional processing. In particular, approaches have been developed for the synthesis of submicron multiple metal/metalloid oxide composite particles and other complex metal/metalloid particle compositions as well as doped compositions thereof. The metals/metalloid elements are introduced into the reactant stream. By appropriately selecting the composition in the reactant stream and the processing conditions, submicron particles incorporating the desired metal/metalloid composition stoichiometry optionally with selected dopants can be formed. The synthesis of doped particles with laser pyrolysis is described further in U.S. Pat. No. 6,849,334 to Home et al., entitled “Optical Materials and Optical Devices,” incorporated herein by reference.

In general, the inks can comprise a suitable liquid to form dispersions of the particles. Suitable liquids to disperse metal oxide and metalloid oxide particles generally can comprise water, alcohols, other organic solvents and mixtures thereof. The dispersions can have concentrations from low concentrations to about 30 weight or in some embodiments to about 20 weight percent or greater. Well dispersed particles can have a reasonably small secondary particle size indicating that the particles are not highly agglomerated in the dispersion. The particles can have a surface modification to stabilize the particles dispersion and/or other surface active agents can be included in the dispersion.

The formation of suitable inks comprising silicon oxide particles for performing semiconductor doping is described in copending U.S. patent application Ser. No. 12/006,459 to Hieslmair et al., filed on Jan. 2, 2008, entitled “Silicon/Germanium Oxide Particle Inks, Inkjet Printing and Processes for Doping Semiconductor Substrates,” incorporated herein by reference. The formation of suitable inks comprising silicon particles for forming doped semiconductor domains is described further in copending U.S. patent application Ser. No. 12/006,453 to Hieslmair et al. filed on Jan. 2, 2008, entitled “Silicon/Germanium Particle Inks, Doped Particles, Printing and Processes for Semiconductor Applications,” incorporated herein by reference. These materials described in these patent applications can be applied to the processes described herein.

Cell Processing and Module Processing

The processing steps described here are appropriate and efficient for the processing of photovoltaic modules with dynamically designed solar cells within the module. In some embodiments, the solar cells are designed for fabrication from thin silicon foils as the semiconducting sheet. However, at least some of the processing procedures are generally applicable and advantageous for the production of photovoltaic cells with a silicon sheet of any thickness as well as cells formed from other semiconductor materials.

The dynamic processing is structured around the measurement of expected performance at a distribution of locations across the semiconductor surface. Then, based on a selected algorithm, the further processing is designed dynamically using the performance measurements. This dynamic processing can include, for example, selecting the positions for cutting the semiconductor sheet into individual solar cells and/or the selection of the placement of doped-contacts along the cell. Once the design is completed, additional processing steps are performed to complete a photovoltaic module with improved performance relative to modules formed from the semiconductor material without the advantage of dynamic processing.

In some embodiments, some of the processing steps in the following discussion are directed specifically to the formation of rear side contacts for harvesting of current from the cell, although dynamic processing can be performed for other cell contact configurations as noted above. In general, the processing steps can comprise, for example, semiconductor sheet preparation 190, semiconductor measurements 192, dynamic cell design 194, cell structure processing 196 and module completion 198, as shown in FIG. 9. In some embodiments of the overall processing approach described herein, the process generally involves the use of one or more large sheets of semiconductor, e.g., silicon, that are divided during the process into individual cells based on measurements of the semiconductor properties at points across the sheet. In general, the processes can provide for appropriate handling of the materials as well as efficient processing with reduced waste and reduced numbers of processing steps without sacrificing the quality of module performance.

The semiconductor sheet preparation 190 is directed to the formation of an initial semiconductor sheet in preparation for performing further processing to form solar cells from the semiconductor sheet. The initial semiconductor sheet structure can be formed generally by any suitable approach. For example, the semiconductor sheet can be cut from a silicon ingot. However, in other embodiments, the semiconductor sheet is formed at least in part with a reactive deposition process. Appropriate reactive deposition processes for forming the semiconductor sheets are described above. Through a reactive deposition process, a very thin foil of silicon can be formed for use in the module. Even though the silicon foil is thin, it can be handled with appropriate transfer techniques that avoid damage to the foil. Some steps relating to cell structure processing 196 can be performed prior to semiconductor sheet preparation 190. For example, a passivation layer can be deposited prior to forming the semiconductor sheet with the semiconductor sheet being deposited onto the passivation layer.

Similarly, some of the cell structure processing steps 196 may or may not be performed prior to performing measurements 192 on the semiconductor sheet. For example, a surface of the semiconductor may be exposed for performing the measurements such that passivation layers may not placed on both surfaces prior to making the measurements. For these embodiments, one passivation layer can be placed prior to performing the measurements of the semiconductor and/or the semiconductor layer can be associated with a transparent layer prior to performing the semiconductor measurements. The transparent substrate can provide mechanical support for the semiconductor sheet during the subsequent processing steps. However, in alternative embodiments, the semiconductor measurements may be performed after formation of a top passivation layer and bottom passivation layer. One or both of the passivation layers can be formed as part of the reactive deposition process.

In some embodiments, in the reactive deposition process, the one or more layers of the structure with a semiconductor layer are formed sequentially onto a release layer. The release layer can have a composition and/or mechanical properties that provide for fracture or release of the structure from the original substrate. Depending on further handling of the silicon foil, either the rear surface or the front surface of the silicon foil can be formed against the release layer. In alternative embodiments, the silicon is directly deposited onto the transparent front sheet so that the front surface of the cell is formed onto the transparent front sheet without any need for a release layer or corresponding transfer. In either orientation, the structure can be further processed, such as heat treated, while associated with the original substrate. While in principle the dopant regions of the cells can be formed through the reactive deposition process, efficient and convenient approaches for forming dopant contacts are described herein that provide for electrical connection to the doped contacts.

In the reactive deposition process involving a release layer, the release layer can be deposited onto a substrate, which may be reusable. The release layer can be a porous, particulate ceramic composition that can be deposited through a reactive deposition process, and suitable compositions include, for example, similar compositions as are suitable for passivation layers. Since the substrates can be reusable, high quality substrates can be used without excessively increasing the cost. In one example of an embodiment, a thin silicon nitride or silicon oxynitride rear passivation layer can be deposited over the release layer. Then, a crystalline silicon layer can be deposited over the rear passivation layer. In some embodiments, a thin front passivation layer can be deposited over the crystalline silicon layer. If a rear passivation layer is deposited, the measurements of the semiconductor can be performed prior to separating the structure from the release layer. If a front passivation layer is deposited, the measurements of the semiconductor layer can be performed on the exposed rear surface of the semiconductor after separation from the release layer and optionally removal of remnants of the release layer.

Reactive deposition to form silicon foils and passivation layers is described further above in the materials section. In some embodiments, the structure formed by reactive deposition can then be heated to consolidate the passivation layers and/or to anneal the crystalline silicon layer and/or otherwise modify the properties of the layers. An improved method for performing zone melt recrystallization of thin silicon foils is also referenced above.

Measurements of semiconductor 192 to estimate performance in a solar cell can be based on carrier lifetime evaluation. In particular, the photo-current generation of a semiconductor material can be estimated as a function of carrier lifetime of the semiconductor. The evaluation generally is performed to estimate performance at different positions on the sheet prior to doping and/or cutting individual cells. In particular, the measurements can be performed on a selected grid of points along the semiconductor sheet. Additional values of carrier lifetime can be interpolated and or extrapolated relative to the measured points using established linear or nonlinear fitting routines. Thus, for convenience, the measurements can be based on a rectangular grid with a spacing that can be based at least in part on the resolution of the measurement technique. The area of a segment along the grid can be set at a resolution of, for example, about 0.0001 mm2 to about 400 mm2 for each grid position along the measurement grid, with the edges possibly being fragments of a grid area, where these grid divisions correspond respectively to about 10 microns to about 20 mm resolutions. A person of ordinary skill in the art will recognize that addition ranges of resolution within these explicit ranges are contemplated and are within the present disclosure.

The measuring apparatus and/or the semiconductor sheet can be translated on a stage or other conveyor system relative to each other to perform the measurements. In some embodiments, optical components can be moved to scan the semiconductor surface. These measurements can be used to determine cell configuration and corresponding cell contact placement.

In particular, optical techniques can be used to evaluate the carrier density and/or carrier lifetimes of the semiconductor. In some embodiments, carrier densities can be used to estimate carrier lifetimes, which is correlated with current generation of the material as a photoconductor. The optical measurement of minority carrier diffusion lengths along a map of the semiconductor surface, which can be used to evaluate carrier lifetimes, is described in published U.S. patent application 2007/0126458 A to Shi et al., entitled Methods and Systems for Determining one or More Properties of a Specimen,” incorporated herein by reference. Also, the carrier density can be estimated from infrared lifetime mapping on the semiconductor material before or after formation of a passivation layer. The infrared lifetimes can be measured, for example, with a charge coupled camera operating in the infrared portions of the spectrum that is used to measure infrared transmission of the sample. High resolution scans of the material can be obtained quickly. An article by Isenberg et al. describes the use of an infrared laser and a commercial CCD camera to obtain a resolution down to 30 microns across the surface of the semiconductor material. The citation for the Isenberg article is Journal of Applied Physics, 93(7):4268-4275 (1 Apr. 2003), entitled “Imaging method for laterally resolved measurement of minority carrier densities and lifetimes: Measurement principle and first applications,” incorporated herein by reference. An article by Goldschmidt et al. discusses the calculation of short-circuit current and open-circuit voltage based on measurements of carrier lifetimes. The Goldschmidt article was presented at the 20th European Photovoltaic Solar Energy Conference and Exhibition, 6-10 Jun. 2005, Barcelona, Spain, entitled “Predicting Multi-Crystalline Silicon Solar Cell Parameters From Carrier Density Images,” incorporated herein by reference. An alternative approach for contact-less estimation of charge-current performance of silicon material is described in Trupke et al., Applied Physics Letters 87:093503 (2005), entitled “Suns-photoluminescence: Contactless determination of current-voltage characteristics of silicon wafers,” incorporated herein by reference. The processes in the Trupke article can be generalized for spatial resolution across the semiconductor surface.

The semiconductor measurements can be used to perform dynamic cell design 194, see the process steps of FIG. 9. In general, based on the measurements across the semiconductor surface, a range of algorithms can be used to layout the resulting cells. In general, the ability to correlate initial materials properties with the final cell power characteristics allows one to adjust cell sizes, contact spacing/pitch, and even the ‘stringing’ of cells (connecting subsets of cells in series and/or parallel) to increase the entire module power production and compensate for areas of poor performance.

Given a carrier lifetime map of the silicon foil, the cell sizes can be selected such that the output currents of the cells at the anticipated peak power point are well matched. A lower carrier lifetime and/or carrier density measurement correlates with a lower expected current of that region at the peak power point per unit area. Thus, the lower carrier lifetime regions should be made into larger cells compared to the higher carrier lifetime regions. The proportionality between initial material carrier lifetime and the proper cell area to achieve current matching can be determined empirically and need not necessarily be linear. In particular, for a specific solar cell design, measurements of the photocurrent from measured domains can be made to determine the functional relationship between the material carrier lifetime with the corresponding photocurrent and voltage. These functional relationships can then be used to perform the dynamic cell design.

Since photovoltaic modules are typically installed at a site in series and/or in parallel, it is often desirable for modules to have a certain rated current (series) or rated voltage (parallel). Given a carrier lifetime mapping of the silicon foil or other semiconductor material as well as empirical knowledge of the cell manufacturing process and the resulting cell properties, a scheme can be devised to divide the foil into cells such that a target current or target voltage at a higher power is achieved. To achieve a target current, the cells are divided such that each cell produces a current of approximately the target value. Then, the series connected cells of the module produce an overall current approximately equal to the target value. To reach a target voltage, the rough voltage value of a cell can be used to select a total number of cells to reach the target value. Then, appropriate division of the sheet into cells that add in series to the target value. Setting a current and voltage target simultaneously is possible generally by sacrificing some degree of the power performance. In general, through dynamic processing, the current variation between any two cells in a module can be reduced to no more than 8 percent relative to the average current for the cells, and in further embodiments, no more than about 5 percent variation in the current under equivalent illumination at the maximum power point for the combined cells. Similarly, the power of the module with more uniform current generation of the individual cells is roughly higher as the corresponding current increase for the module. A person of ordinary skill in the art will recognize that additional ranges of current and power improvement within the explicit ranges above are contemplated and are within the present disclosure.

There has been interest in integrating inverters into modules. If such inverters become commercially viable, then no target voltage or current is required. In such a situation, the cell sizes, contact pitch, and stringing of cells can be entirely selected for increased power generation. The integrated inverter can condition the module power output into a standard 120V 60 Hz output (US) that can feed directly into the power line, or into other standard electrical outputs as selected.

As a representative example, consider the division of the semiconductor substrate into one or more stripes. As shown in FIG. 10A, substrate 220 is shown with a line 224 indicating the eventual division of the sheet into two stripes 226, 228. The position of line 224 can be based on the estimated total current from each stripe. As a hypothetic example based on the embodiment shown in FIG. 10A, if the addition of the current estimate from all of the measurements in the top stripe is expected to be higher than the current estimate from the sum of all of the measurements in the bottom stripe, then the area of the top strip can be made appropriately less than the area of the bottom stripe to compensate.

Then, each stripe can be subdivided so that the current from each cell after division is roughly equal. This division is based on a selected total number of cells for the sheet and correspondingly each stripe. In some embodiments, estimated current for the area around each measurement point can be assumed approximately constant around this point. Alternatively, the estimated current at each measurement point can be extrapolated or interpolated using a linear or nonlinear algorithm. The stripe size can be taken into account. Then, the estimated current from each cell in the stripe is obtained from the total estimated current divided by the total number of cells in a stripe. Then, the area of each cell can be determined to yield the target current. A representative division into 10 cells 232 is shown in FIG. 10A.

The sheet following cutting into the 10 cells 232 is shown in FIG. 10B with a substrate 234 supporting the cut cells. FIG. 10B also shows positioning for doped domains 236 in which the doped domain positions are dynamically selected so that the positions are not on a rectangular grid. In alternative, the doped contacts can be placed on a rectangular grid. In the embodiment shown in FIG. 10B, each vertical, but not necessarily straight, row is selected to receive the same dopant so that contacts can be formed along a row.

The number and placement of the doped domains for the doping process can be determined once the cell size is determined. Selection of doped domain placement can be based on keeping the number of doped domains constant within a cell and placing the doped domains in a particular cell based on the actual size of the cell to approximately evenly space the doped domains according to a selected pattern. Alternatively, the spacing between the doped domains can be targeted at a fixed value, and the doped domains are then placed accordingly by fitting the most doped domains according to the space available in the cell based on the target spacing and size of the doped domains.

Another embodiment is shown in FIG. 11 after cutting the semiconductor sheet into individual cell. In this embodiment, the sheet is cut into five roughly equal sized rows 240, 242, 244, 246, 248. Then, each row is cut into appropriately sized cells based on measurements of the semiconductor properties. As noted above, the number of cells generally can be selected based on target module performance, such as based on a target voltage. In general, a photovoltaic module can comprise, for example, from 2 to 2000 solar cells, and in other embodiments from 10 to 500 solar cells, as well as any ranges within these explicit ranges. Generally, the layout can be based on first a division into rows as in the examples above, or the division can be any number of mathematical algorithms that improve current matching, such as an iterative process that starts with equal area cells and shifts area to compensate for current differences, with this correction process continuing until the currents are estimated to be equal within a specified tolerance.

The semiconductor sheet is further processed to form the solar cell through the formation of doped contacts to harvest the photocurrent and the placement of current collectors to direct the harvested photocurrent. In embodiments of particular interest, the individual solar cells are cut from a larger semiconductor sheet. The solar cells can be positioned to receive light through a transparent front sheet. The discussion herein focuses on the formation of rear contact solar cells, but the processing can be generalized for other doped contact placement based on the teachings herein. The cell structure processing 196 (FIG. 9) can comprise, for example, one or more of the steps in FIG. 12, although the steps are not necessarily performed in the order presented when not necessary for processing considerations, and generally additional processing steps can be included for specific commercial designs. Furthermore, some of the steps of the cell structure processing 196 can be done prior to or concurrently in parallel with steps relating to semiconductor measurement 192 and/or dynamic cell design 194 of FIG. 9.

In general, referring to FIG. 12, cell structure processing 196 can comprise, for example, depositing one or more additional layers 260, transferring the semiconductor to the transparent front sheet 262, cutting cells 264, preparing the structure for dopant deposition 266, depositing dopant composition 268, curing the dopant 270, depositing cell current collectors 272 and curing the current collectors 274, although additional steps can be used, and some steps may be combinable or optional. The deposition of additional layers can involve the formation of, for example, passivation layers along the top and/or bottom surface of the semiconductor sheet. In alternative embodiments, one or more passivation layer can be formed during the process for forming the semiconductor layer. Compositions, parameters and methods for forming passivation layers are described above. Additional protective layers, adhesive layers and processing layers can also be deposited, which can be temporary or layers for the finished solar cell.

The passivation layers for the respective sides of the semiconductor layer can be deposited at appropriate times in the process. The passivation layers are generally textured. The texturing can be done with plasma etching or other suitable method, and/or the texture can be incorporated into the layer during deposition. Additional layers can be deposited as appropriate to form desired structures, such as layered current collectors. Similarly, etching processes and lithographic and photolithographic approaches can be used to pattern layers.

With respect to the transfer of the semiconductor sheet to the transparent front sheet 262, this process depends to a significant degree on the nature of the semiconductor. In general, this process can be performed for thicker semiconductor structures straightforwardly. For thin silicon foils, this process can be directly performed from a structure involving a porous, particulate release layer or prior transfer steps can be performed so that the transfer to the transparent front sheet can take place from a temporary receiving surface. Processes and apparatus for the handling and transfer of thin inorganic foils is described further in copending U.S. provisional patent application 61/062,399 filed on Jan. 25, 2008 to Mosso et al., entitled “Layer Transfer for Large Area Inorganic Foils,” incorporated herein by reference. The semiconducting structure with any passivation layers and the like can be laminated to the transparent front sheet with a transparent adhesive or the like.

Using the measurements of semiconductor properties across the semiconductor sheet, the cells can be laid out on the sheet based on dynamic cell design discussed above. The cells are cut 264 from the semiconductor sheet at an appropriate point in the cell structure processing process. Generally, the sheet is cut into cells at some point after measurement of the semiconductor and before final processing steps to form the complete module. Additionally, the solar cells can be cut from the semiconductor sheet before or after positioning on the transparent front sheet. Cutting after placement on the transparent front sheet eliminates any separate alignment steps, but this processing order generally more or less fixes the particular arrangement of the cells unless additional removal and replacement steps are performed. With the semiconductor structure for the cell in position on the transparent substrate, additional processing can be performed on the back side of the cell until the cells are completed and integrated into the module.

The solar cells can be cut from the semiconductor sheet based on the selected division that generally is mapped during the dynamic cell design. The cells can be cut using reasonable mechanical methods, such as with a saw having a hard edge blade, a fluid jet cutting apparatus or other mechanical methods. However, available laser cutting techniques provide for particular convenience especially with the real time determination of cell placement. Suitable laser cutting systems are available from Oxford Lasers, Inc., Shirley, Mass., USA, and IPG Photonics Corp., Oxford, Mass., USA as well as other commercial sources. In general, any reasonable laser frequency can be used that oblates the material, such as Ytterbium lasers operating at 1070 nm. If the semiconductor sheet is cut while adhered to the transparent substrate, the selected cutting approach may cut into the transparent substrate slightly without damaging cell performance as long as the transparent substrate maintains its mechanical integrity. In general, the laser cutting of the cells can be performed before, after or between steps relating to formation of the doped contacts.

The preparation for dopant deposition 266, if performed, generally involves providing access to the semiconductor surface with respect to passivation layers or other layers that can be placed along the semiconductor surface along with the dopant. In some embodiments, a passivation layer can be patterned to provide exposed regions that can accept dopant. Photolithographic techniques, other lithographic techniques, which can involve various etching approaches, can be used for patterning of the structure. In principle, the patterning of the passivation layer or other covering layers can performed after the doping process if the dopants can be placed without migration, although this processing order of doping first provides constraints on the other processing steps and involves fairly precise relative positioning to properly expose the resulting dopants. In some embodiments, a desirable approach comprises the drilling of holes through a passivation layer. The dopants can be printed into the holes, which become the location of the doped contacts. The reference to holes is not intended to imply cylindrical structures, and holes can have selected shapes and sizes. Appropriate ranges of hole dimensions are discussed above.

Appropriate positions for dopant deposition can be determined dynamically within each cell as described above. Holes through a passivation layer can be laser drilled or mechanically drilled. For example, laser hole drilling can use a green to UV laser can be used with a short pulse from 10 nanoseconds (ns) to 100 ns, although other laser frequencies and firing sequences can be used. Shorter wavelengths and shorter pulse times are expected to cause less damage to the underlying silicon, but there may be a range of tradeoffs from a commercial perspective, such as cost.

The laser drilling of the holes is expected to create some debris. A shallow silicon etch can remove the debris as well as a damaged layer in the silicon. Suitable chemical etching can be performed with nitric/hydrofluoric acid mixtures, tetramethyl-ammonium hydroxide (TMAH) or potassium hydroxide (KOH) etching compositions. In some embodiments, after the laser ablation and chemical etch, about 1% to about 50%, in further embodiments from about 5% to about 30% and in additional embodiments about 10% to about 25% of the dielectric passivation layer is removed to expose clean, effectively undamaged silicon underneath the holes with the remaining portions being covered by the passivation layer. A person of ordinary skill in the art will recognize that additional ranges of passivation layer removal within the explicit ranges above are contemplated and are within the present disclosure.

A dopant composition can then be applied through the holes to contact the exposed silicon. In some embodiments, the dopant is delivered in a dopant carrying ink, which can be dispensed, for example, using an inkjet printer of the like. Inkjet resolution over large areas is presently readily available at 200 to 800 dpi, which is adequate to pattern 100 to 200 pitch lines with single drops to cover the laser scribed holes. Also, inkjet resolution is continuing to improve. Two inks generally are used, with one ink providing n-type dopants, such as phosphorous and/or arsenic, and the second ink providing p-type dopants, such as boron, aluminum and/or gallium. Suitable inks are described above that can comprise a dopant composition as a liquid or dissolved in a liquid, or comprising dopant particles, such as doped silica particles or doped silicon particles.

After the dopant is deposited, the dopant can be cured 270 (FIG. 12) as appropriate to provide desired electrical interaction between the doped contact and the semiconductor material. For example, after depositing the dopant inks, an optional drying step can be used to remove solvents and/or other organics. In some embodiments, a thin film with a thickness of less than a micron can be left for further dopant cure processing. The nature of the dopant cure depends on the nature of the dopant composition. For dopant comprising liquids and silica particle inks, the dopant is driven into the silicon layer to form the doped contacts, while for silicon particle inks, the silicon can be fused in place to form the doped contacts.

For appropriate embodiments, during the drive-in step, the deposited dopant element is driven into the silicon to form a doped contact in the silicon. The drive-in can be performed with heating in an oven to accelerate solid state diffusion. Thermal drive-in of dopants generally results in a Gaussian profile of dopant in the silicon so that a relatively deep dopant structure generally is obtained to obtain a desired overall doping level. Generally, the dopant levels can be from about 5.0×1018 to about 5×1019 atoms per cubic centimeter (cc).

However, in some embodiments, a laser drive-in is performed, for example, with a UV laser, such as an excimer laser, although a wide range of laser frequencies can be suitable for the laser-based dopant drive in. In particular, excimer laser pulses of 10 to 1000 ns can result in melting of silicon at temperatures exceeding 1400° C. to depths of 20 to 80 nm. As a specific example, excimer laser fluences of about 0.75 J/cm2 for a 20 ns pulse or 1.8 J/cm2 for a 200 ns pulse are suitable parameters for molten regions, although other lasers, laser frequencies and other power parameters can be used as appropriate. Dopants in the overlayer diffuse rapidly into the melted silicon, but generally diffuse very little past the melted silicon. Thus, an approximately step-wise dopant profile can be achieved with dopant concentrations possibly reaching levels greater than solubility. Additionally, the bulk of the silicon layer and lower layers remain at or near ambient room temperature, and a lower temperature process can be advantageous since less energy is consumed.

In some embodiment, with a laser based drive in, a heavily doped contact can be formed with a relatively shallow profile, with thickness from about 20 nm to about 500 nm. In some embodiments with a shallow profile, the dopant profile has at least about 95 atomic percent of the dopant in the semiconductor within about 500 nm of the semiconductor surface and in further embodiments within about 100 nm of the semiconductor surface. The dopant profile can be measured using Secondary Ion Mass Spectrometry (SIMS) to evaluate the elemental composition along with sputtering or other etching to sample different depths from the surface.

Similarly, a doped-silicon deposit on the surface of the silicon semiconducting sheet can be melted to form a doped contact in association with the semiconducting sheet. The silicon particles can be melted in an oven or the like, or by placing the structure in a light based heating system, such as a laser-based scanning apparatus. Again, light sources, such as lasers, with a wide range of frequencies can be adapted to cure the silicon particles into a doped contact.

Some dopant inks may leave little if any residue after drive-in. Dopant inks using doped silica (SiO2) generally are cleaned from the surface following dopant drive-in. Residual SiO2 and some impurities can be removed with an HF etch.

Referring to FIG. 12, current collector materials are deposited 272 to form electrical connections with the doped contacts so that the harvested photocurrent can be guided external to the cell. Current collectors are formed to electrically connect the doped contacts to form two poles of the cell that are suitable to connection to a module terminal or another cell. Within a cell, the doped contacts are electrically connected within the cell configuration, generally with particular polarities, i.e., types of dopant contacts, connected in parallel. The deposition of the current collector material can be performed, for example, using an inkjet to deposit metallization materials directly or to deposit a conductive seed pattern for subsequent electroplating. In some embodiments, direct deposition of metallization material can comprise depositing with an inkjet an ink with a polymer-silver particle composite For electroplating based embodiments, a seed layer can comprise any electrically conductive material, such as a layer of Cu, Ag, or Ni. Use of a seed layer and subsequent electroplating is described further, for example, in U.S. Pat. No. 6,630,387 to Horii, entitled “Method for Forming Capacitor of Semiconductor Memory Device Using Electroplating Method,” incorporated herein by reference.

An appropriate approach for curing of the current collector material 274 (FIG. 12) depends on the nature of the current collector material. In some embodiments, the current collector material can be heated to anneal metal or other materials to form a good juncture. Polymer metal particle composites can be cured into a highly conductive material upon moderate heating that is effective to crosslink the polymer. Some polymer composites can be cured with radiation.

In some embodiments, inkjet metallization can be extended to connect multiple solar cells in series if a bridge is used to span the gap formed from cutting the cells. The bridge should be formed from an electrically insulating filler. Suitable fillers include, for example, compliant, flexible polymers that do not introduce strains into the module structure. Suitable polymers can be deposited using straightforward processes, such as extrusion, molding or the like. The formation of a bridge and inkjet metallization over the bridge eliminates the need for soldering cells together. Alternatively, the cells can be soldered together with copper wires or the like, or other approaches to form the electrical connections can be used.

Referring to FIG. 9, once the cells car completed, further processing steps can be performed to complete module formation 198. During final processing steps to complete the module, electrodes of the solar cells can be connected in series, and other electrical connects can be formed as desired. Also, appropriate electrodes of cells at the end of the series are connected to module terminals. Specifically, once the electrical connections between cells are completed, the external module connections can be formed, and the rear plane of the module can be sealed. A backing layer can be applied to seal the rear of the cell. Since the rear sealing material does not need to be transparent, a range of materials and processes can be used, as discussed above. If a heat sealing film is used, the film is put in place, and the module is heated to moderate temperatures to form the seal without affecting the other components. Then, the module can be mounted into a frame as desired.

The embodiments above are intended to be illustrative and not limiting. Additional embodiments are within the claims. In addition, although the present invention has been described with reference to particular embodiments, those skilled in the art will recognize that changes can be made in form and detail without departing from the spirit and scope of the invention. Any incorporation by reference of documents above is limited such that no subject matter is incorporated that is contrary to the explicit disclosure herein.