Title:
System and Method for Stopping Functional Macro Clocks to Aid in Debugging
Kind Code:
A1


Abstract:
A system and method for debugging an integrated circuit. According to a preferred embodiment of the present invention, the integrated circuit includes a collection of macros. Each macro further includes a collection of latches controlled by a local clock control. A pattern matcher monitors data patterns in at least one macro. In response to detecting a data pattern indicative of a failure signature within the at least one macro, a check stop logic sends an error detection signal to at least one additional macro and to the local clock control. In response to receiving the error detection signal, the local clock control halts operation with the at least one macro such that data values contributing to said data pattern indicative of said failure signature are retained in the collection of latches.



Inventors:
Williams, Derek E. (Austin, TX, US)
Application Number:
11/550036
Publication Date:
01/10/2008
Filing Date:
10/17/2006
Primary Class:
Other Classes:
257/E27.113
International Classes:
G06F17/50
View Patent Images:



Primary Examiner:
SIEK, VUTHE
Attorney, Agent or Firm:
DILLON & YUDELL LLP (8911 N. CAPITAL OF TEXAS HWY.,, SUITE 2110, AUSTIN, TX, 78759, US)
Claims:
What is claimed is:

1. A method for debugging an integrated circuit, wherein said integrated circuit includes a plurality of macros, wherein each macro among said plurality of macros further includes a plurality of latches controlled by a local clock control, said method comprising: monitoring data patterns in at least one macro among said plurality of macros; in response to detecting a data pattern indicative of a failure signature within said at least one macro, sending an error detection signal to at least one additional macro among said plurality of macros and to said local clock control; in response to receiving said error detection signal, halting operation within said at least one macro via said local clock control such that data values contributing to said data pattern indicative of said failure signature are retained in said plurality of latches.

2. The method according to claim 1, further comprising: in response to said halting operation within said at least one macro, reading contents of said plurality of latches.

3. The method according to claim 1, further comprising: in response to receiving said error detection signal in a master macro, sending out a global stop signal to said plurality of macros.

4. The method according to claim 3, further comprising: stopping said at least one additional macro among said plurality of macros with said error detection signal transmitted from said at least one macro instead of waiting for said global stop signal.

5. A system for debugging an integrated circuit, wherein said integrated circuit includes a plurality of macros, wherein each macro among said plurality of macros further includes a plurality of latches controlled by a local clock control, said system comprising: a pattern matcher for monitoring data patterns in at least one macro among said plurality of macros; check stop logic for sending an error detection signal to at least one additional macro among said plurality of macros and to said local clock control, in response to detecting a data pattern indicative of a failure signature within said at least one macro; a local clock control for halting operation within said at least one macro via said local clock control such that data values contributing to said data pattern indicative of said failure signature are retained in said plurality of latches, in response to receiving said error detection signal.

6. The system according to claim 5, further comprising: test equipment for reading contents of said plurality of latches, in response to said halting operation within said at least one macro.

7. The system according to claim 5, further comprising: a master macro for sending out a global stop signal to said plurality of macros, in response to receiving said error detection signal.

8. The system according to claim 7, wherein said check stop logic stops said at least one additional macro among said plurality of macros with said error detection signal transmitted from said at least one macro instead of waiting for said global stop signal.

Description:

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates in general to the field of data processing systems. More specifically, the present invention relates to a system and method for stopping functional macro clocks to aid in debugging.

2. Description of the Related Art

Modern computer systems include a large number of integrated circuits. The integrated circuits generally include multiple macros, which each include a collection of integrated circuit elements utilized to perform a discrete function in the integrated circuit.

Frequently, when debugging an integrated circuit, a circuit tester would like to view the latch data values in one or more macros at the time of an error. As well-known by those skilled in the art, often when a particular macro encounters an error, the particular macro sends an error detection signal to a master macro signifying error detection. The master macro, upon receiving the error detection signal from the particular macro, sends a stop signal that halts the functional clock of all macros in the integrated circuit. This allows the values of the latches in the integrated circuit to then be “scanned out” for examination. By the time the particular macro stops operating in response to the stop signal, the data values present in the macro at the time of the error are often lost because the functional clock was halted not at the time the error was detected, but many clock cycles later in response to the master macro's stop signal. Therefore, there is a need for a system and method for addressing the aforementioned limitations of the prior art.

SUMMARY OF THE INVENTION

The present invention includes a system and method for debugging an integrated circuit. According to a preferred embodiment of the present invention, the integrated circuit includes a collection of macros. A reliability and serviceability (RAS) macro controls a clock source, scans the contents of the collection of macros via scan chains, and stops operations within the macros by sending out a global clock stop signal in response to receiving an error detection signal sent by any of the macros within the integrated circuit.

Each macro may further include a collection of latches controlled by a local clock control. A pattern matcher monitors data patterns in a current macro. In response to detecting a data pattern indicative of a failure signature within the current macro, a check stop logic sends an error detection signal to the RAS macro and possibly to one or more neighboring macros. The local clock control in the current macro immediately halts operation within the current macro such that the data values that contributed to the data pattern indicated of a failure signature are more likely retained in the collection of latches. In response to receiving the error detection signal from the current macro, the neighboring macro(s) (if enabled) will also immediately stop operations to preserve values in the neighboring macro(s). The RAS macro, upon receiving the error detection signal from the current macro, sends a global clock stop signal to all macros within the integrated circuit. After all macros have been stopped, the latch values within the macro may be scanned out for examination.

The aforementioned features, as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed description.

BRIEF DESCRIPTION OF THE FIGURES

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying figures, wherein:

FIG. 1 is a block diagram illustrating an exemplary data processing system in which a preferred embodiment of the present invention may be implemented;

FIG. 2 is a block diagram depicting an exemplary integrated circuit in which a preferred embodiment of the present invention may be implemented;

FIG. 3 is a more detailed block diagram illustrating an exemplary macro as shown in FIG. 2;

FIG. 4 is a more detailed block diagram depicting an exemplary check stop logic as illustrated in FIG. 3;

FIG. 5 is a high-level logical flowchart illustrating an exemplary method for stopping functional macro clocks to aid in debugging in accordance with a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT

The present invention includes an integrated circuit that is implemented as a reliability and serviceability (RAS) macro, a collection of macros, and a clock source. Utilizing check stop logic, each macro, including the RAS macro monitors activity within the macros to detect internal data patterns that are indicative of a failure signature (e.g., illegal value). In response to detecting internal data patterns that are indicative of a failure signature within a first macro, the check stop logic sends an error detection signal to a local clock control, any neighboring macros that have elected to receive failure detection signals from the first macro, and to the RAS macro. While the local clock control halts operation of the first macro, any neighboring macros are also halted, if requested, thus more likely preserving the values that generated the illegal value, instead of halting the first macro upon receiving a global clock stop signal from the RAS macro.

With reference now to the figures, and in particular, with reference to FIG. 1, there is depicted an exemplary data processing system 6 in which a preferred embodiment of the present invention may be implemented. The depicted embodiment can be realized, for example, as a workstation, server, or mainframe computer.

As illustrated, data processing system 6 includes one or more processing nodes 8a-8n, which, if more than one processing node 8 is implemented, are interconnected by node interconnect 22. Processing nodes 8a-8n may each include one or more processors 10, a local interconnect 16, and a system memory 18 that is accessed via a memory controller 17. Processors 10a-10m are preferably (but not necessarily) identical and may comprise a processor within the PowerPC™ line of processors available from International Business Machines (IBM) Corporation of Armonk, N.Y. In addition to the registers, instruction flow logic and execution units utilized to execute program instructions, which are generally designated as processor core 12, each of processors 10a-10m also includes an on-chip cache hierarchy 14 that is utilized to stage data to the associated processor core 12 from system memories 18.

Each of processing nodes 8a-8n further includes a respective node controller 20 coupled between local interconnect 16 and node interconnect 22. Each node controller 20 serves as a local agent for remote processing nodes 8 by performing at least two functions. First, each node controller 20 snoops the associated local interconnect 16 and facilitates the transmission of local communication transactions to remote processing nodes 8. Second, each node controller 20 snoops communication transactions on node interconnect 22 and masters relevant communication transactions on the associated local interconnect 16. Communication on each local interconnect 16 is controlled by an arbiter 24. Arbiters 24 regulate access to local interconnects 16 based on bus request signals generated by processors 10 and compile coherency responses for snooped communication transactions on local interconnects 16.

Local interconnect 16 is coupled, via mezzanine bus bridge 26, to a mezzanine bus 30. Mezzanine bus bridge 26 provides both a low latency path through which processors 10 may directly access devices among I/O devices 32 and storage devices 34 that are mapped to bus memory and/or I/O address spaces and a high bandwidth path through which I/O devices 32 and storage devices 34 may access system memory 18. I/O devices 32 may include, for example, a display device, a keyboard, a graphical pointer, and serial and parallel ports for connection to external networks or attached devices. Storage devices 34 may include, for example, optical or magnetic disks that provide non-volatile storage for operating system, middleware and application software.

FIG. 2 is a block diagram illustrating an exemplary integrated circuit 200, such as processor 10 within data processing system 6 of FIG. 1. Integrated circuit 200 is preferably implemented as a semiconductor or insulating substrate with integrated circuitry, implemented in various functional blocks referred to herein as reliability and serviceability (RAS) macro 204, macros 205a-205n, and clock source 232. Clock source 232 supplies a clock signal to all the macros 205a-205n and RAS macro 204 and is controlled by RAS macro 204.

According to a preferred embodiment of the present invention, RAS macro 204 controls clock source 232, controls scanning of the contents of macros 205a-205n via a scan chain or chains (discussed herein in more detail in conjunction with FIGS. 3-5), and stops operation of macros 205a-205n by sending out a global clock stop signal in response to an error detection signal sent by any of the macros within integrated circuit 200. Those with skill in the art will appreciate that RAS macro 204 may also include many of the similar structures (e.g., latches, functional logic, and check stop logic, all discussed herein in more detail in conjunction with FIGS. 3-4) as macro 205a-n. While FIG. 2 depicts integrated circuit 200 with four macros (RAS macro 204 and macros 205a-n), those with skill in the art will appreciate that integrated circuit 200 is not limited to four macros and may include any number of macros.

RAS macro 204 is coupled to macros 205a-205n via a variety of signals lines 234a-234n, 236a-236n, and signal 240a. As illustrated, signal lines 234a-234n are signal lines that enable RAS macro 204 to stop macros 205a-205n directly via clk_stop 208 located on RAS macro 204 and clk_stop 220a-220n on macros 205. Signal lines 236a-236n enable macros 205a-205n to send an error detection signal to RAS macro 204 from error_out 222a-222n to error 210 located on RAS macro 204. Signal lines 240a-220n couple scan_out 228a-228n and scan_in 230a-230n and form a scan chain among macros 205a-205n. The scan chain originates at scan_chain_out 216 and terminates at scan_chain_in 214, located on RAS macro 204.Test equipment 202 utilizes the scan chain to scan out the values of the latches in macros 205a-205n and RAS macro 204 after RAS macro 204 sends a global clock stop signal in response to receiving an error detection signal from another macro 205a-205n.

As previously discussed, clock source 232 supplies a clock signal to RAS macro 204 and macros 205a-n. As illustrated, signal lines 238a-238n supply the clock signal to macros 205a-205n. Signal line 239 supplies the clock signal to RAS macro 204.

Macros 205a-205b illustrate a pair of macros connected to enable one macro (macro 205b) to stop a neighboring macro (macro 205a) when the first macro detects an error if the second macro is enabled to receive a “local stop” signal. The “neighbor stop” procedure is accomplished by tying local stop 226a of macro 205a to error_out 222b of macro 205b via signal line 242a. For example, if macro 205b encounters a failure signature, check stop logic within macro 205b sends out an error detection signal that not only propagates to RAS macro 204, but is forwarded to macro 205a via signal line 242a. If the checkstop logic within macro 205a is enabled to receive a local stop signal, the clocks within macro 205a will be stopped upon receipt of local stop signal 242a. This “neighbor stop” procedure enables neighboring macros to be stopped before RAS macro 204 sends the global clock stop signal, thus more likely preserving values present within macro 205a at the time of the failure. Signal lines 242a-242n are included in FIG. 2, but those with skill in the art will appreciate that not all local stop 226a-226n need to be coupled to neighboring macros and that it is also possible for a given macro 205 to have a plurality of local stop inputs connected to a number of neighboring macros.

FIG. 3 is a block diagram depicting an exemplary macro 205 from FIG. 2. As illustrated, macro 205 includes local clock control 302, check stop logic 310, and functional logic 304. Local clock control is coupled to clock source 232 via signal line 238 and distributes the clock signal to functional logic 304. Function logic 304 includes both latches 306a-306n and logic gates 308. While FIG. 3 illustrates only three latches within macro 205, those with skill in the art will appreciate that macro 205 may include any number of latches.

During operation of macro 205, there are three ways in which macro 205 may be stopped: (1) upon detection of a failure signature from signal line 300; (2) upon receiving an error detection signal from a neighboring macro on signal 226; and (3) upon receiving a global stop signal from RAS macro 204 on signal 220. When enabled, check stop logic 310 monitors signal line 300 for failure signatures (e.g., illegal values) generated by functional logic 304. Once check stop logic 310 detects a failure signature, check stop logic 310 sends an error detection signal to local clock control 302, which stops operation of macro 205.

Macros within integrated circuit 200 may be coupled so that if one macro sends out an error detection signal, that signal propagates to neighboring macros via local stop 226a-226n coupled to signal line 242. For example, if macro 205a and macro 205b are paired, an error detection signal sent from error_out 222a in macro 205b can stop operations within macro 205a when the error detection signal is received via local stop 226a.

Also, as previously discussed, after a macro 205 detects a failure signature, check stop logic 310 sends an error detection signal to local clock control 302 and to RAS macro 204 via error_out 222. In response to receiving the error detection signal, RAS macro 204 sends out a global stop signal to all macros 205a-205n. Upon receipt of the global stop signal on signal line 234 via CLK_stop 220, any macros 205a-205n still operating will stop.

FIG. 4 is a more detailed block diagram illustrating check stop logic 310 from FIG. 3. As depicted, check stop logic 310 includes pattern matcher 402, pattern matching configuration 404, a collection of logic gates (OR gates 412a-412b and AND gates 414a-414c), and latches 400a-400c. Pattern matching configuration 404 is preferably implemented as a set of latches that instructs pattern matcher 402 of the patterns of signals on signal line 300 that are indicative of a failure signature. Pattern matcher 402 is preferably implemented as a set of logic that monitors signals within macro 205 to detect signals from signal line 300 that are indicative of a failure signature. As previously discussed, signal line 300 receives signals from functional logic 304.

AND gate 414c, signal line 408, and latch 400a enable or disable the output of pattern matcher 402 depending on a current setting of latch 400a. For example, a circuit tester may not be interested in whether or not a current macro encounters any signals indicated of a failure signature. To disable the output of pattern matcher 402, latch 400a may be scanned with a value of “0” at system startup.

AND gates 414a-414b, latches 400b-400c and signal lines 242a-242b enable or disable error detection signals from neighboring macros. For example, if a circuit tester requires that an error detection signal from macro 205b be sent to not only RAS macro 204, but macro 205a as well, the error detection signal from macro 205b would propagate to macro 205a via a signal line, such as signal lines 242a-242b. Latches 400b-400c would be scanned with a value of “1” to enable the error detection signal to propagate from AND gates 414a-414b to OR gate 412a.

OR gate 412a combines the error detection signals from AND gates 414a-414b sent from neighboring macros. OR gate 412b further combines the signal from OR gate 412a with the signal from AND gate 414c, which represents the error detection signal from pattern matcher 402. The output of AND gate 412b then propagates to signals 222 and 314 to signal neighboring macros 205 and RAS macro 204 and to stop the local clocks via local clock control 302.

As previously discussed, the logic within check stop logic 310 enables a circuit tester to enable or disable error detection signals from a current macro and/or neighboring macros. Depending on the configuration of the current macro, stopping operating of the current macro in response to an error detection signal from a neighboring macro is desired.

Those with skill in the art will appreciate that latches 400a-400c as well as the latches within pattern matching configuration 404 are also coupled via an unillustrated scan chain or chains to enable these latches to be initialized during scanning of integrated circuit 200, as show in step 501 of FIG. 5. In this manner test equipment 202 may configure which error patterns are detected and which macros, if any, are stopped in response to an error.

FIG. 5 is a high-level logical flowchart depicting an exemplary method for stopping functional macro clocks to aid in debugging in accordance with a preferred embodiment of the present invention. The process begins at step 500 and proceeds to step 502, which shows integrated circuit 200 being initialized by scanning initial values into the latches within integrated circuit 200. In this process, latches 400a-400c are initialized with values that either enable or disable error detection signals from passing through AND gates 414a-414c in check stop logic 310. Also, latches within pattern match configuration 404 are initialized and specify signals patterns that are indicative of a failure signature. The process continues to step 504, which depicts integrated circuit beginning operation. The process then proceeds to step 506, which shows check stop logic 310 determining if an enabled local stop has been received via an error detection signal via local stop 226 and signal line 242 from a neighboring macro.

If an enabled local stop has not been received, the process continues to step 508, which illustrates check stop logic 310 determining if pattern matcher 402 has detected a signal indicative of a failure signature. If pattern matcher 402 has not detected a signal indicative of a failure signature, the process returns to step 506 and proceeds in an iterative fashion. If pattern matcher 402 has detected a signal indicative of a failure signal, the process proceeds to step 510.

Returning to step 506, if check stop logic 310 has received an enabled local stop signal, the process continues to step 510, which illustrates check stop logic 310 presenting an error detection signal via signal line 314 to local clock control 302 and error out 222 via signal line 236, which propagates to neighboring macros (if connected and also configured by circuit tester to do so) and RAS macro 204. RAS macro 204, upon receiving the error detection signal, sends a clock stop signal via CLK_stop 208 to all macros 205 to stop operation of all remaining macros 205 in integrated circuit 200.

The process continues to step 512, which illustrates test equipment 202 scanning latches via scan_chain_in 214 when all clocks within all macros 205 have been stopped. The process then ends, as illustrated in step 514.

The present invention includes a system and method for debugging an integrated circuit. According to a preferred embodiment of the present invention, the integrated circuit includes a collection of macros. A reliability and serviceability (RAS) macro controls a clock sources, scans the contents of the collection of macros via scan chains, and stops operations within the macros by sending out a global clock stop signal in response to receiving an error detection signal sent by any of the macros within the integrated circuit.

Each macro further includes a collection of latches controlled by a local clock control. A pattern matcher monitors data patterns in a current macro. In response to detecting a data pattern indicative of a failure signature within the current macro, a check stop logic sends an error detection signal to the RAS macro and possibly to one or more neighboring macros. The local clock control in the current macro halts operation within the current macro such that the data values that contributed to the data pattern indicated of a failure signature are more likely retained in the collection of latches.

The RAS macro sends a global clock stop signal to all macros within the integrated circuit in response to receiving the error detection signal. In response to receiving the error detection signal from the current macro, the neighboring macro also halts operation, preferably before receiving the global clock stop signal from the RAS macro.

Also, it should be understood that at least some aspects of the present invention may be alternatively implemented in a computer-readable medium that stores a program product. Programs defining functions in the present invention can be delivered to a data storage system or a computer system via a variety of signal-bearing media, which include, without limitation, non-writable storage media (e.g., CD-ROM), writable storage media (e.g., floppy diskette, hard disk drive, read/write CD-ROM, optical media), and communication media, such as computer and telephone networks including Ethernet. It should be understood, therefore, in such signal-bearing media, when carrying or encoding computer-readable instructions that direct method functions in the present invention, represent alternative embodiments of the present invention. Further, it is understood that the present invention may be implemented by a system having means in the form of hardware, software, or a combination of software and hardware as described herein or their equivalent.

While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.