Title:
Methods of enabling polysilicon gate electrodes for high-k gate dielectrics
Kind Code:
A1


Abstract:
Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors are formed with an optional interfacial oxide, such as SiO2 or oxy-nitride, to overlay a semiconductor substrate which will be conductively doped for PMOS and NMOS regions. Then a dielectric possessing a high dielectric constant of least seven or greater (also referred to as a high-k dielectric) is deposited on the interfacial oxide. The high-k dielectric is covered with a thin monolayer of metal oxide (i.e., aluminum oxide, Al2O3) that is removed from the NMOS regions, but remains in the PMOS regions. The resulting NMOS transistor diffusion regions contain predominately metal to silicon bonds that create predominately Fermi level pinning near the valence band while the resulting PMOS transistor diffusion regions contain metal to silicon bonds that create predominately Fermi level pinning near the conduction band.



Inventors:
Weiner, Ronald A. (Boise, ID, US)
Application Number:
11/495653
Publication Date:
11/23/2006
Filing Date:
07/28/2006
Primary Class:
Other Classes:
257/274, 257/E21.637, 257/E21.639
International Classes:
H01L21/8238; H01L29/80
View Patent Images:
Related US Applications:



Primary Examiner:
AHMED, SELIM U
Attorney, Agent or Firm:
David J. Paul;Micron Technology, Inc. (8000 S. Federal Way, MS 1-525, Boise, ID, 83716, US)
Claims:
What is claimed is:

1. A complementary transistor pair on a semiconductor assembly comprising: an NMOS transistor comprising first metal-silicon bonds that create predominately Fermi level pinning near the valance band; and a PMOS transistor comprising second metal-silicon bonds that create predominately Fermi level pinning near the conductive band.

2. The complementary transistor pair of claim 1, wherein the first metal-silicon bonds comprise hafnium-silicon bonds.

3. The complementary transistor pair of claim 1, wherein the second metal-silicon bonds comprise aluminum-silicon bonds.

4. A complementary transistor pair on a semiconductor assembly comprising: an NMOS transistor comprising hafnium-silicon bonds that create predominately Fermi level pinning near the valance band; and a PMOS transistor comprising aluminum-silicon bonds that create predominately Fermi level pinning near the conductive band.

5. A semiconductor memory device having a complementary transistor pair comprising: an NMOS transistor comprising first metal-silicon bonds that create predominately Fermi level pinning near the valance band; and a PMOS transistor comprising second metal-silicon bonds that create predominately Fermi level pinning near the conductive band.

6. The complementary transistor pair of claim 5, wherein the first metal-silicon bonds comprise hafnium-silicon bonds.

7. The complementary transistor pair of claim 5, wherein the second metal-silicon bonds comprise aluminum-silicon bonds.

8. A semiconductor memory device having a complementary transistor pair comprising: an NMOS transistor comprising hafnium-silicon bonds that create predominately Fermi level pinning near the valance band; and a PMOS transistor comprising aluminum-silicon bonds that create predominately Fermi level pinning near the conductive band.

9. A complementary transistor pair on a semiconductor assembly comprising: a PMOS transistor comprising: a PMOS transistor gate dielectric of silicon dioxide, a hafnium containing oxide and an aluminum oxide; and a PMOS transistor gate comprising a silicon material directly overlying the aluminum oxide, the silicon material and the aluminum oxide forming aluminum-silicon bonds that create predominately Fermi level pinning near the valance band; and an NMOS transistor comprising: an NMOS transistor gate dielectric of the silicon dioxide and the hafnium containing oxide; and an NMOS transistor gate comprising the silicon material directly overlying the hafnium containing oxide, the silicon material and the hafnium containing oxide forming hafnium-silicon bonds that create predominately Fermi level pinning near the conductive band.

10. The complementary transistor pair of claim 9, wherein the hafnium containing oxide is HfO2.

11. The complementary transistor pair of claim 9, wherein the hafnium containing oxide is HfSiO.

12. The complementary transistor pair of claim 9, wherein the silicon material is polysilicon.

13. The complementary transistor pair of claim 9, wherein the silicon dioxide is a nitrided silicon dioxide.

14. A semiconductor memory device having a complementary transistor pair comprising: a PMOS transistor comprising: a PMOS transistor gate dielectric of silicon dioxide, a hafnium containing oxide and an aluminum oxide; and a PMOS transistor gate comprising a silicon material directly overlying the aluminum oxide, the silicon material and the aluminum oxide forming aluminum-silicon bonds that create predominately Fermi level pinning near the valance band; and an NMOS transistor comprising: an NMOS transistor gate dielectric of the silicon dioxide and the hafnium containing oxide; and an NMOS transistor gate comprising the silicon material directly overlying the hafnium containing oxide, the silicon material and the hafnium containing oxide forming hafnium-silicon bonds that create predominately Fermi level pinning near the conductive band.

15. The complementary transistor pair of claim 14, wherein the hafnium containing oxide is HfO2.

16. The complementary transistor pair of claim 14, wherein the hafnium containing oxide is HfSiO.

17. The complementary transistor pair of claim 14, wherein the silicon material is polysilicon.

18. The complementary transistor pair of claim 14, wherein the silicon dioxide is a nitrided silicon dioxide.

Description:

This application is a divisional to U.S. patent application Ser. No. 10/913,281, filed Aug. 6, 2004.

FIELD OF THE INVENTION

This invention relates to semiconductor devices and fabrication processes thereof. The invention particularly relates to complementary transistors and a method to fabricate the complementary transistors that utilize transistor gate dielectric materials possessing a high dielectric constant.

BACKGROUND OF THE INVENTION

Complementary Metal Oxide Semiconductor (CMOS) devices are dominated by n-channel (NMOS) and p-channel (PMOS) transistor structures. Various physical characteristics of each type of transistor determine the threshold voltage (Vt) that must be overcome to invert the channel region and cause a given transistor to conduct majority carriers (either by electrons movement in an NMOS device or by hole movement in a PMOS device).

One of the controlling physical characteristics is the work function of the material used to form the gate electrode of the transistor device. In semiconductor devices, such as a Dynamic Random Access Memory (DRAM) device, the transistor gates are predominantly made of polysilicon and an overlying layer of metal silicide, such as tungsten silicide and the gate dielectric is typically a high quality silicon oxide. The industry has moved to a transistor gate dielectric possessing a high dielectric constant of seven or greater (high-k dielectrics) for better leakage at given Effective Oxide Thickness (EOT). However, choosing a material with the appropriate work function as a gate electrode is still a challenge.

Studies have been conducted in one area of using high-k dielectric concerning Fermi-level pinning at the polysilicon/metal oxide interface of the transistor gate structure. Taking HfO2, for example, the hafnium and the polysilicon form Hafnium-Silicon bonds whose energy level in the band gap causes the Fermi-Level of the polysilicon to be pinned near the conduction band. With this scenario, using the HfO2 as the transistor gate dielectric in an NMOS device, a small shift in the transistor Vt, relative to N+ polysilicon on SiO2 will occur due to Hafnium-Silicon interface. However, applying this case in a PMOS device, a large shift in the transistor Vt will occur due to the Hafnium-Silicon bonds still pinning the Fermi-Level of the polysilicon near the conduction band.

Taking Al2O3, for example, the aluminum and the polysilicon form Aluminum-Silicon bonds that cause the Fermi-Level of the polysilicon to be pinned near the valence band due to the creation of the interface states that reside close to the valence band. With this scenario, using the Al2O3 as the transistor gate dielectric in a PMOS device, a small shift in the transistor Vt will occur due to P+ Aluminum-Silicon interface. However, applying this case in an NMOS device a large shift in the transistor Vt will occur due to the Aluminum-Silicon interface still having the Fermi-Level of the polysilicon being pinned near the conduction band and the transistor will not function in the desired range.

CMOS transistor devices that use the traditional polysilicon gate electrodes in combination with a metal oxide dielectric (high-k dielectric) must be fabricated such that the NMOS and PMOS devices will each possess a suitable transistor threshold voltage (Vt).

There is a need for the construction of CMOS devices using high-k dielectric materials for the transistor gate dielectric which will successfully be used to form both n-channel (NMOS) and p-channel (PMOS) transistors in semiconductor devices.

SUMMARY OF THE INVENTION

Exemplary implementations of the present invention include complementary transistors and methods of forming the complementary transistors on a semiconductor assembly by optionally forming an interfacial oxide, such as SiO2 or oxy-nitride, for electron or hole mobility, to overlay a semiconductor substrate which will be conductively doped for PMOS and NMOS regions. Then a dielectric possessing a high dielectric constant of least seven or greater (also referred to herein as a high-k dielectric) is deposited on the interfacial oxide. The high-k dielectric is covered with a thin monolayer of metal oxide (i.e., aluminum oxide, Al2O3) that is removed from the NMOS regions, but remains in the PMOS regions. The resulting NMOS transistor diffusion regions contain predominately metal to silicon bonds that create predominately Fermi level pinning near the valence band while the resulting PMOS transistor diffusion regions contain metal to silicon bonds that create predominately Fermi level pinning near the conduction band.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a semiconductor substrate section showing the early stages of an semiconductor assembly having N-WELL and P-WELL regions formed in a silicon substrate partially separated by an isolation material and a thermally grown dielectric layer, which can having varying thickness, is formed over the Well regions, according to an embodiment of the present invention.

FIG. 2 is a subsequent cross-sectional view taken from FIG. 1 following the formation of a first high-k dielectric layer on the thermally grown dielectric layer which in turn is covered with a second high-k dielectric layer.

FIG. 3 is a subsequent cross-sectional view taken from FIG. 2 following the patterning of a photoresist over the N-WELL region, thus exposing the second high-k dielectric layer overlying the P-WELL region.

FIG. 4 is a subsequent cross-sectional view taken from FIG. 3 following removal of the exposed second high-k dielectric layer and the stripping of the photoresist.

FIG. 5 is a subsequent cross-sectional view taken from FIG. 4 following the deposition of a polysilicon layer and conductive implanting thereof.

FIG. 6 is a subsequent cross-sectional view taken from FIG. 5 following the completion of a complementary transistor pair having differing transistor gate dielectrics.

FIG. 7 is a simplified block diagram of a semiconductor system comprising a processor and memory device to which the present invention may be applied.

DETAILED DESCRIPTION OF THE INVENTION

The following exemplary implementations are in reference to complementary transistors and the formation thereof. While the concepts of the present invention are conducive to transistor structures for semiconductor memory devices, the concepts taught herein may be applied to other semiconductor devices that would likewise benefit from the use of the process disclosed herein. Therefore, the depictions of the present invention in reference to transistor structures for semiconductor memory devices are not meant to so limit the extent to which one skilled in the art may apply the concepts taught hereinafter.

In the following description, the terms “wafer” and “substrate” are to be understood as a semiconductor-based material including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, silicon-on-insulator, silicon-on-saphire, germanium, or gallium arsenide, among others.

An exemplary implementation of the present invention is depicted in FIGS. 1-6. Referring now to FIG. 1, substrate 10 is processed to the point where P-WELL region 12 and N-WELL region 13 are formed in substrate 10. P-WELL region 12 represents a region containing a concentration of p-type conductive dopants, while N-WELL region 13 represents a region containing a concentration of n-type conductive dopants. Isolation material 11 partially separates and electrically isolates the upper portions of the Well regions from one another. Dielectric material 14 is deposited over the surfaces of N-WELL region 12, P-WELL region 13 and isolation material 11. Dielectric material 14 may be a thermally grown oxide material or a nitrided thermally grown oxide material formed by methods know to those skilled in the art. Though not shown, a boron barrier layer may also be included if desired.

Referring now to FIG. 2, a first material 20 and second material 21, each being a high-k dielectric material, are deposited on dielectric material 14. The first material 20 may be a metal oxide, preferably HfO2 or HfSiO and the second material 21 may be a metal oxide, preferably Al2O3. The first metal oxide dielectric material 20 must be a material that contains a metal component that when allowed to form a metal silicon interface (such an interface will be formed by a subsequent deposition of a polysilicon layer as described in reference to FIG. 5), the metal-Silicon bonds will create predominately Fermi level pinning near the valence band for a subsequently formed NMOS transistor. The second metal oxide dielectric material 21 must be a material that contains a metal component that when allowed to form a metal silicon interface, the metal-Silicon bonds will create predominately Fermi level pinning near the conduction band in a subsequently formed PMOS transistor. The second metal oxide dielectric material 21 is deposited by a Atomic Layer Deposition (ALD) process know to one skilled in the art. It is preferred that the second metal oxide dielectric material 21, such as Al2O3, be deposited only several monolayers in thickness (i.e., several atomic layers), such that a sufficient amount of aluminum atoms cover the surface of the first metal dielectric material in order to provide the desired Fermi-Level pinning as discussed in the subsequent processing steps.

Referring now to FIG. 3, photoresist 30 is formed and patterned to cover the portion of second metal oxide dielectric material 21 that overlies N-WELL region 13, while exposing the portion of second metal oxide dielectric material 21 that overlies P-WELL region 12.

Referring now to FIG. 4, the exposed portion of the second metal oxide dielectric material is removed and photoresist 30 is stripped, thus leaving behind the portion of second metal oxide dielectric material 21 that overlies N-WELL region 13. The remaining portion of second metal oxide dielectric material 21 will provide the necessary metal-silicon bonds required to create predominately Fermi level pinning near the conduction band in a subsequently formed PMOS transistor. For the exposed portion of the first metal oxide dielectric material the necessary metal-silicon bonds required to create predominately Fermi level pinning near the valance band in a subsequently formed NMOS transistor.

Referring now to FIG. 5, a silicon material 50, such as a polysilicon layer, is formed over the exposed portion of first metal oxide dielectric material 20 and the remaining portion of second metal dielectric material 21. The silicon material 50 creates a first interface between the first metal oxide dielectric material, containing metal 1 atoms (overlying the P-WELL region) and a second interface between the second metal oxide dielectric material containing metal 2 atoms (overlying the N-WELL region). During deposition of the silicon material, metal 1 to silicon bonds will form along the first interface. In the same manner metal 2 to silicon bonds will form along the second interface. In one example, if first metal oxide dielectric material is HfO2 or HfSiO, hafnium to silicon bonds will be formed. If the second metal oxide dielectric material is Al2O3, then aluminum-silicon bonds will be formed.

Referring now to FIG. 6, process steps known to one skilled in the art are conducted to form a pair of completed CMOS transistors, namely NMOS transistor 67 and PMOS transistor 68, separated by trench isolation material 11. The transistors are formed using conventional fabrication techniques to pattern and etch each transistor gate, followed by implanting the source and drain regions 64 into P-WELL 12 to an n-type conductivity to form an n-channel transistor (NMOS) 67 and implanting the source and drain regions 65 into N-WELL 13 to a p-type conductivity to form a p-channel transistor (PMOS) 68. The transistor gate structure of NMOS transistor 67 is electrically isolated from P-WELL 12 by gate dielectric 60 which is made up of thermally grown oxide 14 and a first metal oxide dielectric material 20, such as HfO2. The transistor gate structure is made up of silicon material 50, such as polysilicon and a metal silicide 62, such as tungsten silicide. The gate structure is then covered with isolation gate spacers 66 and isolation cap 63. Silicon material 50 and first metal oxide dielectric material form a metal dielectric/silicon interface and thus metal-silicon bonds in the NMOS transistor gate structure that create predominately Fermi level pinning near the valance band as described in the present invention. In the example using HfO2 or HfSiO as the first metal oxide dielectric material, the hafnium atoms and the silicon atoms form hafnium-silicon bonds that create predominately Fermi level pinning near the valance band.

The transistor gate structure of PMOS transistor 68 is isolated from N-WELL 13 by gate dielectric 61, which is made up of thermally grown oxide 14, a first metal dielectric material 20, such as HfO2, and a second metal oxide dielectric material 21, such as Al2O3. The transistor gate structure is made up of silicon material 50, such as polysilicon and a metal silicide 62, such as tungsten silicide. The gate structure is then covered with isolation gate spacers 66 and isolation cap 63. Silicon material 50 and second metal oxide dielectric material form a metal dielectric/silicon interface and thus metal-silicon bonds in the PMOS transistor gate structure that create predominately Fermi level pinning near the conduction band as described in the present invention. In the example using Al2O3 as the second metal oxide dielectric material, the aluminum atoms and the silicon atoms form aluminum-silicon bonds that create predominately Fermi level pinning near the conduction band.

The exemplary embodiment has been discussed in reference to forming a complementary transistor pair for use in CMOS applications, such as memory devices. However, these concepts, taught in the exemplary embodiments, may be utilized by one of ordinary skill in the art to form complementary transistor pairs for use in most all CMOS applications. For example, the present invention may be applied to a semiconductor system, such as the one depicted in FIG. 7, the general operation of which is known to one skilled in the art.

FIG. 7 represents a general block diagram of a semiconductor system comprising a processor 70 and a memory device 71 showing the basic sections of a memory integrated circuit, such as row and column address buffers, 73 and 74, row and column decoders, 75 and 76, sense amplifiers 77, memory array 78 and data input/output 79, which are manipulated by control/timing signals from the processor through control 72.

It is to be understood that, although the present invention has been described with reference to two exemplary embodiments, various modifications, known to those skilled in the art, may be made to the disclosed structure and process herein without departing from the invention as recited in the several claims appended hereto.