Title:
Compensation for horizontal skew between adjacent rows of nozzles on a printhead module
Kind Code:
A1


Abstract:
A printer controller for supplying dot data to a printhead in a predetermined order, the printhead comprising at least a first printhead module having a plurality of rows of printing nozzles, the printer controller being configured to order and time the supply of the dot data to the first printhead module such that a relative skew between adjacent rows of printing nozzles on the at least one printhead module, in a direction normal to a direction of printing, is at least partially compensated for.



Inventors:
Walmsley, Simon Robert (Balmain, AU)
Plunkett, Richard Thomas (Balmain, AU)
Application Number:
10/727162
Publication Date:
04/20/2006
Filing Date:
12/02/2003
Assignee:
SILVERBROOK RESEARCH PTY LTD
Primary Class:
International Classes:
B41J29/38; B41J2/05; G06F21/00; H04L9/00; H04N1/405
View Patent Images:



Primary Examiner:
UHLENHAKE, JASON S
Attorney, Agent or Firm:
SILVERBROOK RESEARCH PTY LTD (393 DARLING STREET, BALMAIN, 2041, AU)
Claims:
1. A printer controller for supplying dot data to a printhead in a predetermined order, the printhead comprising at least a first printhead module having a plurality of rows of printing nozzles, the printer controller being configured to order and time the supply of the dot data to the first printhead module such that a relative skew between adjacent rows of printing nozzles on the at least one printhead module, in a direction normal to a direction of printing, is at least partially compensated for.

2. A printer controller according to claim 1, wherein the printer controller is configured to at least partially compensate for the relative skew between adjacent rows in each of a plurality of sets of the adjacent rows.

3. A printer controller according to claim 1, wherein the relative skew between each of the plurality of the sets of the adjacent rows is the same.

4. A printer controller according to claim 1, wherein the printer controller is configured to compensate for the skew by introducing a relative delay into the dot data destined for at least one of the rows of printing nozzles.

5. A printer controller according to claim 4, wherein the printhead is configured to print the dots at a predetermined spacing across its width, and wherein the delay introduced by the printer controller equates to an integral multiple of the spacing.

6. A printer controller according to claim 5, wherein the printhead defines a printable region between printing boundaries, and wherein nozzles of at least one of the rows of at least one of the at least one printhead modules are positioned outside the printable region due to the skew between adjacent rows of the nozzles on the at least one printhead module, the printer controller being configured to introduce a relative delay into the dot data supplied to at least one of the rows such that the nozzles outside the printable region do not print.

7. A printer controller according to claim 1, wherein the at least one printhead module includes at least one pair of adjacent rows of the nozzles such that each row of the pair is configured to print the same ink, the printhead being configured to provide the dot data to the pair of adjacent rows such that the dot data is shifted serially through the first of the rows then through the second of the rows, until the dot data has been supplied to all the nozzles.

8. A printer controller according to claim 7, the printhead being configured to provide the dot data to the pair of adjacent rows such that the dot data is shifted serially through the first of the rows in a first direction then looped back through the second of the rows in a second direction opposite the first, until the dot data has been supplied to all the nozzles.

9. A printer controller according to claim 7, wherein the printhead is configured to print a series of printhead-width rows of the dots, and wherein the first and second rows are configured to print odd and even dots, respectively, of the printhead-width rows, the printhead controller being configured to supply the one or more first rows with odd dot data and the one or more second rows with even dot data.

10. A printer controller according to claim 7, including a plurality of the pairs of rows, the printer controller being configured to supply the dot data such that any relative skew between the first and second rows of each pair of rows, in a direction normal to a direction of printing, is at least partially compensated for.

11. A printer controller according to claim 1, wherein each printhead module is configured to print a plurality of independent inks, and wherein the nozzles in each row are configured to print in one of the inks, the printhead controller being configured to supply each of the inks to at least one row of at least one of the printhead modules.

12. A printer controller according to claim 1, wherein the printhead is a pagewidth printhead.

13. A printer controller according to claim 1, wherein the printhead comprises a plurality of the printhead modules.

14. A printer controller according to claim 13, wherein at least some of the printhead modules are of mutually unequal length, the printer controller being configured to order and time the supply of the dot data to the compensate for the unequal length.

15. A printer controller according to claim 13, configured to at least partially compensate for any relative skew between adjacent rows of the nozzles on adjacent ones of the printhead modules.

16. A printer controller according to claim 1, being selectively configurable to compensate at least partially for a plurality of potential relative skews.

17. A printer controller according to claim 1, being configured to compensate at least partly for a fixed amount of the skew.

18. A printer engine comprising the printer engine controller and the printhead according to claim 5, wherein the nozzles of the printhead are disposed in a printable region between printing boundaries of the printhead, and the printhead includes at least one logical nozzle located outside the printable zone that can accept data but is not capable of printing, the logical nozzles being arranged to introduce a relative delay into the dot data supplied to at least one of the rows, such that dot data is supplied to the correct nozzles for printing.

Description:

FIELD OF INVENTION

The present invention relates to techniques for compensating for horizontal displacement between adjacent rows of printhead nozzles that extend across a printhead.

The invention has primarily been developed for use with a printhead comprising one or more printhead modules constructed using microelectromechanical systems (MEMS) techniques, and will be described with reference to this application. However, it will be appreciated that the invention can be applied to other types of printing technologies in which analogous problems are faced.

BACKGROUND OF INVENTION

Manufacturing a printhead that has relatively high resolution and print-speed raises a number of problems.

Difficulties in manufacturing pagewidth printheads of any substantial size arise due to the relatively small dimensions of standard silicon wafers that are used in printhead (or printhead module) manufacture. For example, if it is desired to make an 8 inch wide pagewidth printhead, only one such printhead can be laid out on a standard 8-inch wafer, since such wafers are circular in plan. Manufacturing a pagewidth printhead from two or more smaller modules can reduce this limitation to some extent, but raises other problems related to providing a joint between adjacent printhead modules that is precise enough to avoid visible artefacts (which would typically take the form of noticeable lines) when the printhead is used. The problem is exacerbated in relatively high-resolution applications because of the tight tolerances dictated by the small spacing between nozzles.

The quality of a joint region between adjacent printhead modules relies on factors including a precision with which the abutting ends of each module can be manufactured, the accuracy with which they can be aligned when assembled into a single printhead, and other more practical factors such as management of ink channels behind the nozzles. It will be appreciated that the difficulties include relative vertical displacement of the printhead modules with respect to each other.

Whilst some of these issues may be dealt with by careful design and manufacture, the level of precision required renders it relatively expensive to manufacture printheads within the required tolerances. It would be desirable to provide a solution to one or more of the problems associated with precision manufacture and assembly of multiple printhead modules to form a printhead, and especially a pagewidth printhead.

In some cases, it is desirable to produce a number of different printhead module types or lengths on a substrate to maximise usage of the substrate's surface area. However, different sizes and types of modules will have different numbers and layouts of print nozzles, potentially including different horizontal and vertical offsets. Where two or more modules are to be joined to form a single printhead, there is also the problem of dealing with different seam shapes between abutting ends of joined modules, which again may incorporate vertical or horizontal offsets between the modules. Printhead controllers are usually dedicated application specific integrated circuits (ASICs) designed for specific use with a single type of printhead module, that is used by itself rather than with other modules. It would be desirable to provide a way in which different lengths and types of printhead modules could be accounted for using a single printer controller.

Printer controllers face other difficulties when two or more printhead modules are involved, especially if it is desired to send dot data to each of the printheads directly (rather than via a single printhead connected to the controller). One concern is that data delivered to different length controllers at the same rate will cause the shorter of the modules to be ready for printing before any longer modules. Where there is little difference involved, the issue may not be of importance, but for large length differences, the result is that the bandwidth of a shared memory from which the dot data is supplied to the modules is effectively left idle once one of the modules is full and the remaining module or modules is still being filled. It would be desirable to provide a way of improving memory bandwidth usage in a system comprising a plurality of printhead modules of uneven length.

In any printing system that includes multiple nozzles on a printhead or printhead module, there is the possibility of one or more of the nozzles failing in the field, or being inoperative due to manufacturing defect. Given the relatively large size of a typical printhead module, it would be desirable to provide some form of compensation for one or more “dead” nozzles. Where the printhead also outputs fixative on a per-nozzle basis, it is also desirable that the fixative is provided in such a way that dead nozzles are compensated for.

A printer controller can take the form of an integrated circuit, comprising a processor and one or more peripheral hardware units for implementing specific data manipulation functions. A number of these units and the processor may need access to a common resource such as memory. One way of arbitrating between multiple access requests for a common resource is timeslot arbitration, in which access to the resource is guaranteed to a particular requestor during a predetermined timeslot.

One difficulty with this arrangement lies in the fact that not all access requests make the same demands on the resource in terms of timing and latency. For example, a memory read requires that data be fetched from memory, which may take a number of cycles, whereas a memory write can commence immediately. Timeslot arbitration does not take into account these differences, which may result in accesses being performed in a less efficient manner than might otherwise be the case. It would be desirable to provide a timeslot arbitration scheme that improved this efficiency as compared with prior art timeslot arbitration schemes.

Also of concern when allocating resources in a timeslot arbitration scheme is the fact that the priority of an access request may not be the same for all units. For example, it would be desirable to provide a timeslot arbitration scheme in which one requestor (typically the memory) is granted special priority such that its requests are dealt with earlier than would be the case in the absence of such priority.

In systems that use a memory and cache, a cache miss (in which an attempt to load data or an instruction from a cache fails) results in a memory access followed by a cache update. It is often desirable when updating the cache in this way to update data other than that which was actually missed. A typical example would be a cache miss for a byte resulting in an entire word or line of the cache associated with that byte being updated. However, this can have the effect of tying up bandwidth between the memory (or a memory manager) and the processor where the bandwidth is such that several cycles are required to transfer the entire word or line to the cache. It would be desirable to provide a mechanism for updating a cache that improved cache update speed and/or efficiency.

Most integrated circuits an externally provided signal as (or to generate) a clock, often provided from a dedicated clock generation circuit. This is often due to the difficulties of providing an onboard clock that can operate at a speed that is predictable. Manufacturing tolerances of such on-board clock generation circuitry can result in clock rates that vary by a factor of two, and operating temperatures can increase this margin by an additional factor of two. In some cases, the particular rate at which the clock operates is not of particular concern. However, where the integrated circuit will be writing to an internal circuit that is sensitive to the time over which a signal is provided, it may be undesirable to have the signal be applied for too long or short a time. For example, flash memory is sensitive to being written too for too long a period. It would be desirable to provide a mechanism for adjusting a rate of an on-chip system clock to take into account the impact of manufacturing variations on clockspeed.

One form of attacking a secure chip is to induce (usually by increasing) a clock speed that takes the logic outside its rated operating frequency. One way of doing this is to reduce the temperature of the integrated circuit, which can cause the clock to race. Above a certain frequency, some logic will start malfunctioning. In some cases, the malfunction can be such that information on the chip that would otherwise be secure may become available to an external connection. It would be desirable to protect an integrated circuit from such attacks.

In an integrated circuit comprising non-volatile memory, a power failure can result in unintentional behaviour. For example, if an address or data becomes unreliable due to falling voltage supplied to the circuit but there is still sufficient power to cause a write, incorrect data can be written. Even worse, the data (incorrect or not) could be written to the wrong memory. The problem is exacerbated with multi-word writes. It would be desirable to provide a mechanism for reducing or preventing spurious writes when power to an integrated circuit is failing.

In an integrated circuit, it is often desirable to reduce unauthorised access to the contents of memory. This is particularly the case where the memory includes a key or some other form of security information that allows the integrated circuit to communicate with another entity (such as another integrated circuit, for example) in a secure manner. It would be particularly advantageous to prevent attacks involving direct probing of memory addresses by physically investigating the chip (as distinct from electronic or logical attacks via manipulation of signals and power supplied to the integrated circuit).

It is also desirable to provide an environment where the manufacturer of the integrated circuit (or some other authorised entity) can verify or authorize code to be run on an integrated circuit.

Another desideratum would be the ability of two or more entities, such as integrated circuits, to communicate with each other in a secure manner. It would also be desirable to provide a mechanism for secure communication between a first entity and a second entity, where the two entities, whilst capable of some form of secure communication, are not able to establish such communication between themselves.

In a system that uses resources (such as a printer, which uses inks) it may be desirable to monitor and update a record related to resource usage. Authenticating ink quality can be a major issue, since the attributes of inks used by a given printhead can be quite specific. Use of incorrect ink can result in anything from misfiring or poor performance to damage or destruction of the printhead. It would therefore be desirable to provide a system that enables authentication of the correct ink being used, as well as providing various support systems secure enabling refilling of ink cartridges.

In a system that prevents unauthorized programs from being loaded onto or run on an integrated circuit, it can be laborious to allow developers of software to access the circuits during software development. Enabling access to integrated circuits of a particular type requires authenticating software with a relatively high-level key. Distributing the key for use by developers is inherently unsafe, since a single leak of the key outside the organization could endanger security of all chips that use a related key to authorize programs. Having a small number of people with high-security clearance available to authenticate programs for testing can be inconvenient, particularly in the case where frequent incremental changes in programs during development require testing. It would be desirable to provide a mechanism for allowing access to one or more integrated circuits without risking the security of other integrated circuits in a series of such integrated circuits.

In symmetric key security, a message, denoted by M, is plaintext. The process of transforming M into ciphertext C, where the substance of M is hidden, is called encryption. The process of transforming C back into M is called decryption. Referring to the encryption function as E, and the decryption function as D, we have the following identities:
E[M]=C
D[C]=M

Therefore the following identity is true:
D[E[M]]=M

A symmetric encryption algorithm is one where:

    • the encryption function E relies on key K1,
    • the decryption function D relies on key K2,
    • K2 can be derived from K1, and
    • K1 can be derived from K2,

In most symmetric algorithms, K1 equals K2. However, even if K1 does not equal K2, given that one key can be derived from the other, a single key K can suffice for the mathematical definition. Thus:
EK[M]=C
DK[C]=M

The security of these algorithms rests very much in the key K. Knowledge of K allows anyone to encrypt or decrypt. Consequently K must remain a secret for the duration of the value of M. For example, M may be a wartime message “My current position is grid position 123-456”. Once the war is over the value of M is greatly reduced, and if K is made public, the knowledge of the combat unit's position may be of no relevance whatsoever. The security of the particular symmetric algorithm is a function of two things: the strength of the algorithm and the length of the key.

An asymmetric encryption algorithm is one where:

    • the encryption function E relies on key K1,
    • the decryption function D relies on key K2,
    • K2 cannot be derived from K1 in a reasonable amount of time, and
    • K1 cannot be derived from K2 in a reasonable amount of time.

Thus:
EK1[M]=C
DK2[C]=M

These algorithms are also called public-key because one key K1 can be made public. Thus anyone can encrypt a message (using K1) but only the person with the corresponding decryption key (K2) can decrypt and thus read the message.

In most cases, the following identity also holds:
EK2[M]=C
DK1[C]=M

This identity is very important because it implies that anyone with the public key K1 can see M and know that it came from the owner of K2. No-one else could have generated C because to do so would imply knowledge of K2. This gives rise to a different application, unrelated to encryption - digital signatures.

A number of public key cryptographic algorithms exist. Most are impractical to implement, and many generate a very large C for a given M or require enormous keys. Still others, while secure, are far too slow to be practical for several years. Because of this, many public key systems are hybrid—a public key mechanism is used to transmit a symmetric session key, and then the session key is used for the actual messages.

All of the algorithms have a problem in terms of key selection. A random number is simply not secure enough. The two large primes p and q must be chosen carefully—there are certain weak combinations that can be factored more easily (some of the weak keys can be tested for). But nonetheless, key selection is not a simple matter of randomly selecting 1024 bits for example. Consequently the key selection process must also be secure.

Symmetric and asymmetric schemes both suffer from a difficulty in allowing establishment of multiple relationships between one entity and a two or more others, without the need to provide multiple sets of keys. For example, if a main entity wants to establish secure communications with two or more additional entities, it will need to maintain a different key for each of the additional entities. For practical reasons, it is desirable to avoid generating and storing large numbers of keys. To reduce key numbers, two or more of the entities may use the same key to communicate with the main entity. However, this means that the main entity cannot be sure which of the entities it is communicating with. Similarly, messages from the main entity to one of the entities can be decrypted by any of the other entities with the same key. It would be desirable if a mechanism could be provided to allow secure communication between a main entity and one or more other entities that overcomes at least some of the shortcomings of prior art.

In a system where a first entity is capable of secure communication of some form, it may be desirable to establish a relationship with another entity without providing the other entity with any information related the first entity's security features. Typically, the security features might include a key or a cryptographic function. It would be desirable to provide a mechanism for enabling secure communications between a first and second entity when they do not share the requisite secret function, key or other relationship to enable them to establish trust.

A number of other aspects, features, preferences and embodiments are disclosed in the Detailed Description of the Preferred Embodiment below.

SUMMARY OF INVENTION

In accordance with a first aspect of the invention, there is provided a printer controller for supplying dot data to a printhead in a predetermined order, the printhead comprising at least a first printhead module having a plurality of rows of printing nozzles, the printer controller being configured to order and time the supply of the dot data to the first printhead module such that a relative skew between adjacent rows of printing nozzles on the at least one printhead module, in a direction normal to a direction of printing, is at least partially compensated for.

Preferably, the printer controller is configured to at least partially compensate for the relative skew between adjacent rows in each of a plurality of sets of the adjacent rows.

In a preferred embodiment, wherein the relative skew between each of the plurality of the sets of the adjacent rows is the same.

Preferably, the printer controller is configured to compensate for the skew by introducing a relative delay into the dot data destined for at least one of the rows of printing nozzles. More preferably, the printhead is configured to print the dots at a predetermined spacing across its width, and the delay introduced by the printer controller equates to an integral multiple of the spacing.

It is particularly preferred, that the printhead defines a printable region between printing boundaries. Nozzles of at least one of the rows of at least one of the at least one printhead modules are positioned outside the printable region due to the skew between adjacent rows of the nozzles on the at least one printhead module. The printer controller is configured to introduce a relative delay into the dot data supplied to at least one of the rows such that the nozzles outside the printable region do not print.

Preferably, the at least one printhead module includes at least one pair of adjacent rows of the nozzles such that each row of the pair is configured to print the same ink. The printhead is configured to provide the dot data to the pair of adjacent rows such that the dot data is shifted serially through the first of the rows then through the second of the rows, until the dot data has been supplied to all the nozzles. More preferably, the printhead is configured to provide the dot data to the pair of adjacent rows such that the dot data is shifted serially through the first of the rows in a first direction then looped back through the second of the rows in a second direction opposite the first, until the dot data has been supplied to all the nozzles.

Preferably, the printhead is configured to print a series of printhead-width rows of the dots, and wherein the first and second rows are configured to print odd and even dots, respectively, of the printhead-width rows, the printhead controller being configured to supply the one or more first rows with odd dot data and the one or more second rows with even dot data.

Preferably, the printhead has a plurality of the pairs of rows. The printer controller is configured to supply the dot data such that any relative skew between the first and second rows of each pair of rows, in a direction normal to a direction of printing, is at least partially compensated for.

In one embodiment, each printhead module is configured to print a plurality of independent inks, and the nozzles in each row are configured to print in one of the inks. The printhead controller being configured to supply each of the inks to at least one row of at least one of the printhead modules.

Preferably, at least some of the printhead modules are of mutually unequal length, the printer controller being configured to order and time the supply of the dot data to the compensate for the unequal length.

It is also preferable that the printer controller is configured to at least partially compensate for any relative skew between adjacent rows of the nozzles on adjacent ones of the printhead modules.

In a preferred form of the invention, the printer controller is selectively configurable to compensate at least partially for a plurality of potential relative skews.

In one form, the controller is configured to compensate at least partly for a fixed amount of the skew.

In accordance with a second aspect, the invention comprises the printer engine comprising a printer controller according to the first aspect and a printhead, wherein the nozzles of the printhead are disposed in a printable region between printing boundaries of the printhead. The printhead includes at least one logical nozzle located outside the printable zone that can accept data but is not capable of printing. The logical nozzles are arranged to introduce a relative delay into the dot data supplied to at least one of the rows, such that dot data is supplied to the correct nozzles for printing.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred and other embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 is an example of state machine notation

FIG. 2 shows document data flow in a printer

FIG. 3 is an example of a single printer controller (hereinafter “SoPEC”) A4 simplex printer system

FIG. 4 is an example of a dual SoPEC A4 duplex printer system

FIG. 5 is an example of a dual SoPEC A3 simplex printer system

FIG. 6 is an example of a quad SoPEC A3 duplex printer system

FIG. 7 is an example of a SoPEC A4 simplex printing system with an extra SoPEC used as DRAM storage

FIG. 8 is an example of an A3 duplex printing system featuring four printing SoPECs

FIG. 9 shows pages containing different numbers of bands

FIG. 10 shows the contents of a page band

FIG. 11 illustrates a page data path from host to SoPEC

FIG. 12 shows a page structure

FIG. 13 shows a SoPEC system top level partition

FIG. 14 shows a SoPEC CPU memory map (not to scale)

FIG. 15 is a block diagram of CPU

FIG. 16 shows CPU bus transactions

FIG. 17 shows a state machine for a CPU subsystem slave

FIG. 18 shows a SoPEC CPU memory map (not to scale)

FIG. 19 shows an external signal view of a memory management unit (hereinafter “MMU”) sub-block partition

FIG. 20 shows an internal signal view of an MMU sub-block partition

FIG. 21 shows a DRAM write buffer

FIG. 22 shows DIU waveforms for multiple transactions

FIG. 23 shows a SoPEC LEON CPU core

FIG. 24 shows a cache data RAM wrapper

FIG. 25 shows a realtime debug unit block diagram

FIG. 26 shows interrupt acknowledge cycles for single and pending interrupts

FIG. 27 shows an A3 duplex system featuring four printing SoPECs with a single SoPEC DRAM device

FIG. 28 is an SCB block diagram

FIG. 29 is a logical view of the SCB of FIG. 28

FIG. 30 shows an ISI configuration with four SoPEC devices

FIG. 31 shows half-duplex interleaved transmission from ISIMaster to ISISlave

FIG. 32 shows ISI transactions

FIG. 33 shows an ISI long packet

FIG. 34 shows an ISI ping packet

FIG. 35 shows a short ISI packet

FIG. 36 shows successful transmission of two long packets with sequence bit toggling

FIG. 37 shows sequence bit operation with errored long packet

FIG. 38 shows sequence bit operation with ACK error

FIG. 39 shows an ISI sub-block partition

FIG. 40 shows an ISI serial interface engine functional block diagram

FIG. 41 is an SIE edge detection and data 10 diagram

FIG. 42 is an SIE Rx/Tx state machine Tx cycle state diagram

FIG. 43 shows an SIE Rx/Tx state machine Tx bit stuff ‘0’ cycle state diagram

FIG. 44 shows an SIE Rx/Tx state machine Tx bit stuff ‘1’ cycle state diagram

FIG. 45 shows an SIE Rx/Tx state machine Rx cycle state diagram

FIG. 46 shows an SIE Tx functional timing example

FIG. 47 shows an SIE Rx functional timing example

FIG. 48 shows an SIE Rx/Tx FIFO block diagram

FIG. 49 shows SIE Rx/Tx FIFO control signal gating

FIG. 50 shows an SIE bit stuffing state machine Tx cycle state diagram

FIG. 51 shows an SIE bit stripping state machine Rx cycle state diagram

FIG. 52 shows a CRC16 generation/checking shift register

FIG. 53 shows circular buffer operation

FIG. 54 shows duty cycle select

FIG. 55 shows a GPIO partition

FIG. 56 shows a motor control RTL diagram

FIG. 57 is an input de-glitch RTL diagram

FIG. 58 is a frequency analyser RTL diagram

FIG. 59 shows a brushless DC controller

FIG. 60 shows a period measure unit

FIG. 61 shows line synch generation logic

FIG. 62 shows an ICU partition

FIG. 63 is an interrupt clear state diagram

FIG. 64 is a watchdog timer RTL diagram

FIG. 65 is a generic timer RTL diagram

FIG. 67 is a Pulse generator RTL diagram

FIG. 68 shows a SoPEC clock relationship

FIG. 69 shows a CPR block partition

FIG. 70 shows reset deglitch logic

FIG. 71 shows reset synchronizer logic

FIG. 72 is a clock gate logic diagram

FIG. 73 shows a PLL and Clock divider logic

FIG. 74 shows a PLL control state machine diagram

FIG. 75 shows a LSS master system-level interface

FIG. 76 shows START and STOP conditions

FIG. 77 shows an LSS transfer of 2 data bytes

FIG. 78 is an example of an LSS write to a QA Chip

FIG. 79 is an example of an LSS read from QA Chip

FIG. 80 shows an LSS block diagram

FIG. 81 shows an LSS multi-command transaction

FIG. 82 shows start and stop generation based on previous bus state

FIG. 83 shows an LSS master state machine

FIG. 84 shows LSS master timing

FIG. 85 shows a SoPEC system top level partition

FIG. 86 shows an ead bus with 3 cycle random DRAM read accesses

FIG. 87 shows interleaving of CPU and non-CPU read accesses

FIG. 88 shows interleaving of read and write accesses with 3 cycle random DRAM accesses

FIG. 89 shows interleaving of write accesses with 3 cycle random DRAM accesses

FIG. 90 shows a read protocol for a SoPEC Unit making a single 256-bit access

FIG. 91 shows a read protocol for a SoPEC Unit making a single 256-bit access

FIG. 92 shows a write protocol for a SoPEC Unit making a single 256-bit access

FIG. 93 shows a protocol for a posted, masked, 128-bit write by the CPU

FIG. 94 shows a write protocol shown for CDU making four contiguous 64-bit accesses

FIG. 95 shows timeslot-based arbitration

FIG. 96 shows timeslot-based arbitration with separate pointers

FIG. 97 shows a first example (a) of separate read and write arbitration

FIG. 98 shows a second example (b) of separate read and write arbitration

FIG. 99 shows a third example (c) of separate read and write arbitration

FIG. 100 shows a DIU partition

FIG. 101 shows a DIU partition

FIG. 102 shows multiplexing and address translation logic for two memory instances

FIG. 103 shows a timing of dau_dcu_valID, dcu_dau_adv and dcu_dau_wadv

FIG. 104 shows a DCU state machine

FIG. 105 shows random read timing

FIG. 106 shows random write timing

FIG. 107 shows refresh timing

FIG. 108 shows page mode write timing

FIG. 109 shows timing of non-CPU DIU read access

FIG. 110 shows timing of CPU DIU read access

FIG. 111 shows a CPU DIU read access

FIG. 112 shows timing of CPU DIU write access

FIG. 113 shows timing of a non-CDU/non-CPU DIU write access

FIG. 114 shows timing of CDU DIU write access

FIG. 115 shows command multiplexor sub-block partition

FIG. 116 shows command multiplexor timing at DIU requesters interface

FIG. 117 shows generation of re_arbitrate and re_arbitrate_wadv

FIG. 118 shows CPU interface and arbitration logic

FIG. 119 shows arbitration timing

FIG. 120 shows setting RotationSync to enable a new rotation.

FIG. 121 shows a timeslot based arbitration

FIG. 122 shows a timeslot based arbitration with separate pointers

FIG. 123 shows a CPU pre-access write lookahead pointer

FIG. 124 shows arbitration hierarchy

FIG. 125 shows hierarchical round-robin priority comparison

FIG. 126 shows a read multiplexor partition

FIG. 127 shows a read command queue (4 deep buffer)

FIG. 128 shows state-machines for shared read bus accesses

FIG. 129 shows a write multiplexor partition

FIG. 130 shows a read multiplexer timing for back-to-back shared read bus transfer

FIG. 131 shows a write multiplexer partition

FIG. 132 shows a block diagram of a PCU

FIG. 133 shows PCU accesses to PEP registers

FIG. 134 shows command arbitration and execution

FIG. 135 shows DRAM command access state machine

FIG. 136 shows an outline of contone data flow with respect to CDU

FIG. 137 shows a DRAM storage arrangement for a single line of JPEG 8×8 blocks in 4 colors

FIG. 138 shows a read control unit state machine

FIG. 139 shows a memory arrangement of JPEG blocks

FIG. 140 shows a contone data write state machine

FIG. 141 shows lead-in and lead-out clipping of contone data in multi-SoPEC environment

FIG. 142 shows a block diagram of CFU

FIG. 143 shows a DRAM storage arrangement for a single line of JPEG blocks in 4 colors

FIG. 144 shows a block diagram of color space converter

FIG. 145 shows a converter/invertor

FIG. 146 shows a high-level block diagram of LBD in context

FIG. 147 shows a schematic outline of the LBD and the SFU

FIG. 148 shows a block diagram of lossless bi-level decoder

FIG. 149 shows a stream decoder block diagram

FIG. 150 shows a command controller block diagram

FIG. 151 shows a state diagram for command controller (CC) state machine

FIG. 152 shows a next edge unit block diagram

FIG. 153 shows a next edge unit buffer diagram

FIG. 154 shows a next edge unit edge detect diagram

FIG. 155 shows a state diagram for the next edge unit state machine

FIG. 156 shows a line fill unit block diagram

FIG. 157 shows a state diagram for the Line Fill Unit (LFU) state machine

FIG. 158 shows a bi-level DRAM buffer

FIG. 159 shows interfaces between LBD/SFU/HCU

FIG. 160 shows an SFU sub-block partition

FIG. 161 shows an LBDPrevLineFifo sub-block

FIG. 162 shows timing of signals on the LBDPrevLineFIFO interface to DIU and address generator

FIG. 163 shows timing of signals on LBDPrevLineFIFO interface to DIU and address generator

FIG. 164 shows LBDNextLineFifo sub-block

FIG. 165 shows timing of signals on LBDNextLineFIFO interface to DIU and address generator

FIG. 166 shows LBDNextLineFIFO DIU interface state diagram

FIG. 167 shows an LDB to SFU write interface

FIG. 168 shows an LDB to SFU read interface (within a line)

FIG. 169 shows an HCUReadLineFifo Sub-block

FIG. 170 shows a DIU write Interface

FIG. 171 shows a DIU Read Interface multiplexing by select_hrfplf

FIG. 172 shows DIU read request arbitration logic

FIG. 173 shows address generation

FIG. 174 shows an X scaling control unit

FIG. 175 Y shows a scaling control unit

FIG. 176 shows an overview of X and Y scaling at HCU interface

FIG. 177 shows a high level block diagram of TE in context

FIG. 178 shows a QR Code

FIG. 179 shows Netpage tag structure

FIG. 180 shows a Netpage tag with data rendered at 1600 dpi (magnified view)

FIG. 181 shows an example of 2×2 dots for each block of QR code

FIG. 182 shows placement of tags for portrait & landscape printing

FIG. 183 shows agGeneral representation of tag placement

FIG. 184 shows composition of SoPEC's tag format structure

FIG. 185 shows a simple 3×3 tag structure

FIG. 186 shows 3×3 tag redesigned for 21×21 area (not simple replication)

FIG. 187 shows a TE Block Diagram

FIG. 188 shows a TE Hierarchy

FIG. 189 shows a block diagram of PCU accesses

FIG. 190 shows a tag encoder top-level FSM

FIG. 191 shows generated control signals

FIG. 192 shows logic to combine dot information and encoded data

FIG. 193 shows generation of Lastdotintag/1

FIG. 194 shows generation of Dot Position Valid

FIG. 195 shows generation of write enable to the TFU

FIG. 196 shows generation of Tag Dot Number

FIG. 197 shows TDI Architecture

FIG. 198 shows data flow through the TDI

FIG. 199 shows raw tag data interface block diagram

FIG. 200 shows an RTDI State Flow Diagram

FIG. 201 shows a relationship between TE_endoftagdata, cdu_startofbandstore and cdu_endofbandstore

FIG. 202 shows a TDi State Flow Diagram

FIG. 203 shows mapping of the tag data to codewords 0-7

FIG. 204 shows coding and mapping of uncoded fixed tag data for (15,5) RS encoder

FIG. 205 shows mapping of pre-coded fixed tag data

FIG. 206 shows coding and mapping of variable tag data for (15,7) RS encoder

FIG. 207 shows coding and mapping of uncoded fixed tag data for (15,7) RS encoder

FIG. 208 shows mapping of 2D decoded variable tag data

FIG. 209 shows a simple block diagram for an m=4 Reed Solomon encoder

FIG. 210 shows an RS encoder I/O diagram

FIG. 211 shows a (15,5) & (15,7) RS encoder block diagram

FIG. 212 shows a (15,5) RS encoder timing diagram

FIG. 213 shows a (15,7) RS encoder timing diagram

FIG. 214 shows a circuit for multiplying by alpha3

FIG. 215 shows adding two field elements

FIG. 216 shows an RS encoder implementation

FIG. 217 shows an encoded tag data interface

FIG. 218 shows an encoded fixed tag data interface

FIG. 219 shows an encoded variable tag data interface

FIG. 220 shows an encoded variable tag data sub-buffer

FIG. 221 shows a breakdown of the tag format structure

FIG. 222 shows a TFSI FSM state flow diagram

FIG. 223 shows a TFS block diagram

FIG. 224 shows a table A interface block diagram

FIG. 225 shows a table A address generator

FIG. 226 shows a table C interface block diagram

FIG. 227 shows a table B interface block diagram

FIG. 228 shows interfaces between TE, TFU and HCU

FIG. 229 shows a 16-byte FIFO in TFU

FIG. 230 shows a high level block diagram showing the HCU and its external interfaces

FIG. 231 shows a block diagram of the HCU

FIG. 232 shows a block diagram of the control unit

FIG. 233 shows a block diagram of determine advdot unit

FIG. 234 shows a page structure

FIG. 235 shows a block diagram of a margin unit

FIG. 236 shows a block diagram of a dither matrix table interface

FIG. 237 shows an example of reading lines of dither matrix from DRAM

FIG. 238 shows a state machine to read dither matrix table

FIG. 239 shows a contone dotgen unit

FIG. 240 shows a block diagram of dot reorg unit

FIG. 241 shows an HCU to DNC interface (also used in DNC to DWU, LLU to PHI)

FIG. 242 shows SFU to HCU interface (all feeders to HCU)

FIG. 243 shows representative logic of the SFU to HCU interface

FIG. 244 shows a high-level block diagram of DNC

FIG. 245 shows a dead nozzle table format

FIG. 246 shows set of dots operated on for error diffusion

FIG. 247 shows a block diagram of DNC

FIG. 248 shows a sub-block diagram of ink replacement unit

FIG. 249 shows a dead nozzle table state machine

FIG. 250 shows logic for dead nozzle removal and ink replacement

FIG. 251 shows a sub-block diagram of error diffusion unit

FIG. 252 shows a maximum length 32-bit LFSR used for random bit generation

FIG. 253 shows a high-level data flow diagram of DWU in context

FIG. 254 shows a printhead nozzle layout for 36-nozzle bi-lithic printhead

FIG. 255 shows a printhead nozzle layout for a 36-nozzle bi-lithic printhead

FIG. 256 shows a dot line store logical representation

FIG. 257 shows a conceptual view of printhead row alignment

FIG. 258 shows a conceptual view of printhead rows (as seen by the LLU and PHI)

FIG. 259 shows a comparison of 1.5×v 2× buffering

FIG. 260 shows an even dot order in DRAM (increasing sense, 13320 dot wide line)

FIG. 261 shows an even dot order in DRAM (decreasing sense, 13320 dot wide line)

FIG. 262 shows a dotline FIFO data structure in DRAM

FIG. 263 shows a DWU partition

FIG. 264 shows a buffer address generator sub-block

FIG. 265 shows a DIU Interface sub-block

FIG. 266 shows an interface controller state diagram

FIG. 267 shows a high level data flow diagram of LLU in context

FIG. 268 shows paper and printhead nozzles relationship (example with D1=D2=5)

FIG. 269 shows printhead structure and dot generate order

FIG. 270 shows an order of dot data generation and transmission

FIG. 271 shows a conceptual view of printhead rows

FIG. 272 shows a dotline FIFO data structure in DRAM (LLU specification)

FIG. 273 shows an LLU partition

FIG. 274 shows a dot generator RTL diagram

FIG. 275 shows a DIU interface

FIG. 276 shows an interface controller state diagram

FIG. 277 shows high-level data flow diagram of PHI in context

FIG. 278 is intentionally omitted

FIG. 279 shows printhead data rate equalization

FIG. 280 shows a printhead structure and dot generate order

FIG. 281 shows an order of dot data generation and transmission

FIG. 282 shows an order of dot data generation and transmission (single printhead case)

FIG. 283 shows printhead interface timing parameters

FIG. 284 shows printhead timing with margining

FIG. 285 shows a PHI block partition

FIG. 286 shows a sync generator state diagram

FIG. 287 shows a line sync de-glitch RTL diagram

FIG. 288 shows a fire generator state diagram

FIG. 289 shows a PHI controller state machine

FIG. 290 shows a datapath unit partition

FIG. 291 shows a dot order controller state diagram

FIG. 292 shows a data generator state diagram

FIG. 293 shows data serializer timing

FIG. 294 shows a data serializer RTL Diagram

FIG. 295 shows printhead types 0 to 7

FIG. 296 shows an ideal join between two dilithic printhead segments

FIG. 297 shows an example of a join between two bilithic printhead segments

FIG. 298 shows printable vs non-printable area under new definition (looking at colors as if 1 row only)

FIG. 299 shows identification of printhead nozzles and shift-register sequences for printheads in arrangement 1

FIG. 300 shows demultiplexing of data within the printheads in arrangement 1

FIG. 301 shows double data rate signalling for a type 0 printhead in arrangement 1

FIG. 302 shows double data rate signalling for a type 1 printhead in arrangement 1

FIG. 303 shows identification of printheads nozzles and shift-register sequences for printheads in arrangement 2

FIG. 304 shows demultiplexing of data within the printheads in arrangement 2

FIG. 305 shows double data rate signalling for a type 0 printhead in arrangement 2

FIG. 306 shows double data rate signalling for a type 1 printhead in arrangement 2

FIG. 307 shows all 8 printhead arrangements

FIG. 308 shows a printhead structure

FIG. 309 shows a column Structure

FIG. 310 shows a printhead dot shift register dot mapping to page

FIG. 311 shows data timing during printing

FIG. 312 shows print quality

FIG. 313 shows fire and select shift register setup for printing

FIG. 314 shows a fire pattern across butt end of printhead chips

FIG. 315 shows fire pattern generation

FIG. 316 shows determination of select shift register value

FIG. 317 shows timing for printing signals

FIG. 318 shows initialisation of printheads

FIG. 319 shows a nozzle test latching circuit

FIG. 320 shows nozzle testing

FIG. 321 shows a temperature reading

FIG. 322 shows CMOS testing

FIG. 323 shows a reticle layout

FIG. 324 shows a stepper pattern on Wafer

FIG. 325 shows relationship between datasets

FIG. 326 shows a validation hierarchy

FIG. 327 shows development of operating system code

FIG. 328 shows protocol for directly verifying reads from ChipR

FIG. 329 shows a protocol for signature translation protocol

FIG. 330 shows a protocol for a direct authenticated write

FIG. 331 shows an alternative protocol for a direct authenticated write

FIG. 332 shows a protocol for basic update of permissions

FIG. 333 shows a protocol for a multiple-key update

FIG. 334 shows a protocol for a single-key authenticated read

FIG. 335 shows a protocol for a single-key authenticated write

FIG. 336 shows a protocol for a single-key update of permissions

FIG. 337 shows a protocol for a single-key update

FIG. 338 shows a protocol for a multiple-key single-M authenticated read

FIG. 339 shows a protocol for a multiple-key authenticated write

FIG. 340 shows a protocol for a multiple-key update of permissions

FIG. 341 shows a protocol for a multiple-key update

FIG. 342 shows a protocol for a multiple-key multiple-M authenticated read

FIG. 343 shows a protocol for a multiple-key authenticated write

FIG. 344 shows a protocol for a multiple-key update of permissions

FIG. 345 shows a protocol for a multiple-key update

FIG. 346 shows relationship of permissions bits to M[n] access bits

FIG. 347 shows 160-bit maximal period LFSR

FIG. 348 shows clock filter

FIG. 349 shows tamper detection line

FIG. 350 shows an oversize nMOS transistor layout of Tamper Detection Line

FIG. 351 shows a Tamper Detection Line

FIG. 352 shows how Tamper Detection Lines cover the Noise Generator

FIG. 353 shows a prior art FET Implementation of CMOS inverter

FIG. 354 shows non-flashing CMOS

FIG. 355 shows components of a printer-based refill device

FIG. 356 shows refilling of printers by printer-based refill device

FIG. 357 shows components of a home refill station

FIG. 358 shows a three-ink reservoir unit

FIG. 359 shows refill of ink cartridges in a home refill station

FIG. 360 shows components of a commercial refill station

FIG. 361 shows an ink reservoir unit

FIG. 362 shows refill of ink cartridges in a commercial refill station (showing a single refill unit)

FIG. 363 shows equivalent signature generation

FIG. 364 shows a basic field definition

FIG. 365 shows an example of defining field sizes and positions

FIG. 366 shows permissions

FIG. 367 shows a first example of permissions for a field

FIG. 368 shows a second example of permissions for a field

FIG. 369 shows field attributes

FIG. 370 shows an output signature generation data format for Read

FIG. 371 shows an input signature verification data format for Test

FIG. 372 shows an output signature generation data format for Translate

FIG. 373 shows an input signature verification data format for WriteAuth

FIG. 374 shows input signature data format for ReplaceKey

FIG. 375 shows a key replacement map

FIG. 376 shows a key replacement map after K1 is replaced

FIG. 377 shows a key replacement process

FIG. 378 shows an output signature data format for GetProgramKey

FIG. 379 shows transfer and rollback process

FIG. 380 shows an upgrade flow

FIG. 381 shows authorised ink refill paths in the printing system

FIG. 382 shows an input signature verification data format for XferAmount

FIG. 383 shows a transfer and rollback process

FIG. 384 shows an upgrade flow

FIG. 385 shows authorised upgrade paths in the printing system

FIG. 386 shows a direct signature validation sequence

FIG. 387 shows signature validation using translation

FIG. 388 shows setup of preauth field attributes

FIG. 388A shows setup for multiple preauth fields

FIG. 389 shows a high level block diagram of QA Chip

FIG. 390 shows an analogue unit

FIG. 391 shows a serial bus protocol for trimming

FIG. 392 shows a block diagram of a trim unit

FIG. 393 shows a block diagram of a CPU of the QA chip

FIG. 394 shows block diagram of an MIU

FIG. 395 shows a block diagram of memory components

FIG. 396 shows a first byte sent to an IOU

FIG. 397 shows a block diagram of the IOU

FIG. 398 shows a relationship between external SDa and SClk and generation of internal signals

FIG. 399 shows block diagram of ALU

FIG. 400 shows a block diagram of DataSel

FIG. 401 shows a block diagram of ROR

FIG. 402 shows a block diagram of the ALU's IO block

FIG. 403 shows a block diagram of PCU

FIG. 404 shows a block diagram of an Address Generator Unit

FIG. 405 shows a block diagram for a Counter Unit

FIG. 406 shows a block diagram of PMU

FIG. 407 shows a state machine for PMU

FIG. 408 shows a block diagram of MRU

FIG. 409 shows simplified MAU state machine

FIG. 410 shows power-on reset behaviour

FIG. 411 shows a ring oscillator block diagram

FIG. 412 shows a system clock duty cycle

FIG. 413 shows power-on reset

DETAILED DESCRIPTION OF PREFERRED AND OTHER EMBODIMENTS

It will be appreciated that the detailed description that follows takes the form of a highly detailed design of the invention, including supporting hardware and software. A high level of detailed disclosure is provided to ensure that one skilled in the art will have ample guidance for implementing the invention.

Imperative phrases such as “must”, “requires”, “necessary” and “important” (and similar language) should be read as being indicative of being necessary only for the preferred embodiment actually being described. As such, unless the opposite is clear from the context, imperative wording should not be interpreted as such. Nothing in the detailed description is to be understood as limiting the scope of the invention, which is intended to be defined as widely as is defined in the accompanying claims.

Indications of expected rates, frequencies, costs, and other quantitative values are exemplary and estimated only, and are made in good faith. Nothing in this specification should be read as implying that a particular commercial embodiment is or will be capable of a particular performance level in any measurable area.

It will be appreciated that the principles, methods and hardware described throughout this document can be applied to other fields. Much of the security-related disclosure, for example, can be applied to many other fields that require secure communications between entities, and certainly has application far beyond the field of printers.

System Overview

The preferred of the present invention is implemented in a printer using microelectromechanical systems (MEMS) printheads. The printer can receive data from, for example, a personal computer such as an IBM compatible PC or Apple computer. In other embodiments, the printer can receive data directly from, for example, a digital still or video camera. The particular choice of communication link is not important, and can be based, for example, on USB, Firewire, Bluetooth or any other wireless or hardwired communications protocol.

Print System Overview

3 Introduction

This document describes the SoPEC (Small office home office Print Engine Controller) ASIC (Application Specific Integrated Circuit) suitable for use in, for example, SoHo printer products. The SoPEC ASIC is intended to be a low cost solution for bi-lithic printhead control, replacing the multichip solutions in larger more professional systems with a single chIP. The increased cost competitiveness is achieved by integrating several systems such as a modified PEC1 printing pipeline, CPU control system, peripherals and memory sub-system onto one SoC ASIC, reducing component count and simplifying board design.

This section will give a general introduction to Memjet printing systems, introduce the components that make a bi-lithic printhead system, describe possible system architectures and show how several SoPECs can be used to achieve A3 and A4 duplex printing. The section “SoPEC ASIC” describes the SoC SoPEC ASIC, with subsections describing the CPU, DRAM and Print Engine Pipeline subsystems. Each section gives a detailed description of the blocks used and their operation within the overall print system. The final section describes the bi-lithic printhead construction and associated implications to the system due to its makeup.

4 Nomenclature

4.1 Bi-Lithic Printhead Notation

A bi-lithic based printhead is constructed from 2 printhead ICs of varying sizes. The notation M:N is used to express the size relationship of each IC, where M specifies one printhead IC in inches and N specifies the remaining printhead IC in inches.

The ‘SoPEC/MoPEC Bilithic Printhead Reference’ document [10] contains a description of the bilithic printhead and related terminology.

4.2 Definitions

The following terms are used throughout this specification:

  • Bi-lithic printhead Refers to printhead constructed from 2 printhead ICs
  • CPU Refers to CPU core, caching system and MMU.
  • ISI-Bridge chip A device with a high speed interface (such as USB2.0, Ethernet or IEEE1394) and one or more ISI interfaces. The ISI-Bridge would be the ISIMaster for each of the ISI buses it interfaces to.
  • ISIMaster The ISIMaster is the only device allowed to initiate communication on the Inter Sopec Interface (ISI) bus. The ISIMaster interfaces with the host.
  • ISISlave Multi-SoPEC systems will contain one or more ISISlave SoPECs connected to the ISI bus. ISISlaves can only respond to communication initiated by the ISIMaster.
  • LEON Refers to the LEON CPU core.
  • LineSyncMaster The LineSyncMaster device generates the line synchronisation pulse that all SoPECs in the system must synchronise their line outputs to.
  • Multi-SoPEC Refers to SoPEC based print system with multiple SoPEC devices
  • Netpage Refers to page printed with tags (normally in infrared ink).
  • PEC1 Refers to Print Engine Controller version 1, precursor to SoPEC used to control printheads constructed from multiple angled printhead segments.
  • Printhead IC Single MEMS IC used to construct bi-lithic printhead
  • PrintMaster The PrintMaster device is responsible for coordinating all aspects of the print operation. There may only be one PrintMaster in a system.
  • QA Chip Quality Assurance Chip
  • Storage SoPEC An ISISlave SoPEC used as a DRAM store and which does not print.
  • Tag Refers to pattern which encodes information about its position and orientation which allow it to be optically located and its data contents read.
    4.3 Acronym and Abbreviations

The following acronyms and abbreviations are used in this specification

  • CFU Contone FIFO Unit
  • CPU Central Processing Unit
  • DIU DRAM Interface Unit
  • DNC Dead Nozzle Compensator
  • DRAM Dynamic Random Access Memory
  • DWU DotLine Writer Unit
  • GPIO General Purpose Input Output
  • HCU Halftoner Compositor Unit
  • ICU Interrupt Controller Unit
  • ISI Inter SoPEC Interface
  • LDB Lossless Bi-level Decoder
  • LLU Line Loader Unit
  • LSS Low Speed Serial interface
  • MEMS Micro Electro Mechanical System
  • MMU Memory Management Unit
  • PCU SoPEC Controller Unit
  • PHI PrintHead Interface
  • PSS Power Save Storage Unit
  • RDU Real-time Debug Unit
  • ROM Read Only Memory
  • SCB Serial Communication Block
  • SFU Spot FIFO Unit
  • SMG4 Silverbrook Modified Group 4.
  • SoPEC Small office home office Print Engine
  • Controller
  • SRAM Static Random Access Memory
  • TE Tag Encoder
  • TFU Tag FIFO Unit
  • TIM Timers Unit
  • USB Universal Serial Bus
    4.4 Pseudocode Notation

In general the pseudocode examples use C like statements with some exceptions. Symbol and naming convections used for pseudocode.

//Comment
=Assignment
==, !=, <, >Operator equal, not equal, less than, greater than
+, −, *, /, %Operator addition, subtraction, multiply, divide,
modulus
&, |, {circumflex over ( )}, <<, >>, ˜Bitwise AND, bitwise OR, bitwise exclusive OR, left
shift, right shift, complement
AND, OR, NOTLogical AND, Logical OR, Logical inversion
[XX:YY]Array/vector specifier
{a, b, c}Concatenation operation
++, −−Increment and decrement

4.4.1 Register and Signal Naming Conventions

In general register naming uses the C style conventions with capitalization to denote word delimiters. Signals use RTL style notation where underscore denote word delimiters. There is a direct translation between both convention. For example the CmdSourceFifo register is equivalent to cmd_source_fifo signal.

4.5 State Machine Notation

State machines should be described using the pseudocode notation outlined above. State machine descriptions use the convention of underline to indicate the cause of a transition from one state to another and plain text (no underline) to indicate the effect of the transition i.e. signal transitions which occur when the new state is entered.

A sample state machine is shown in FIG. 1.

5 Printing Considerations

A bi-lithic printhead produces 1600 dpi bi-level dots. On low-diffusion paper, each ejected drop forms a 22.5 μm diameter dot. Dots are easily produced in isolation, allowing dispersed-dot dithering to be exploited to its fullest. Since the bi-lithic printhead is the width of the page and operates with a constant paper velocity, color planes are printed in perfect registration, allowing ideal dot-on-dot printing. Dot-on-dot printing minimizes ‘muddying’ of midtones caused by inter-color bleed. A page layout may contain a mixture of images, graphics and text. Continuous-tone (contone) images and graphics are reproduced using a stochastic dispersed-dot dither. Unlike a clustered-dot (or amplitude-modulated) dither, a dispersed-dot (or frequency-modulated) dither reproduces high spatial frequencies (i.e. image detail) almost to the limits of the dot resolution, while simultaneously reproducing lower spatial frequencies to their full color depth, when spatially integrated by the eye. A stochastic dither matrix is carefully designed to be free of objectionable low-frequency patterns when tiled across the image. As such its size typically exceeds the minimum size required to support a particular number of intensity levels (e.g. 16×16×8 bits for 257 intensity levels).

Human contrast sensitivity peaks at a spatial frequency of about 3 cycles per degree of visual field and then falls off logarithmically, decreasing by a factor of 100 beyond about 40 cycles per degree and becoming immeasurable beyond 60 cycles per degree [25][25]. At a normal viewing distance of 12 inches (about 300 mm), this translates roughly to 200-300 cycles per inch (cpi) on the printed page, or 400-600 samples per inch according to Nyquist's theorem.

In practice, contone resolution above about 300 ppi is of limited utility outside special applications such as medical imaging. Offset printing of magazines, for example, uses contone resolutions in the range 150 to 300 ppi. Higher resolutions contribute slightly to color error through the dither.

Black text and graphics are reproduced directly using bi-level black dots, and are therefore not anti-aliased (i.e. low-pass filtered) before being printed. Text should therefore be supersampled beyond the perceptual limits discussed above, to produce smoother edges when spatially integrated by the eye. Text resolution up to about 1200 dpi continues to contribute to perceived text sharpness (assuming low-diffusion paper, of course).

A Netpage printer, for example, may use a contone resolution of 267 ppi (i.e. 1600 dpi/6), and a black text and graphics resolution of 800 dpi. A high end office or departmental printer may use a contone resolution of 320 ppi (1600 dpi/5) and a black text and graphics resolution of 1600 dpi. Both formats are capable of exceeding the quality of commercial (offset) printing and photographic reproduction.

6 Document Data Flow

6.1 Considerations

Because of the page-width nature of the bi-lithic printhead, each page must be printed at a constant speed to avoid creating visible artifacts. This means that the printing speed can't be varied to match the input data rate. Document rasterization and document printing are therefore decoupled to ensure the printhead has a constant supply of data. A page is never printed until it is fully rasterized. This can be achieved by storing a compressed version of each rasterized page image in memory. This decoupling also allows the RIP(s) to run ahead of the printer when rasterizing simple pages, buying time to rasterize more complex pages.

Because contone color images are reproduced by stochastic dithering, but black text and line graphics are reproduced directly using dots, the compressed page image format contains a separate foreground bi-level black layer and background contone color layer. The black layer is composited over the contone layer after the contone layer is dithered (although the contone layer has an optional black component). A final layer of Netpage tags (in infrared or black ink) is optionally added to the page for printout.

FIG. 2 shows the flow of a document from computer system to printed page.

At 267 ppi for example, a A4 page (8.26 inches×11.7 inches) of contone CMYK data has a size of 26.3 MB. At 320 ppi, an A4 page of contone data has a size of 37.8 MB. Using lossy contone compression algorithms such as JPEG [27], contone images compress with a ratio up to 10:1 without noticeable loss of quality, giving compressed page sizes of 2.63 MB at 267 ppi and 3.78 MB at 320 ppi.

At 800 dpi, a A4 page of bi-level data has a size of 7.4 MB. At 1600 dpi, a Letter page of bi-level data has a size of 29.5 MB. Coherent data such as text compresses very well. Using lossless bi-level compression algorithms such as SMG4 fax as discussed in Section 8.1.2.3.1, ten-point plain text compresses with a ratio of about 50:1. Lossless bi-level compression across an average page is about 20:1 with 10:1 possible for pages which compress poorly. The requirement for SoPEC is to be able to print text at 10:1 compression. Assuming 10:1 compression gives compressed page sizes of 0.74 MB at 800 dpi, and 2.95 MB at 1600 dpi.

Once dithered, a page of CMYK contone image data consists of 116 MB of bi-level data. Using lossless bi-level compression algorithms on this data is pointless precisely because the optimal dither is stochastic—i.e. since it introduces hard-to-compress disorder.

Netpage tag data is optionally supplied with the page image. Rather than storing a compressed bi-level data layer for the Netpage tags, the tag data is stored in its raw form. Each tag is supplied up to 120 bits of raw variable data (combined with up to 56 bits of raw fixed data) and covers up to a 6 mm×6 mm area (at 1600 dpi). The absolute maximum number of tags on a A4 page is 15,540 when the tag is only 2 mm×2 mm (each tag is 126 dots×126 dots, for a total coverage of 148 tags×105 tags). 15,540 tags of 128 bits per tag gives a compressed tag page size of 0.24 MB.

The multi-layer compressed page image format therefore exploits the relative strengths of lossy JPEG contone image compression, lossless bi-level text compression, and tag encoding. The format is compact enough to be storage-efficient, and simple enough to allow straightforward real-time expansion during printing.

Since text and images normally don't overlap, the normal worst-case page image size is image only, while the normal best-case page image size is text only. The addition of worst case Netpage tags adds 0.24 MB to the page image size. The worst-case page image size is text over image plus tags. The average page size assumes a quarter of an average page contains images. Table 1 shows data sizes for compressed Letter page for these different options.

TABLE 1
Data sizes for A4 page (8.26 inches × 11.7 inches)
320 ppi
contone
267 ppi contone1600
800 dpi bi-leveldpi bi-level
Image only (contone), 10:1 compression2.63 MB3.78 MB
Text only (bi-level), 10:1 compression0.74 MB2.95 MB
Netpage tags, 1600 dpi0.24 MB0.24 MB
Worst case (text + image + tags)3.61 MB6.67 MB
Average (text + 25% image + tags)1.64 MB4.25 MB

6.2 Document Data Flow

The Host PC rasterizes and compresses the incoming document on a page by page basis. The page is restructured into bands with one or more bands used to construct a page. The compressed data is then transferred to the SoPEC device via the USB link. A complete band is stored in SoPEC embedded memory. Once the band transfer is complete the SoPEC device reads the compressed data, expands the band, normalizes contone, bi-level and tag data to 1600 dpi and transfers the resultant calculated dots to the bi-lithic printhead.

The document data flow is

    • The RIP software rasterizes each page description and compress the rasterized page image.
    • The infrared layer of the printed page optionally contains encoded Netpage [5] tags at a programmable density.
    • The compressed page image is transferred to the SoPEC device via the USB normally on a band by band basis.
    • The print engine takes the compressed page image and starts the page expansion.
    • The first stage page expansion consists of 3 operations performed in parallel
    • expansion of the JPEG-compressed contone layer
    • expansion of the SMG4 fax compressed bi-level layer
    • encoding and rendering of the bi-level tag data.
    • The second stage dithers the contone layer using a programmable dither matrix, producing up to four bi-level layers at full-resolution.
    • The second stage then composites the bi-level tag data layer, the bi-level SMG4 fax de-compressed layer and up to four bi-level JPEG de-compressed layers into the full-resolution page image.
    • A fixative layer is also generated as required.
    • The last stage formats and prints the bi-level data through the bi-lithic printhead via the printhead interface.

The SoPEC device can print a full resolution page with 6 color planes. Each of the color planes can be generated from compressed data through any channel (either JPEG compressed, bi-level SMG4 fax compressed, tag data generated, or fixative channel created) with a maximum number of 6 data channels from page RIP to bi-lithic printhead color planes.

The mapping of data channels to color planes is programmable, this allows for multiple color planes in the printhead to map to the same data channel to provide for redundancy in the printhead to assist dead nozzle compensation.

Also a data channel could be used to gate data from another data channel. For example in stencil mode, data from the bilevel data channel at 1600 dpi can be used to filter the contone data channel at 320 dpi, giving the effect of 1600 dpi contone image.

6.3 Page Considerations Due to SoPEC

The SoPEC device typically stores a complete page of document data on chIP. The amount of storage available for compressed pages is limited to 2 Mbytes, imposing a fixed maximum on compressed page size. A comparison of the compressed image sizes in Table 2 indicates that SoPEC would not be capable of printing worst case pages unless they are split into bands and printing commences before all the bands for the page have been downloaded. The page sizes in the table are shown for comparison purposes and would be considered reasonable for a professional level printing system. The SoPEC device is aimed at the consumer level and would not be required to print pages of that complexity. Target document types for the SoPEC device are shown Table 2.

TABLE 2
Page content targets for SoPEC
Size
Page Content DescriptionCalculation(MByte)
Best Case picture Image, 267 ppi with 3 colors,8.26 × 11.7 × 267 × 267 × 31.97
A4 size@10:1
Full page text, 800 dpi A4 size8.26 × 11.7 × 800 × 800 @0.74
10:1
Mixed Graphics and Text
Image of 6 inches × 4 inches @ 267 ppi and 36 × 4 × 267 × 267 × 3 @ 5:11.55
colors
Remaining area text ˜73 inches2, 800 dpi800 × 800 × 73 @ 10:1
Best Case Photo, 3 Colors, 6.6 MegaPixel Image6.6 Mpixel @ 10:12.00

If a document with more complex pages is required, the page RIP software in the host PC can determine that there is insufficient memory storage in the SoPEC for that document. In such cases the RIP software can take two courses of action. It can increase the compression ratio until the compressed page size will fit in the SoPEC device, at the expense of document quality, or divide the page into bands and allow SoPEC to begin printing a page band before all bands for that page are downloaded. Once SoPEC starts printing a page it cannot stop, if SoPEC consumes compressed data faster than the bands can be downloaded a buffer underrun error could occur causing the print to fail. A buffer underrun occurs if a line synchronisation pulse is received before a line of data has been transferred to the printhead.

Other options which can be considered if the page does not fit completely into the compressed page store are to slow the printing or to use multiple SoPECs to print parts of the page. A Storage SoPEC (Section 7.2.5) could be added to the system to provide guaranteed bandwidth data delivery. The print system could also be constructed using an ISI-Bridge chip (Section 7.2.6) to provide guaranteed data delivery.

7 Memjet Printer Architecture

The SoPEC device can be used in several printer configurations and architectures.

In the general sense every SoPEC based printer architecture will contain:

    • One or more SoPEC devices.
    • One or more bi-lithic printheads.
    • Two or more LSS busses.
    • Two or more QA chips.
    • USB 1.1 connection to host or ISI connection to Bridge ChIP.
    • ISI bus connection between SoPECs (when multiple SoPECs are used).

Some example printer configurations as outlined in Section 7.2. The various system components are outlined briefly in Section 7.1.

7.1 System Components

7.1.1 SoPEC Print Engine Controller

The SoPEC device contains several system on a chip (SoC) components, as well as the print engine pipeline control application specific logic.

7.1.1.1 Print Engine Pipeline (PEP) Logic

The PEP reads compressed page store data from the embedded memory, optionally decompresses the data and formats it for sending to the printhead. The print engine pipeline functionality includes expanding the page image, dithering the contone layer, compositing the black layer over the contone layer, rendering of Netpage tags, compensation for dead nozzles in the printhead, and sending the resultant image to the bi-lithic printhead.

7.1.1.2 Embedded CPU

SoPEC contains an embedded CPU for general purpose system configuration and management. The CPU performs page and band header processing, motor control and sensor monitoring (via the GPIO) and other system control functions. The CPU can perform buffer management or report buffer status to the host. The CPU can optionally run vendor application specific code for general print control such as paper ready monitoring and LED status update.

7.1.1.3 Embedded Memory Buffer

A 2.5 Mbyte embedded memory buffer is integrated onto the SoPEC device, of which approximately 2 Mbytes are available for compressed page store data. A compressed page is divided into one or more bands, with a number of bands stored in memory. As a band of the page is consumed by the PEP for printing a new band can be downloaded. The new band may be for the current page or the next page.

Using banding it is possible to begin printing a page before the complete compressed page is downloaded, but care must be taken to ensure that data is always available for printing or a buffer underrun may occur.

An Storage SoPEC acting as a memory buffer (Section 7.2.5) or an ISI-Bridge chip with attached DRAM (Section 7.2.6) could be used to provide guaranteed data delivery.

7.1.1.4 Embedded USB 1.1 Device

The embedded USB 1.1 device accepts compressed page data and control commands from the host PC, and facilitates the data transfer to either embedded memory or to another SoPEC device in multi-SoPEC systems.

7.1.2 Bi-lithic Printhead

The printhead is constructed by abutting 2 printhead ICs together. The printhead ICs can vary in size from 2 inches to 8 inches, so to produce an A4 printhead several combinations are possible. For example two printhead ICs of 7 inches and 3 inches could be used to create a A4 printhead (the notation is 7:3). Similarly 6 and 4 combination (6:4), or 5:5 combination. For an A3 printhead it can be constructed from 8:6 or an 7:7 printhead IC combination. For photographic printing smaller printheads can be constructed.

7.1.3 LSS Interface Bus

Each SoPEC device has 2 LSS system buses for communication with QA devices for system authentication and ink usage accounting. The number of QA devices per bus and their position in the system is unrestricted with the exception that PRINTER_QA and INK_QA devices should be on separate LSS busses.

7.1.4 QA Devices

Each SoPEC system can have several QA devices. Normally each printing SoPEC will have an associated PRINTER_QA. Ink cartridges will contain an INK_QA chIP. PRINTER_QA and INK_QA devices should be on separate LSS busses. All QA chips in the system are physically identical with flash memory contents defining PRINTER_QA from INK_QA chIP.

7.1.5 ISI Interface

The Inter-SoPEC Interface (ISI) provides a communication channel between SoPECs in a multi-SoPEC system. The ISIMaster can be SoPEC device or an ISI-Bridge chip depending on the printer configuration. Both compressed data and control commands are transferred via the interface.

7.1.6 ISI-Bridge Chip

A device, other than a SoPEC with a USB connection, which provides print data to a number of slave SoPECs. A bridge chip will typically have a high bandwidth connection, such as USB2.0, Ethernet or IEEE1394, to a host and may have an attached external DRAM for compressed page storage. A bridge chip would have one or more ISI interfaces. The use of multiple ISI buses would allow the construction of independent print systems within the one printer. The ISI-Bridge would be the ISIMaster for each of the ISI buses it interfaces to.

7.2 Possible SoPEC Systems

Several possible SoPEC based system architectures exist. The following sections outline some possible architectures. It is possible to have extra SoPEC devices in the system used for DRAM storage. The QA chip configurations shown are indicative of the flexibility of LSS bus architecture, but not limited to those configurations.

7.2.1 A4 Simplex with 1 SoPEC Device

In FIG. 3, a single SoPEC device can be used to control two printhead ICs. The SoPEC receives compressed data through the USB device from the host. The compressed data is processed and transferred to the printhead.

7.2.2 A4 Duplex with 2 SoPEC Devices

In FIG. 4, two SoPEC devices are used to control two bi-lithic printheads, each with two printhead ICs. Each bi-lithic printhead prints to opposite sides of the same page to achieve duplex printing. The SoPEC connected to the USB is the ISIMaster SoPEC, the remaining SoPEC is an ISISlave. The ISIMaster receives all the compressed page data for both SoPECs and re-distributes the compressed data over the Inter-SoPEC Interface (ISI) bus.

It may not be possible to print an A4 page every 2 seconds in this configuration since the USB 1.1 connection to the host may not have enough bandwidth. An alternative would be for each SoPEC to have its own USB 1.1 connection. This would allow a faster average print speed.

7.2.3 A3 Simplex with 2 SoPEC Devices

In FIG. 5, two SoPEC devices are used to control one A3 bi-lithic printhead. Each SoPEC controls only one printhead IC (the remaining PHI port typically remains idle). This system uses the SoPEC with the USB connection as the ISIMaster. In this dual SoPEC configuration the compressed page store data is split across 2 SoPECs giving a total of 4 Mbyte page store, this allows the system to use compression rates as in an A4 architecture, but with the increased page size of A3. The ISIMaster receives all the compressed page data for all SoPECs and re-distributes the compressed data over the Inter-SoPEC Interface (ISI) bus.

It may not be possible to print an A3 page every 2 seconds in this configuration since the USB 1.1 connection to the host will only have enough bandwidth to supply 2 Mbytes every 2 seconds. Pages which require more than 2 MBytes every 2 seconds will therefore print more slowly. An alternative would be for each SoPEC to have its own USB 1.1 connection. This would allow a faster average print speed.

7.2.4 A3 Duplex with 4 SoPEC Devices

In FIG. 6 a 4 SoPEC system is shown. It contains 2 A3 bi-lithic printheads, one for each side of an A3 page. Each printhead contain 2 printhead ICs, each printhead IC is controlled by an independent SoPEC device, with the remaining PHI port typically unused. Again the SoPEC with USB 1.1 connection is the ISIMaster with the other SoPECs as ISISlaves. In total, the system contains 8 Mbytes of compressed page store (2 Mbytes per SoPEC), so the increased page size does not degrade the system print quality, from that of an A4 simplex printer. The ISIMaster receives all the compressed page data for all SoPECs and re-distributes the compressed data over the Inter-SoPEC Interface (ISI) bus.

It may not be possible to print an A3 page every 2 seconds in this configuration since the USB 1.1 connection to the host will only have enough bandwidth to supply 2 Mbytes every 2 seconds. Pages which require more than 2 MBytes every 2 seconds will therefore print more slowly. An alternative would be for each SoPEC or set of SoPECs on the same side of the page to have their own USB 1.1 connection (as ISISlaves may also have direct USB connections to the host). This would allow a faster average print speed.

7.2.5 SoPEC DRAM storage solution: A4 Simplex with 1 printing SoPEC and 1 memory SoPEC Extra SoPECs can be used for DRAM storage e.g. in FIG. 7 an A4 simplex printer can be built with a single extra SoPEC used for DRAM storage. The DRAM SoPEC can provide guaranteed bandwidth delivery of data to the printing SoPEC. SoPEC configurations can have multiple extra SoPECs used for DRAM storage.

7.2.6 ISI-Bridge Chip Solution: A3 Duplex System with 4 SoPEC Devices

In FIG. 8, an ISI-Bridge chip provides slave-only ISI connections to SoPEC devices. FIG. 8 shows a ISI-Bridge chip with 2 separate ISI ports. The ISI-Bridge chip is the ISIMaster on each of the ISI busses it is connected to. All connected SoPECs are ISISlaves. The ISI-Bridge chip will typically have a high bandwidth connection to a host and may have an attached external DRAM for compressed page storage.

An alternative to having a ISI-Bridge chip would be for each SoPEC or each set of SoPECs on the same side of a page to have their own USB 1.1 connection. This would allow a faster average print speed.

8 Page Format and Printflow

When rendering a page, the RIP produces a page header and a number of bands (a non-blank page requires at least one band) for a page. The page header contains high level rendering parameters, and each band contains compressed page data. The size of the band will depend on the memory available to the RIP, the speed of the RIP, and the amount of memory remaining in SoPEC while printing the previous band(s). FIG. 9 shows the high level data structure of a number of pages with different numbers of bands in the page.

Each compressed band contains a mandatory band header, an optional bi-level plane, optional sets of interleaved contone planes, and an optional tag data plane (for Netpage enabled applications). Since each of these planes is optional1, the band header specifies which planes are included with the band. FIG. 10 gives a high-level breakdown of the contents of a page band.

A single SoPEC has maximum rendering restrictions as follows:

    • 1 bi-level plane
    • 1 contone interleaved plane set containing a maximum of 4 contone planes
    • 1 tag data plane
    • a bi-lithic printhead with a maximum of 2 printhead ICs

The requirement for single-sided A4 single SoPEC printing is

    • average contone JPEG compression ratio of 10:1, with a local minimum compression ratio of 5:1 for a single line of interleaved JPEG blocks.
    • average bi-level compression ratio of 10:1, with a local minimum compression ratio of 1:1 for a single line.

If the page contains rendering parameters that exceed these specifications, then the RIP or the Host PC must split the page into a format that can be handled by a single SoPEC.

In the general case, the SoPEC CPU must analyze the page and band headers and generate an appropriate set of register write commands to configure the units in SoPEC for that page. The various bands are passed to the destination SoPEC(s) to locations in DRAM determined by the host.

The host keeps a memory map for the DRAM, and ensures that as a band is passed to a SoPEC, it is stored in a suitable free area in DRAM. Each SoPEC is connected to the ISI bus or USB bus via its Serial communication Block (SCB). The SoPEC CPU configures the SCB to allow compressed data bands to pass from the USB or ISI through the SCB to SoPEC DRAM. FIG. 11 shows an example data flow for a page destined to be printed by a single SoPEC. Band usage information is generated by the individual SoPECs and passed back to the host.

SoPEC has an addressing mechanism that permits circular band memory allocation, thus facilitating easy memory management. However it is not strictly necessary that all bands be stored together. As long as the appropriate registers in SoPEC are set up for each band, and a given band is contiguous2, the memory can be allocated in any way.
1Although a band must contain at least one plane

2Contiguous allocation also includes wrapping around in SoPEC's band store memory.

8.1 Print Engine Example Page Format

This section describes a possible format of compressed pages expected by the embedded CPU in SoPEC. The format is generated by software in the host PC and interpreted by embedded software in SoPEC. This section indicates the type of information in a page format structure, but implementations need not be limited to this format. The host PC can optionally perform the majority of the header processing.

The compressed format and the print engines are designed to allow real-time page expansion during printing, to ensure that printing is never interrupted in the middle of a page due to data underrun.

The page format described here is for a single black bi-level layer, a contone layer, and a Netpage tag layer. The black bi-level layer is defined to composite over the contone layer.

The black bi-level layer consists of a bitmap containing a 1-bit opacity for each pixel. This black layer matte has a resolution which is an integer or non-integer factor of the printer's dot resolution.

The highest supported resolution is 1600 dpi, i.e. the printer's full dot resolution.

The contone layer, optionally passed in as YCrCb, consists of a 24-bit CMY or 32-bit CMYK color for each pixel. This contone image has a resolution which is an integer or non-integer factor of the printer's dot resolution. The requirement for a single SoPEC is to support 1 side per 2 seconds A4/Letter printing at a resolution of 267 ppi, i.e. one-sixth the printer's dot resolution.

Non-integer scaling can be performed on both the contone and bi-level images. Only integer scaling can be performed on the tag data.

The black bi-level layer and the contone layer are both in compressed form for efficient storage in the printer's internal memory.

8.1.1 Page Structure

A single SoPEC is able to print with full edge bleed for Letter and A3 via different stitch part combinations of the bi-lithic printhead. It imposes no margins and so has a printable page area which corresponds to the size of its paper. The target page size is constrained by the printable page area, less the explicit (target) left and top margins specified in the page description. These relationships are illustrated below.

8.1.2 Compressed Page Format

Apart from being implicitly defined in relation to the printable page area, each page description is complete and self-contained. There is no data stored separately from the page description to which the page description refers.3 The page description consists of a page header which describes the size and resolution of the page, followed by one or more page bands which describe the actual page content.

8.1.2.1 Page Header

Table 3 shows an example format of a page header.
3SoPEC relies on dither matrices and tag structures to have already been set up, but these are not considered to be part of a general page format. It is trivial to extend the page format to allow exact specification of dither matrices and tag structures.

TABLE 3
Page header format
fieldformatdescription
signature16-bit integerPage header format signature.
version16-bit integerPage header format version number.
structure size16-bit integerSize of page header.
band count16-bit integerNumber of bands specified for this page.
target resolution (dpi)16-bit integerResolution of target page. This is always
1600 for the Memjet printer.
target page width16-bit integerWidth of target page, in dots.
target page height32-bit integerHeight of target page, in dots.
target left margin for black and16-bit integerWidth of target left margin, in dots, for black
contoneand contone.
target top margin for black and16-bit integerHeight of target top margin, in dots, for black
contoneand contone.
target right margin for black and16-bit integerWidth of target right margin, in dots, for black
contoneand contone.
target bottom margin for black16-bit integerHeight of target bottom margin, in dots, for
and contoneblack and contone.
target left margin for tags16-bit integerWidth of target left margin, in dots, for tags.
target top margin for tags16-bit integerHeight of target top margin, in dots, for tags.
target right margin for tags16-bit integerWidth of target right margin, in dots, for tags.
target bottom margin for tags16-bit integerHeight of target bottom margin, in dots, for
tags.
generate tags16-bit integerSpecifies whether to generate tags for this
page (0 - no, 1 - yes).
fixed tag data128-bit integer This is only valid if generate tags is set.
tag vertical scale factor16-bit integerScale factor in vertical direction from tag data
resolution to target resolution. Valid range = 1-511.
Integer scaling only
tag horizontal scale factor16-bit integerScale factor in horizontal direction from tag
data resolution to target resolution. Valid
range = 1-511. Integer scaling only.
bi-level layer vertical scale factor16-bit integerScale factor in vertical direction from bi-level
resolution to target resolution (must be 1 or
greater). May be non-integer.
Expressed as a fraction with upper 8-bits the
numerator and the lower 8 bits the
denominator.
bi-level layer horizontal scale factor16-bit integerScale factor in horizontal direction from bi-
level resolution to target resolution (must be 1
or greater). May be non-integer. Expressed
as a fraction with upper 8-bits the numerator
and the lower 8 bits the denominator.
bi-level layer page width16-bit integerWidth of bi-level layer page, in pixels.
bi-level layer page height32-bit integerHeight of bi-level layer page, in pixels.
contone flags16 bit integerDefines the color conversion that is required
for the JPEG data.
Bits 2-0 specify how many contone planes
there are (e.g. 3 for CMY and 4 for CMYK).
Bit 3 specifies whether the first 3 color planes
need to be converted back from YCrCb to
CMY. Only valid if b2-0 = 3 or 4.
0 - no conversion, leave JPEG colors alone
1 - color convert.
Bits 7-4 specifies whether the YCrCb was
generated directly from CMY, or whether it
was converted to RGB first via the step: R = 255-
C, G = 255-M, B = 255-Y. Each of the
color planes can be individually inverted.
Bit 4:
0 - do not invert color plane 0
1 - invert color plane 0
Bit 5:
0 - do not invert color plane 1
1 - invert color plane 1
Bit 6:
0 - do not invert color plane 2
1 - invert color plane 2
Bit 7:
0 - do not invert color plane 3
1 - invert color plane 3
Bit 8 specifies whether the contone data is
JPEG compressed or non-compressed:
0 - JPEG compressed
1 - non-compressed
The remaining bits are reserved (0).
contone vertical scale factor16-bit integerScale factor in vertical direction from contone
channel resolution to target resolution. Valid
range = 1-255. May be non-integer.
Expressed as a fraction with upper 8-bits the
numerator and the lower 8 bits the
denominator.
contone horizontal scale factor16-bit integerScale factor in horizontal direction from
contone channel resolution to target
resolution. Valid range = 1-255. May be non-
integer.
Expressed as a fraction with upper 8-bits the
numerator and the lower 8 bits the
denominator.
contone page width16-bit integerWidth of contone page, in contone pixels.
contone page height32-bit integerHeight of contone page, in contone pixels.
reservedup to 128 bytesReserved and 0 pads out page header to
multiple of 128 bytes.

The page header contains a signature and version which allow the CPU to identify the page header format. If the signature and/or version are missing or incompatible with the CPU, then the CPU can reject the page.

The contone flags define how many contone layers are present, which typically is used for defining whether the contone layer is CMY or CMYK. Additionally, if the color planes are CMY, they can be optionally stored as YCrCb, and further optionally color space converted from CMY directly or via RGB. Finally the contone data is specified as being either JPEG compressed or non-compressed. The page header defines the resolution and size of the target page. The bi-level and contone layers are clipped to the target page if necessary. This happens whenever the bi-level or contone scale factors are not factors of the target page width or height.

The target left, top, right and bottom margins define the positioning of the target page within the printable page area.

The tag parameters specify whether or not Netpage tags should be produced for this page and what orientation the tags should be produced at (landscape or portrait mode). The fixed tag data is also provided.

The contone, bi-level and tag layer parameters define the page size and the scale factors.

8.1.2.2 Band Format

Table 4 shows the format of the page band header.

TABLE 4
Band header format
fieldformatdescription
signature16-bit integerPage band header format signature.
version16-bit integerPage band header format version number.
structure size16-bit integerSize of page band header.
bi-level layer band height16-bit integerHeight of bi-level layer band, in black pixels.
bi-level layer band data size32-bit integerSize of bi-level layer band data, in bytes.
contone band height16-bit integerHeight of contone band, in contone pixels.
contone band data size32-bit integerSize of contone plane band data, in bytes.
tag band height16-bit integerHeight of tag band, in dots.
tag band data size32-bit integerSize of unencoded tag data band, in bytes. Can be
0 which indicates that no tag data is provided.
reservedup to 128 bytesReserved and 0 pads out band header to multiple
of 128 bytes.

The bi-level layer parameters define the height of the black band, and the size of its compressed band data. The variable-size black data follows the page band header.

The contone layer parameters define the height of the contone band, and the size of its compressed page data. The variable-size contone data follows the black data.

The tag band data is the set of variable tag data half-lines as required by the tag encoder. The format of the tag data is found in Section 26.5.2. The tag band data follows the contone data.

Table 5 shows the format of the variable-size compressed band data which follows the page band header.

TABLE 5
Page band data format
fieldformatDescription
black dataModified G4Compressed bi-level layer.
facsimile bitstream4
contone dataJPEG bytestreamCompressed contone datalayer.
tag data mapTag data arrayTag data format. See Section 26.5.2.

4See section 8.1.2.3 on page 36 for note regarding the use of this standard

The start of each variable-size segment of band data should be aligned to a 256-bit DRAM word boundary.

The following sections describe the format of the compressed bi-level layers and the compressed contone layer. section 26.5.1 on page 410 describes the format of the tag data structures.

8.1.2.3 Bi-Level Data Compression

The (typically 1600 dpi) black bi-level layer is losslessly compressed using Silverbrook Modified Group 4 (SMG4) compression which is a version of Group 4 Facsimile compression [22] without Huffman and with simplified run length encodings. Typically compression ratIOs exceed 10:1. The encoding are listed in Table 6 and Table 7.

EncodingDescription
same as1000Pass Command: a0 custom character b2, skip next two
Group 4edges
Facsimile
1Vertical(0): a0 custom character b1, color = !color
110Vertical(1): a0 custom character b1 + 1, color = !color
010Vertical(−1): a0 custom character b1 − 1, color = !color
110000Vertical(2): a0 custom character b1 + 2, color = !color
010000Vertical(−2): a0 custom character b1 − 2, color = !color
Unique to100000Vertical(3): a0 custom character b1 + 3, color = !color
this
implemen-
tation
000000Vertical(−3): a0 custom character b1 − 3, color = !color
<RL><RL>100Horizontal: a0 custom character a0 + <RL> + <RL>

SMG4 has a pass through mode to cope with local negative compression. Pass through mode is activated by a special run-length code. Pass through mode continues to either end of line or for a pre-programmed number of bits, whichever is shorter. The special run-length code is always executed as a run-length code, followed by pass through. The pass through escape code is a medium length run-length with a run of less than or equal to 31.

TABLE 7
Run length (RL) encodings
EncodingDescription
Unique to thisRRRRR1Short Black Runlength (5 bits)
implementation
RRRRR1Short White Runlength (5 bits)
RRRRRRRRRR10Medium Black Runlength (10 bits)
RRRRRRRR10Medium White Runlength (8 bits)
RRRRRRRRRR10Medium Black Runlength with RRRRRRRRRR <= 31,
Enter pass through
RRRRRRRR10Medium White Runlength with RRRRRRRR <= 31,
Enter pass through
RRRRRRRRRRRRRRR00Long Black Runlength (15 bits)
RRRRRRRRRRRRRRR00Long White Runlength (15 bits)

Since the compression is a bitstream, the encodings are read right (least significant bit) to left (most significant bit). The run lengths given as RRRR in Table are read in the same way (least significant bit at the right to most significant bit at the left).

Each band of bi-level data is optionally self contained. The first line of each band therefore is based on a ‘previous’ blank line or the last line of the previous band.

8.1.2.3.1 Group 3 and 4 Facsimile Compression

The Group 3 Facsimile compression algorithm [22] losslessly compresses bi-level data for transmission over slow and noisy and noisy telephone lines. The bi-level data represents scanned black text and graphics on a while background, and the algorithm is tuned for this class of images (it is explicitly not tuned, for example, for halftoned bi-level images). The 1D Group 3 algorithm runlength-encodes each scanline and then Huffman-encodes the resulting runlengths. Runlengths in the range 0 to 63 are coded with terminating codes. Runlengths in the range 64 to 2623 are coded with make-up codes, each representing a multiple of 64, followed by a terminating code. Runlengths exceeding 2623 are coded with multiple make-up codes followed by a terminating code. The Huffman tables are fixed, but are separately tuned for black and white runs (except for make-up codes above 1728, which are common). When possible, the 2D Group 3 algorithm encodes a scanline as a set of short edge deltas (0, +1, +2, +3) with reference to the previous scanline. The delta symbols are entropy-encoded (so that the zero delta symbol is only one bit long etc.) Edges within a 2D-encoded line which can't be delta-encoded are runlength-encoded, and are identified by a prefix. 1D- and 2D-encoded lines are marked differently. 1D-encoded lines are generated at regular intervals, whether actually required or not, to ensure that the decoder can recover from line noise with minimal image degradation. 2D Group 3 achieves compression ratIOs of up to 6:1 [32]. The Group 4 Facsimile algorithm [22] losslessly compresses bi-level data for transmission over error-free communications lines (i.e. the lines are truly error-free, or error-correction is done at a lower protocol level). The Group 4 algorithm is based on the 2D Group 3 algorithm, with the essential modification that since transmission is assumed to be error-free, 1D-encoded lines are no longer generated at regular intervals as an aid to error-recovery. Group 4 achieves compression ratIOs ranging from 20:1 to 60:1 for the CCITT set of test images [32].

The design goals and performance of the Group 4 compression algorithm qualify it as a compression algorithm for the bi-level layers. However, its Huffman tables are tuned to a lower scanning resolution (100-400 dpi), and it encodes runlengths exceeding 2623 awkwardly.

8.1.2.4 Contone Data Compression

The contone layer (CMYK) is either a non-compressed bytestream or is compressed to an interleaved JPEG bytestream. The JPEG bytestream is complete and self-contained. It contains all data required for decompression, including quantization and Huffman tables.

The contone data is optionally converted to YCrCb before being compressed (there is no specific advantage in color-space converting if not compressing). Additionally, the CMY contone pixels are optionally converted (on an individual basis) to RGB before color conversion using R=255-C, G=255-M, B=255-Y. Optional bitwise inversion of the K plane may also be performed. Note that this CMY to RGB conversion is not intended to be accurate for display purposes, but rather for the purposes of later converting to YCrCb. The inverse transform will be applied before printing.

8.1.2.4.1 JPEG Compression

The JPEG compression algorithm [27] lossily compresses a contone image at a specified quality level. It introduces imperceptible image degradation at compression ratIOs below 5:1, and negligible image degradation at compression ratIOs below 10:1 [33].

JPEG typically first transforms the image into a color space which separates luminance and chrominance into separate color channels. This allows the chrominance channels to be subsampled without appreciable loss because of the human visual system's relatively greater sensitivity to luminance than chrominance. After this first step, each color channel is compressed separately.

The image is divided into 8×8 pixel blocks. Each block is then transformed into the frequency domain via a discrete cosine transform (DCT). This transformation has the effect of concentrating image energy in relatively lower-frequency coefficients, which allows higher-frequency coefficients to be more crudely quantized. This quantization is the principal source of compression in JPEG. Further compression is achieved by ordering coefficients by frequency to maximize the likelihood of adjacent zero coefficients, and then runlength-encoding runs of zeroes. Finally, the runlengths and non-zero frequency coefficients are entropy coded. Decompression is the inverse process of compression.

8.1.2.4.2 Non-Compressed Format

If the contone data is non-compressed, it must be in a block-based format bytestream with the same pixel order as would be produced by a JPEG decoder. The bytestream therefore consists of a series of 8×8 block of the original image, starting with the top left 8×8 block, and working horizontally across the page (as it will be printed) until the top rightmost 8×8 block, then the next row of 8×8 blocks (left to right) and so on until the lower row of 8×8 blocks (left to right). Each 8×8 block consists of 64 8-bit pixels for color plane 0 (representing 8 rows of 8 pixels in the order top left to bottom right) followed by 64 8-bit pixels for color plane 1 and so on for up to a maximum of 4 color planes.

If the original image is not a multiple of 8 pixels in X or Y, padding must be present (the extra pixel data will be ignored by the setting of margins).

8.1.2.4.3 Compressed Format

If the contone data is compressed the first memory band contains JPEG headers (including tables) plus MCUs (minimum coded units). The ratio of space between the various color planes in the JPEG stream is 1:1:1:1. No subsampling is permitted. Banding can be completely arbitrary i.e there can be multiple JPEG images per band or 1 JPEG image divided over multiple bands. The break between bands is only memory alignment based.

8.1.2.4.4 Conversion of RGB to YCrCb (in RIP)

YCrCb is defined as per CCIR 601-1 [24] except that Y, Cr and Cb are normalized to occupy all 256 levels of an 8-bit binary encoding and take account of the actual hardware implementation of the inverse transform within SoPEC.

The exact color conversion computation is as follows:

    • Y*=(9805/32768)R+(19235/32768)G+(3728/32768)B
    • Cr*=(16375/32768)R−(13716/32768)G−(2659/32768)B+128
    • Cb*=−(5529/32768)R−(10846/32768)G+(16375/32768)B+128

Y, Cr and Cb are obtained by rounding to the nearest integer. There is no need for saturation since ranges of Y*, Cr* and Cb* after rounding are [0-255], [1-255] and [1-255] respectively. Note that full accuracy is possible with 24 bits. See [14] for more information.

SoPEC ASIC

9 Overview

The Small Office Home Office Print Engine Controller (SoPEC) is a page rendering engine ASIC that takes compressed page images as input, and produces decompressed page images at up to 6 channels of bi-level dot data as output. The bi-level dot data is generated for the Memjet bi-lithic printhead. The dot generation process takes account of printhead construction, dead nozzles, and allows for fixative generation.

A single SoPEC can control 2 bi-lithic printheads and up to 6 color channels at 10,000 lines/sec5, equating to 30 pages per minute. A single SoPEC can perform full-bleed printing of A3, A4 and Letter pages. The 6 channels of colored ink are the expected maximum in a consumer SOHO, or office Bi-lithic printing environment:
510,000 lines per second equates to 30 A4/Letter pages per minute at 1600 dpi

    • CMY, for regular color printing.

K, for black text, line graphics and gray-scale printing.

IR (infrared), for Netpage-enabled [5] applications.

F (fixative), to enable printing at high speed. Because the bi-lithic printer is capable of printing so fast, a fixative may be required to enable the ink to dry before the page touches the page already printed. Otherwise the pages may bleed on each other. In low speed printing environments the fixative may not be required.

SoPEC is color space agnostic. Although it can accept contone data as CMYX or RGBX, where X is an optional 4th channel, it also can accept contone data in any print color space. Additionally, SoPEC provides a mechanism for arbitrary mapping of input channels to output channels, including combining dots for ink optimization, generation of channels based on any number of other channels etc. However, inputs are typically CMYK for contone input, K for the bi-level input, and the optional Netpage tag dots are typically rendered to an infra-red layer. A fixative channel is typically generated for fast printing applications.

SoPEC is resolution agnostic. It merely provides a mapping between input resolutions and output resolutions by means of scale factors. The expected output resolution is 1600 dpi, but SoPEC actually has no knowledge of the physical resolution of the Bi-lithic printhead.

SoPEC is page-length agnostic. Successive pages are typically split into bands and downloaded into the page store as each band of information is consumed and becomes free.

SoPEC provides an interface for synchronization with other SoPECs. This allows simple multi-SoPEC solutions for simultaneous A3/A4/Letter duplex printing. However, SoPEC is also capable of printing only a portion of a page image. Combining synchronization functionality with partial page rendering allows multiple SoPECs to be readily combined for alternative printing requirements including simultaneous duplex printing and wide format printing.

Table 8 lists some of the features and corresponding benefits of SoPEC.

TABLE 8
Features and Benefits of SoPEC
FeatureBenefits
Optimised print architecture in30 ppm full page photographic quality color printing from a
hardwaredesktop PC
0.13micron CMOSHigh speed
(>3 million transistors)Low cost
High functionality
900 Million dots per secondExtremely fast page generation
10,000 lines per second at 1600 dpi0.5 A4/Letter pages per SoPEC chip per second
1 chip drives up to 133,920Low cost page-width printers
nozzles
1 chip drives up to 6 color planes99% of SoHo printers can use 1 SoPEC device
Integrated DRAMNo external memory required, leading to low cost systems
Power saving sleep modeSoPEC can enter a power saving sleep mode to reduce
power dissipation between print jobs
JPEG expansionLow bandwidth from PC
Low memory requirements in printer
Lossless bitplane expansionHigh resolution text and line art with low bandwidth from PC
(e.g. over USB)
Netpage tag expansionGenerates interactive paper
Stochastic dispersed dot ditherOptically smooth image quality
No moire effects
Hardware compositor for 6 imagePages composited in real-time
planes
Dead nozzle compensationExtends printhead life and yield
Reduces printhead cost
Color space agnosticCompatible with all inksets and image sources including
RGB, CMYK, spot, CIE L*a*b*, hexachrome, YCrCbK,
sRGB and other
Color space conversionHigher quality/lower bandwidth
Computer interfaceUSB1.1 interface to host and ISI interface to ISI-Bridge chip
thereby allowing connection to IEEE 1394, Bluetooth etc.
Cascadable in resolutionPrinters of any resolution
Cascadable in color depthSpecial color sets e.g. hexachrome can be used
Cascadable in image sizePrinters of any width up to 16 inches
Cascadable in pagesPrinters can print both sides simultaneously
Cascadable in speedHigher speeds are possible by having each SoPEC print one
vertical strip of the page.
Fixative channel data generationExtremely fast ink drying without wastage
Built-in securityRevenue models are protected
Undercolor removal on dot-by-dotReduced ink usage
basis
Does not require fonts for highNo font substitution or missing fonts
speed operation
Flexible printhead configurationMany configurations of printheads are supported by one chip
type
Drives Bi-lithic printheads directlyNo print driver chips required, results in lower cost
Determines dot accurate ink usageRemoves need for physical ink monitoring system in ink
cartridges

9.1 Printing Rates

The required printing rate for SoPEC is 30 sheets per minute with an inter-sheet spacing of 4 cm. To achieve a 30 sheets per minute print rate, this requires:

    • 300 mm×63 (dot/mm)/2 sec=105.8 μseconds per line, with no inter-sheet gap.
    • 340 mm×63 (dot/mm)/2 sec=93.3 μseconds per line, with a 4 cm inter-sheet gap.

A printline for an A4 page consists of 13824 nozzles across the page [2]. At a system clock rate of 160 MHz 13824 dots of data can be generated in 86.4 μseconds. Therefore data can be generated fast enough to meet the printing speed requirement. It is necessary to deliver this print data to the print-heads.

Printheads can be made up of 5:5, 6:4, 7:3 and 8:2 inch printhead combinations [2]. Print data is transferred to both print heads in a pair simultaneously. This means the longest time to print a line is determined by the time to transfer print data to the longest print segment. There are 9744 nozzles across a 7 inch printhead. The print data is transferred to the printhead at a rate of 106 MHz (2/3 of the system clock rate) per color plane. This means that it will take 91.9 μs to transfer a single line for a 7:3 printhead configuration. So we can meet the requirement of 30 sheets per minute printing with a 4 cm gap with a 7:3 printhead combination. There are 11160 across an 8 inch printhead. To transfer the data to the printhead at 106 MHz will take 105.3 μs. So an 8:2 printhead combination printing with an inter-sheet gap will print slower than 30 sheets per minute.

9.2 SoPEC Basic Architecture

From the highest point of view the SoPEC device consists of 3 distinct subsystems

    • CPU Subsystem
    • DRAM Subsystem
    • Print Engine Pipeline (PEP) Subsystem

See FIG. 13 for a block level diagram of SoPEC.

9.2.1 CPU Subsystem

The CPU subsystem controls and configures all aspects of the other subsystems. It provides general support for interfacing and synchronising the external printer with the internal print engine. It also controls the low speed communication to the QA chips. The CPU subsystem contains various peripherals to aid the CPU, such as GPIO (includes motor control), interrupt controller, LSS Master and general timers. The Serial Communications Block (SCB) on the CPU subsystem provides a full speed USB1.1 interface to the host as well as an Inter SoPEC Interface (ISI) to other SoPEC devices.

9.2.2 DRAM Subsystem

The DRAM subsystem accepts requests from the CPU, Serial Communications Block (SCB) and blocks within the PEP subsystem. The DRAM subsystem (in particular the DIU) arbitrates the various requests and determines which request should win access to the DRAM. The DIU arbitrates based on configured parameters, to allow sufficient access to DRAM for all requesters. The DIU also hides the implementation specifics of the DRAM such as page size, number of banks, refresh rates etc.

9.2.3 Print Engine Pipeline (PEP) Subsystem

The Print Engine Pipeline (PEP) subsystem accepts compressed pages from DRAM and renders them to bi-level dots for a given print line destined for a printhead interface that communicates directly with up to 2 segments of a bi-lithic printhead.

The first stage of the page expansion pipeline is the CDU, LBD and TE. The CDU expands the JPEG-compressed contone (typically CMYK) layer, the LBD expands the compressed bi-level layer (typically K), and the TE encodes Netpage tags for later rendering (typically in IR or K ink). The output from the first stage is a set of buffers: the CFU, SFU, and TFU. The CFU and SFU buffers are implemented in DRAM.

The second stage is the HCU, which dithers the contone layer, and composites position tags and the bi-level spot0 layer over the resulting bi-level dithered layer. A number of options exist for the way in which compositing occurs. Up to 6 channels of bi-level data are produced from this stage. Note that not all 6 channels may be present on the printhead. For example, the printhead may be CMY only, with K pushed into the CMY channels and IR ignored. Alternatively, the position tags may be printed in K if IR ink is not available (or for testing purposes).

The third stage (DNC) compensates for dead nozzles in the printhead by color redundancy and error diffusing dead nozzle data into surrounding dots.

The resultant bi-level 6 channel dot-data (typically CMYK-IRF) is buffered and written out to a set of line buffers stored in DRAM via the DWU.

Finally, the dot-data is loaded back from DRAM, and passed to the printhead interface via a dot FIFO. The dot FIFO accepts data from the LLU at the system clock rate (pclk), while the PHI removes data from the FIFO and sends it to the printhead at a rate of ⅔ times the system clock rate (see Section 9.1).

9.3 SoPEC Block Description

Looking at FIG. 13, the various units are described here in summary form:

TABLE 9
Units within SoPEC
Unit
SubsystemAcronymUnit NameDescription
DRAMDIUDRAM interface unitProvides the interface for DRAM read and write
access for the various SoPEC units, CPU and
the SCB block. The DIU provides arbitration
between competing units controls DRAM
access.
DRAMEmbedded DRAM20 Mbits of embedded DRAM,
CPUCPUCentral ProcessingCPU for system configuration and control
Unit
MMUMemory ManagementLimits access to certain memory address areas
Unitin CPU user mode
RDUReal-time Debug UnitFacilitates the observation of the contents of
most of the CPU addressable registers in
SoPEC in addition to some pseudo-registers in
realtime.
TIMGeneral TimerContains watchdog and general system timers
LSSLow Speed SerialLow level controller for interfacing with the QA
Interfaceschips
GPIOGeneral Purpose IOsGeneral IO controller, with built-in Motor control
unit, LED pulse units and de-glitch circuitry
ROMBoot ROM16 KBytes of System Boot ROM code
ICUInterrupt ControllerGeneral Purpose interrupt controller with
Unitconfigurable priority, and masking.
CPRClock, Power andCentral Unit for controlling and generating the
Reset blocksystem clocks and resets and powerdown
mechanisms
PSSPower Save StorageStorage retained while system is powered down
USBUniversal Serial BusUSB device controller for interfacing with the
Devicehost USB.
ISIInter-SoPEC InterfaceISI controller for data and control
communication with other SoPEC's in a multi-
SoPEC system
SCBSerial CommunicationContains both the USB and ISI blocks.
Block
Print EnginePCUPEP controllerProvides external CPU with the means to read
Pipelineand write PEP Unit registers, and read and
(PEP)write DRAM in single 32-bit chunks.
CDUContone decoder unitExpands JPEG compressed contone layer and
writes decompressed contone to DRAM
CFUContone FIFO UnitProvides line buffering between CDU and HCU
LBDLossless Bi-levelExpands compressed bi-level layer.
Decoder
SFUSpot FIFO UnitProvides line buffering between LBD and HCU
TETag encoderEncodes tag data into line of tag dots.
TFUTag FIFO UnitProvides tag data storage between TE and
HCU
HCUHalftoner compositorDithers contone layer and composites the bi-
unitlevel spot 0 and position tag dots.
DNCDead NozzleCompensates for dead nozzles by color
Compensatorredundancy and error diffusing dead nozzle
data into surrounding dots.
DWUDotline Writer UnitWrites out the 6 channels of dot data for a
given printline to the line store DRAM
LLULine Loader UnitReads the expanded page image from line
store, formatting the data appropriately for the
bi-lithic printhead.
PHIPrintHead InterfaceIs responsible for sending dot data to the bi-
lithic printheads and for providing line
synchronization between multiple SoPECs.
Also provides test interface to printhead such
as temperature monitoring and Dead Nozzle
Identification.

9.4 Addressing Scheme in SoPEC

SoPEC must address

    • 20 Mbit DRAM.
    • PCU addressed registers in PEP.
    • CPU-subsystem addressed registers.

SoPEC has a unified address space with the CPU capable of addressing all CPU-subsystem and PCU-bus accessible registers (in PEP) and all locations in DRAM. The CPU generates byte-aligned addresses for the whole of SoPEC.

22 bits are sufficient to byte address the whole SoPEC address space.

9.4.1 DRAM Addressing Scheme

The embedded DRAM is composed of 256-bit words. However the CPU-subsystem may need to write individual bytes of DRAM. Therefore it was decided to make the DIU byte addressable. 22 bits are required to byte address 20 Mbits of DRAM. Most blocks read or write 256-bit words of DRAM. Therefore only the top 17 bits i.e. bits 21 to 5 are required to address 256-bit word aligned locations.

The exceptions are

    • CDU which can write 64-bits so only the top 19 address bits i.e. bits 21-3 are required.
    • The CPU-subsystem always generates a 22-bit byte-aligned DIU address but it will send flags to the DIU indicating whether it is an 8, 16 or 32-bit write.

All DIU accesses must be within the same 256-bit aligned DRAM word.

9.4.2 PEP Unit DRAM Addressing

PEP Unit configuration registers which specify DRAM locations should specify 256-bit aligned DRAM addresses i.e. using address bits 21:5. Legacy blocks from PEC1 e.g. the LBD and TE may need to specify 64-bit aligned DRAM addresses if these reused blocks DRAM addressing is difficult to modify. These 64-bit aligned addresses require address bits 21:3. However, these 64-bit aligned addresses should be programmed to start at a 256-bit DRAM word boundary.

Unlike PEC1, there are no constraints in SoPEC on data organization in DRAM except that all data structures must start on a 256-bit DRAM boundary. If data stored is not a multiple of 256-bits then the last word should be padded.

9.4.3 CPU Subsystem Bus Addressed Registers

The CPU subsystem bus supports 32-bit word aligned read and write accesses with variable access timings. See section 11.4 for more details of the access protocol used on this bus. The CPU subsystem bus does not currently support byte reads and writes but this can be added at a later date if required by imported IP.

9.4.4 PCU Addressed Registers in PEP

The PCU only supports 32-bit register reads and writes for the PEP blocks. As the PEP blocks only occupy a subsection of the overall address map and the PCU is explicitly selected by the MMU when a PEP block is being accessed the PCU does not need to perform a decode of the higher-order address bits. See Table 11 for the PEP subsystem address map.

9.5 SoPEC Memory Map

9.5.1 Main Memory Map

The system wide memory map is shown in FIG. 14 below. The memory map is discussed in detail in Section 11 11 Central Processing Unit (CPU).

9.5.2 CPU-Bus Peripherals Address Map

The address mapping for the peripherals attached to the CPU-bus is shown in Table 10 below. The MMU performs the decode of cpu_adr[21:12] to generate the relevant cpu_block_select signal for each block. The addressed blocks decode however many of the lower order bits of cpu_adr[11:2] are required to address all the registers within the block.

TABLE 10
CPU-bus peripherals address map
Block_baseAddress
ROM_base0x0000_0000
MMU_base0x0001_0000
TIM_base0x0001_1000
LSS_base0x0001_2000
GPIO_base0x0001_3000
SCB_base0x0001_4000
ICU_base0x0001_5000
CPR_base0x0001_6000
DIU_base0x0001_7000
PSS_base0x0001_8000
Reserved0x0001_9000 to 0x0001_FFFF
PCU_base0x0002_0000 to 0x0002_BFFF

9.5.3 PCU Mapped Registers (PEP Blocks) Address Map

The PEP blocks are addressed via the PCU. From FIG. 14, the PCU mapped registers are in the range 0x00020000 to 0x0002_BFFF. From Table 11 it can be seen that there are 12 sub-blocks within the PCU address space. Therefore, only four bits are necessary to address each of the sub-blocks within the PEP part of SoPEC. A further 12 bits may be used to address any configurable register within a PEP block. This gives scope for 1024 configurable registers per sub-block (the PCU mapped registers are all 32-bit addressed registers so the upper 10 bits are required to individually address them). This address will come either from the CPU or from a command stored in DRAM. The bus is assembled as follows:

    • address[15:12]=sub-block address,
      • address[n:2]=register address within sub-block, only the number of bits required to decode the registers within each sub-block are used,
      • address[1:0]=byte address, unused as PCU mapped registers are all 32-bit addressed registers.

So for the case of the HCU, its addresses range from 0x7000 to 0x7FFF within the PEP subsystem or from 0x00027000 to 0x00027FFF in the overall system.

TABLE 11
PEP blocks address map
Block_baseAddress
PCU_base0x0002_0000
CDU_base0x0002_1000
CFU_base0x0002_2000
LBD_base0x0002_3000
SFU_base0x0002_4000
TE_base0x0002_5000
TFU_base0x0002_6000
HCU_base0x0002_7000
DNC_base0x0002_8000
DWU_base0x0002_9000
LLU_base0x0002_A000
PHI_base0x0002_B000 to 0x0002_BFFF

9.6 Buffer Management in SoPEC

As outlined in Section 9.1, SoPEC has a requirement to print 1 side every 2 seconds i.e. 30 sides per minute.

9.6.1 Page Buffering

Approximately 2 Mbytes of DRAM are reserved for compressed page buffering in SoPEC. If a page is compressed to fit within 2 Mbyte then a complete page can be transferred to DRAM before printing. However, the time to transfer 2 Mbyte using USB 1.1 is approximately 2 seconds. The worst case cycle time to print a page then approaches 4 seconds. This reduces the worst-case print speed to 15 pages per minute.

9.6.2 Band Buffering

The SoPEC page-expansion blocks support the notion of page banding. The page can be divided into bands and another band can be sent down to SoPEC while we are printing the current band. Therefore we can start printing once at least one band has been downloaded.

The band size granularity should be carefully chosen to allow efficient use of the USB bandwidth and DRAM buffer space. It should be small enough to allow seamless 30 sides per minute printing but not so small as to introduce excessive CPU overhead in orchestrating the data transfer and parsing the band headers. Band-finish interrupts have been provided to notify the CPU of free buffer space. It is likely that the host PC will supervise the band transfer and buffer management instead of the SoPEC CPU.

If SoPEC starts printing before the complete page has been transferred to memory there is a risk of a buffer underrun occurring if subsequent bands are not transferred to SoPEC in time e.g. due to insufficient USB bandwidth caused by another USB peripheral consuming USB bandwidth. A buffer underrun occurs if a line synchronisation pulse is received before a line of data has been transferred to the printhead and causes the print job to fail at that line. If there is no risk of buffer underrun then printing can safely start once at least one band has been downloaded.

If there is a risk of a buffer underrun occurring due to an interruption of compressed page data transfer, then the safest approach is to only start printing once we have loaded up the data for a complete page. This means that a worst case latency in the region of 2 seconds (with USB1.1) will be incurred before printing the first page. Subsequent pages will take 2 seconds to print giving us the required sustained printing rate of 30 sides per minute.

A Storage SoPEC (Section 7.2.5) could be added to the system to provide guaranteed bandwidth data delivery. The print system could also be constructed using an ISI-Bridge chip (Section 7.2.6) to provide guaranteed data delivery.

The most efficient page banding strategy is likely to be determined on a per page/print job basis and so SoPEC will support the use of bands of any size.

10 SoPEC Use Cases

10.1 Introduction

This chapter is intended to give an overview of a representative set of scenarIOs or use cases which SoPEC can perform. SoPEC is by no means restricted to the particular use cases described and not every SoPEC system is considered here.

In this chapter we discuss SoPEC use cases under four headings:

  • 1) Normal operation use cases.
  • 2) Security use cases.
  • 3) Miscellaneous use cases.
  • 4) Failure mode use cases.

Use cases for both single and multi-SoPEC systems are outlined.

Some tasks may be composed of a number of sub-tasks.

The realtime requirements for SoPEC software tasks are discussed in “11 Central Processing Unit (CPU)” under Section 11.3 Realtime requirements.

10.2 Normal Operation in a single SoPEC System with USB Host Connection

SoPEC operation is broken up into a number of sections which are outlined below. Buffer management in a SoPEC system is normally performed by the host.

10.2.1 Powerup

Powerup describes SoPEC initialisation following an external reset or the watchdog timer system reset.

A typical powerup sequence is:

  • 1) Execute reset sequence for complete SoPEC.
  • 2) CPU boot from ROM.
  • 3) Basic configuration of CPU peripherals, SCB and DIU. DRAM initialisation. USB Wakeup.
  • 4) Download and authentication of program (see Section 10.5.2).
  • 5) Execution of program from DRAM.
  • 6) Retrieve operating parameters from PRINTER_QA and authenticate operating parameters.
  • 7) Download and authenticate any further datasets.
    10.2.2 USB Wakeup

The CPU can put different sections of SoPEC into sleep mode by writing to registers in the CPR block (chapter 16). Normally the CPU sub-system and the DRAM will be put in sleep mode but the SCB and power-safe storage (PSS) will still be enabled.

Wakeup describes SoPEC recovery from sleep mode with the SCB and power-safe storage (PSS) still enabled. In a single SoPEC system, wakeup can be initiated following a USB reset from the SCB.

A typical USB wakeup sequence is:

  • 1) Execute reset sequence for sections of SoPEC in sleep mode.
  • 2) CPU boot from ROM, if CPU-subsystem was in sleep mode.
  • 3) Basic configuration of CPU peripherals and DIU, and DRAM initialisation, if required.
  • 4) Download and authentication of program using results in Power-Safe Storage (PSS) (see Section 10.5.2).
  • 5) Execution of program from DRAM.
  • 6) Retrieve operating parameters from PRINTER_QA and authenticate operating parameters.
  • 7) Download and authenticate using results in PSS of any further datasets (programs).
    10.2.3 Print Initialization

This sequence is typically performed at the start of a print job following powerup or wakeup:

  • 1) Check amount of ink remaining via QA chips.
  • 2) Download static data e.g. dither matrices, dead nozzle tables from host to DRAM.
  • 3) Check printhead temperature, if required, and configure printhead with firing pulse profile etc. accordingly.
  • 4) Initiate printhead pre-heat sequence, if required.
    10.2.4 First Page Download

Buffer management in a SoPEC system is normally performed by the host.

First page, first band download and processing:

  • 1) The host communicates to the SoPEC CPU over the USB to check that DRAM space remaining is sufficient to download the first band.
  • 2) The host downloads the first band (with the page header) to DRAM.
  • 3) When the complete page header has been downloaded the SoPEC CPU processes the page header, calculates PEP register commands and writes directly to PEP registers or to DRAM.
  • 4) If PEP register commands have been written to DRAM, execute PEP commands from DRAM via PCU.

Remaining bands download and processing:

  • 1) Check DRAM space remaining is sufficient to download the next band.
  • 2) Download the next band with the band header to DRAM.
  • 3) When the complete band header has been downloaded, process the band header according to whichever band-related register updating mechanism is being used.
    10.2.5 Start Printing
  • 1) Wait until at least one band of the first page has been downloaded. One approach is to only start printing once we have loaded up the data for a complete page. If we start printing before the complete page has been transferred to memory we run the risk of a buffer underrun occurring because compressed page data was not transferred to SoPEC in time e.g. due to insufficient USB bandwidth caused by another USB peripheral consuming USB bandwidth.

2) Start all the PEP Units by writing to their Go registers, via PCU commands executed from DRAM or direct CPU writes. A rapid startup order for the PEP units is outlined in Table 12.

TABLE 12
Typical PEP Unit startup order for printing a page.
Step#Unit
1DNC
2DWU
3HCU
4PHI
5LLU
6CFU, SFU, TFU
7CDU
8TE, LBD
  • 3) Print ready interrupt occurs (from PHI).
  • 4) Start motor control, if first page, otherwise feed the next page. This step could occur before the print ready interrupt.
  • 5) Drive LEDs, monitor paper status.
  • 6) Wait for page alignment via page sensor(s) GPIO interrupt.
  • 7) CPU instructs PHI to start producing line syncs and hence commence printing, or wait for an external device to produce line syncs.
  • 8) Continue to download bands and process page and band headers for next page.
    10.2.6 Next Page(s) Download

As for first page download, performed during printing of current page.

10.2.7 Between Bands

When the finished band flags are asserted band related registers in the CDU, LBD, TE need to be re-programmed before the subsequent band can be printed. This can be via PCU commands from DRAM. Typically only 3-5 commands per decompression unit need to be executed. These registers can also be reprogrammed directly by the CPU or most likely by updating from shadow registers. The finished band flag interrupts the CPU to tell the CPU that the area of memory associated with the band is now free.

10.2.8 During Page Print

Typically during page printing ink usage is communicated to the QA chips.

  • 1) Calculate ink printed (from PHI).
  • 2) Decrement ink remaining (via QA chips).
  • 3) Check amount of ink remaining (via QA chips). This operation may be better performed while the page is being printed rather than at the end of the page.
    10.2.9 Page Finish

These operations are typically performed when the page is finished:

  • 1) Page finished interrupt occurs from PHI.
  • 2) Shutdown the PEP blocks by de-asserting their Go registers. A typical shutdown order is defined in Table 13. This will set the PEP Unit state-machines to their idle states without resetting their configuration registers.

3) Communicate ink usage to QA chips, if required.

TABLE 13
End of page shutdown order for PEP Units.
Step#Unit
1PHI (will shutdown by itself in the normal case at the end of a
page)
2DWU (shutting this down stalls the DNC and therefore the HCU
and above)
3LLU (should already be halted due to PHI at end of last line of
page)
4TE (this is the only dot supplier likely to be running, halted by the
HCU)
5CDU (this is likely to already be halted due to end of contone
band)
6CFU, SFU, TFU, LBD (order unimportant, and should already be
halted due to end of band)
7HCU, DNC (order unimportant, should already have halted)

10.2.10 Start of Next Page

These operations are typically performed before printing the next page:

  • 1) Re-program the PEP Units via PCU command processing from DRAM based on page header.
  • 2) Go to Start printing.
    10.2.11 End of Document
  • 1) Stop motor control.
    10.2.12 Sleep Mode

The CPU can put different sections of SoPEC into sleep mode by writing to registers in the CPR block described in Section 16.

  • 1) Instruct host PC via USB that SoPEC is about to sleep.
  • 2) Store reusable authentication results in Power-Safe Storage (PSS).
  • 3) Put SoPEC into defined sleep mode.
    10.3 Normal Operation in a Multi-SoPEC System—ISIMaster SoPEC

In a multi-SoPEC system the host generally manages program and compressed page download to all the SoPECs. Inter-SoPEC communication is over the ISI link which will add a latency. In the case of a multi-SoPEC system with just one USB 1.1 connection, the SoPEC with the USB connection is the ISIMaster. The ISI-bridge chip is the ISIMaster in the case of an ISI-Bridge SoPEC configuration. While it is perfectly possible for an ISISlave to have a direct USB connection to the host we do not treat this scenario explicitly here to avoid possible confusion.

In a multi-SoPEC system one of the SoPECs will be the PrintMaster. This SoPEC must manage and control sensors and actuators e.g. motor control. These sensors and actuators could be distributed over all the SoPECs in the system. An ISIMaster SoPEC may also be the PrintMaster SoPEC.

In a multi-SoPEC system each printing SoPEC will generally have its own PRINTER_QA chip (or at least access to a PRINTER_QA chip that contains the SoPEC's SoPEC_id_key) to validate operating parameters and ink usage. The results of these operations may be communicated to the PrintMaster SoPEC.

In general the ISIMaster may need to be able to:

Send messages to the ISISlaves which will cause the ISISlaves to send their status to the ISIMaster.

Instruct the ISISlaves to perform certain operations.

As the ISI is an insecure interface commands issued over the ISI are regarded as user mode commands. Supervisor mode code running on the SoPEC CPUs will allow or disallow these commands. The software protocol needs to be constructed with this in mind.

The ISIMaster will initiate all communication with the ISISlaves.

SoPEC operation is broken up into a number of sections which are outlined below.

10.3.1 Powerup

Powerup describes SoPEC initialisation following an external reset or the watchdog timer system reset.

  • 1) Execute reset sequence for complete SoPEC.
  • 2) CPU boot from ROM.
  • 3) Basic configuration of CPU peripherals, SCB and DIU. DRAM initialisation USB Wakeup
  • 4) SoPEC identification by activity on USB end-points 2-4 indicates it is the ISIMaster (unless the SoPEC CPU has explicitly disabled this function).
  • 5) Download and authentication of program (see Section 10.5.3).
  • 6) Execution of program from DRAM.
  • 7) Retrieve operating parameters from PRINTER_QA and authenticate operating parameters.
  • 8) Download and authenticate any further datasets (programs).
  • 9) The initial dataset may be broadcast to all the ISISlaves.
  • 10) ISIMaster master SoPEC then waits for a short time to allow the authentication to take place on the ISISlave SoPECs.
  • 11) Each ISISlave SoPEC is polled for the result of its program code authentication process.
  • 12) If all ISISlaves report successful authentication the OEM code module can be distributed and authenticated. OEM code will most likely reside on one SoPEC.
    10.3.2 USB Wakeup

The CPU can put different sections of SoPEC into sleep mode by writing to registers in the CPR block [16]. Normally the CPU sub-system and the DRAM will be put in sleep mode but the SCB and power-safe storage (PSS) will still be enabled.

Wakeup describes SoPEC recovery from sleep mode with the SCB and power-safe storage (PSS) still enabled. For an ISIMaster SoPEC connected to the host via USB, wakeup can be initiated following a USB reset from the SCB.

A typical USB wakeup sequence is:

  • 1) Execute reset sequence for sections of SoPEC in sleep mode.
  • 2) CPU boot from ROM, if CPU-subsystem was in sleep mode.
  • 3) Basic configuration of CPU peripherals and DIU, and DRAM initialisation, if required.
  • 4) SoPEC identification by activity on USB end-points 2-4 indicates it is the ISIMaster (unless the SoPEC CPU has explicitly disabled this function).
  • 5) Download and authentication of program using results in Power-Safe Storage (PSS) (see Section 10.5.3).
  • 6) Execution of program from DRAM.
  • 7) Retrieve operating parameters from PRINTER_QA and authenticate operating parameters.
  • 8) Download and authenticate any further datasets (programs) using results in Power-Safe Storage (PSS) (see Section 10.5.3).
  • 9) Following steps as per Powerup.
    10.3.3 Print Initialization

This sequence is typically performed at the start of a print job following powerup or wakeup:

  • 1) Check amount of ink remaining via QA chips which may be present on a ISISlave SoPEC.
  • 2) Download static data e.g. dither matrices, dead nozzle tables from host to DRAM.
  • 3) Check printhead temperature, if required, and configure printhead with firing pulse profile etc. accordingly. Instruct ISISlaves to also perform this operation.
  • 4) Initiate printhead pre-heat sequence, if required. Instruct ISISlaves to also perform this operation
    10.3.4 First Page Download

Buffer management in a SoPEC system is normally performed by the host.

  • 1) The host communicates to the SoPEC CPU over the USB to check that DRAM space remaining is sufficient to download the first band.
  • 2) The host downloads the first band (with the page header) to DRAM.
  • 3) When the complete page header has been downloaded the SoPEC CPU processes the page header, calculates PEP register commands and write directly to PEP registers or to DRAM.
  • 4) If PEP register commands have been written to DRAM, execute PEP commands from DRAM via PCU.

Poll ISISlaves for DRAM status and download compressed data to ISISlaves.

Remaining first page bands download and processing:

  • 1) Check DRAM space remaining is sufficient to download the next band.
  • 2) Download the next band with the band header to DRAM.
  • 3) When the complete band header has been downloaded, process the band header according to whichever band-related register updating mechanism is being used.

Poll ISISlaves for DRAM status and download compressed data to ISISlaves.

10.3.5 Start Printing

  • 1) Wait until at least one band of the first page has been downloaded.
  • 2) Start all the PEP Units by writing to their Go registers, via PCU commands executed from DRAM or direct CPU writes, in the suggested order defined in Table.
  • 3) Print ready interrupt occurs (from PHI). Poll ISISlaves until print ready interrupt.
  • 4) Start motor control (which may be on an ISISlave SoPEC), if first page, otherwise feed the next page. This step could occur before the print ready interrupt.
  • 5) Drive LEDS, monitor paper status (which may be on an ISISlave SoPEC).
  • 6) Wait for page alignment via page sensor(s) GPIO interrupt (which may be on an ISISlave SoPEC).
  • 7) If the LineSyncMaster is a SoPEC its CPU instructs PHI to start producing master line syncs. Otherwise wait for an external device to produce line syncs.
  • 8) Continue to download bands and process page and band headers for next page.
    10.3.6 Next Page(s) Download

As for first page download, performed during printing of current page.

10.3.7 Between Bands

When the finished band flags are asserted band related registers in the CDU, LBD and TE need to be re-programmed. This can be via PCU commands from DRAM. Typically only 3-5 commands per decompression unit need to be executed. These registers can also be reprogrammed directly by the CPU or by updating from shadow registers. The finished band flag interrupts to the CPU, tell the CPU that the area of memory associated with the band is now free.

10.3.8 During Page Print

Typically during page printing ink usage is communicated to the QA chips.

  • 1) Calculate ink printed (from PHI).
  • 2) Decrement ink remaining (via QA chips).
  • 3) Check amount of ink remaining (via QA chips). This operation may be better performed while the page is being printed rather than at the end of the page.
    10.3.9 Page Finish

These operations are typically performed when the page is finished:

  • 1) Page finished interrupt occurs from PHI. Poll ISISlaves for page finished interrupts.
  • 2) Shutdown the PEP blocks by de-asserting their Go registers in the suggested order in Table. This will set the PEP Unit state-machines to their startup states.
  • 3) Communicate ink usage to QA chips, if required.
    10.3.10 Start of Next Page

These operations are typically performed before printing the next page:

  • 1) Re-program the PEP Units via PCU command processing from DRAM based on page header.
  • 2) Go to Start printing.
    10.3.11 End of Document
  • 1) Stop motor control. This may be on an ISISlave SoPEC.
    10.3.12 Sleep Mode

The CPU can put different sections of SoPEC into sleep mode by writing to registers in the CPR block [16]. This may be as a result of a command from the host or as a result of a timeout.

  • 1) Inform host PC of which parts of SoPEC system are about to sleep.
  • 2) Instruct ISISlaves to enter sleep mode.
  • 3) Store reusable cryptographic results in Power-Safe Storage (PSS).
  • 4) Put ISIMaster SoPEC into defined sleep mode.
    10.4 Normal Operation in a Multi-SoPEC System—ISISlave SoPEC

This section the outline typical operation of an ISISlave SoPEC in a multi-SoPEC system. The ISIMaster can be another SoPEC or an ISI-Bridge chIP. The ISISlave communicates with the host either via the ISIMaster or using a direct connection such as USB. For this use case we consider only an ISISlave that does not have a direct host connection. Buffer management in a SoPEC system is normally performed by the host.

10.4.1 Powerup

Powerup describes SoPEC initialisation following an external reset or the watchdog timer system reset.

A typical powerup sequence is:

  • 1) Execute reset sequence for complete SoPEC.
  • 2) CPU boot from ROM.
  • 3) Basic configuration of CPU peripherals, SCB and DIU. DRAM initialisation.
  • 4) Download and authentication of program (see Section 10.5.3).
  • 5) Execution of program from DRAM.
  • 6) Retrieve operating parameters from PRINTER_QA and authenticate operating parameters.
  • 7) SoPEC identification by sampling GPIO pins to determine ISIId. Communicate ISIId to ISIMaster.
  • 8) Download and authenticate any further datasets.
    10.4.2 ISI Wakeup

The CPU can put different sections of SoPEC into sleep mode by writing to registers in the CPR block [16]. Normally the CPU sub-system and the DRAM will be put in sleep mode but the SCB and power-safe storage (PSS) will still be enabled.

Wakeup describes SoPEC recovery from sleep mode with the SCB and power-safe storage (PSS) still enabled. In an ISISlave SoPEC, wakeup can be initiated following an ISI reset from the SCB. A typical ISI wakeup sequence is:

  • 1) Execute reset sequence for sections of SoPEC in sleep mode.
  • 2) CPU boot from ROM, if CPU-subsystem was in sleep mode.
  • 3) Basic configuration of CPU peripherals and DIU, and DRAM initialisation, if required.
  • 4) Download and authentication of program using results in Power-Safe Storage (PSS) (see Section 10.5.3).
  • 5) Execution of program from DRAM.
  • 6) Retrieve operating parameters from PRINTER_QA and authenticate operating parameters.
  • 7) SoPEC identification by sampling GPIO pins to determine ISIId. Communicate ISIId to ISIMaster.
  • 8) Download and authenticate any further datasets.
    10.4.3 Print Initialization

This sequence is typically performed at the start of a print job following powerup or wakeup:

  • 1) Check amount of ink remaining via QA chips.
  • 2) Download static data e.g. dither matrices, dead nozzle tables from ISI to DRAM.
  • 3) Check printhead temperature, if required, and configure printhead with firing pulse profile etc. accordingly.
  • 4) Initiate printhead pre-heat sequence, if required.
    10.4.4 First Page Download

Buffer management in a SoPEC system is normally performed by the host via the ISI.

  • 1) Check DRAM space remaining is sufficient to download the first band.
  • 2) The host downloads the first band (with the page header) to DRAM via the ISI.
  • 3) When the complete page header has been downloaded, process the page header, calculate PEP register commands and write directly to PEP registers or to DRAM.
  • 4) If PEP register commands have been written to DRAM, execute PEP commands from DRAM via PCU.

Remaining first page bands download and processing:

  • 1) Check DRAM space remaining is sufficient to download the next band.
  • 2) The host downloads the first band (with the page header) to DRAM via the ISI.
  • 3) When the complete band header has been downloaded, process the band header according to whichever band-related register updating mechanism is being used.
    10.4.5 Start Printing
  • 1) Wait until at least one band of the first page has been downloaded.
  • 2) Start all the PEP Units by writing to their Go registers, via PCU commands executed from DRAM or direct CPU writes, in the order defined in Table
  • 3) Print ready interrupt occurs (from PHI). Communicate to PrintMaster via ISI.
  • 4) Start motor control, if attached to this ISISlave, when requested by PrintMaster, if first page, otherwise feed next page. This step could occur before the print ready interrupt
  • 5) Drive LEDS, monitor paper status, if on this ISISlave SoPEC, when requested by PrintMaster
  • 6) Wait for page alignment via page sensor(s) GPIO interrupt, if on this ISISlave SoPEC, and send to PrintMaster.
  • 7) Wait for line sync and commence printing.
  • 8) Continue to download bands and process page and band headers for next page.
    10.4.6 Next Page(s) Download

As for first band download, performed during printing of current page.

10.4.7 Between Bands

When the finished band flags are asserted band related registers in the CDU, LBD and TE need to be re-programmed. This can be via PCU commands from DRAM. Typically only 3-5 commands per decompression unit need to be executed. These registers can also be reprogrammed directly by the CPU or by updating from shadow registers. The finished band flag interrupts to the CPU tell the CPU that the area of memory associated with the band is now free.

10.4.8 During Page Print

Typically during page printing ink usage is communicated to the QA chips.

  • 1) Calculate ink printed (from PHI).
  • 2) Decrement ink remaining (via QA chips).
  • 3) Check amount of ink remaining (via QA chips). This operation may be better performed while the page is being printed rather than at the end of the page.
    10.4.9 Page Finish

These operations are typically performed when the page is finished:

  • 1) Page finished interrupt occurs from PHI. Communicate page finished interrupt to PrintMaster.
  • 2) Shutdown the PEP blocks by de-asserting their Go registers in the suggested order in Table. This will set the PEP Unit state-machines to their startup states.
  • 3) Communicate ink usage to QA chips, if required.
    10.4.10 Start of Next Page

These operations are typically performed before printing the next page:

  • 1) Re-program the PEP Units via PCU command processing from DRAM based on page header.
  • 2) Go to Start printing.
    10.4.11 End of Document

Stop motor control, if attached to this ISISlave, when requested by PrintMaster.

10.4.12 Powerdown

In this mode SoPEC is no longer powered.

  • 1) Powerdown ISISlave SoPEC when instructed by ISIMaster.
    10.4.13 Sleep

The CPU can put different sections of SoPEC into sleep mode by writing to registers in the CPR block [16]. This may be as a result of a command from the host or ISIMaster or as a result of a timeout.

  • 1) Store reusable cryptographic results in Power-Safe Storage (PSS).
  • 2) Put SoPEC into defined sleep mode.
    10.5 Security Use Cases

Please see the ‘SoPEC Security Overview’ [9] document for a more complete description of SoPEC security issues. The SoPEC boot operation is described in the ROM chapter of the SoPEC hardware design specification, Section 17.2.

10.5.1 Communication with the QA Chips

Communication between SoPEC and the QA chips (i.e. INK_QA and PRINTER_QA) will take place on at least a per power cycle and per page basis. Communication with the QA chips has three principal purposes: validating the presence of genuine QA chips (i.e the printer is using approved consumables), validation of the amount of ink remaining in the cartridge and authenticating the operating parameters for the printer. After each page has been printed, SoPEC is expected to communicate the number of dots fired per ink plane to the QA chipset. SoPEC may also initiate decoy communications with the QA chips from time to time.

Process:

    • When validating ink consumption SoPEC is expected to principally act as a conduit between the PRINTER_QA and INK_QA chips and to take certain actions (basically enable or disable printing and report status to host PC) based on the result. The communication channels are insecure but all traffic is signed to guarantee authenticity.
      Known Weaknesses
    • All communication to the QA chips is over the LSS interfaces using a serial communication protocol. This is open to observation and so the communication protocol could be reverse engineered. In this case both the PRINTER_QA and INK_QA chips could be replaced by impostor devices (e.g. a single FPGA) that successfully emulated the communication protocol. As this would require physical modification of each printer this is considered to be an acceptably low risk. Any messages that are not signed by one of the symmetric keys (such as the SoPEC_id_key) could be reverse engineered. The imposter device must also have access to the appropriate keys to crack the system.
    • If the secret keys in the QA chips are exposed or cracked then the system, or parts of it, is compromised.
      Assumptions:
  • [1] The QA chips are not involved in the authentication of downloaded SoPEC code
  • [2] The QA chip in the ink cartridge (INK_QA) does not directly affect the operation of the cartridge in any way i.e. it does not inhibit the flow of ink etc.
  • [3] The INK_QA and PRINTER_QA chips are identical in their virgin state. They only become a INK_QA or PRINTER_QA after their FlashROM has been programmed.
    10.5.2 Authentication of Downloaded Code in a Single SoPEC System
    Process:
  • 1) SoPEC identification by activity on USB end-points 2-4 indicates it is the ISIMaster (unless the SoPEC CPU has explicitly disabled this function).
  • 2) The program is downloaded to the embedded DRAM.
  • 3) The CPU calculates a SHA-1 hash digest of the downloaded program.
  • 4) The ResetSrc register in the CPR block is read to determine whether or not a power-on reset occurred.
  • 5) If a power-on reset occurred the signature of the downloaded code (which needs to be in a known location such as the first or last N bytes of the downloaded code) is decrypted using the Silverbrook public boot0key stored in ROM. This decrypted signature is the expected SHA-1 hash of the accompanying program. The encryption algorithm is likely to be a public key algorithm such as RSA. If a power-on reset did not occur then the expected SHA-1 hash is retrieved from the PSS and the compute intensive decryption is not required.
  • 6) The calculated and expected hash values are compared and if they match then the programs authenticity has been verified.
  • 7) If the hash values do not match then the host PC is notified of the failure and the SoPEC will await a new program download.
  • 8) If the hash values match then the CPU starts executing the downloaded program.
  • 9) If, as is very likely, the downloaded program wishes to download subsequent programs (such as OEM code) it is responsible for ensuring the authenticity of everything it downloads. The downloaded program may contain public keys that are used to authenticate subsequent downloads, thus forming a hierarchy of authentication. The SoPEC ROM does not control these authentications—it is solely concerned with verifying that the first program downloaded has come from a trusted source.
  • 10) At some subsequent point OEM code starts executing. The Silverbrook supervisor code acts as an O/S to the OEM user mode code. The OEM code must access most SoPEC functionality via system calls to the Silverbrook code.
  • 11) The OEM code is expected to perform some simple ‘turn on the lights’ tasks after which the host PC is informed that the printer is ready to print and the Start Printing use case comes into play.
    Known Weaknesses:
    • If the Silverbrook private boot0key is exposed or cracked then the system is seriously compromised. A ROM mask change would be required to reprogram the boot0key.
      10.5.3 Authentication of Downloaded Code in a Multi-SoPEC System
      10.5.3.1 ISIMaster SoPEC Process:
  • 1) SoPEC identification by activity on USB end-points 2-4 indicates it is the ISIMaster.
  • 2) The SCB is configured to broadcast the data received from the host PC.
  • 3) The program is downloaded to the embedded DRAM and broadcasted to all ISISlave SoPECs over the ISI.
  • 4) The CPU calculates a SHA-1 hash digest of the downloaded program.
  • 5) The ResetSrc register in the CPR block is read to determine whether or not a power-on reset occurred.
  • 6) If a power-on reset occurred the signature of the downloaded code (which needs to be in a known location such as the first or last N bytes of the downloaded code) is decrypted using the Silverbrook public boot0key stored in ROM. This decrypted signature is the expected SHA-1 hash of the accompanying program. The encryption algorithm is likely to be a public key algorithm such as RSA. If a power-on reset did not occur then the expected SHA-1 hash is retrieved from the PSS and the compute intensive decryption is not required.
  • 7) The calculated and expected hash values are compared and if they match then the programs authenticity has been verified.
  • 8) If the hash values do not match then the host PC is notified of the failure and the SoPEC will await a new program download.
  • 9) If the hash values match then the CPU starts executing the downloaded program.
  • 10) It is likely that the downloaded program will poll each ISISlave SoPEC for the result of its authentication process and to determine the number of slaves present and their ISIIds.
  • 11) If any ISISlave SoPEC reports a failed authentication then the ISIMaster communicates this to the host PC and the SoPEC will await a new program download.
  • 12) If all ISISlaves report successful authentication then the downloaded program is responsible for the downloading, authentication and distribution of subsequent programs within the multi-SoPEC system.
  • 13) At some subsequent point OEM code starts executing. The Silverbrook supervisor code acts as an O/S to the OEM user mode code. The OEM code must access most SoPEC functionality via system calls to the Silverbrook code.
  • 14) The OEM code is expected to perform some simple ‘turn on the lights’ tasks after which the master SoPEC determines that all SoPECs are ready to print. The host PC is informed that the printer is ready to print and the Start Printing use case comes into play.
    10.5.3.2 ISISlave SoPEC Process:
  • 1) When the CPU comes out of reset the SCB will be in slave mode, and the SCB is already configured to receive data from both the ISI and USB.
  • 2) The program is downloaded (via ISI or USB) to embedded DRAM.
  • 3) The CPU calculates a SHA-1 hash digest of the downloaded program.
  • 4) The ResetSrc register in the CPR block is read to determine whether or not a power-on reset occurred.
  • 5) If a power-on reset occurred the signature of the downloaded code (which needs to be in a known location such as the first or last N bytes of the downloaded code) is decrypted using the Silverbrook public boot0key stored in ROM. This decrypted signature is the expected SHA-1 hash of the accompanying program. The encryption algorithm is likely to be a public key algorithm such as RSA. If a power-on reset did not occur then the expected SHA-1 hash is retrieved from the PSS and the compute intensive decryption is not required.
  • 6) The calculated and expected hash values are compared and if they match then the programs authenticity has been verified.
  • 7) If the hash values do not match, then the ISISlave device will await a new program again
  • 8) If the hash values match then the CPU starts executing the downloaded program.
  • 9) It is likely that the downloaded program will communicate the result of its authentication process to the ISIMaster. The downloaded program is responsible for determining the SoPECs ISIID, receiving and authenticating any subsequent programs.
  • 10) At some subsequent point OEM code starts executing. The Silverbrook supervisor code acts as an O/S to the OEM user mode code. The OEM code must access most SoPEC functionality via system calls to the Silverbrook code.
  • 11) The OEM code is expected to perform some simple ‘turn on the lights’ tasks after which the master SoPEC is informed that this slave is ready to print. The Start Printing use case then comes into play.
    Known Weaknesses
    • If the Silverbrook private boot0key is exposed or cracked then the system is seriously compromised.
    • ISI is an open interface i.e. messages sent over the ISI are in the clear. The communication channels are insecure but all traffic is signed to guarantee authenticity. As all communication over the ISI is controlled by Supervisor code on both the ISIMaster and ISISlave then this also provides some protection against software attacks.
      10.5.4 Authentication and Upgrade of Operating Parameters for a Printer

The SoPEC IC will be used in a range of printers with different capabilities (e.g. A3/A4 printing, printing speed, resolution etc.). It is expected that some printers will also have a software upgrade capability which would allow a user to purchase a license that enables an upgrade in their printer's capabilities (such as print speed). To facilitate this it must be possible to securely store the operating parameters in the PRINTER_QA chip, to securely communicate these parameters to the SoPEC and to securely reprogram the parameters in the event of an upgrade. Note that each printing SoPEC (as opposed to a SoPEC that is only used for the storage of data) will have its own PRINTER_QA chip (or at least access to a PRINTER_QA that contains the SoPEC's SoPEC_id_key). Therefore both ISIMaster and ISISlave SoPECs will need to authenticate operating parameters.

Process:

  • 1) Program code is downloaded and authenticated as described in sections 10.5.2 and 10.5.3 above.
  • 2) The program code has a function to create the SoPEC_id_key from the unique SoPEC_id that was programmed when the SoPEC was manufactured.
  • 3) The SoPEC retrieves the signed operating parameters from its PRINTER_QA chIP. The PRINTER_QA chip uses the SoPEC_id_key (which is stored as part of the pairing process executed during printhead assembly manufacture & test) to sign the operating parameters which are appended with a random number to thwart replay attacks.
  • 4) The SoPEC checks the signature of the operating parameters using its SoPEC_id_-key. If this signature authentication process is successful then the operating parameters are considered valid and the overall boot process continues. If not the error is reported to the host PC.
  • 5) Operating parameters may also be set or upgraded using a second key, the PrintEngineLicense_key, which is stored on the PRINTER_QA and used to authenticate the change in operating parameters.
    Known Weaknesses:
    • It may be possible to retrieve the unique SoPEC_id by placing the SoPEC in test mode and scanning it out. It is certainly possible to obtain it by reverse engineering the device. Either way the SoPEC_id (and by extension the SoPEC_id_key) so obtained is valid only for that specific SoPEC and so printers may only be compromised one at a time by parties with the appropriate specialised equipment. Furthermore even if the SoPEC_id is compromised, the other keys in the system, which protect the authentication of consumables and of program code, are unaffected.
      10.6 Miscellaneous Use Cases

There are many miscellaneous use cases such as the following examples. Software running on the SoPEC CPU or host will decide on what actions to take in these scenarios.

10.6.1 Disconnect/Re-Connect of QA Chips.

  • 1) Disconnect of a QA chip between documents or if ink runs out mid-document.
  • 2) Re-connect of a QA chip once authenticated e.g. ink cartridge replacement should allow the system to resume and print the next document
    10.6.2 Page Arrives Before Print Ready Interrupt.
  • 1) Engage clutch to stop paper until print ready interrupt occurs.
    10.6.3 Dead-Nozzle Table Upgrade

This sequence is typically performed when dead nozzle information needs to be updated by performing a printhead dead nozzle test.

  • 1) Run printhead nozzle test sequence
  • 2) Either host or SoPEC CPU converts dead nozzle information into dead nozzle table.
  • 3) Store dead nozzle table on host.
  • 4) Write dead nozzle table to SoPEC DRAM.
    10.7 Failure Mode Use Cases
    10.7.1 System Errors and Security Violations

System errors and security violations are reported to the SoPEC CPU and host. Software running on the SoPEC CPU or host will then decide what actions to take.

Silverbrook code authentication failure.

  • 1) Notify host PC of authentication failure.
  • 2) Abort print run.

OEM code authentication failure.

  • 1) Notify host PC of authentication failure.
  • 2) Abort print run.

Invalid QA chip(s).

  • 1) Report to host PC.
  • 2) Abort print run.

MMU security violation interrupt.

  • 1) This is handled by exception handler.
  • 2) Report to host PC
  • 3) Abort print run.

Invalid address interrupt from PCU.

  • 1) This is handled by exception handler.
  • 2) Report to host PC.
  • 3) Abort print run.

Watchdog timer interrupt.

  • 1) This is handled by exception handler.
  • 2) Report to host PC.
  • 3) Abort print run.

Host PC does not acknowledge message that SoPEC is about to power down.

  • 1) Power down anyway.
    10.7.2 Printing Errors

Printing errors are reported to the SoPEC CPU and host. Software running on the host or SoPEC CPU will then decide what actions to take.

Insufficient space available in SoPEC compressed band-store to download a band.

  • 1) Report to the host PC.

Insufficient ink to print.

  • 1) Report to host PC.

Page not downloaded in time while printing.

  • 1) Buffer underrun interrupt will occur.
  • 2) Report to host PC and abort print run.

JPEG decoder error interrupt.

  • 1) Report to host PC.
    CPU Subsystem
    11 Central Processing Unit (CPU)
    11.1 Overview

The CPU block consists of the CPU core, MMU, cache and associated logic. The principal tasks for the program running on the CPU to fulfill in the system are:

Communications:

    • Control the flow of data from the USB interface to the DRAM and ISI
    • Communication with the host via USB or ISI
    • Running the USB device driver
      PEP Subsystem Control:
    • Page and band header processing (may possibly be performed on host PC)
    • Configure printing options on a per band, per page, per job or per power cycle basis
    • Initiate page printing operation in the PEP subsystem
    • Retrieve dead nozzle information from the printhead interface (PHI) and forward to the host PC
    • Select the appropriate firing pulse profile from a set of predefined profiles based on the printhead characteristics
    • Retrieve printhead temperature via the PHI
      Security:
    • Authenticate downloaded program code
    • Authenticate printer operating parameters
    • Authenticate consumables via the PRINTER_QA and INK_QA chips
    • Monitor ink usage
    • Isolation of OEM code from direct access to the system resources
      Other:
    • Drive the printer motors using the GPIO pins
    • Monitoring the status of the printer (paper jam, tray empty etc.)
    • Driving front panel LEDs
    • Perform post-boot initialisation of the SoPEC device
    • Memory management (likely to be in conjunction with the host PC)
    • Miscellaneous housekeeping tasks

To control the Print Engine Pipeline the CPU is required to provide a level of performance at least equivalent to a 16-bit Hitachi H8-3664 microcontroller running at 16 MHz. An as yet undetermined amount of additional CPU performance is needed to perform the other tasks, as well as to provide the potential for such activity as Netpage page assembly and processing, RIPing etc. The extra performance required is dominated by the signature verification task and the SCB (including the USB) management task. An operating system is not required at present. A number of CPU cores have been evaluated and the LEON P1754 is considered to be the most appropriate solution. A diagram of the CPU block is shown in FIG. 15 below.

11.2 Definitions of I/Os

TABLE 14
CPU Subsystem I/Os
Port namePinsI/ODescription
Clocks and Resets
prst_n1InGlobal reset. Synchronous to pclk, active low.
Pclk1InGlobal clock
CPU to DIU DRAM interface
cpu_adr[21:2]20OutAddress bus for both DRAM and peripheral
access
cpu_dataout[31:0]32OutData out to both DRAM and peripheral devices.
This should be driven at the same time as the
cpu_adr and request signals.
dram_cpu_data[255:0]256InRead data from the DRAM
cpu_diu_rreq1OutRead request to the DIU DRAM
diu_cpu_rack1InAcknowledge from DIU that read request has
been accepted.
diu_cpu_rvalid1InSignal from DIU telling SoPEC Unit that valid read
data is on the dram_cpu_data bus
cpu_diu_wdatavalid1OutSignal from the CPU to the DIU indicating that the
data currently on the cpu_diu_wdata bus is valid
and should be committed to the DIU posted write
buffer
diu_cpu_write_rdy1InSignal from the DIU indicating that the posted
write buffer is empty
cpu_diu_wdadr[21:4]18OutWrite address bus to the DIU
cpu_diu_wdata[127:0]128OutWrite data bus to the DIU
cpu_diu_wmask[15:0]16OutWrite mask for the cpu_diu_wdata bus. Each bit
corresponds to a byte of the 128-bit
cpu_diu_wdata bus.
CPU to peripheral blocks
cpu_rwn1OutCommon read/not-write signal from the CPU
cpu_acode[1:0]2OutCPU access code signals.
cpu_acode[0] - Program (0)/Data (1) access
cpu_acode[1] - User (0)/Supervisor (1) access
cpu_cpr_sel1OutCPR block select.
cpr_cpu_rdy1InReady signal to the CPU. When cpr_cpu_rdy is
high it indicates the last cycle of the access. For a
write cycle this means cpu_dataout has been
registered by the CPR block and for a read cycle
this means the data on cpr_cpu_data is valid.
cpr_cpu_berr1InCPR bus error signal to the CPU.
cpr_cpu_data[31:0]32InRead data bus from the CPR block
cpu_gpio_sel1OutGPIO block select.
gpio_cpu_rdy1InGPIO ready signal to the CPU.
gpio_cpu_berr1InGPIO bus error signal to the CPU.
gpio_cpu_data[31:0]32InRead data bus from the GPIO block
cpu_icu_sel1OutICU block select.
icu_cpu_rdy1InICU ready signal to the CPU.
icu_cpu_berr1InICU bus error signal to the CPU.
icu_cpu_data[31:0]32InRead data bus from the ICU block
cpu_lss_sel1OutLSS block select.
lss_cpu_rdy1InLSS ready signal to the CPU.
lss_cpu_berr1InLSS bus error signal to the CPU.
lss_cpu_data[31:0]32InRead data bus from the LSS block
cpu_pcu_sel1OutPCU block select.
pcu_cpu_rdy1InPCU ready signal to the CPU.
pcu_cpu_berr1InPCU bus error signal to the CPU.
pcu_cpu_data[31:0]32InRead data bus from the PCU block
cpu_scb_sel1OutSCB block select.
scb_cpu_rdy1InSCB ready signal to the CPU.
scb_cpu_berr1InSCB bus error signal to the CPU.
scb_cpu_data[31:0]32InRead data bus from the SCB block
cpu_tim_sel1OutTimers block select.
tim_cpu_rdy1InTimers block ready signal to the CPU.
tim_cpu_berr1InTimers bus error signal to the CPU.
tim_cpu_data[31:0]32InRead data bus from the Timers block
cpu_rom_sel1OutROM block select.
rom_cpu_rdy1InROM block ready signal to the CPU.
rom_cpu_berr1InROM bus error signal to the CPU.
rom_cpu_data[31:0]32InRead data bus from the ROM block
cpu_pss_sel1OutPSS block select.
pss_cpu_rdy1InPSS block ready signal to the CPU.
pss_cpu_berr1InPSS bus error signal to the CPU.
pss_cpu_data[31:0]32InRead data bus from the PSS block
cpu_diu_sel1OutDIU register block select.
diu_cpu_rdy1InDIU register block ready signal to the CPU.
diu_cpu_berr1InDIU bus error signal to the CPU.
diu_cpu_data[31:0]32InRead data bus from the DIU block
Interrupt signals
icu_cpu_ilevel[3:0]3InAn interrupt is asserted by driving the appropriate
priority level on icu_cpu_ilevel. These signals
must remain asserted until the CPU executes an
interrupt acknowledge cycle.
3OutIndicates the level of the interrupt the CPU is
acknowledging when cpu_iack is high
cpu_iack1OutInterrupt acknowledge signal. The exact timing
depends on the CPU core implementation
Debug signals
diu_cpu_debug_valid1InSignal indicating the data on the diu_cpu_data
bus is valid debug data.
tim_cpu_debug_valid1InSignal indicating the data on the tim_cpu_data
bus is valid debug data.
scb_cpu_debug_valid1InSignal indicating the data on the scb_cpu_data
bus is valid debug data.
pcu_cpu_debug_valid1InSignal indicating the data on the pcu_cpu_data
bus is valid debug data.
lss_cpu_debug_valid1InSignal indicating the data on the lss_cpu_data bus
is valid debug data.
icu_cpu_debug_valid1InSignal indicating the data on the icu_cpu_data bus
is valid debug data.
gpio_cpu_debug_valid1InSignal indicating the data on the gpio_cpu_data
bus is valid debug data.
cpr_cpu_debug_valid1InSignal indicating the data on the cpr_cpu_data
bus is valid debug data.
debug_data_out32OutOutput debug data to be muxed on to the GPIO &
PHI pins
debug_data_valid1OutDebug valid signal indicating the validity of the
data on debug_data_out. This signal is used in all
debug configurations
debug_cntrl33OutControl signal for each PHI bound debug data line
indicating whether or not the debug data should
be selected by the pin mux

11.3 Realtime Requirements

The SoPEC realtime requirements have yet to be fully determined but they may be split into three categories: hard, firm and soft

11.3.1 Hard Realtime Requirements

Hard requirements are tasks that must be completed before a certain deadline or failure to do so will result in an error perceptible to the user (printing stops or functions incorrectly). There are three hard realtime tasks:

    • Motor control: The motors which feed the paper through the printer at a constant speed during printing are driven directly by the SoPEC device. Four periodic signals with different phase relationships need to be generated to ensure the paper travels smoothly through the printer. The generation of these signals is handled by the GPIO hardware (see section 13.2 for more details) but the CPU is responsible for enabling these signals (i.e. to start or stop the motors) and coordinating the movement of the paper with the printing operation of the printhead.
    • Buffer management: Data enters the SoPEC via the SCB at an uneven rate and is consumed by the PEP subsystem at a different rate. The CPU is responsible for managing the DRAM buffers to ensure that neither overrun nor underrun occur. This buffer management is likely to be performed under the direction of the host.
    • Band processing: In certain cases PEP registers may need to be updated between bands. As the timing requirements are most likely too stringent to be met by direct CPU writes to the PCU a more likely scenario is that a set of shadow registers will programmed in the compressed page units before the current band is finished, copied to band related registers by the finished band signals and the processing of the next band will continue immediately. An alternative solution is that the CPU will construct a DRAM based set of commands (see section 21.8.5 for more details) that can be executed by the PCU. The task for the CPU here is to parse the band headers stored in DRAM and generate a DRAM based set of commands for the next number of bands. The location of the DRAM based set of commands must then be written to the PCU before the current band has been processed by the PEP subsystem. It is also conceivable (but currently considered unlikely) that the host PC could create the DRAM based commands. In this case the CPU will only be required to point the PCU to the correct location in DRAM to execute commands from.
      11.3.2 Firm Requirements

Firm requirements are tasks that should be completed by a certain time or failure to do so will result in a degradation of performance but not an error. The majority of the CPU tasks for SoPEC fall into this category including all interactions with the QA chips, program authentication, page feeding, configuring PEP registers for a page or job, determining the firing pulse profile, communication of printer status to the host over the USB and the monitoring of ink usage. The authentication of downloaded programs and messages will be the most compute intensive operation the CPU will be required to perform. Initial investigations indicate that the LEON processor, running at 160 MHz, will easily perform three authentications in under a second.

TABLE 15
Expected firm requirements
RequirementDuration
Power-on to start of printing first page [USB  ˜8 secs ??
and slave SoPEC enumeration, 3 or
more RSA signature verifications, code and
compressed page data download and chip initialisation]
Wake-up from sleep mode to start printing [3 or more  ˜2 secs
SHA-1/RSA operations, code and compressed
page data download and chip re-initialisation
Authenticate ink usage in the printer˜0.5 secs
Determining firing pulse profile˜0.1 secs
Page feeding, gap between pagesOEM dependent
Communication of printer status to host PC ˜10 ms
Configuring PEP registers??

11.3.3 Soft Requirements

Soft requirements are tasks that need to be done but there are only light time constraints on when they need to be done. These tasks are performed by the CPU when there are no pending higher priority tasks. As the SoPEC CPU is expected to be lightly loaded these tasks will mostly be executed soon after they are scheduled.

11.4 Bus Protocols

As can be seen from FIG. 15 above there are different buses in the CPU block and different protocols are used for each bus. There are three buses in operation:

11.4.1 AHB Bus

The LEON CPU core uses an AMBA2.0 AHB bus to communicate with memory and peripherals (usually via an APB bridge). See the AMBA specification [38], section 5 of the LEON users manual [37] and section 11.6.6.1 of this document for more details.

11.4.2 CPU to DIU Bus

This bus conforms to the DIU bus protocol described in Section 20.14.8. Note that the address bus used for DIU reads (i.e. cpu_adr(21:2)) is also that used for CPU subsystem with bus accesses while the write address bus (cpu_diu_wadr) and the read and write data buses (dram_cpu_data and cpu_diu_wdata) are private buses between the CPU and the DIU. The effective bus width differs between a read (256 bits) and a write (128 bits). As certain CPU instructions may require byte write access this will need to be supported by both the DRAM write buffer (in the AHB bridge) and the DIU. See section 11.6.6.1 for more details.

11.4.3 CPU Subsystem Bus

For access to the on-chip peripherals a simple bus protocol is used. The MMU must first determine which particular block is being addressed (and that the access is a valid one) so that the appropriate block select signal can be generated. During a write access CPU write data is driven out with the address and block select signals in the first cycle of an access. The addressed slave peripheral responds by asserting its ready signal indicating that it has registered the write data and the access can complete. The write data bus is common to all peripherals and is also used for CPU writes to the embedded DRAM. A read access is initiated by driving the address and select signals during the first cycle of an access. The addressed slave responds by placing the read data on its bus and asserting its ready signal to indicate to the CPU that the read data is valid. Each block has a separate point-to-point data bus for read accesses to avoid the need for a tri-stateable bus. All peripheral accesses are 32-bit (Programming note: char or short C types should not be used to access peripheral registers). The use of the ready signal allows the accesses to be of variable length. In most cases accesses will complete in two cycles but three or four (or more) cycles accesses are likely for PEP blocks or IP blocks with a different native bus interface. All PEP blocks are accessed via the PCU which acts as a bridge. The PCU bus uses a similar protocol to the CPU subsystem bus but with the PCU as the bus master.

The duration of accesses to the PEP blocks is influenced by whether or not the PCU is executing commands from DRAM. As these commands are essentially register writes the CPU access will need to wait until the PCU bus becomes available when a register access has been completed. This could lead to the CPU being stalled for up to 4 cycles if it attempts to access PEP blocks while the PCU is executing a command. The size and probability of this penalty is sufficiently small to have any significant impact on performance.

In order to support user mode (i.e. OEM code) access to certain peripherals the CPU subsystem bus propagates the CPU function code signals (cpu_acode[1:0]). These signals indicate the type of address space (i.e. User/Supervisor and Program/Data) being accessed by the CPU for each access. Each peripheral must determine whether or not the CPU is in the correct mode to be granted access to its registers and in some cases (e.g. Timers and GPIO blocks) different access permissions can apply to different registers within the block. If the CPU is not in the correct mode then the violation is flagged by asserting the block's bus error signal (block_cpu_berr) with the same timing as its ready signal (block_cpu_rdy) which remains deasserted. When this occurs invalid read accesses should return 0 and write accesses should have no effect.

FIG. 16 shows two examples of the peripheral bus protocol in action. A write to the LSS block from code running in supervisor mode is successfully completed. This is immediately followed by a read from a PEP block via the PCU from code running in user mode. As this type of access is not permitted the access is terminated with a bus error. The bus error exception processing then starts directly after this—no further accesses to the peripheral should be required as the exception handler should be located in the DRAM.

Each peripheral acts as a slave on the CPU subsystem bus and its behavior is described by the state machine in section 11.4.3.1

11.4.3.1 CPU Subsystem Bus Slave State Machine

CPU subsystem bus slave operation is described by the state machine in FIG. 17. This state machine will be implemented in each CPU subsystem bus slave. The only new signals mentioned here are the valid_access and reg_available signals. The valid_access is determined by comparing the cpu_acode value with the block or register (in the case of a block that allow user access on a per register basis such as the GPIO block) access permissions and asserting valid_access if the permissions agree with the CPU mode. The reg_available signal is only required in the PCU or in blocks that are not capable of two-cycle access (e.g. blocks containing imported IP with different bus protocols). In these blocks the reg_available signal is an internal signal used to insert wait states (by delaying the assertion of block_cpu_rdy) until the CPU bus slave interface can gain access to the register.

When reading from a register that is less than 32 bits wide the CPU subsystems bus slave should return zeroes on the unused upper bits of the block_cpu_data bus.

To support debug mode the contents of the register selected for debug observation, debug_reg, are always output on the block_cpu_data bus whenever a read access is not taking place. See section

11.8 for More Details of Debug Operation.

11.5 LEON CPU

The LEON processor is an open-source implementation of the IEEE-1754 standard (SPARC V8) instruction set. LEON is available from and actively supported by Gaisler Research (www.gaisler.com).

The following features of the LEON-2 processor will be utilised on SoPEC:

    • IEEE-1754 (SPARC V8) compatible integer unit with 5-stage pipeline
    • Separate instruction and data cache (Harvard architecture). 1 kbyte direct mapped caches will be used for both.
    • Full implementation of AMBA-2.0 AHB on-chip bus

The standard release of LEON incorporates a number of peripherals and support blocks which will not be included on SoPEC. The LEON core as used on SoPEC will consist of: 1) the LEON integer unit, 2) the instruction and data caches (currently 1 kB each), 3) the cache control logic, 4) the AHB interface and 5) possibly the AHB controller (although this functionality may be implemented in the LEON AHB bridge).

The version of the LEON database that the SoPEC LEON components will be sourced from is LEON2-1.0.7 although later versions may be used if they offer worthwhile functionality or bug fixes that affect the SoPEC design.

The LEON core will be clocked using the system clock, pclk, and reset using the prst_n_section[1] signal. The ICU will assert all the hardware interrupts using the protocol described in section 11.9. The LEON hardware multipliers and floating-point unit are not required. SoPEC will use the recommended 8 register window configuration.

Further details of the SPARC V8 instruction set and the LEON processor can be found in [36] and [37] respectively.

11.5.1 LEON Registers

Only two of the registers described in the LEON manual are implemented on SoPEC—the LEON configuration register and the Cache Control Register (CCR). The addresses of these registers are shown in Table 16. The configuration register bit fields are described below and the CCR is described in section 11.7.1.1.

11.5.1.1 LEON Configuration Register

The LEON configuration register allows runtime software to determine the settings of LEONs various configuration options. This is a read-only register whose value for the SoPEC ASIC will be 0x10718C00. Further descriptions of many of the bitfileds can be found in the LEON manual. The values used for SoPEC are highlighted in bold for clarity.

TABLE 16
LEON Configuration Register
Field Namebit(s)Description
WriteProtection1:0Write protection type.
00 - none
01 - standard
PCICore3:2PCI core type
00 - none
01 - InSilicon
10 - ESA
11 - Other
FPUType5:4FPU type.
00 - none
01 - Meiko
MemStatus60 - No memory status and failing address register present
1 - Memory status and failing address register present
Watchdog70 - Watchdog timer not present (Note this refers to the LEON
watchdog timer in the LEON timer block).
1 - Watchdog timer present
UMUL/SMUL80 - UMUL/SMUL instructions are not implemented
1 - UMUL/SMUL instructions are implemented
UDIV/SDIV90 - UMUL/SMUL instructions are not implemented
1 - UMUL/SMUL instructions are implemented
DLSZ11:10Data cache line size in 32-bit words:
00 - 1 word
01 - 2 words
10 - 4 words
11 - 8 words
DCSZ14:12Data cache size in kBbytes = 2DCSZ. SoPEC DCSZ = 0.
ILSZ16:15Instruction cache line size in 32-bit words:
00 - 1 word
01 - 2 words
10 - 4 words
11 - 8 words
ICSZ19:17Instruction cache size in kBbytes = 2ICSZ. SoPEC ICSZ = 0.
RegWin24:20The implemented number of SPARC register windows −1.
SoPEC value = 7.
UMAC/SMAC25 0 - UMAC/SMAC instructions are not implemented
1 - UMAC/SMAC instructions are implemented
Watchpoints28:26The implemented number of hardware watchpoints. SoPEC value = 4.
SDRAM29 0 - SDRAM controller not present
1 - SDRAM controller present
DSU30 0 - Debug Support Unit not present
1 - Debug Support Unit present
Reserved31 Reserved. SoPEC value = 0.

11.6 Memory Management Unit (MMU)

Memory Management Units are typically used to protect certain regions of memory from invalid accesses, to perform address translation for a virtual memory system and to maintain memory page status (swapped-in, swapped-out or unmapped)

The SoPEC MMU is a much simpler affair whose function is to ensure that all regions of the SoPEC memory map are adequately protected. The MMU does not support virtual memory and physical addresses are used at all times. The SoPEC MMU supports a full 32-bit address space. The SoPEC memory map is depicted in FIG. 18 below.

The MMU selects the relevant bus protocol and generates the appropriate control signals depending on the area of memory being accessed. The MMU is responsible for performing the address decode and generation of the appropriate block select signal as well as the selection of the correct block read bus during a read access. The MMU will need to support all of the bus transactions the CPU can produce including interrupt acknowledge cycles, aborted transactions etc. When an MMU error occurs (such as an attempt to access a supervisor mode only region when in user mode) a bus error is generated. While the LEON can recognise different types of bus error (e.g. data store error, instruction access error) it handles them in the same manner as it handles all traps i.e it will transfer control to a trap handler. No extra state information is be stored because of the nature of the trap. The location of the trap handler is contained in the TBR (Trap Base Register). This is the same mechanism as is used to handle interrupts.

11.6.1 CPU-Bus Peripherals Address Map

The address mapping for the peripherals attached to the CPU-bus is shown in Table 17 below. The MMU performs the decode of the high order bits to generate the relevant cpu_block_select signal. Apart from the PCU, which decodes the address space for the PEP blocks, each block only needs to decode as many bits of cpu_adr[1 1:2] as required to address all the registers within the block.

TABLE 17
CPU-bus peripherals address map
Block_baseAddress
ROM_base0x0000_0000
MMU_base0x0001_0000
TIM_base0x0001_1000
LSS_base0x0001_2000
GPIO_base0x0001_3000
SCB_base0x0001_4000
ICU_base0x0001_5000
CPR_base0x0001_6000
DIU_base0x0001_7000
PSS_base0x0001_8000
Reserved0x0001_9000 to 0x0001_FFFF
PCU_base0x0002_0000

11.6.2 DRAM Region Mapping

The embedded DRAM is broken into 8 regions, with each region defined by a lower and upper bound address and with its own access permissions.

The association of an area in the DRAM address space with a MMU region is completely under software control. Table 18 below gives one possible region mapping. Regions should be defined according to their access requirements and position in memory. Regions that share the same access requirements and that are contiguous in memory may be combined into a single region. The example below is purely for indicative purposes—real mappings are likely to differ significantly from this. Note that the RegionBottom and RegionTop fields in this example include the DRAM base address offset (0x40000000) which is not required when programming the RegionNTop and RegionNBottom registers. For more details, see 11.6.5.1 and 11.6.5.2.

TABLE 18
Example region mapping
RegionRegionBottomRegionTopDescription
00x4000_00000x4000_0FFFSilverbrook OS (supervisor)
data
10x4000_10000x4000_BFFFSilverbrook OS (supervisor)
code
20x4000_C0000x4000_C3FFSilverbrook (supervisor/user)
data
30x4000_C4000x4000_CFFFSilverbrook (supervisor/user)
code
40x4026_D0000x4026_D3FFOEM (user) data
50x4026_D4000x4026_DFFFOEM (user) code
60x4027_E0000x4027_FFFFShared Silverbrook/OEM
space
70x4000_D0000x4026_CFFFCompressed page store
(supervisor data)

11.6.3 Non-DRAM Regions

As shown in FIG. 18 the DRAM occupies only 2.5 MBytes of the total 4 GB SoPEC address space. The non-DRAM regions of SoPEC are handled by the MMU as follows:

ROM (1x0000000 to 1x0000_FFFF): The ROM block will control the access types allowed. The cpu_acode[1:0] signals will indicate the CPU mode and access type and the ROM block will assert rom_cpu_berr if an attempted access is forbidden. The protocol is described in more detail in section 11.4.3. The ROM block access permissions are hard wired to allow all read accesses except to the FuseChipID registers which may only be read in supervisor mode.

MMU Internal Registers (0x00010000 to 1x00010FFF): The MMU is responsible for controlling the accesses to its own internal registers and will only allow data reads and writes (no instruction fetches) from supervisor data space. All other accesses will result in the mmu_cpu_berr signal being asserted in accordance with the CPU native bus protocol.

CPU Subsystem Peripheral Registers (1x00011000 to 1x0001_FFFF): Each peripheral block will control the access types allowed. Every peripheral will allow supervisor data accesses (both read and write) and some blocks (e.g. Timers and GPIO) will also allow user data space accesses as outlined in the relevant chapters of this specification. Neither supervisor nor user instruction fetch accesses are allowed to any block as it is not possible to execute code from peripheral registers. The bus protocol is described in section 11.4.3.

PCU Mapped Registers (0x00020000 to 0x0002_BFFF): All of the PEP blocks registers which are accessed by the CPU via the PCU will inherit the access permissions of the PCU. These access permissions are hard wired to allow supervisor data accesses only and the protocol used is the same as for the CPU peripherals.

Unused address space (0x0002_C000 to 0x3FFF_FFFF and 0x40280000 to 1xFFFF_FFFF): All accesses to the unused portion of the address space will result in the mmu_cpu_berr signal being asserted in accordance with the CPU native bus protocol. These accesses will not propagate outside of the MMU i.e. no external access will be initiated.

11.6.4 Reset Exception Vector and Reference Zero Traps

When a reset occurs the LEON processor starts executing code from address 0x00000000. A common software bug is zero-referencing or null pointer de-referencing (where the program attempts to access the contents of address 0x00000000). To assist software debug the MMU will assert a bus error every time the locations 0x00000000 to 0x0000000F (i.e. the first 4 words of the reset trap) are accessed after the reset trap handler has legitimately been retrieved immediately after reset.

11.6.5 MMU Configuration Registers

The MMU configuration registers include the RDU configuration registers and two LEON registers. Note that all the MMU configuration registers may only be accessed when the CPU is running in supervisor mode.

TABLE 19
MMU Configuration Registers
Address
offset from
MMU_baseRegister#bitsResetDescription
0x00Region0Bottom[21:5]170x0_0000This register contains the physical address that
marks the bottom of region 0
0x04Region0Top[21:5]170xF_FFFFThis register contains the physical address that
marks the top of region 0. Region 0 covers the
entire address space after reset whereas all
other regions are zero-sized initially.
0x08Region1Bottom[21:5]170xF_FFFFThis register contains the physical address that
marks the bottom of region 1
0x0CRegion1Top[21:5]170x0_0000This register contains the physical address that
marks the top of region 1
0x10Region2Bottom[21:5]170xF_FFFFThis register contains the physical address that
marks the bottom of region 2
0x14Region3Top[21:5]170x0_0000This register contains the physical address that
marks the top of region 2
0x18Region3Bottom[21:5]170xF_FFFFThis register contains the physical address that
marks the bottom of region 3
0x1CRegion3Top[21:5]170x0_0000This register contains the physical address that
marks the top of region 3
0x20Region4Bottom[21:5]170xF_FFFFThis register contains the physical address that
marks the bottom of region 4
0x24Region4Top[21:5]170x0_0000This register contains the physical address that
marks the top of region 4
0x28Region5Bottom[21:5]170xF_FFFFThis register contains the physical address that
marks the bottom of region 5
0x2CRegion5Top[21:5]170x0_0000This register contains the physical address that
marks the top of region 5
0x30Region6Bottom[21:5]170xF_FFFFThis register contains the physical address that
marks the bottom of region 6
0x34Region6Top[21:5]170x0_0000This register contains the physical address that
marks the top of region 6
0x38Region7Bottom[21:5]170xF_FFFFThis register contains the physical address that
marks the bottom of region 7
0x3CRegion7Top[21:5]170x0_0000This register contains the physical address that
marks the top of region 7
0x40Region0Control60x07Control register for region 0
0x44Region1Control60x07Control register for region 1
0x48Region2Control60x07Control register for region 2
0x4CRegion3Control60x07Control register for region 3
0x50Region4Control60x07Control register for region 4
0x54Region5Control60x07Control register for region 5
0x58Region6Control60x07Control register for region 6
0x5CRegion7Control60x07Control register for region 7
0x60RegionLock80x00Writing a 1 to a bit in the RegionLock register
locks the value of the corresponding Region-
Top, RegionBottom and RegionControl registers.
The lock can only be cleared by a reset
and any attempt to write to a locked register will
result in a bus error.
0x64BusTimeout80xFFThis register should be set to the number of
pclk cycles to wait after an access has started
before aborting the access with a bus error.
Writing 0 to this register disables the bus time-
out feature.
0x68ExceptionSource60x00This register identifies the source of the last
exception. See Section 11.6.5.3 for details.
0x6CDebugSelect70x00Contains address of the register selected for
debug observation. It is expected that a number
of pseudo-registers will be made available for
debug observation and these will be outlined
during the implementation phase.
0x80 toRDU RegistersSee Table for details.
0x108
0x140LEON Configuration320x1071_8The LEON configuration register is used by
RegisterC00software to determine the configuration of this
LEON implementation. See section 11.5.1.1 for
details. This register is ReadOnly.
0x144LEON Cache320x0000_0The LEON Cache Control Register is used to
Control Register000control the operation of the caches. See section
11.6 for details.

11.6.5.1 RegionTop and RegionBottom Registers

The 20 Mbit of embedded DRAM on SoPEC is arranged as 81920 words of 256 bits each. All region boundaries need to align with a 256-bit word. Thus only 17 bits are required for the RegionNTop and RegionNBottom registers. Note that the bottom 5 bits of the RegionNTop and RegionNBottom registers cannot be written to and read as ‘0’ i.e. the RegionNTop and RegionNBottom registers represent byte-aligned DRAM addresses

Both the RegionNTop and RegionNBottom registers are inclusive i.e. the addresses in the registers are included in the region. Thus the size of a region is (RegionNTop—RegionNBottom)+1 DRAM words.

If DRAM regions overlap (there is no reason for this to be the case but there is nothing to prohibit it either) then only accesses allowed by all overlapping regions are permitted. That is if a DRAM address appears in both Region1 and Region3 (for example) the cpu_acode of an access is checked against the access permissions of both regions. If both regions permit the access then it will proceed but if either or both regions do not permit the access then it will not be allowed. The MMU does not support negatively sized regions i.e. the value of the RegionNTop register should always be greater than or equal to the value of the RegionNBottom register. If RegionNTop is lower in the address map than RegionNTop then the region is considered to be zero-sized and is ignored.

When both the RegionNTop and RegionNBottom registers for a region contain the same value the region is then simply one 256-bit word in length and this corresponds to the smallest possible active region.

11.6.5.2 Region Control Registers

Each memory region has a control register associated with it. The RegionNControl register is used to set the access conditions for the memory region bounded by the RegionNTop and RegionNBottom registers. Table 20 describes the function of each bit field in the RegionNControl registers. All bits in a RegionNControl register are both readable and writable by design. However, like all registers in the MMU, the RegionNControl registers can only be accessed by code running in supervisor mode.

TABLE 20
Region Control Register
Field Namebit(s)Description
SupervisorAccess2:0Denotes the type of access allowed when the
CPU is running in Supervisor mode. For each
access type a 1 indicates the access is permitted
and a 0 indicates the access is not permitted.
bit0 - Data read access permission
bit1 - Data write access permission
bit2 - Instruction fetch access permission
UserAccess5:3Denotes the type of access allowed when the
CPU is running in User mode. For each access
type a 1 indicates the access is permitted and a
0 indicates the access is not permitted.
bit3 - Data read access permission
bit4 - Data write access permission
bit5 - Instruction fetch access permission

11.6.5.3 ExceptionSource Register

The SPARC V8 architecture allows for a number of types of memory access error to be trapped. These trap types and trap handling in general are described in chapter 7 of the SPARC architecture manual [36]. However on the LEON processor only data_store_error and data_access_exception trap types will result from an external (to LEON) bus error. According to the SPARC architecture manual the processor will automatically move to the next register window (i.e. it decrements the current window pointer) and copies the program counters (PC and nPC) to two local registers in the new window. The supervisor bit in the PSR is also set and the PSR can be saved to another local register by the trap handler (this does not happen automatically in hardware). The ExceptionSource register aids the trap handler by identifying the source of an exception. Each bit in the ExceptionSource register is set when the relevant trap condition and should be cleared by the trap handler by writing a ‘1’ to that bit position.

TABLE 21
ExceptionSource Register
Field Namebit(s)Description
DramAccessExcptn0The permissions of an access did not match those of the DRAM
region it was attempting to access. This bit will also be set if an
attempt is made to access an undefined DRAM region (i.e. a location
that is not within the bounds of any RegionTop/RegionBottom
pair)
PeriAccessExcptn1An access violation occurred when accessing a CPU subsystem
block. This occurs when the access permissions disagree with
those set by the block.
UnusedAreaExcptn2An attempt was made to access an unused part of the memory
map
LockedWriteExcptn3An attempt was made to write to a regions registers (RegionTop/
Bottom/Control) after they had been locked.
ResetHandlerExcptn4An attempt was made to access a ROM location between
0x0000_0000 and 0x0000_000F after the reset handler was executed.
The most likely cause of such an access is the use of an
uninitialised pointer or structure.
TimeoutExcptn5A bus timeout condition occurred.

11.6.6 MMU Sub-Block Partition

As can be seen from FIG. 19 and FIG. 20 the MMU consists of three principal sub-blocks. For clarity the connections between these sub-blocks and other SoPEC blocks and between each of the sub-blocks are shown in two separate diagrams.

11.6.6.1 LEON AHB Bridge

The LEON AHB bridge consists of an AHB bridge to DIU and an AHB to CPU subsystem bus bridge. The AHB bridge will convert between the AHB and the DIU and CPU subsystem bus protocols but the address decoding and enabling of an access happens elsewhere in the MMU. The AHB bridge will always be a slave on the AHB. Note that the AMBA signals from the LEON core are contained within the ahbso and ahbsi records. The LEON records are described in more detail in section 11.7. Glue logic may be required to assist with enabling memory accesses, endianness coherency, interrupts and other miscellaneous signalling.

TABLE 22
LEON AHB bridge I/Os
Port namePinsI/ODescription
Global SoPEC signals
prst_n1InGlobal reset. Synchronous to pclk, active low.
pclk1InGlobal clock
LEON core to LEON AHB signals (ahbsi and ahbso records)
ahbsi.haddr[31:0]32InAHB address bus
ahbsi.hwdata[31:0]32InAHB write data bus
ahbso.hrdata[31:0]32OutAHB read data bus
ahbsi.hsel1InAHB slave select signal
ahbsi.hwrite1InAHB write signal:
1 - Write access
0 - Read access
ahbsi.htrans2InIndicates the type of the current transfer:
00 - IDLE
01 - BUSY
10 - NONSEQ
11 - SEQ
ahbsi.hsize3InIndicates the size of the current transfer:
000 - Byte transfer
001 - Halfword transfer
010 - Word transfer
011 - 64-bit transfer (unsupported?)
1xx - Unsupported larger wordsizes
ahbsi.hburst3InIndicates if the current transfer forms part of a
burst and the type of burst:
000 - SINGLE
001 - INCR
010 - WRAP4
011 - INCR4
100 - WRAP8
101 - INCR8
110 - WRAP16
111 - INCR16
ahbsi.hprot4InProtection control signals pertaining to the
current access:
hprot[0] - Opcode(0)/Data(1) access
hprot[1] - User(0)/Supervisor access
hprot[2] - Non-bufferable(0)/Bufferable(1)
access (unsupported)
hprot[3] - Non-cacheable(0)/Cacheable
access
ahbsi.hmaster4InIndicates the identity of the current bus master.
This will always be the LEON core.
ahbsi.hmastlock1InIndicates that the current master is performing
a locked sequence of transfers.
ahbso.hready1OutActive high ready signal indicating the access
has completed
ahbso.hresp2OutIndicates the status of the transfer:
00 - OKAY
01 - ERROR
10 - RETRY
11 - SPLIT
ahbso.hsplit[15:0]16OutThis 16-bit split bus is used by a slave to
indicate to the arbiter which bus masters should
be allowed attempt a split transaction. This
feature will be unsupported on the AHB bridge
Toplevel/Common LEON AHB bridge signals
cpu_dataout[31:0]32OutData out bus to both DRAM and peripheral
devices.
cpu_rwn1OutRead/NotWrite signal. 1 = Current access is a
read access, 0 = Current access is a write
access
icu_cpu_ilevel[3:0]4InAn interrupt is asserted by driving the
appropriate priority level on icu_cpu_ilevel.
These signals must remain asserted until the
CPU executes an interrupt acknowledge cycle.
cpu_icu_ilevel[3:0]4InIndicates the level of the interrupt the CPU is
acknowledging when cpu_iack is high
cpu_iack1OutInterrupt acknowledge signal. The exact timing
depends on the CPU core implementation
cpu_start_access1OutStart Access signal indicating the start of a data
transfer and that the cpu_adr, cpu_dataout,
cpu_rwn and cpu_acode signals are all valid.
This signal is only asserted during the first
cycle of an access.
cpu_ben[1:0]2OutByte enable signals.
dram_cpu_data[255:0]256InRead data from the DRAM.
diu_cpu_rreq1OutRead request to the DIU.
diu_cpu_rack1InAcknowledge from DIU that read request has
been accepted.
diu_cpu_rvalid1InSignal from DIU indicating that valid read data
is on the dram_cpu_data bus
cpu_diu_wdatavalid1OutSignal from the CPU to the DIU indicating that
the data currently on the cpu_diu_wdata bus is
valid and should be committed to the DIU
posted write buffer
diu_cpu_write_rdy1InSignal from the DIU indicating that the posted
write buffer is empty
cpu_diu_wdadr[21:4]18OutWrite address bus to the DIU
cpu_diu_wdata[127:0]128OutWrite data bus to the DIU
cpu_diu_wmask[15:0]16OutWrite mask for the cpu_diu_wdata bus. Each
bit corresponds to a byte of the 128-bit
cpu_diu_wdata bus.
LEON AHB bridge to MMU Control Block signals
cpu_mmu_adr32OutCPU Address Bus.
mmu_cpu_data32InData bus from the MMU
mmu_cpu_rdy1InReady signal from the MMU
cpu_mmu_acode2OutAccess code signals to the MMU
mmu_cpu_berr1InBus error signal from the MMU
dram_access_en1InDRAM access enable signal. A DRAM access
cannot be initiated unless it has been enabled
by the MMU control unit.

Description:

The LEON AHB bridge must ensure that all CPU bus transactions are functionally correct and that the timing requirements are met. The AHB bridge also implements a 128-bit DRAM write buffer to improve the efficiency of DRAM writes, particularly for multiple successive writes to DRAM. The AHB bridge is also responsible for ensuring endianness coherency i.e. guaranteeing that the correct data appears in the correct position on the data buses (hrdata, cpu_dataout and cpu_mmu_wdata) for every type of access. This is a requirement because the LEON uses big-endian addressing while the rest of SoPEC is little-endian.

The LEON AHB bridge will assert request signals to the DIU if the MMU control block deems the access to be a legal access. The validity (i.e. is the CPU running in the correct mode for the address space being accessed) of an access is determined by the contents of the relevant RegionNControl register. As the SPARC standard requires that all accesses are aligned to their word size (i.e. byte, half-word, word or double-word) and so it is not possible for an access to traverse a 256-bit boundary (as required by the DIU). Invalid DRAM accesses are not propagated to the DIU and will result in an error response (ahbso.hresp=‘01’) on the AHB. The DIU bus protocol is described in more detail in section 20.9. The DIU will return a 256-bit dataword on dram_cpu_data[255:0] for every read access.

The CPU subsystem bus protocol is described in section 11.4.3. While the LEON AHB bridge performs the protocol translation between AHB and the CPU subsystem bus the select signals for each block are generated by address decoding in the CPU subsystem bus interface. The CPU subsystem bus interface also selects the correct read data bus, ready and error signals for the block being addressed and passes these to the LEON AHB bridge which puts them on the AHB bus. It is expected that some signals (especially those external to the CPU block) will need to be registered here to meet the timing requirements. Careful thought will be required to ensure that overall CPU access times are not excessively degraded by the use of too many register stages.

11.6.6.1.1 DRAM Write Buffer

The DRAM write buffer improves the efficiency of DRAM writes by aggregating a number of CPU write accesses into a single DIU write access. This is achieved by checking to see if a CPU write is to an address already in the write buffer and if so the write is immediately acknowledged (i.e. the ahbsi.hready signal is asserted without any wait states) and the DRAM write buffer updated accordingly. When the CPU write is to a DRAM address other than that in the write buffer then the current contents of the write buffer are sent to the DIU (where they are placed in the posted write buffer) and the DRAM write buffer is updated with the address and data of the CPU write. The DRAM write buffer consists of a 128-bit data buffer, an 18-bit write address tag and a 16-bit write mask. Each bit of the write mask indicates the validity of the corresponding byte of the write buffer as shown in FIG. 21 below.

The operation of the DRAM write buffer is summarised by the following set of rules:

  • 1) The DRAM write buffer only contains DRAM write data i.e. peripheral writes go directly to the addressed peripheral.
  • 2) CPU writes to locations within the DRAM write buffer or to an empty write buffer (i.e. the write mask bits are all 0) complete with zero wait states regardless of the size of the write (byte/half-word/word/ double-word).
  • 3) The contents of the DRAM write buffer are flushed to DRAM whenever a CPU write to a location outside the write buffer occurs, whenever a CPU read from a location within the write buffer occurs or whenever a write to a peripheral register occurs.
  • 4) A flush resulting from a peripheral write will not cause any extra wait states to be inserted in the peripheral write access.
  • 5) Flushes resulting from a DRAM accesses will cause wait states to be inserted until the DIU posted write buffer is empty. If the DIU posted write buffer is empty at the time the flush is required then no wait states will be inserted for a flush resulting from a CPU write or one wait state will be inserted for a flush resulting from a CPU read (this is to ensure that the DIU sees the write request ahead of the read request). Note that in this case further wait states will also be inserted as a result of the delay in servicing the read request by the DIU.
    11.6.6.1.2 DIU Interface Waveforms

FIG. 22 below depicts the operation of the AHB bridge over a sample sequence of DRAM transactions consisting of a read into the DCache, a double-word store to an address other than that currently in the DRAM write buffer followed by an ICache line refill. To avoid clutter a number of AHB control signals that are inputs to the MMU have been grouped together as ahbsi.CONTROL and only the ahbso.HREADY is shown of the output AHB control signals.

The first transaction is a single word load (‘LD’). The MMU (specifically the MMU control block) uses the first cycle of every access (i.e. the address phase of an AHB transaction) to determine whether or not the access is a legal access. The read request to the DIU is then asserted in the following cycle (assuming the access is a valid one) and is acknowledged by the DIU a cycle later. Note that the time from cpu_diu_rreq being asserted and diu_cpu_rack being asserted is variable as it depends on the DIU configuration and access patterns of DIU requestors. The AHB bridge will insert wait states until it sees the diu_cpu_rvalid signal is high, indicating the data (‘LD1’) on the dram_cpu_data bus is valid. The AHB bridge terminates the read access in the same cycle by asserting the ahbso.HREADY signal (together with an ‘OKAY’ HRESP code). The AHB bridge also selects the appropriate 32 bits (‘RD1’) from the 256-bit DRAM line data (‘LD1’) returned by the DIU corresponding to the word address given by A1.

The second transaction is an AHB two-beat incrementing burst issued by the LEON acache block in response to the execution of a double-word store instruction. As LEON is a big endian processor the address issued (‘A2’) during the address phase of the first beat of this transaction is the address of the most significant word of the double-word while the address for the second beat (‘A3’) is that of the least significant word i.e. A3=A2+4. The presence of the DRAM write buffer allows these writes to complete without the insertion of any wait states. This is true even when, as shown here, the DRAM write buffer needs to be flushed into the DIU posted write buffer, provided the DIU posted write buffer is empty. If the DIU posted write buffer is not empty (as would be signified by diu_cpu_write_rdy being low) then wait states would be inserted until it became empty. The cpu_diu_wdata buffer builds up the data to be written to the DIU over a number of transactions (‘BD1’ and ‘BD2’ here) while the cpu_dui_wmask records every byte that has been written to since the last flush—in this case the lowest word and then the second lowest word are written to as a result of the double-word store operation.

The final transaction shown here is a DRAM read caused by an ICache miss. Note that the pipelined nature of the AHB bus allows the address phase of this transaction to overlap with the final data phase of the previous transaction. All ICache misses appear as single word loads (‘LD’) on the AHB bus. In this case we can see that the DIU is slower to respond to this read request than to the first read request because it is processing the write access caused by the DRAM write buffer flush. The ICache refill will complete just after the window shown in FIG. 22.

11.6.6.2 CPU Subsystem Bus Interface

The CPU Subsystem Interface block handles all valid accesses to the peripheral blocks that comprise the CPU Subsystem.

TABLE 23
CPU Subsystem Bus Interface I/Os
Port namePinsI/ODescription
Global SoPEC signals
prst_n1InGlobal reset. Synchronous to pclk, active low.
pclk1InGlobal clock
Toplevel/Common CPU Subsystem Bus Interface signals
cpu_cpr_sel1OutCPR block select.
cpu_gpio_sel1OutGPIO block select.
cpu_icu_sel1OutICU block select.
cpu_lss_sel1OutLSS block select.
cpu_pcu_sel1OutPCU block select.
cpu_scb_sel1OutSCB block select.
cpu_tim_sel1OutTimers block select.
cpu_rom_sel1OutROM block select.
cpu_pss_sel1OutPSS block select.
cpu_diu_sel1OutDIU block select.
cpr_cpu_data[31:0]32InRead data bus from the CPR block
gpio_cpu_data[31:0]32InRead data bus from the GPIO block
icu_cpu_data[31:0]32InRead data bus from the ICU block
lss_cpu_data[31:0]32InRead data bus from the LSS block
pcu_cpu_data[31:0]32InRead data bus from the PCU block
scb_cpu_data[31:0]32InRead data bus from the SCB block
tim_cpu_data[31:0]32InRead data bus from the Timers block
rom_cpu_data[31:0]32InRead data bus from the ROM block
pss_cpu_data[31:0]32InRead data bus from the PSS block
diu_cpu_data[31:0]32InRead data bus from the DIU block
cpr_cpu_rdy1InReady signal to the CPU. When cpr_cpu_rdy is
high it indicates the last cycle of the access. For a
write cycle this means cpu_dataout has been
registered by the CPR block and for a read cycle
this means the data on cpr_cpu_data is valid.
gpio_cpu_rdy1InGPIO ready signal to the CPU.
icu_cpu_rdy1InICU ready signal to the CPU.
lss_cpu_rdy1InLSS ready signal to the CPU.
pcu_cpu_rdy1InPCU ready signal to the CPU.
scb_cpu_rdy1InSCB ready signal to the CPU.
tim_cpu_rdy1InTimers block ready signal to the CPU.
rom_cpu_rdy1InROM block ready signal to the CPU.
pss_cpu_rdy1InPSS block ready signal to the CPU.
diu_cpu_rdy1InDIU register block ready signal to the CPU.
cpr_cpu_berr1InBus Error signal from the CPR block
gpio_cpu_berr1InBus Error signal from the GPIO block
icu_cpu_berr1InBus Error signal from the ICU block
lss_cpu_berr1InBus Error signal from the LSS block
pcu_cpu_berr1InBus Error signal from the PCU block
scb_cpu_berr1InBus Error signal from the SCB block
tim_cpu_berr1InBus Error signal from the Timers block
rom_cpu_berr1InBus Error signal from the ROM block
pss_cpu_berr1InBus Error signal from the PSS block
diu_cpu_berr1InBus Error signal from the DIU block
CPU Subsystem Bus Interface to MMU Control Block signals
cpu_adr[19:12]8InToplevel CPU Address bus. Only bits 19-12 are
required to decode the peripherals address space
peri_access_en1InEnable Access signal. A peripheral access cannot
be initiated unless it has been enabled by the MMU
Control Unit
peri_mmu_data[31:0]32OutData bus from the selected peripheral
peri_mmu_rdy1OutData Ready signal. Indicates the data on the
peri_mmu_data bus is valid for a read cycle or that
the data was successfully written to the peripheral
for a write cycle.
peri_mmu_berr1OutBus Error signal. Indicates a bus error has occurred
in accessing the selected peripheral
CPU Subsystem Bus Interface to LEON AHB bridge signals
cpu_start_access1InStart Access signal from the LEON AHB bridge
indicating the start of a data transfer and that the
cpu_adr, cpu_dataout, cpu_rwn and cpu_acode
signals are all valid. This signal is only asserted
during the first cycle of an access.

Description:

The CPU Subsystem Bus Interface block performs simple address decoding to select a peripheral and multiplexing of the returned signals from the various peripheral blocks. The base addresses used for the decode operation are defined in Table. Note that access to the MMU configuration registers are handled by the MMU Control Block rather than the CPU Subsystem Bus Interface block. The CPU Subsystem Bus Interface block operation is described by the following pseudocode:

masked_cpu_adr = cpu_adr[17:12]
case (masked_cpu_adr)
when TIM_base[17:12]
cpu_tim_sel = peri_access_en // The peri_access_en
signal will have the
peri_mmu_data = tim_cpu_data // timing required for
block selects
peri_mmu_rdy = tim_cpu_rdy
peri_mmu_berr = tim_cpu_berr
all_other_selects = 0 // Shorthand to ensure other
cpu_block_sel signals
// remain deasserted
when LSS_base[17:12]
cpu_lss_sel = peri_access_en
peri_mmu_data = lss_cpu_data
peri_mmu_rdy = lss_cpu_rdy
peri_mmu_berr = lss_cpu_berr
all_other_selects = 0
when GPIO_base[17:12]
cpu_gpio_sel = peri_access_en
peri_mmu_data = gpio_cpu_data
peri_mmu_rdy = gpio_cpu_rdy
peri_mmu_berr = gpio_cpu_berr
all_other_selects = 0
when SCB_base[17:12]
cpu_scb_sel = peri_access_en
peri_mmu_data = scb_cpu_data
peri_mmu_rdy = scb_cpu_rdy
peri_mmu_berr = scb_cpu_berr
all_other_selects = 0
when ICU_base[17:12]
cpu_icu_sel = peri_access_en
peri_mmu_data = icu_cpu_data
peri_mmu_rdy = icu_cpu_rdy
peri_mmu_berr = icu_cpu_berr
all_other_selects = 0
when CPR_base[17:12]
cpu_cpr_sel = peri_access_en
peri_mmu_data = cpr_cpu_data
peri_mmu_rdy = cpr_cpu_rdy
peri_mmu_berr = cpr_cpu_berr
all_other_selects = 0
when ROM_base[17:12]
cpu_rom_sel = peri_access_en
peri_mmu_data = rom_cpu_data
peri_mmu_rdy = rom_cpu_rdy
peri_mmu_berr = rom_cpu_berr
all_other_selects = 0
when PSS_base[17:12]
cpu_pss_sel = peri_access_en
peri_mmu_data = pss_cpu_data
peri_mmu_rdy = pss_cpu_rdy
peri_mmu_berr = pss_cpu_berr
all_other_selects = 0
when DIU_base[17:12]
cpu_diu_sel = peri_access_en
peri_mmu_data = diu_cpu_data
peri_mmu_rdy = diu_cpu_rdy
peri_mmu_berr = diu_cpu_berr
all_other_selects = 0
when PCU_base[17:12]
cpu_pcu_sel = peri_access_en
peri_mmu_data = pcu_cpu_data
peri_mmu_rdy = pcu_cpu_rdy
peri_mmu_berr = pcu_cpu_berr
all_other_selects = 0
when others
all_block_selects = 0
peri_mmu_data = 0x00000000
peri_mmu_rdy = 0
peri_mmu_berr = 1
end case

11.6.6.3 MMU Control Block

The MMU Control Block determines whether every CPU access is a valid access. No more than one cycle is to be consumed in determining the validity of an access and all accesses must terminate with the assertion of either mmu_cpu_rdy or mmu_cpu_berr. To safeguard against stalling the CPU a simple bus timeout mechanism will be supported.

TABLE 24
MMU Control Block I/Os
Port namePinsI/ODescription
Global SoPEC signals
prst_n1InGlobal reset. Synchronous to pclk, active low.
pclk1InGlobal clock
Toplevel/Common MMU Control Block signals
cpu_adr[21:2]22OutAddress bus for both DRAM and peripheral access.
cpu_acode[1:0]2OutCPU access code signals (cpu_mmu_acode) retimed
to meet the CPU Subsystem Bus timing requirements
dram_access_en1OutDRAM Access Enable signal. Indicates that the
current CPU access is a valid DRAM access.
MMU Control Block to LEON AHB bridge signals
cpu_mmu_adr[31:0]32InCPU core address bus.
cpu_dataout[31:0]32InToplevel CPU data bus
mmu_cpu_data[31:0]32OutData bus to the CPU core. Carries the data for all
CPU read operations
cpu_rwn1InToplevel CPU Read/notWrite signal.
cpu_mmu_acode[1:0]2InCPU access code signals
mmu_cpu_rdy1OutReady signal to the CPU core. Indicates the
completion of all valid CPU accesses.
mmu_cpu_berr1OutBus Error signal to the CPU core. This signal is
asserted to terminate an invalid access.
cpu_start_access1InStart Access signal from the LEON AHB bridge
indicating the start of a data transfer and that the
cpu_adr, cpu_dataout, cpu_rwn and cpu_acode
signals are all valid. This signal is only asserted
during the first cycle of an access.
cpu_iack1InInterrupt Acknowledge signal from the CPU. This
signal is only asserted during an interrupt
acknowledge cycle.
cpu_ben[1:0]2InByte enable signals indicating which bytes of the 32-
bit bus are being accessed.
MMU Control Block to CPU Subsystem Bus Interface signals
cpu_adr[17:12]8OutToplevel CPU Address bus. Only bits 17-12 are
required to decode the peripherals address space
peri_access_en1OutEnable Access signal. A peripheral access cannot be
initiated unless it has been enabled by the MMU
Control Unit
peri_mmu_data[31:0]32InData bus from the selected peripheral
peri_mmu_rdy1InData Ready signal. Indicates the data on the
peri_mmu_data bus is valid for a read cycle or that
the data was successfully written to the peripheral for
a write cycle.
peri_mmu_berr1InBus Error signal. Indicates a bus error has occurred in
accessing the selected peripheral

Description:

The MMU Control Block is responsible for the MMU's core functionality, namely determining whether or not an access to any part of the address map is valid. An access is considered valid if it is to a mapped area of the address space and if the CPU is running in the appropriate mode for that address space. Furthermore the MMU control block must correctly handle the special cases that are: an interrupt acknowledge cycle, a reset exception vector fetch, an access that crosses a 256-bit DRAM word boundary and a bus timeout condition. The following pseudocode shows the logic required to implement the MMU Control Block functionality. It does not deal with the timing relationships of the various signals—it is the designer's responsibility to ensure that these relationships are correct and comply with the different bus protocols. For simplicity the pseudocode is split up into numbered sections so that the functionality may be seen more easily.

It is important to note that the style used for the pseudocode will differ from the actual coding style used in the RTL implementation. The pseudocode is only intended to capture the required functionality, to clearly show the criteria that need to be tested rather than to describe how the implementation should be performed. In particular the different comparisons of the address used to determine which part of the memory map, which DRAM region (if applicable) and the permission checking should all be performed in parallel (with results ORed together where appropriate) rather than sequentially as the pseudocode implies.

PS0 Description: This first segment of code defines a number of constants and variables that are used elsewhere in this description. Most signals have been defined in the I/O descriptions of the MMU sub-blocks that precede this section of the document. The post_reset_state variable is used later (in section PS4) to determine if we should trap a null pointer access.

PS0:
const UnusedBottom = 0x002AC000
const DRAMTop = 0x4027FFFF
const UserDataSpace = b01
const UserProgramSpace = b00
const SupervisorDataSpace = b11
const SupervisorProgramSpace = b10
const ResetExceptionCycles = 0x2
cpu_adr_peri_masked[5:0] = cpu_mmu_adr[17:12]
cpu_adr_dram_masked[16:0] = cpu_mmu_adr & 0x003FFFE0
if (prst_n == 0) then // Initialise everything
cpu_adr = cpu_mmu_adr[21:2]
peri_access_en = 0
dram_access_en = 0
mmu_cpu_data = peri_mmu_data
mmu_cpu_rdy = 0
mmu_cpu_berr = 0
post_reset_state = TRUE
access_initiated = FALSE
cpu_access_cnt = 0
// The following is used to determine if we are coming out
of reset for the purposes of
// reset exception vector redirection. There may be a
convenient signal in the CPU core
// that we could use instead of this.
if ((cpu_start_access == 1) AND (cpu_access_cnt <
ResetExceptionCycles) AND
(clock_tick == TRUE)) then
cpu_access_cnt = cpu_access_cnt +1
else
post_reset_state = FALSE

PS1 Description: This section is at the top of the hierarchy that determines the validity of an access. The address is tested to see which macro-region (i.e. Unused, CPU Subsystem or DRAM) it falls into or whether the reset exception vector is being accessed.

PS1:
if (cpu_mmu_adr >= UnusedBottom) then
// The access is to an invalid area of the address
space. See section PS2
elsif ((cpu_mmu_adr  > DRAMTop)  AND  (cpu_mmu_adr  <
UnusedBottom)) then
// We are in the CPU Subsystem/PEP Subsystem address
space. See section PS3
// Only remaining possibility is an access to DRAM address
space
// First we need to intercept the special case for the
reset exception vector
elsif (cpu_mmu_adr < 0x00000010) then
// The reset exception is being accessed. See section PS4
elsif ((cpu_adr_dram_masked >= Region0Bottom) AND
(cpu_adr_dram_masked <=
Region0Top) ) then
// We are in Region0. See section PS5
elsif ((cpu_adr_dram_masked >= RegionNBottom) AND
(cpu_adr_dram_masked <=
RegionNTop) ) then // we are in RegionN
// Repeat the Region0 (i.e. section PS5) logic for
each of Region1 to Region7
else // We could end up here if there were gaps in the
DRAM regions
peri_access_en = 0
dram_access_en = 0
mmu_cpu_berr = 1 // we have an unknown access error,
most likely due to hitting
mmu_cpu_rdy = 0 // a gap in the DRAM regions
// Only thing remaining is to implement a bus timeout
function. This is done in PS6
end

PS2 Description: Accesses to the large unused area of the address space are trapped by this section. No bus transactions are initiated and the mmu_cpu_berr signal is asserted.

PS2:
elsif (cpu_mmu_adr >= UnusedBottom) then
peri_access_en = 0 // The access is to an invalid area
of the address space
dram_access_en = 0
mmu_cpu_berr = 1
mmu_cpu_rdy = 0

PS3 Description: This section deals with accesses to CPU Subsystem peripherals, including the MMU itself. If the MMU registers are being accessed then no external bus transactions are required. Access to the MMU registers is only permitted if the CPU is making a data access from supervisor mode, otherwise a bus error is asserted and the access terminated. For non-MMU accesses then transactions occur over the CPU Subsystem Bus and each peripheral is responsible for determining whether or not the CPU is in the correct mode (based on the cpu_acode signals) to be permitted access to its registers. Note that all of the PEP registers are accessed via the PCU which is on the CPU Subsystem Bus.

PS3:
elsif  ((cpu_mmu_adr  > DRAMTop)  AND  (cpu_mmu_adr  <
UnusedBottom)) then
// We are in the CPU Subsystem/PEP Subsystem address
space
cpu_adr = cpu_mmu_adr[21:2]
if (cpu_adr_peri_masked == MMU_base) then  // access is
to local registers
peri_access_en = 0
dram_access_en = 0
if (cpu_acode == SupervisorDataSpace) then
for (i=0; i<26; i++) {
if ((i == cpu_mmu_adr[6:2]) then  // selects the
addressed register
if (cpu_rwn == 1) then
mmu_cpu_data[16:0] = MMUReg[i] // MMUReg[i]
is one of the
mmu_cpu_rdy = 1 // registers
in Table
mmu_cpu_berr = 0
else // write cycle
MMUReg[i] = cpu_dataout[16:0]
mmu_cpu_rdy = 1
mmu_cpu_berr = 0
else // there is no register mapped to this
address
mmu_cpu_berr = 1  // do we really want a
bus_error here as registers
mmu_cpu_rdy = 0  // are just mirrored in other
blocks
else // we have an access violation
mmu_cpu_berr = 1
mmu_cpu_rdy = 0
else // access is to something else on the CPU Subsystem
Bus
peri_access_en = 1
dram_access_en = 0
mmu_cpu_data = peri_mmu_data
mmu_cpu_rdy = peri_mmu_rdy
mmu_cpu_berr = peri_mmu_berr

PS4 Description: The only correct accesses to the locations beneath 0x00000010 are fetches of the reset trap handling routine and these should be the first accesses after reset. Here we trap all other accesses to these locations regardless of the CPU mode. The most likely cause of such an access will be the use of a null pointer in the program executing on the CPU.

PS4:
elsif (cpu_mmu_adr < 0x00000010) then
if (post_reset_state == TRUE)) then
cpu adr = cpu mmu adr[21:2]
peri_access_en = 1
dram_access_en = 0
mmu_cpu_data = peri_mmu_data
mmu_cpu_rdy = peri_mmu_rdy
mmu_cpu_berr = peri_mmu_berr
else // we have a problem (almost certainly a null
pointer)
peri_access_en = 0
dram_access_en = 0
mmu_cpu_berr = 1
mmu_cpu_rdy = 0

PS5 Description: This large section of pseudocode simply checks whether the access is within the bounds of DRAM Region0 and if so whether or not the access is of a type permitted by the Region0Control register. If the access is permitted then a DRAM access is initiated. If the access is not of a type permitted by the Region0Control register then the access is terminated with a bus error.

PS5:
elsif ((cpu_adr_dram_masked >= Region0Bottom) AND
(cpu_adr_dram_masked <=
Region0Top) ) then // we are in Region0
cpu_adr = cpu_mmu_adr[21:2]
if (cpu_rwn == 1) then
if ((cpu_acode == SupervisorProgramSpace AND
Region0Control[2] == 1))
OR (cpu_acode == UserProgramSpace AND
Region0Control[5] == 1)) then
// this is a valid instruction
fetch from Region0
// The dram_cpu_data bus goes
directly to the LEON
// AHB bridge which also handles
the hready generation
peri_access_en = 0
dram_access_en = 1
mmu_cpu_berr = 0
elsif ((cpu_acode == SupervisorDataSpace AND
Region0Control[0] == 1)
OR (cpu_acode == UserDataSpace AND
Region0Control[3] == 1)) then
// this is a valid
read access from Region0
peri_access_en = 0
dram_access_en = 1
mmu_cpu_berr = 0
else // we have an access
violation
peri_access_en = 0
dram_access_en = 0
mmu_cpu_berr = 1
mmu_cpu_rdy = 0
else // it is a write access
if ((cpu_acode == SupervisorDataSpace AND
Region0Control[1] == 1)
OR (cpu_acode == UserDataSpace AND
Region0Control[4] == 1)) then
// this is a valid
write access to Region0
peri_access_en = 0
dram_access_en = 1
mmu_cpu_berr = 0
else // we have an access
violation
peri_access_en = 0
dram_access_en = 0
mmu_cpu_berr = 1
mmu_cpu_rdy = 0

PS6 Description: This final section of pseudocode deals with the special case of a bus timeout. This occurs when an access has been initiated but has not completed before the BusTimeout number of pclk cycles. While access to both DRAM and CPU/PEP Subsystem registers will take a variable number of cycles (due to DRAM traffic, PCU command execution or the different timing required to access registers in imported IP) each access should complete before a timeout occurs. Therefore it should not be possible to stall the CPU by locking either the CPU Subsystem or DIU buses. However given the fatal effect such a stall would have it is considered prudent to implement bus timeout detection.

PS6:
// Only thing remaining is to implement a bus timeout
function.
if ((cpu_start_access == 1) then
access_initiated = TRUE
timeout_countdown = BusTimeout
if ((mmu_cpu_rdy == 1 ) OR (mmu_cpu_berr ==1 )) then
access_initiated = FALSE
peri_access_en = 0
dram_access_en = 0
if ((clock_tick == TRUE) AND (access_initiated == TRUE) AND
(BusTimeout != 0))
if (timeout_countdown > 0) then
timeout_countdown−−
else // timeout has occurred
peri_access_en = 0 // abort the access
dram_access_en = 0
mmu_cpu_berr = 1
mmu_cpu_rdy = 0

11.7 LEON Caches

The version of LEON implemented on SoPEC features 1 kB of ICache and 1 kB of DCache. Both caches are direct mapped and feature 8 word lines so their data RAMs are arranged as 32×256-bit and their tag RAMs as 32×30-bit (itag) or 32×32-bit (dtag). Like most of the rest of the LEON code used on SoPEC the cache controllers are taken from the leon2-1.0.7 release. The LEON cache controllers and cache RAMs have been modified to ensure that an entire 256-bit line is refilled at a time to make maximum use out of the memory bandwidth offered by the embedded DRAM organization (DRAM lines are also 256-bit). The data cache controller has also been modified to ensure that user mode code cannot access the DCache contents unless it is authorised to do so. A block diagram of the LEON CPU core as implemented on SoPEC is shown in FIG. 23 below.

In this diagram dotted lines are used to indicate hierarchy and red items represent signals or wrappers added as part of the SoPEC modifications. LEON makes heavy use of VHDL records and the records used in the CPU core are described in Table 25. Unless otherwise stated the records are defined in the iface.vhd file (part of the LEON release) and this should be consulted for a complete breakdown of the record elements.

TABLE 25
Relevant LEON records
Record NameDescription
rfiRegister File Input record. Contains address, datain and control signals for the
register file.
rfoRegister File Output record. Contains the data out of the dual read port register
file.
iciInstruction Cache In record. Contains program counters from different stages
of the pipeline and various control signals
icoInstruction Cache Out record. Contains the fetched instruction data and
various control signals. This record is also sent to the DCache (i.e. icol) so that
diagnostic accesses (e.g. lda/sta) can be serviced.
dciData Cache In record. Contains address and data buses from different stages
of the pipeline (execute & memory) and various control signals
dcoData Cache Out record. Contains the data retrieved from either memory or the
caches and various control signals. This record is also sent to the ICache (i.e.
dcol) so that diagnostic accesses (e.g. lda/sta) can be serviced.
iuiInteger Unit In record. This record contains the interrupt request level and a
record for use with LEONs Debug Support Unit (DSU)
iuoInteger Unit Out record. This record contains the acknowledged interrupt
request level with control signals and a record for use with LEONs Debug
Support Unit (DSU)
mciiMemory to Cache Icache In record. Contains the address of an Icache miss
and various control signals
mcioMemory to Cache Icache Out record. Contains the returned data from memory
and various control signals
mcdiMemory to Cache Dcache In record. Contains the address and data of a
Dcache miss or write and various control signals
mcdoMemory to Cache Dcache Out record. Contains the returned data from
memory and various control signals
ahbiAHB In record. This is the input record for an AHB master and contains the
data bus and AHB control signals. The destination for the signals in this record
is the AHB controller. This record is defined in the amba.vhd file
ahboAHB Out record. This is the output record for an AHB master and contains the
address and data buses and AHB control signals. The AHB controller drives
the signals in this record. This record is defined in the amba.vhd file
ahbsiAHB Slave In record. This is the input record for an AHB slave and contains
the address and data buses and AHB control signals. It is used by the DCache
to facilitate cache snooping (this feature is not enabled in SoPEC). This record
is defined in the amba.vhd file
cramiCache RAM In record. This record is composed of records of records which
contain the address, data and tag entries with associated control signals for
both the ICache RAM and DCache RAM
cramoCache RAM Out record. This record is composed of records of records which
contain the data and tag entries with associated control signals for both the
ICache RAM and DCache RAM
iline_rdyControl signal from the ICache controller to the instruction cache memory. This
signal is active (high) when a full 256-bit line (on dram_cpu_data) is to be
written to cache memory.
dline_rdyControl signal from the DCache controller to the data cache memory. This
signal is active (high) when a full 256-bit line (on dram_cpu_data) is to be
written to cache memory.
dram_cpu_data256-bit data bus from the embedded DRAM

11.7.1 Cache Controllers

The LEON cache module consists of three components: the ICache controller (icache.vhd), the DCache controller (dcache.vhd) and the AHB bridge (acache.vhd) which translates all cache misses into memory requests on the AHB bus.

In order to enable full line refill operation a few changes had to be made to the cache controllers. The ICache controller was modified to ensure that whenever a location in the cache was updated (i.e. the cache was enabled and was being refilled from DRAM) all locations on that cache line had their valid bits set to reflect the fact that the full line was updated. The iline_rdy signal is asserted by the ICache controller when this happens and this informs the cache wrappers to update all locations in the idata RAM for that line.

A similar change was made to the DCache controller except that the entire line was only updated following a read miss and that existing write through operation was preserved. The DCache controller uses the dline_rdy signal to instruct the cache wrapper to update all locations in the ddata RAM for a line. An additional modification was also made to ensure that a double-word load instruction from a non-cached location would only result in one read access to the DIU i.e. the second read would be serviced by the data cache. Note that if the DCache is turned off then a double-word load instruction will cause two DIU read accesses to occur even though they will both be to the same 256-bit DRAM line.

The DCache controller was further modified to ensure that user mode code cannot access cached data to which it does not have permission (as determined by the relevant RegionNControl register settings at the time the cache line was loaded). This required an extra 2 bits of tag information to record the user read and write permissions for each cache line. These user access permissions can be updated in the same manner as the other tag fields (i.e. address and valid bits) namely by line refill, STA instruction or cache flush. The user access permission bits are checked every time user code attempts to access the data cache and if the permissions of the access do not agree with the permissions returned from the tag RAM then a cache miss occurs. As the MMU evaluates the access permissions for every cache miss it will generate the appropriate exception for the forced cache miss caused by the errant user code. In the case of a prohibited read access the trap will be immediate while a prohibited write access will result in a deferred trap. The deferred trap results from the fact that the prohibited write is committed to a write buffer in the DCache controller and program execution continues until the prohibited write is detected by the MMU which may be several cycles later. Because the errant write was treated as a write miss by the DCache controller (as it did not match the stored user access permissions) the cache contents were not updated and so remain coherent with the DRAM contents (which do not get updated because the MMU intercepted the prohibited write). Supervisor mode code is not subject to such checks and so has free access to the contents of the data cache.

In addition to AHB bridging, the ACache component also performs arbitration between ICache and DCache misses when simultaneous misses occur (the DCache always wins) and implements the Cache Control Register (CCR). The leon2-1.0.7 release is inconsistent in how it handles cacheability: For instruction fetches the cacheability (i.e. is the access to an area of memory that is cacheable) is determined by the ICache controller while the ACache determines whether or not a data access is cacheable. To further complicate matters the DCache controller does determine if an access resulting from a cache snoop by another AHB master is cacheable (Note that the SoPEC ASIC does not implement cache snooping as it has no need to do so). This inconsistency has been cleaned up in more recent LEON releases but is preserved here to minimise the number of changes to the LEON RTL. The cache controllers were modified to ensure that only DRAM accesses (as defined by the SoPEC memory map) are cached.

The only functionality removed as a result of the modifications was support for burst fills of the ICache. When enabled burst fills would refill an ICache line from the location where a miss occurred up to the end of the line. As the entire line is now refilled at once (when executing from DRAM) this functionality is no longer required. Furthermore more substantial modifications to the ICache controller would be needed if we wished to preserve this function without adversely affecting full line refills. The CCR was therefore modified to ensure that the instruction burst fetch bit (bit16) was tied low and could not be written to.

11.7.1.1 LEON Cache Control Register

The CCR controls the operation of both the I and D caches. Note that the bitfields used on the SoPEC implementation of this register are based on the LEON v1.0.7 implementation and some bits have their values tied off. See section 4 of the LEON manual for a description of the LEON cache controllers.

TABLE 26
LEON Cache Control Register
Field Namebit(s)Description
ICS1:0Instruction cache state:
00 - disabled
01 - frozen
10 - disabled
11 - enabled
Reserved13:6 Reserved. Reads as 0.
DCS3:2Data cache state:
00 - disabled
01 - frozen
10 - disabled
11 - enabled
IF4ICache freeze on interrupt
0 - Do not freeze the ICache contents on taking an interrupt
1 - Freeze the ICache contents on taking an interrupt
DF5DCache freeze on interrupt
0 - Do not freeze the DCache contents on taking an interrupt
1 - Freeze the DCache contents on taking an interrupt
Reserved13:6 Reserved. Reads as 0.
DP14Data cache flush pending.
0 - No DCache flush in progress
1 - DCache flush in progress
This bit is ReadOnly.
IP15Instruction cache flush pending.
0 - No ICache flush in progress
1 - ICache flush in progress
This bit is ReadOnly.
IB16Instruction burst fetch enable. This bit is tied low on SoPEC because it
would interfere with the operation of the cache wrappers. Burst refill
functionality is automatically provided in SoPEC by the cache
wrappers.
Reserved20:17Reserved. Reads as 0.
FI21Flush instruction cache. Writing a 1 this bit will flush the ICache. Reads
as 0.
FD22Flush data cache. Writing a 1 this bit will flush the DCache. Reads as
0.
DS23Data cache snoop enable. This bit is tied low in SoPEC as there is no
requirement to snoop the data cache.
Reserved31:24Reserved. Reads as 0.

11.7.2 Cache Wrappers

The cache RAMs used in the leon2-1.0.7 release needed to be modified to support full line refills and the correct IBM macros also needed to be instantiated. Although they are described as RAMs throughout this document (for consistency), register arrays are actually used to implement the cache RAMs. This is because IBM SRAMs were not available in suitable configurations (offered configurations were too big) to implement either the tag or data cache RAMs. Both instruction and data tag RAMs are implemented using dual port (1 Read & 1 Write) register arrays and the clocked write-through versions of the register arrays were used as they most closely approximate the single port SRAM LEON expects to see.

11.7.2.1 Cache Tag RAM Wrappers

The itag and dtag RAMs differ only in their width—the itag is a 32×30 array while the dtag is a 32×32 array with the extra 2 bits being used to record the user access permissions for each line. When read using a LDA instruction both tags return 32-bit words. The tag fields are described in Table 27 and Table 28 below. Using the IBM naming conventions the register arrays used for the tag RAMs are called RA032X30D2P2W1R1M3 for the itag and RA032X32D2P2W1R1M3 for the dtag. The ibm_syncram wrapper used for the tag RAMs is a simple affair that just maps the wrapper ports on to the appropriate ports of the IBM register array and ensures the output data has the correct timing by registering it. The tag RAMs do not require any special modifications to handle full line refills.

TABLE 27
LEON Instruction Cache Tag
Field Namebit(s)Description
Valid7:0Each valid bit indicates whether or not the
corresponding word of the cache line contains
valid data
Reserved9:8Reserved - these bits do not exist in the itag RAM.
Reads as 0.
Address31:10The tag address of the cache line

TABLE 28
LEON Data Cache Tag
Field
Namebit(s)Description
Valid7:0Each valid bit indicates whether or not the corresponding
word of the cache line contains valid data
URP8User read permission.
0 - User mode reads will force a refill of this line
1 - User mode code can read from this cache line.
UWP9User write permission.
0 - User mode writes will not be written to the cache
1 - User mode code can write to this cache line.
Address31:10The tag address of the cache line

11.7.2.2 Cache Data RAM Wrappers

The cache data RAM contains the actual cached data and nothing else. Both the instruction and data cache data RAMs are implemented using 8 32×32-bit register arrays and some additional logic to support full line refills. Using the IBM naming conventions the register arrays used for the tag RAMs are called RA032X32D2P2W1R1M3. The ibm_cdram_wrap wrapper used for the tag RAMs is shown in FIG. 24 below.

To the cache controllers the cache data RAM wrapper looks like a 256×32 single port SRAM (which is what they expect to see) with an input to indicate when a full line refill is taking place (the line_rdy signal). Internally the 8-bit address bus is split into a 5-bit lineaddress, which selects one of the 32 256-bit cache lines, and a 3-bit wordaddress which selects one of the 8 32-bit words on the cache line. Thus each of the 8 32×32 register arrays contains one 32-bit word of each cache line. When a full line is being refilled (indicated by both the line rdy and write signals being high) every register array is written to with the appropriate 32 bits from the linedatain bus which contains the 256-bit line returned by the DIU after a cache miss. When just one word of the cache line is to be written (indicated by the write signal being high while the line_rdy is low) then the wordaddress is used to enable the write signal to the selected register array only—all other write enable signals are kept low. The data cache controller handles byte and half-word write by means of a read-modify-write operation so writes to the cache data RAM are always 32-bit.

The wordaddress is also used to select the correct 32-bit word from the cache line to return to the LEON integer unit.

11.8 Realtime Debug Unit (RDU)

The RDU facilitates the observation of the contents of most of the CPU addressable registers in the SoPEC device in addition to some pseudo-registers in realtime. The contents of pseudo-registers, i.e. registers that are collections of otherwise unobservable signals and that do not affect the functionality of a circuit, are defined in each block as required. Many blocks do not have pseudo-registers and some blocks (e.g. ROM, PSS) do not make debug information available to the RDU as it would be of little value in realtime debug.

Each block that supports realtime debug observation features a DebugSelect register that controls a local mux to determine which register is output on the block's data bus (i.e. block_cpu_data). One small drawback with reusing the blocks data bus is that the debug data cannot be present on the same bus during a CPU read from the block. An accompanying active high block_cpu_debug_valid signal is used to indicate when the data bus contains valid debug data and when the bus is being used by the CPU. There is no arbitration for the bus as the CPU will always have access when required. A block diagram of the RDU is shown in FIG. 25.

TABLE 29
RDU I/Os
Port namePinsI/ODescription
diu_cpu_data32InRead data bus from the DIU block
cpr_cpu_data32InRead data bus from the CPR block
gpio_cpu_data32InRead data bus from the GPIO block
icu_cpu_data32InRead data bus from the ICU block
lss_cpu_data32InRead data bus from the LSS block
pcu_cpu_debug_data32InRead data bus from the PCU block
scb_cpu_data32InRead data bus from the SCB block
tim_cpu_data32InRead data bus from the TIM block
diu_cpu_debug_valid1InSignal indicating the data on the diu_cpu_data bus is
valid debug data.
tim_cpu_debug_valid1InSignal indicating the data on the tim_cpu_data bus is
valid debug data.
scb_cpu_debug_valid1InSignal indicating the data on the scb_cpu_data bus is
valid debug data.
pcu_cpu_debug_valid1InSignal indicating the data on the pcu_cpu_data bus is
valid debug data.
lss_cpu_debug_valid1InSignal indicating the data on the lss_cpu_data bus is
valid debug data.
icu_cpu_debug_valid1InSignal indicating the data on the icu_cpu_data bus is
valid debug data.
gpio_cpu_debug_valid1InSignal indicating the data on the gpio_cpu_data bus is
valid debug data.
cpr_cpu_debug_valid1InSignal indicating the data on the cpr_cpu_data bus is
valid debug data.
debug_data_out32OutOutput debug data to be muxed on to the
PHI/GPIO/other pins
debug_data_valid1OutDebug valid signal indicating the validity of the data on
debug_data_out. This signal is used in all debug
configurations
debug_cntrl33OutControl signal for each debug data line indicating
whether or not the debug data should be selected by
the pin mux

As there are no spare pins that can be used to output the debug data to an external capture device some of the existing I/Os will have a debug multiplexer placed in front of them to allow them be used as debug pins. Furthermore not every pin that has a debug mux will always be available to carry the debug data as they may be engaged in their primary purpose e.g. as a GPIO pin. The RDU therefore outputs a debug_cntrl signal with each debug data bit to indicate whether the mux associated with each debug pin should select the debug data or the normal data for the pin. The DebugPinSel1 and DebugPinSel2 registers are used to determine which of the 33 potential debug pins are enabled for debug at any particular time.

As it may not always be possible to output a full 32-bit debug word every cycle the RDU supports the outputting of an n-bit sub-word every cycle to the enabled debug pins. Each debug test would then need to be re-run a number of times with a different portion of the debug word being output on the n-bit sub-word each time. The data from each run should then be correlated to create a full 32-bit (or whatever size is needed) debug word for every cycle. The debug_data_valid and pclk_out signals will accompany every sub-word to allow the data to be sampled correctly. The pclk_out signal is sourced close to its output pad rather than in the RDU to minimise the skew between the rising edge of the debug data signals (which should be registered close to their output pads) and the rising edge of pclk_out.

As multiple debug runs will be needed to obtain a complete set of debug data the n-bit sub-word will need to contain a different bit pattern for each run. For maximum flexibility each debug pin has an associated DebugDataSrc register that allows any of the 32 bits of the debug data word to be output on that particular debug data pin. The debug data pin must be enabled for debug operation by having its corresponding bit in the DebugPinSel registers set for the selected debug data bit to appear on the pin.

The size of the sub-word is determined by the number of enabled debug pins which is controlled by the DebugPinSel registers. Note that the debug_data_valid signal is always output. Furthermore debug_cntrl[0] (which is configured by DebugPinSel1) controls the mux for both the debug_data_valid and pclk_out signals as both of these must be enabled for any debug operation. The mapping of debug_data_out[n] signals onto individual pins will take place outside the RDU. This mapping is described in Table 30 below.

TABLE 30
DebugPinSel mapping
bit #Pin
DebugPinSel1phi_frclk. The debug_data_valid signal will
appear on this pin when enabled. Enabling this
pin also automatically enables the phi_readl pin
which will output the pclk_out signal
DebugPinSel2(0-31)gpio[0...31]

TABLE 31
RDU Configuration Registers
Address offset from
MMU_baseRegister#bitsResetDescription
0x80DebugSrc40x00Denotes which block is supplying the debug
data. The encoding of this block is given
below.
0 - MMU
1 - TIM
2 - LSS
3- GPIO
4 - SCB
5 - ICU
6 - CPR
7 - DIU
8 - PCU
0x84DebugPinSel110x0Determines whether the phi_frclk and
phi_readl pins are used for debug output.
1 - Pin outputs debug data
0 - Normal pin function
0x88DebugPinSel232 0x0000_0000Determines whether a pin is used for debug
data output.
1 - Pin outputs debug data
0 - Normal pin function
0x8C to 0x108DebugDataSrc[31:0]32x50x00Selects which bit of the 32-bit debug data
word will be output on debug_data_out[N]

11.9 Interrupt Operation

The interrupt controller unit (see chapter 14) generates an interrupt request by driving interrupt request lines with the appropriate interrupt level. LEON supports 15 levels of interrupt with level 15 as the highest level (the SPARC architecture manual [36] states that level 15 is non-maskable but we have the freedom to mask this if desired). The CPU will begin processing an interrupt exception when execution of the current instruction has completed and it will only do so if the interrupt level is higher than the current processor priority. If a second interrupt request arrives with the same level as an executing interrupt service routine then the exception will not be processed until the executing routine has completed.

When an interrupt trap occurs the LEON hardware will place the program counters (PC and nPC) into two local registers. The interrupt handler routine is expected, as a minimum, to place the PSR register in another local register to ensure that the LEON can correctly return to its pre-interrupt state. The 4-bit interrupt level (irl) is also written to the trap type (tt) field of the TBR (Trap Base Register) by hardware. The TBR then contains the vector of the trap handler routine the processor will then jump. The TBA (Trap Base Address) field of the TBR must have a valid value before any interrupt processing can occur so it should be configured at an early stage.

Interrupt pre-emption is supported while ET (Enable Traps) bit of the PSR is set. This bit is cleared during the initial trap processing. In initial simulations the ET bit was observed to be cleared for up to 30 cycles. This causes significant additional interrupt latency in the worst case where a higher priority interrupt arrives just as a lower priority one is taken.

The interrupt acknowledge cycles shown in FIG. 26 below are derived from simulations of the LEON processor. The SoPEC toplevel interrupt signals used in this diagram map directly to the LEON interrupt signals in the iui and iuo records. An interrupt is asserted by driving its (encoded) level on the icu_cpu_ilevel[3:0] signals (which map to iui.irl[3:0]). The LEON core responds to this, with variable timing, by reflecting the level of the taken interrupt on the cpu_icu_ilevel[3:0] signals (mapped to iuo.irl[3:0]) and asserting the acknowledge signal cpu_iack (iuo.intack). The interrupt controller then removes the interrupt level one cycle after it has seen the level been acknowledged by the core. If there is another pending interrupt (of lower priority) then this should be driven on icu_cpu_ilevel[3:0] and the CPU will take that interrupt (the level 9 interrupt in the example below) once it has finished processing the higher priority interrupt. The cpu_icu_ilevel[3:0] signals always reflect the level of the last taken interrupt, even when the CPU has finished processing all interrupts.

11.10 Boot Operation

See section 17.2 for a description of the SoPEC boot operation.

11.11 Software Debug

Software debug mechanisms are discussed in the “SoPEC Software Debug” document [15].

12 Serial Communications Block (SCB)

12.1 Overview

The Serial Communications Block (SCB) handles the movement of all data between the SoPEC and the host device (e.g. PC) and between master and slave SoPEC devices. The main components of the SCB are a Full-Speed (FS) USB Device Core, a FS USB Host Core, a Inter-SoPEC Interface (ISI), a DMA manager, the SCB Map and associated control logic. The need for these components and the various types of communication they provide is evident in a multi-SoPEC printer configuration.

12.1.1 Multi-SoPEC Systems

While single SoPEC systems are expected to form the majority of SoPEC systems the SoPEC device must also support its use in multi-SoPEC systems such as that shown in FIG. 27. A SoPEC may be assigned any one of a number of identities in a multi-SoPEC system. A SoPEC may be one or more of a PrintMaster, a LineSyncMaster, an ISIMaster, a StorageSoPEC or an ISISlave SoPEC.

12.1.1.1 ISIMaster Device

The ISIMaster is the only device that controls the common ISI lines (see FIG. 30) and typically interfaces directly with the host. In most systems the ISIMaster will simply be the SoPEC connected to the USB bus. Future systems, however, may employ an ISI-Bridge chip to interface between the host and the ISI bus and in such systems the ISI-Bridge chip will be the ISIMaster. There can only be one ISIMaster on an ISI bus.

Systems with multiple SoPECs may have more than one host connection, for example there could be two SoPECs communicating with the external host over their FS USB links (this would of course require two USB cables to be connected), but still only one ISIMaster.

While it is not expected to be required, it is possible for a device to hand over its role as the ISIMaster to another device on the ISI i.e. the ISIMaster is not necessarily fixed.

12.1.1.2 PrintMaster Device

The PrintMaster device is responsible for coordinating all aspects of the print operation. This includes starting the print operation in all printing SoPECs and communicating status back to the external host. When the ISIMaster is a SoPEC device it is also likely to be the PrintMaster as well. There may only be one PrintMaster in a system and it is most likely to be a SoPEC device.

12.1.1.3 LineSyncMaster Device

The LineSyncMaster device generates the lsync pulse that all SoPECs in the system must synchronize their line outputs with. Any SoPEC in the system could act as a LineSyncMaster although the PrintMaster is probably the most likely candidate. It is possible that the LineSyncMaster may not be a SoPEC device at all—it could, for example, come from some OEM motor control circuitry. There may only be one LineSyncMaster in a system.

12.1.1.4 Storage Device

For certain printer types it may be realistic to use one SoPEC as a storage device without using its print engine capability—that is to effectively use it as an ISI-attached DRAM. A storage SoPEC would receive data from the ISIMaster (most likely to be an ISI-Bridge chIP) and then distribute it to the other SoPECs as required. No other type of data flow (e.g. ISISlave->storage SoPEC->ISISlave) would need to be supported in such a scenario. The SCB supports this functionality at no additional cost because the CPU handles the task of transferring outbound data from the embedded DRAM to the ISI transmit buffer. The CPU in a storage SoPEC will have almost nothing else to do.

12.1.1.5 ISISlave Device

Multi-SoPEC systems will contain one or more ISISlave SoPECs. An ISISlave SoPEC is primarily used to generate dot data for the printhead IC it is driving. An ISISlave will not transmit messages on the ISI without first receiving permission to do so, via a ping packet (see section 12.4.4.6), from the ISIMaster

12.1.1.6 ISI-Bridge Device

SoPEC is targeted at the low-cost small office/home office (SoHo) market. It may also be used in future systems that target different market segments which are likely to have a high speed interface capability. A future device, known as an ISI-Bridge chip, is envisaged which will feature both a high speed interface (such as High-Speed (HS) USB, Ethernet or IEEE1394) and one or more ISI interfaces. The use of multiple ISI buses would allow the construction of independent print systems within the one printer. The ISI-Bridge would be the ISIMaster for each of the ISI buses it interfaces to.

12.1.1.7 External Host

The external host is most likely (but is not required) to be, a PC. Any system that can act as a USB host or that can interface to an ISI-Bridge chip could be the external host. In particular, with the development of USB On-The-Go (USB OTG), it is possible that a number of USB OTG enabled products such as PDAs or digital cameras will be able to directly interface with a SoPEC printer.

12.1.1.8 External USB Device

The external USB device is most likely (but is not required) to be, a digital camera. Any system that can act as a USB device could be connected as an external USB device. This is to facilitate printing in the absence of a PC.

12.1.2 Types of Communication

12.1.2.1 Communications with External Host

The external host communicates directly with the ISIMaster in order to print pages. When the ISIMaster is a SoPEC, the communications channel is FS USB.

12.1.2.1.1 External Host to ISIMaster Communication

The external host will need to communicate the following information to the ISIMaster device:

    • Communications channel configuration and maintenance information
    • Most data destined for PrintMaster, ISISlave or storage SoPEC devices. This data is simply relayed by the ISIMaster
    • Mapping of virtual communications channels, such as USB endpoints, to ISI destination
      12.1.2.1.2 ISIMaster to External Host Communication

The ISIMaster will need to communicate the following information to the external host:

    • Communications channel configuration and maintenance information
    • All data originating from the PrintMaster, ISISlave or storage SoPEC devices and destined for the external host. This data is simply relayed by the ISIMaster
      12.1.2.1.3 External Host to PrintMaster Communication

The external host will need to communicate the following information to the PrintMaster device:

    • Program code for the PrintMaster
    • Compressed page data for the PrintMaster
    • Control messages to the PrintMaster
    • Tables and static data required for printing e.g. dead nozzle tables, dither matrices etc.
    • Authenticatable messages to upgrade the printer's capabilities
      12.1.2.1.4 PrintMaster to External Host Communication

The PrintMaster will need to communicate the following information to the external host:

    • Printer status information (i.e. authentication results, paper empty/jammed etc.)
    • Dead nozzle information
    • Memory buffer status information
    • Power management status
    • Encrypted SoPEC_id for use in the generation of PRINTER_QA keys during factory programming
      12.1.2.1.5 External Host to ISISlave Communication

All communication between the external host and ISISlave SoPEC devices must be direct (via a dedicated connection between the external host and the ISISlave) or must take place via the ISIMaster. In the case of a SoPEC ISIMaster it is possible to configure each individual USB endpoint to act as a control channel to an ISISlave SoPEC if desired, although the endpoints will be more usually used to transport data. The external host will need to communicate the following information to ISISlave devices over the comms/lSI:

    • Program code for ISISlave SoPEC devices
    • Compressed page data for ISISlave SoPEC devices
    • Control messages to the ISISlave SoPEC (where a control channel is supported)
    • Tables and static data required for printing e.g. dead nozzle tables, dither matrices etc.
    • Authenticatable messages to upgrade the printer's capabilities
      12.1.2.1.6 ISISlave to External Host Communication

All communication between the ISISlave SoPEC devices and the external host must take place via the ISIMaster. The ISISlave will need to communicate the following information to the external host over the comms/ISI:

    • Responses to the external host's control messages (where a control channel is supported)
    • Dead nozzle information from the ISISlave SoPEC.
    • Encrypted SoPEC_id for use in the generation of PRINTER_QA keys during factory programming
      12.1.2.2 Communication with External USB Device
      12.1.2.2.1 ISIMaster to External USB Device Communication
    • Communications channel configuration and maintenance information.
      12.1.2.2.2 External USB Device to ISIMaster Communication
    • Print data from a function on the external USB device.
      12.1.2.3 Communication Over ISI
      12.1.2.3.1 ISIMaster to PrintMaster Communication

The ISIMaster and PrintMaster will often be the same physical device. When they are different devices then the following information needs to be exchanged over the ISI:

    • All data from the external host destined for the PrintMaster (see section 12.1.2.1.4).

This data is simply relayed by the ISIMaster

12.1.2.3.2 PrintMaster to ISIMaster Communication

The ISIMaster and PrintMaster will often be the same physical device. When they are different devices then the following information needs to be exchanged over the ISI:

    • All data from the PrintMaster destined for the external host (see section 12.1.2.1.4).

This data is simply relayed by the ISIMaster

12.1.2.3.3 ISIMaster to ISISlave Communication

The ISIMaster may wish to communicate the following information to the ISISlaves:

    • All data (including program code such as ISIId enumeration) originating from the external host and destined for the ISISlave (see section 12.1.2.1.5). This data is simply relayed by the ISIMaster
    • wake up from sleep mode
      12.1.2.3.4 ISISlave to ISIMaster Communication

The ISISlave may wish to communicate the following information to the ISIMaster:

    • All data originating from the ISISlave and destined for the external host (see section 12.1.2.1.6). This data is simply relayed by the ISIMaster
      12.1.2.3.5 PrintMaster to ISISlave Communication

When the PrintMaster is not the ISIMaster all ISI communication is done in response to ISI ping packets (see 12.4.4.6). When the PrintMaster is the ISIMaster then it will of course communicate directly with the ISISlaves. The PrintMaster SoPEC may wish to communicate the following information to the ISISlaves:

    • Ink status e.g. requests for dotCount data i.e. the number of dots in each color fired by the printheads connected to the ISISlaves
    • configuration of GPIO ports e.g. for clutch control and lid open detect
    • power down command telling the ISISlave to enter sleep mode
    • ink cartridge fail information

This list is not complete and the time constraints associated with these requirements have yet to be determined.

In general the PrintMaster may need to be able to:

    • send messages to an ISISlave which will cause the ISISlave to return the contents of ISISlave registers to the PrintMaster or
    • to program ISISlave registers with values sent by the PrintMaster

This should be under the control of software running on the CPU which writes messages to the ISI/SCB interface.

12.1.2.3.6 ISISlave to PrintMaster Communication

ISISlaves may need to communicate the following information to the PrintMaster:

    • ink status e.g. dotCount data i.e. the number of dots in each color fired by the printheads connected to the ISISlaves
    • band related information e.g. finished band interrupts
    • page related information i.e. buffer underrun, page finished interrupts
    • MMU security violation interrupts
    • GPIO interrupts and status e.g. clutch control and lid open detect
    • printhead temperature
    • printhead dead nozzle information from SoPEC printhead nozzle tests
    • power management status

This list is not complete and the time constraints associated with these requirements have yet to be determined.

As the ISI is an insecure interface commands issued over the ISI should be of limited capability e.g. only limited register writes allowed. The software protocol needs to be constructed with this in mind. In general ISISlaves may need to return register or status messages to the PrintMaster or ISIMaster. They may also need to indicate to the PrintMaster or ISIMaster that a particular interrupt has occurred on the ISISlave. This should be under the control of software running on the CPU which writes messages to the ISI block.

12.1.2.3.7 ISISlave to ISISlave Communication

The amount of information that will need to be communicated between ISISlaves will vary considerably depending on the printer configuration. In some systems ISISlave devices will only need to exchange small amounts of control information with each other while in other systems (such as those employing a storage SoPEC or extra USB connection) large amounts of compressed page data may be moved between ISISlaves. ScenarIOs where ISISlave to ISISlave communication is required include: (a) when the PrintMaster is not the ISIMaster, (b) QA Chip ink usage protocols, (c) data transmission from data storage SoPECs, (d) when there are multiple external host connections supplying data to the printer.

12.1.3 SCB Block Diagram

The SCB consists of four main sub-blocks, as shown in the basic block diagram of FIG. 28.

12.1.4 Definitions of I/Os

The toplevel I/Os of the SCB are listed in Table 32. A more detailed description of their functionality will be given in the relevant sub-block sections.

TABLE 32
SCB I/O
Port namesI/ODescription
Clocks and Resets
prst_n1InSystem reset signal. Active low.
Pclk1InSystem clock.
usbclk1In48 MHz clock for the USB device and host
cores. The cores also require a 12 MHz clock,
which will be generated locally by dividing the
48 MHz clock by 4.
isi_cpr_reset_n1OutSignal from the ISI indicating that ISI activity
has been detected while in sleep mode and so
the chip should be reset. Active low.
usbd_cpr_reset_n1OutSignal from the USB device that a USB reset
has occurred. Active low.
USB device IO transceiver
signals
usbd_ts1OutUSB device IO transceiver (BUSB2_PM) driver
three-state control. Active high enable.
usbd_a1OutUSB device IO transceiver (BUSB2_PM) driver
data input.
usbd_se01OutUSB device IO transceiver (BUSB2_PM)
single-ended zero input. Active high.
usbd_zp1InUSB device IO transceiver (BUSB2_PM) D+
receiver output.
usbd_zm1InUSB device IO transceiver (BUSB2_PM) D−
receiver output.
usbd_z1InUSB device IO transceiver (BUSB2_PM)
differential receiver output.
usbd_pull_up_en1OutUSB device pull-up resistor enable. Switches
power to the external pull-up resistor,
connected to the D+ line that is required for
device identification to the USB. Active high.
usbd_vbus_sense1InUSB device VBUS power sense. Used to
detect power on VBUS. NOTE: The IBM Cu11
PADS are 3.3 V, VBUS is 5 V. An external voltage
conversion will be necessary, e.g. resistor
divider network. Active high.
USB host IO transceiver
signals
usbh_ts1OutUSB host IO transceiver (BUSB2_PM) driver
three-state control. Active high enable
usbh_a1OutUSB host IO transceiver (BUSB2_PM) driver
data input.
usbh_se01OutUSB host IO transceiver (BUSB2_PM) single-
ended zero input. Active high.
usbh_zp1InUSB host IO transceiver (BUSB2_PM) D+
receiver output.
usbh_zm1InUSB host IO transceiver (BUSB2_PM) D−
receiver output.
usbh_z1InUSB host IO transceiver (BUSB2_PM)
differential receiver output.
usbh_over_current1InUSB host port power over current indicator.
Active high.
usbh_power_en1OutUSB host VBUS power enable. Used for port
power switching. Active high.
CPU Interface
cpu_adr[n:2]n−1InCPU address bus.
cpu_dataout[31:0]32InShared write data bus from the CPU
scb_cpu_data[31:0]32OutRead data bus to the CPU
cpu_rwn1InCommon read/not-write signal from the CPU
cpu_acode[1:0]2InCPU Access Code signals. These decode as
follows:
00 - User program access
01 - User data access
10 - Supervisor program access
11 - Supervisor data access
cpu_scb_sel1InBlock select from the CPU. When cpu_scb_sel
is high both cpu_adr and cpu_dataout are valid
scb_cpu_rdy1OutReady signal to the CPU. When scb_cpu_rdy is
high it indicates the last cycle of the access.
For a write cycle this means cpu_dataout has
been registered by the SCB and for a read
cycle this means the data on scb_cpu_data is
valid.
scb_cpu_berr1OutBus error signal to the CPU indicating an
invalid access.
scb_cpu_debug_valid1OutSignal indicating that the data currently on
scb_cpu_data is valid debug data
Interrupt signals
dma_icu_irq1OutDMA interrupt signal to the interrupt controller
block.
isi_icu_irq1OutISI interrupt signal to the interrupt controller
block.
usb_icu_irq[1:0]2OutUSB host and device interrupt signals to the
ICU.
Bit 0 - USB Host interrupt
Bit 1 - USB Device interrupt
DIU interface
scb_diu_wadr[21:5]17OutWrite address bus to the DIU
scb_diu_data[63:0]64OutData bus to the DIU.
scb_diu_wreq1OutWrite request to the DIU
diu_scb_wack1InAcknowledge from the DIU that the write
request was accepted.
scb_diu_wvalid1OutSignal from the SCB to the DIU indicating that
the data currently on the scb_diu_data[63:0]
bus is valid
scb_diu_wmask[7:0]7OutByte aligned write mask. A “1” in a bit field of
“scb_diu_wmask[7:0]”
means that the corresponding byte will be
written to DRAM.
scb_diu_rreq1OutRead request to the DIU.
scb_diu_radr[21:5]17OutRead address bus to the DIU
diu_scb_rack1InAcknowledge from the DIU that the read
request was accepted.
diu_scb_rvalid1InSignal from the DIU to the SCB indicating that
the data currently on the diu_data[63:0] bus is
valid
diu_data[63:0]64InCommon DIU data bus.
GPIO interface
isi_gpio_dout[3:0]4OutISI output data to GPIO pins
isi_gpio_e[3:0]4OutISI output enable to GPIO pins
gpio_isi_din[3:0]4InInput data from GPIO pins to ISI

12.1.5 SCB Data Flow

A logical view of the SCB is shown in FIG. 29, depicting the transfer of data within the SCB.

12.2 USBD (USB Device Sub-Block)

12.2.1 Overview

The FS USB device controller core and associated SCB logic are referred to as the USB Device (USBD).

A SoPEC printer has FS USB device capability to facilitate communication between an external USB host and a SoPEC printer. The USBD is self-powered. It connects to an external USB host via a dedicated USB interface on the SoPEC printer, comprising a USB connector, the necessary discretes for USB signalling and the associated SoPEC ASIC I/Os.

The FS USB device core will be third party IP from Synopsys: TymeWare™ USB1.1 Device Controller (UDCVCI). Refer to the UDCVCI User Manual [20] for a description of the core.

The device core does not support LS USB operation. Control and bulk transfers are supported by the device. Interrupt transfers are not considered necessary because the required interrupt-type functionality can be achieved by sending query messages over the control channel on a scheduled basis. There is no requirement to support isochronous transfers.

The device core is configured to support 6 USB endpoints (EPs): the default control EP (EP0), 4 bulk OUT EPs (EP1, EP2, EP3, EP4) and 1 bulk IN EP (EP5). It should be noted that the direction of each EP is with respect to the USB host, i.e. IN refers to data transferred to the external host and OUT refers to data transferred from the external host. The 4 bulk OUT EPs will be used for the transfer of data from the external host to SoPEC, e.g. compressed page data, program data or control messages. Each bulk OUT EP can be mapped on to any target destination in a multi-SoPEC system, via the SCB Map configuration registers. The bulk IN EP is used for the transfer of data from SoPEC to the external host, e.g. a print image downloaded from a digital camera that requires processing on the external host system. Any feedback data will be returned to the external host on EP0, e.g. status information.

The device core does not provide internal buffering for any of its EPs (with the exception of the 8 byte setup data payload for control transfers). All EP buffers are provided in the SCB. Buffers will be grouped according to EP direction and associated packet destination. The SCB Map configuration registers contain a DestISIId and DestISISubId for each OUT EP, defining their EP mapping and therefore their packet destination. Refer to section Section 12.4 ISI (Inter SoPEC Interface Sub-block) for further details on ISIId and ISISubId. Refer to section Section 12.5 CTRL (Control Sub-block) for further details on the mapping of OUT EPs.

12.2.2 USBD Effective Bandwidth

The effective bandwidth between an external USB host and the printer will be influenced by:

    • Amount of activity from other devices that share the USB with the printer.
    • Throughput of the device controller core.
    • EP buffering implementation.
    • Responsiveness of the external host system CPU in handling USB interrupts.

To maximize bandwidth to the printer it is recommended that no other devices are active on the USB between the printer and the external host. If the printer is connected to a HS USB external host or hub it may limit the bandwidth available to other devices connected to the same hub but it would not significantly affect the bandwidth available to other devices upstream of the hub. The EP buffering should not limit the USB device core throughput, under normal operating conditions. Used in the recommended configuration, under ideal operating conditions, it is expected that an effective bandwidth of 8-9 Mbit/s will be achieved with bulk transfers between the external host and the printer.

12.2.3 IN EP Packet Buffer

The IN EP packet buffer stores packets originating from the LEON CPU that are destined for transmission over the USB to the external USB host. CPU writes to the buffer are 32 bits wide. USB device core reads from the buffer 32 bits wide.

128 bytes of local memory are required in total for EP0-IN and EP5-IN buffering. The IN EP buffer is a single, 2-port local memory instance, with a dedicated read port and a dedicated write port. Both ports are 32 bits wide. Each IN EP has a dedicated 64 byte packet location available in the memory array to buffer a single USB packet (maximum USB packet size is 64 bytes). Each individual 64 byte packet location is structured as 16×32 bit words and is read/written in a FIFO manner. When the device core reads a packet entry from the IN EP packet buffer, the buffer must retain the packet until the device core performs a status write, informing the SCB that the packet has been accepted by the external USB host and can be flushed. The CPU can therefore only write a single packet at a time to each IN EP. Any subsequent CPU write request to a buffer location containing a valid packet will be refused, until that packet has been successfully transmitted.

12.2.4 OUT EP Packet Buffer

The OUT EP packet buffer stores packets originating from the external USB host that are destined for transmission over DMAChannel0, DMAChannel1 or the ISI. The SCB control logic is responsible for routing the OUT EP packets from the OUT EP packet buffer to DMA or to the ISITx Buffer, based on the SCB Map configuration register settings. USB core writes to the buffer are 32 bits wide. DMA and ISI associated reads from the buffer are both 64 bits wide.

512 bytes of local memory are required in total for EP0-OUT, EP1-OUT, EP2-OUT, EP3-OUT and EP4-OUT buffering. The OUT EP packet buffer is a single, 2-port local memory instance, with a dedicated read port and a dedicated write port. Both ports are 64 bits wide. Byte enables are used for the 32 bit wide USB device core writes to the buffer. Each OUT EP can be mapped to DMAChannel0, DMAChannel1 or the ISI.

The OUT EP packet buffer is partitioned accordingly, resulting in three distinct packet FIFOs:

    • USBDDMA0FIFO, for USB packets destined for DMAChannel0 on the local SoPEC.
    • USBDDMA1 FIFO, for USB packets destined for DMAChannel1 on the local SoPEC.
    • USBDISIFIFO, for USB packets destined for transmission over the ISI.
      12.2.4.1 USBDDMAnFIFO

This description applies to USBDDMA0FIFO and USBDDMA1 FIFO, where ‘n’ represents the respective DMA channel, i.e. n=0 for USBDDMA0FIFO, n=1 for USBDDMA1 FIFO. USBDDMAnFIFO services any EPs mapped to DMAChanneln on the local SoPEC device. This implies that a packet originating from an EP with an associated ISIId that matches the local SoPEC ISIId and an ISISubId=n will be written to USBDDMAnFIFO, if there is space available for that packet.

USBDDMAnFIFO has a capacity of 2×64 byte packet entries, and can therefore buffer up to 2 USB packets. It can be considered as a 2 packet entry FIFO. Packets will be read from it in the same order in which they were written, i.e. the first packet written will be the first packet read and the second packet written will be the second packet read. Each individual 64 byte packet location is structured as 8×64 bit words and is read/written in a FIFO manner.

The USBDDMAnFIFO has a write granularity of 64 bytes, to allow for the maximum USB packet size. The USBDDMAnFIFO will have a read granularity of 32 bytes to allow for the DMA write access bursts of 4×64 bit words, i.e. the DMA Manager will read 32 byte chunks at a time from the USBDDMAnFIFO 64 byte packet entries, for transfer to the DIU.

It is conceivable that a packet which is not a multiple 32 bytes in size may be written to the USBDDMAnFIFO. When this event occurs, the DMA Manager will read the contents of the remaining address locations associated with the 32 byte chunk in the USBDDMAnFIFO, transferring the packet plus whatever data is present in those locations, resulting in a 32 byte packet (a burst of 4×64 bit words) transfer to the DIU.

The DMA channels should achieve an effective bandwidth of 160 Mbits/sec (1 bit/cycle) and should never become blocked, under normal operating conditions. As the USB bandwidth is considerably less, a 2 entry packet FIFO for each DMA channel should be sufficient.

12.2.4.2 USBDISIFIFO

USBDISIFIFO services any EPs mapped to ISI. This implies that a packet originating from an EP with an associated ISId that does not match the local SoPEC ISId will be written to USBDISIFIFO if there is space available for that packet.

USBDISIFIFO has a capacity of 4×64 byte packet entries, and can therefore buffer up to 4 USB packets. It can be considered as a 4 packet entry FIFO. Packets will be read from it in the same order in which they were written, i.e. the first packet written will be the first packet read and the second packet written will be the second packet read, etc. Each individual 64 byte packet location is structured as 8×64 bit words and is read/written in a FIFO manner.

The ISI long packet format will be used to transfer data across the ISI. Each ISI long packet data payload is 32 bytes. The USBDISIFIFO has a write granularity of 64 bytes, to allow for the maximum USB packet size. The USBDISIFIFO will have a read granularity of 32 bytes to allow for the ISI packet size, i.e. the SCB will read 32 byte chunks at a time from the USBDISIFIFO 64 byte packet entries, for transfer to the ISI.

It is conceivable that a packet which is not a multiple 32 bytes in size may be written to the USBDISIFIFO, either intentionally or due to a software error. A maskable interrupt per EP is provided to flag this event. There will be 2 options for dealing with this scenario on a per EP basis:

    • Discard the packet.
    • Read the contents of the remaining address locations associated with the 32 byte chunk in the USBDISIFIFO, transferring the irregular size packet plus whatever data is present in those locations, resulting in a 32 byte packet transfer to the ISITxBuffer.

The ISI should achieve an effective bandwidth of 100 Mbits/sec (4 wire configuration). It is possible to encounter a number of retries when transmitting an ISI packet and the LEON CPU will require access to the ISI transmit buffer. However, considering the relatively low bandwidth of the USB, a 4 packet entry FIFO should be sufficient.

12.2.5 Wake-Up From Sleep Mode

The SoPEC will be placed in sleep mode after a suspend command is received by the USB device core. The USB device core will continue to be powered and clocked in sleep mode. A USB reset, as opposed to a device resume, will be required to bring SoPEC out of its sleep state as the sleep state is hoped to be logically equivalent to the power down state.

The USB reset signal originating from the USB controller will be propagated to the CPR (as usb_cpr_reset_n) if the USBWakeupEnable bit of the WakeupEnable register (see Table) has been set. The USBWakeupEnable bit should therefore be set just prior to entering sleep mode. There is a scenario that would require SoPEC to initiate a USB remote wake-up (i.e. where SoPEC signals resume to the external USB host after being suspended by the external USB host). A digital camera (or other supported external USB device) could be connected to SoPEC via the internal SoPEC USB host controller core interface. There may be a need to transfer data from this external USB device, via SoPEC, to the external USB host system for processing. If the USB connecting the external host system and SoPEC was suspended, then SoPEC would need to initiate a USB remote wake-up.

12.2.6 Implementation

12.2.6.1 USBD Sub-Block Partition

    • Block diagram
    • Definition of I/Os
      12.2.6.2 USB Device IP Core
      12.2.6.3 PVCI Target
      12.2.6.4 IN EP Buffer
      12.2.6.5 OUT EP Buffer
      12.3 USBH (USB Host Sub-Block)
      12.3.1 Overview

The SoPEC USB Host Controller (HC) core, associated SCB logic and associated SoPEC ASIC I/Os are referred to as the USB Host (USBH).

A SoPEC printer has FS USB host capability, to facilitate communication between an external USB device and a SoPEC printer. The USBH connects to an external USB device via a dedicated USB interface on the SoPEC printer, comprising a USB connector, the necessary discretes for USB signalling and the associated SoPEC ASIC I/Os.

The FS USB HC core are third party IP from Synopsys: DesignWareR USB1.1 OHCI Host Controller with PVCI (UHOSTC_PVCI). Refer to the UHOSTC_PVCI User Manual [18] for details of the core. Refer to the Open Host Controller Interface (OHCI) Specification Release [19] for details of OHCI operation.

The HC core supports Low-Speed (LS) USB devices, although compatible external USB devices are most likely to be FS devices. It is expected that communication between an external USB device and a SoPEC printer will be achieved with control and bulk transfers. However, isochronous and interrupt transfers are also supported by the HC core.

There will be 2 communication channels between the Host Controller Driver (HCD) software running on the LEON CPU and the HC core:

    • OHCI operational registers in the HC core. These registers are control, status, list pointers and a pointer to the Host Controller Communications Area (HCCA) in shared memory. A target Peripheral Virtual Component Interface (PCVI) on the HC core will provide LEON with direct read/write access to the operational registers. Refer to the OHCI Specification for details of these registers.
      • HCCA in SoPEC eDRAM. An initiator Peripheral Virtual Component Interface (PCVI) on the HC core will provide the HC with DMA read/write access to an address space in eDRAM. The HCD running on LEON will have read/write access to the same address space. Refer to the OHCI Specification for details of the HCCA.

The target PVCI interface is a 32 bit word aligned interface, with byte enables for write access. All read/write access to the target PVCI interface by the LEON CPU will be 32 bit word aligned. The byte enables will not be used, as all registers will be read and written as 32 bit words.

The initiator PVCI interface is a 32 bit word aligned interface with byte enables for write access. All DMA read/write accesses are 256 bit word aligned, in bursts of 4×64 bit words. As there is no guarantee that the read/write requests from the HC core will start at a 256 bit boundary or be 256 bits long, it is necessary to provide 8 byte enables for each of the 64 bit words in a write burst form the HC core to DMA. The signal scb_diu_wmask serves this purpose.

Configuration of the HC core will be performed by the HCD.

12.3.2 Read/Write Buffering

The HC core maximum burst size for a read/write access is 4×32 bit words. This implies that the minimum buffering requirements for the HC core will be a 1 entry deep address register and a 4 entry deep data register. It will be necessary to provide data and address mapping functionality to convert the 4×32 bit word HC core read/write bursts into 4×64 bit word DMA read/write bursts. This will meet the minimum buffering requirements.

12.3.3 USBH Effective Bandwidth

The effective bandwidth between an external USB device and a SoPEC printer will be influenced by:

    • Amount of activity from other devices that share the USB with the external USB device.
    • Throughput of the HC core.
    • HC read/write buffering implementation.
    • Responsiveness of the LEON CPU in handling USB interrupts.

Effective bandwidth between an external USB device and a SoPEC printer is not an issue. The primary application of this connectivity is the download of a print image from a digital camera. Printing speed is not important for this type of print operation. However, to maximize bandwidth to the printer it is recommended that no other devices are active on the USB between the printer and the external USB device. The HC read/write buffering in the SCB should not limit the USB HC core throughput, under normal operating conditions.

Used in the recommended configuration, under ideal operating conditions, it is expected that an effective bandwidth of 8-9 Mbit/s will be achieved with bulk transfers between the external USB device and the SoPEC printer.

12.3.4 Implementation

12.3.5 USBH Sub-Block Partition

    • USBH Block Diagram
    • Definition of I/Os.
      12.3.5.1 USB Host IP Core
      12.3.5.2 PVCI Target
      12.3.5.3 PVCI Initiator
      12.3.5.4 Read/Write Buffer
      12.4 ISI (Inter SoPEC Interface Sub-Block)
      12.4.1 Overview

The ISI is utilised in all system configurations requiring more than one SoPEC. An example of such a system which requires four SoPECs for duplex A3 printing and an additional SoPEC used as a storage device is shown in FIG. 27.

The ISI performs much the same function between an ISISlave SoPEC and the ISIMaster as the USB connection performs between the ISIMaster and the external host. This includes the transfer of all program data, compressed page data and message (i.e. commands or status information) passing between the ISIMaster and the ISISlave SoPECs. The ISIMaster initiates all communication with the ISISlaves.

12.4.2 ISI Effective Bandwidth

The ISI will need to run at a speed that will allow error free transmission on the PCB while minimising the buffering and hardware requirements on SoPEC. While an ISI speed of 10 Mbit/s is adequate to match the effective FS USB bandwidth it would limit the system performance when a high-speed connection (e.g. USB2.0, IEEE1394) is used to attach the printer to the PC. Although they would require the use of an extra ISI-Bridge chip such systems are envisaged for more expensive printers (compared to the low-cost basic SoPEC powered printers that are initially being targeted) in the future.

An ISI line speed (i.e. the speed of each individual ISI wire) of 32 Mbit/s is therefore proposed as it will allow ISI data to be over-sampled 5 times (at a pclk frequency of 160 MHz). The total bandwidth of the ISI will depend on the number of pins used to implement the interface. The ISI protocol will work equally well if 2 or 4 pins are used for transmission/reception. The ISINumPins register is used to select between a 2 or 4 wire ISI, giving peak raw bandwidths of 64 Mbit/s and 128 Mbit/s respectively. Using either a 2 or 4 wire ISI solution would allow the movement of data in to and out of a storage SoPEC (as described in 12.1.1.4 above), which is the most bandwidth hungry ISI use, in a timely fashion.

The ISINumPins register is used to select between a 2 or 4 wire ISI. A 2 wire ISI is the default setting for ISINumPins and this may be changed to a 4 wire ISI after initial communication has been established between the ISIMaster and all ISISlaves. Software needs to ensure that the switch from 2 to 4 wires is handled in a controlled and coordinated fashion so that nothing is transmitted on the ISI during the switch over period.

The maximum effective bandwidth of a two wire ISI, after allowing for protocol overheads and bus turnaround times, is expected to be approx. 50 Mbit/s.

12.4.3 ISI Device Identification and Enumeration

The ISIMasterSel bit of the ISICntrl register (see section Table) determines whether a SoPEC is an ISIMaster (ISIMasterSel=1), or an ISISlave (ISIMasterSel=0).

SoPEC defaults to being an ISISlave (ISIMasterSel=0) after a power-on reset—i.e. it will not transmit data on the ISI without first receiving a ping. If a SoPEC's ISIMasterSel bit is changed to 1, then that SoPEC will become the ISIMaster, transmitting data without requiring a ping, and generating pings as appropriately programmed.

ISIMasterSel can be set to 1 explicitly by the CPU writing directly to the ISICntrl register. ISIMasterSel can also be automatically set to 1 when activity occurs on any of USB endpoints 2-4 and the AutoMasterEnable bit of the ISICntrl register is also 1 (the default reset condition). Note that if AutoMasterEnable is 0, then activity on USB endpoints 2-4 will not result in ISIMasterSel being set to 1. USB endpoints 2-4 are chosen for the automatic detection since the power-on-reset condition has USB endpoints 0 and 1 pointing to ISIId 0 (which matches the local SoPEC's ISIId after power-on reset). Thus any transmission on USB endpoints 2-4 indicate a desire to transmit on the ISI which would usually indicate ISIMaster status. The automatic setting of ISIMasterSel can be disabled by clearing AutoMasterEnable, thereby allowing the SoPEC to remain an ISISlave while still making use of the USB endpoints 2-4 as external destinations.

Thus the setting of a SoPEC being ISIMaster or ISISlave can be completely under software control, or can be completely automatic.

The ISIId is established by software downloaded over the ISI (in broadcast mode) which looks at the input levels on a number of GPIO pins to determine the ISIId. For any given printer that uses a multi-SoPEC configuration it is expected that there will always be enough free GPIO pins on the ISISlaves to support this enumeration mechanism.

12.4.4 ISI Protocol

The ISI is a serial interface utilizing a 2/4 wire half-duplex configuration such as the 2-wire system shown in FIG. 30 below. An ISIMaster must always be present and a variable number of ISISlaves may also be on the ISI bus. The ISI protocol supports up to 14 addressable slaves, however to simplify electrical issues the ISI drivers need only allow for 5-6 ISI devices on a particular ISI bus. The ISI bus enables broadcasting of data, ISIMaster to ISISlave communication, ISISlave to ISIMaster communication and ISISlave to ISISlave communication. Flow control, error detection and retransmission of errored packets is also supported. ISI transmission is asynchronous and a Start field is present in every transmitted packet to ensure synchronization for the duration of the packet.

To maximize the effective ISI bandwidth while minimising pin requirements a half-duplex interleaved transmission scheme is used. FIG. 31 below shows how a 16-bit word is transmitted from an ISIMaster to an ISISlave over a 2-wire ISI bus. Since data will be interleaved over the wires and a 4-wire ISI is also supported, all ISI packets should be a multiple of 4 bits.

All ISI transactions are initiated by the ISIMaster and every non-broadcast data packet needs to be acknowledged by the addressed recipient. An ISISlave may only transmit when it receives a ping packet (see section 12.4.4.6) addressed to it. To avoid bus contention all ISI devices must wait ISITurnAround bit-times (5 pclk cycles per bit) after detecting the end of a packet before transmitting a packet (assuming they are required to transmit). All non-transmitting ISI devices must tristate their Tx drivers to avoid line contention. The ISI protocol is defined to avoid devices driving out of order (e.g. when an ISISlave is no longer being addressed). As the ISI uses standard I/O pads there is no physical collision detection mechanism.

There are three types of ISI packet: a long packet (used for data transmission), a ping packet (used by the ISIMaster to prompt ISISlaves for packets) and a short packet (used to acknowledge receipt of a packet). All ISI packets are delineated by a Start and Stop fields and transmission is atomic i.e. an ISI packet may not be split or halted once transmission has started.

12.4.4.1 ISI Transactions

The different types of ISI transactions are outlined in FIG. 32 below. As described later all NAKs are inferred and ACKS are not addressed to any particular ISI device.

12.4.4.2 Start Field Description

The Start field serves two purposes: To allow the start of a packet be unambiguously identified and to allow the receiving device synchronise to the data stream. The symbol, or data value, used to identify a Start field must not legitimately occur in the ensuing packet. Bit stuffing is used to guarantee that the Start symbol will be unique in any valid (i.e. error free) packet. The ISI needs to see a valid Start symbol before packet reception can commence i.e. the receive logic constantly looks for a Start symbol in the incoming data and will reject all data until it sees a Start symbol. Furthermore if a Start symbol occurs (incorrectly) during a data packet it will be treated as the start of a new packet. In this case the partially received packet will be discarded.

The data value of the Start symbol should guarantee that an adequate number of transitions occur on the physical ISI lines to allow the receiving ISI device to determine the best sampling window for the transmitted data. The Start symbol should also be sufficiently long to ensure that the bit stuffing overhead is low but should still be short enough to reduce its own contribution to the packet overhead. A Start symbol of b01010101 is therefore used as it is an effective compromise between these constraints.

Each SoPEC in a multi-SoPEC system will derive its system clock from a unique (i.e. one per SoPEC) crystal. The system clocks of each device will drift relative to each other over any period of time. The system clocks are used for generation and sampling of the ISI data. Therefore the sampling window can drift and could result in incorrect data values being sampled at a later point in time. To overcome this problem the ISI receive circuitry tracks the sampling window against the incoming data to ensure that the data is sampled in the centre of the bit period.

12.4.4.3 Stop Field Description

A 1 bit-time Stop field of b1 per ISI line ensures that all ISI lines return to the high state before the next packet is transmitted. The stop field is driven on to each ISI line simultaneously, i.e. b11 for a 2-wire ISI and b1111 for a 4-wire ISI would be interleaved over the respective ISI lines. Each ISI line is driven high for 1 bit-time. This is necessary because the first bit of the Start field is b0.

12.4.4.4 Bit Stuffing

This involves the insertion of bits into the bitstream at the transmitting SoPEC to avoid certain data patterns. The receiving SoPEC will strip these inserted bits from the bitstream.

Bit-stuffing will be performed when the Start symbol appears at a location other than the start field of any packet, i.e. when the bit pattern b0101010 occurs at the transmitter, a 0 will be inserted to escape the Start symbol, resulting in the bit pattern b01010100. Conversely, when the bit pattern b0101010 occurs at the receiver, if the next bit is a ‘0’ it will be stripped, if it is a ‘1’ then a Start symbol is detected.

If the frequency variations in the quartz crystal were large enough, it is conceivable that the resultant frequency drift over a large number of consecutive 1s or 0s could cause the receiving SoPEC to loose synchronisation.6 The quartz crystal that will be used in SoPEC systems is rated for 32 MHz @ 100 ppm. In a multi-SoPEC system with a 32 MHz+100 ppm crystal and a 32 MHz-100 ppm crystal, it would take approximately 5000 pclk cycles to cause a drift of 1 pclk cycle. This means that we would only need to bit-stuff somewhere before 1000 ISI bits of consecutive 1s or consecutive 0s, to ensure adequate synchronization. As the maximum number of bits transmitted per ISI line in a packet is 145, it should not be necessary to perform bit-stuffing for consecutive 1s or 0s. We may wish to constrain the spec of xtalin and also xtalin for the ISI-Bridge chip to ensure the ISI cannot drift out of sync during packet reception.
6Current max packet size˜=290 bits=145 bits per ISI line (on a 2 wire ISI)=725 160 MHz cycles. Thus the pclks in the two communicating ISI devices should not drift by more than one cycle in 725 i.e. 1379 ppm. Careful analysis of the crystal, PLL and oscillator specs and the sync detection circuit is needed here to ensure our solution is robust.

Note that any violation of bit stuffing will result in the RxFrameErrorSticky status bit being set and the incoming packet will be treated as an errored packet.

12.4.4.5 ISI Long Packet

The format of a long ISI packet is shown in FIG. 33 below. Data may only be transferred between ISI devices using a long packet as both the short and ping packets have no payload field. Except in the case of a broadcast packet, the receiving ISI device will always reply to a long packet with an explicit ACK (if no error is detected in the received packet) or will not reply at all (e.g. an error is detected in the received packet), leaving the transmitter to infer a NAK. As with all ISI packets the bitstream of a long packet is transmitted with its lsb (the leftmost bit in FIG. 33) first. Note that the total length (in bits) of an ISI long packet differs slightly between a 2 and 4-wire ISI system due to the different number of bits required for the Start and Stop fields.

All long packets begin with the Start field as described earlier. The PktDesc field is described in Table 33.

TABLE 33
PktDesc field description
BitDescription
0:100 - Long packet
01 - Reserved
10 - Ping packet
11 - Reserved
2Sequence bit value. Only valid for long packets. See section 12.4.4.9
for a description of sequence bit operation

Any ISI device in the system may transmit a long packet but only the ISIMaster may initiate an ISI transaction using a long packet. An ISISlave may only send a long packet in reply to a ping message from the ISIMaster. A long packet from an ISISlave may be addressed to any ISI device in the system.

The Address field is straightforward and complies with the ISI naming convention described in section 12.5.

The payload field is exactly what is in the transmit buffer of the transmitting ISI device and gets copied into the receive buffer of the addressed ISI device(s). When present the payload field is always 256 bits.

To ensure strong error detection a 16-bit CRC is appended.

12.4.4.6 ISI Ping Packet

The ISI ping packet is used to allow ISISlaves to transmit on the ISI bus. As can be seen from FIG. 34 below the ping packet can be viewed as a special case of the long packet. In other words it is a long packet without any payload. Therefore the PktDesc field is the same as a long packet PktDesc, with the exception of the sequence bit, which is not valid for a ping packet. Both the ISISubId and the sequence bit are fixed at 1 for all ping packets. These values were chosen to maximize the hamming distance from an ACK symbol and to minimize the likelihood of bit stuffing. The ISISubId is unused in ping packets because the ISIMaster is addressing the ISI device rather than one of the DMA channels in the device. The ISISlave may address any ISIId.ISISubId in response if it wishes. The ISISlave will respond to a ping packet with either an explicit ACK (if it has nothing to send), an inferred NAK (if it detected an error in the ping packet) or a long packet (containing the data it wishes to send). Note that inferred NAKS do not result in the retransmission of a ping packet. This is because the ping packet will be retransmitted on a predetermined schedule (see 12.4.4.11 for more details).

An ISISlave should never respond to a ping message to the broadcast ISIId as this must have been sent in error. An ISI ping packet will never be sent in response to any packet and may only originate from an ISIMaster.

12.4.4.7 ISI Short Packet

The ISI short packet is only 17 bits long, including the Start and Stop fields. A value of b11101011 is proposed for the ACK symbol. As a 16-bit CRC is inappropriate for such a short packet it is not used. In fact there is only one valid value for a short ACK packet as the Start, ACK and Stop symbols all have fixed values. Short packets are only used for acknowledgements (i.e. explicit ACKs). The format of a short ISI packet is shown in FIG. 35 below. The ACK value is chosen to ensure that no bit stuffing is required in the packet and to minimize its hamming distance from ping and long ISI packets.

12.4.4.8 Error Detection and Retransmission

The 16-bit CRC will provide a high degree of error detection and the probability of transmission errors occurring is very low as the transmission channel (i.e. PCB traces) will have a low inherent bit error rate. The number of undetected errors should therefore be minute.

The HDLC standard CRC-16 (i.e. G(x)=x16+x12+x5+1) is to be used for this calculation, which is to be performed serially. It is calculated over the entire packet (excluding the Start and Stop fields). A simple retransmission mechanism frees the CPU from getting involved in error recovery for most errors because the probability of a transmission error occurring more than once in succession is very, very low in normal circumstances.

After each non-short ISI packet is transmitted the transmitting device will open a reply window. The size of the reply window will be ISIShortReplyWin bit times when a short packet is expected in reply, i.e. the size of a short packet, allowing for worst case bit stuffing, bus turnarounds and timing differences. The size of the reply window will be ISILongReplyWin bit times when a long packet is expected in reply, i.e. this will be the max size of a long packet, allowing for worst case bit stuffing, bus turnarounds and timing differences. In both cases if an ACK is received the window will close and another packet can be transmitted but if an ACK is not received then the full length of the window must be waited out.

As no reply should be sent to a broadcast packet, no reply window should be required however all other long packets open a reply window in anticipation of an ACK. While the desire is to minimize the time between broadcast transmissions the simplest solution should be employed. This would imply the same size reply window as other long packets.

When a packet has been received without any errors the receiving ISI device must transmit its acknowledge packet (which may be either a long or short packet) before the reply window closes. When detected errors do occur the receiving ISI device will not send any response. The transmitting ISI device interprets this lack of response as a NAK indicating that errors were detected in the transmitted packet or that the receiving device was unable to receive the packet for some reason (e.g. its buffers are full). If a long packet was transmitted the transmitting ISI device will keep the transmitted packet in its transmit buffer for retransmission. If the transmitting device is the ISIMaster it will retransmit the packet immediately while if the transmitting device is an ISISlave it will retransmit the packet in response to the next ping it receives from the ISIMaster.

The transmitting ISI device will continue retransmitting the packet when it receives a NAK until it either receives an ACK or the number of retransmission attempts equals the value of the NumRetries register. If the transmission was unsuccessful then the transmitting device sets the TxErrorSticky bit in its ISIIntStatus register. The receiving device also sets the RxErrorSticky bit in its ISIIntStatus register whenever it detects a CRC error in an incoming packet and is not required to take any further action, as it is up to the transmitting device to detect and rectify the problem. The NumRetries registers in all ISI devices should be set to the same value for consistent operation. Note that successful transmission or reception of ping packets do not affect retransmission operation.

Note that a transmit error will cause the ISI to stop transmitting. CPU intervention will be required to resolve the source of the problem and to restart the ISI transmit operation. Receive errors however do not affect receive operation and they are collected to facilitate problem debug and to monitor the quality of the ISI physical channel. Transmit or receive errors should be extremely rare and their occurrence will most likely indicate a serious problem.

Note that broadcast packets are never acknowledged to avoid contention on the common ISI lines. If an ISISlave detects an error in a broadcast packet it should use the message passing mechanism described earlier to alert the ISIMaster to the error if it so wishes.

12.4.4.9 Sequence Bit Operation

To ensure that communication between transmitting and receiving ISI devices is correctly ordered a sequence bit is included in every long packet to keep both devices in step with each other. The sequence bit field is a constant for short or ping packets as they are not used for data transmission. In addition to the transmitted sequence bit all ISI devices keep two local sequence bits, one for each ISISubId. Furthermore each ISI device maintains a transmit sequence bit for each ISIId and ISISubId it is in communication with. For packets sourced from the external host (via USB) the transmit sequence bit is contained in the relevant USBEPnDest register while for packets sourced from the CPU the transmit sequence bit is contained in the CPUISITxBuffCntrl register. The sequence bits for received packets are stored in ISISubId0Seq and ISISubId1Seq registers. All ISI devices will initialize their sequence bits to 0 after reset. It is-the responsibility of software to ensure that the sequence bits of the transmitting and receiving ISI devices are correctly initialized each time a new source is selected for any ISIId.ISISubId channel.

Sequence bits are ignored by the receiving ISI device for broadcast packets. However the broadcasting ISI device is free to toggle the sequence in the broadcast packets since they will not affect operation. The SCB will do this for all USB source data so that there is no special treatment for the sequence bit of a broadcast packet in the transmitting device. CPU sourced broadcasts will have sequence bits toggled at the discretion of the program code.

Each SoPEC may also ignore the sequence bit on either of its ISISubId channels by setting the appropriate bit in the ISISubIdSeqMask register. The sequence bit should be ignored for ISISubId channels that will carry data that can originate from more than one source and is self ordering e.g. control messages.

A receiving ISI device will toggle its sequence bit addressed by the ISISubId only when the receiver is able to accept data and receives an error-free data packet addressed to it. The transmitting ISI device will toggle its sequence bit for that ISIId.ISISubId channel only when it receives a valid ACK handshake from the addressed ISI device.

FIG. 36 shows the transmission of two long packets with the sequence bit in both the transmitting and receiving devices toggling from 0 to 1 and back to 0 again. The toggling operation will continue in this manner in every subsequent transmission until an error condition is encountered.

When the receiving ISI device detects an error in the transmitted long packet or is unable to accept the packet (because of full buffers for example) it will not return any packet and it will not toggle its local sequence bit. An example of this is depicted in FIG. 37. The absence of any response prompts the transmitting device to retransmit the original (seq=0) packet. This time the packet is received without any errors (or buffer space may have been freed) so the receiving ISI device toggles its local sequence bit and responds with an ACK. The transmitting device then toggles its local sequence bit to a 1 upon correct receipt of the ACK.

However it is also possible for the ACK packet from the receiving ISI device to be corrupted and this scenario is shown in FIG. 38. In this case the receiving device toggles its local sequence bit to 1 when the long packet is received without error and replies with an ACK to the transmitting device. The transmitting device does not receive the ACK correctly and so does not change its local sequence bit. It then retransmits the seq=0 long packet. When the receiving device finds that there is a mismatch between the transmitted sequence bit and the expected (local) sequence bit is discards the long packet and replies with an ACK. When the transmitting ISI device correctly receives the ACK it updates its local sequence bit to a 1, thus restoring synchronization. Note that when the ISISubIdSeqMask bit for the addressed ISISubId is set then the retransmitted packet is not discarded and so a duplicate packet will be received. The data contained in the packet should be self-ordering and so the software handling these packets (most likely control messages) is expected to deal with this eventuality.

12.4.4.10 Flow Control

The ISI also supports flow control by treating it in exactly the same manner as an error in the received packet. Because the SCB enjoys greater guaranteed bandwidth to DRAM than both the ISI and USB can supply flow control should not be required during normal operation. Any blockage on a DMA channel will soon result in the NumRetries value being exceeded and transmission from that SoPEC being halted. If a SoPEC NAKS a packet because its RxBuffer is full it will flag an overflow condition. This condition can potentially cause a CPU interrupt, if the corresponding interrupt is enabled. The RxOverflowSticky bit of its ISIIntStatus register reflects this condition. Because flow control is treated in the same manner as an error the transmitting ISI device will not be able to differentiate a flow control condition from an error in the transmitted packet.

12.4.4.11 Auto-Ping Operation

While the CPU of the ISIMaster could send a ping packet by writing the appropriate header to the CPUISITxBuffCntrl register it is expected that all ping packets will be generated in the ISI itself. The use of automatically generated ping packets ensures that ISISlaves will be given access to the ISI bus with a programmable minimum guaranteed frequency in addition to whenever it would otherwise be idle. Five registers facilitate the automatic generation of ping messages within the ISI: PingSchedule0, PingSchedule1, PingSchedule2, ISITotalPeriod and ISILocalPeriod. Auto-pinging will be enabled if any bit of any of the PingScheduleN registers is set and disabled if all PingScheduleN registers are 0x0000.

Each bit of the 15-bit PingScheduleN register corresponds to an ISIId that is used in the Address field of the ping packet and a 1 in the bit position indicates that a ping packet is to be generated for that ISIId. A 0 in any bit position will ensure that no ping packet is generated for that ISIId. As ISISlaves may differ in their bandwidth requirement (particularly if a storage SoPEC is present) three different PingSchedule registers are used to allow an ISISlave receive up to three times the number of pings as another active ISISlave. When the ISIMaster is not sending long packets (sourced from either the CPU or USB in the case of a SoPEC ISIMaster) ISI ping packets will be transmitted according to the pattern given by the three PingScheduleN registers. The ISI will start with the lsb of PingSchedule0 register and work its way from lsb through msb of each of the PingScheduleN registers. When the msb of PingSchedule2 is reached the ISI returns to the lsb of PingSchedule0 and continues to cycle through each bit position of each PingScheduleN register. The ISI has more than enough time to work out the destination of the next ping packet while a ping or long packet is being transmitted.

With the addition of auto-ping operation we now have three potential sources of packets in an ISIMaster SoPEC: USB, CPU and auto-ping. Arbitration between the CPU and USB for access to the ISI is handled outside the ISI. To ensure that local packets get priority whenever possible and that ping packets can have some guaranteed access to the ISI we use two 4-bit counters whose reload value is contained in the ISITotalPeriod and ISILocalPeriod registers. As we saw in section 12.4.4.1 every ISI transaction is initiated by the ISIMaster transmitting either a long packet or a ping packet. The ISITotalPeriod counter is decremented for every ISI transaction (i.e. either long or ping) when its value is non-zero. The ISILocalPeriod counter is decremented for every local packet that is transmitted. Neither counter is decremented by a retransmitted packet. If the ISITotalPeriod counter is zero then ping packets will not change its value from zero. Both the ISITotalPeriod and ISILocalPeriod counters are reloaded by the next local packet transmit request after the ISITotalPeriod counter has reached zero and this local packet has priority over pings.

The amount of guaranteed ISI bandwidth allocated to both local and ping packets is determined by the values of the ISITotalPeriod and ISILocalPeriod registers. Local packets will always be given priority when the ISILocalPeriod counter is non-zero. Ping packets will be given priority when the ISILocalPeriod counter is zero and the ISITotalPeriod counter is still non-zero.

Note that ping packets are very likely to get more than their guaranteed bandwidth as they will be transmitted whenever the ISI bus would otherwise be idle (i.e. no pending local packets). In particular when the ISITotalPeriod counter is zero it will not be reloaded until another local packet is pending and so ping packets transmitted when the ISITotalPeriod counter is zero will be in addition to the guaranteed bandwidth. Local packets on the other hand will never get more than their guaranteed bandwidth because each local packet transmitted decrements both counters and will cause the counters to be reloaded when the ISITotalPeriod counter is zero. The difference between the values of the ISITotalPeriod and ISILocalPeriod registers determines the number of automatically generated ping packets that are guaranteed to be transmitted every ISITotalPeriod number of ISI transactions. If the ISITotalPeriod and ISILocalPeriod values are the same then the local packets will always get priority and could totally exclude ping packets if the CPU always has packets to send.

For example if ISITotalPeriod=0xC; ISILocalPeriod=0x8; PingSchedule0=0x0E; PingSchedule1=0x0C and PingSchedule2=0x08 then four ping messages are guaranteed to be sent in every 12 ISI transactions. Furthermore ISIId3 will receive 3 times the number of ping packets as ISId1 and ISId2 will receive twice as many as ISId1. Thus over a period of 36 contended ISI transactions (allowing for two full rotations through the three PingScheduleN registers) when local packets are always pending 24 local packets will be sent, ISId1 will receive 2 ping packets, ISId2 will receive 4 pings and ISId3 will receive 6 ping packets. If local traffic is less frequent then the ping frequency will automatically adjust upwards to consume all remaining ISI bandwidth.

12.4.5 Wake-Up From Sleep Mode

Either the PrintMaster SoPEC or the external host may place any of the ISISlave SoPECs in sleep mode prior to going into sleep mode itself. The ISISlave device should then ensure that its ISIWakeupEnable bit of the WakeupEnable register (see Table 34) is set prior to entering sleep mode. In an ISISlave device the ISI block will continue to receive power and clock during sleep mode so that it may monitor the gpio_isi_din lines for activity. When ISI activity is detected during sleep mode and the ISIWakeupEnable bit is set the ISI asserts the isi_cpr_reset_n signal. This will bring the rest of the chip out of sleep mode by means of a wakeup reset. See chapter 16 for more details of reset propagation.

12.4.6 Implementation

Although the ISI consists of either 2 or 4 ISI data lines over which a serial data stream is demultiplexed, each ISI line is treated as a separate serial link at the physical layer. This permits a certain amount of skew between the ISI lines that could not be tolerated if the lines were treated as a parallel bus. A lower Bit Error Rate (BER) can be achieved if the serial data recovery is performed separately on each serial link. FIG. 39 illustrates the ISI sub block partitioning.

12.4.6.1 ISI Sub-Block Partition

Definition of I/Os.

TABLE 34
ISI I/O
Port namePinsI/ODescription
Clock and Reset
isi_pclk1InISI primary clock.
isi_reset_n1InISI reset. Active low.
Asserting isi_reset_n will reset all ISI logic.
Synchronous to isi_pclk.
Configuration
isi_go1InISI GO. Active high.
When GO is de-asserted, all ISI statemachines are
reset to their idle states, all ISI output signals are de-
asserted, but all ISI counters retain their values.
When GO is asserted, all ISI counters are reset and all
ISI statemachines and output signals will return to their
normal mode of operation.
isi_master_select1InISI master select.
Determines whether the SoPEC is an ISIMaster or not
1 = ISIMaster
0 = ISISlave
isi_id[3:0]4InISI ID for this device.
isi_retries[3:0]4InISI number of retries.
Number of times a transmitting ISI device will attempt
retransmission of a NAK'd packet before aborting the
transmission and flagging an error. The value of this
configuration signal should not be changed while there
are valid packets in the Tx buffer.
isi_ping_schedule0[14:0]15InISI auto ping schedule #0.
Denotes which ISIIds will be receive ping packets. Note
that bit0 refers to ISIId0, bit1 to ISIId1...bit14 to ISIId14.
Setting a bit in this schedule will enable auto ping
generation for the corresponding ISI ID. The ISI will
start from the bit 0 of isi_ping_schedule0 and cycle
through to bit 14, generating pings for each bit that is
set. This operation will be performed in sequence from
isi_ping_schedule0 through isi_ping_schedule2.
isi_ping_schedule1[14:0]15InAs per isi_ping_schedule0.
isi_ping_schedule2[14:0]15InAs per isi_ping_schedule0.
isi_total_period[3:0]4InReload value of the ISI Total Period Counter.
isi_local_period[3:0]4InReload value of the ISI Local Period Counter.
isi_number_pins1InNumber of active ISI data pins.
Used to select how many serial data pins will be used
to transmit and receive data. Should reflect the number
of ISI device data pins that are in use.
1 = isi_data[3:0] active
0 = isi_data[1:0] active
isi_turn_around[3:0]4InISI bus turn around time in ISI clock cycles (32 MHz).
isi_short_reply_win[4:0]5InISI long packet reply window in ISI clock cycles
(32 MHz).
isi_long_reply_win[8:0]9InISI long packet reply window in ISI clock cycles
(32 MHz).
isi_tx_enable1InISI transmit enable. Active high.
Enables ISI transmission of long or ping packets. ACKs
may still be transmitted when this bit is 0. The value of
this configuration signal should not be changed while
there are valid packets in the Tx buffer.
isi_rx_enable1InISI receive enable. Active high.
Enables ISI packet reception. Any activity on the ISI
bus will be ignored when this signal is de-asserted.
This signal should only be de-asserted if the ISI block
is not required for use in the design.
isi_bit_stuff_rate[3:0]1InISI bit stuffing limit.
Allows the bit stuffing counter value to be programmed.
Is loaded into the 4 upper bits of the 7bit wide bit
stuffing counter. The lower bits are always loaded with
b111, to prevent bit stuffing for less than 7 consecutive
ones or zeroes. E.g.
b000: stuff_count = b0000111: bit stuff after 7
consecutive 0/1
b111: stuff_count = b1111111: bit stuff after127
consecutive 0/1
Serial Link Signals
isi_ser_data_in[3:0]4InISI Serial data inputs.
Each bit corresponds to a separate serial link.
isi_ser_data_out[3:0]4OutISI Serial data outputs.
Each bit corresponds to a separate serial link.
isi_ser_data_en[3:0]4OutISI Serial data driver enables. Active high.
Each bit corresponds to a separate serial link.
Tx Packet Buffer
isi_tx_wr_en1InISI Tx FIFO write enable. Active high.
Asserting isi_tx_wr_en will write the 64 bit data on
isi_tx_wr_data to the FIFO, providing that space is
available in the FIFO. If isi_tx_wr_en remains asserted
after the last entry in the current packet is written, the
write operation will wrap around to the start of the next
packet, providing that space is available for a second
packet in the FIFO.
isi_tx_wr_data[63:0]64InISI Tx FIFO write data.
isi_tx_ping1InISI Tx FIFO ping packet select. Active high.
Asserting isi_tx_ping will queue a ping packet for
transmission, as opposed to a long packet. Although
there is no data payload for a ping packet, a packet
location in the FIFO is used as a ‘place holder’ for the
ping packet. Any data written to the associated packet
location in the FIFO will be discarded when the ping
packet is transmitted.
isi_tx_id[3:0]5InISI Tx FIFO packet ID.
ISI ID for each packet written to the FIFO. Registered
when the last entry of the packet is written.
isi_tx_sub_id1InISI Tx FIFO packet sub ID.
ISI sub ID for each packet written to the FIFO.
Registered when the last entry of the packet is written.
isi_tx_pkt_count[1:0]2OutISI Tx FIFO packet count.
Indicates the number of packets contained in the FIFO.
The FIFO has a capacity of 2 × 256 bit packets. Range
is b00->b10.
isi_tx_word_count[2:0]3OutISI Tx FIFO current packet word count.
Indicates the number of words contained in the current
Tx packet location of the Tx FIFO. Each packet location
has a capacity of 4 × 64 bit words. Range is b000->b100.
isi_tx_empty1OutISI Tx FIFO empty. Active high.
Indicates that no packets are present in the FIFO.
isi_tx_full1OutISI Tx FIFO full. Active high.
Indicates that 2 packets are present in the FIFO,
therefore no more packets can be transmitted.
isi_tx_over_flow1OutISI Tx FIFO over flow. Active high.
Indicates that a write operation was performed on a full
FIFO. The write operation will have no effect on the
contents of the FIFO or the write pointer.
isi_tx_error1OutISI Tx FIFO error. Active high.
Indicates that an error occurred while transmitting the
packet currently at the head of the FIFO. This will
happen if the number of transmission attempts exceeds
isi_tx_retries.
isi_tx_desc[2:0]3OutISI Tx packet descriptor field.
ISI packet descriptor field for the packet currently at the
head of the FIFO. See Table for details. Only valid
when isi_tx_empty = 0, i.e. when there is a valid packet
in the FIFO.
isi_tx_addr[4:0]5OutISI Tx packet address field.
ISI address field for the packet currently at the head of
the FIFO. See Table for details. Only valid when
isi_tx_empty = 0, i.e. when there is a valid packet in the
FIFO.
Rx Packet FIFO
isi_rx_rd_en1InISI Rx FIFO read enable. Active high.
Asserting isi_rx_rd_en will drive isi_rx_rd_data with
valid data, from the Rx packet at the head of the FIFO,
providing that data is available in the FIFO. If
isi_rx_rd_en remains asserted after the last entry is
read from the current packet, the read operation will
wrap around to the start of the next packet, providing
that a second packet is available in the FIFO.
isi_rx_rd_data[63:0]64OutISI Rx FIFO read data.
isi_rx_sub_id1OutISI Rx packet sub ID.
Indicates the ISI sub ID associated with the packet at
the head of the Rx FIFO.
isi_rx_pkt_count[1:0]2OutISI Rx FIFO packet count.
Indicates the number of packets contained in the FIFO.
The FIFO has a capacity of 2 × 256 bit packets. Range
is b00->b10.
isi_rx_word_count[2:0]3OutISI Rx FIFO current packet word count.
Indicates the number of words contained in the Rx
packet location at the head of the FIFO. Each packet
location has a capacity of 4 × 64 bit words. Range is
b000->b100.
isi_rx_empty1OutISI Rx FIFO empty. Active high.
Indicates that no packets are present in the FIFO.
isi_rx_full1OutISI Rx FIFO full. Active high.
Indicates that 2 packets are present in the FIFO,
therefore no more packets can be received.
isi_rx_over_flow1OutISI Rx FIFO over flow. Active high.
Indicates that a packet was addressed to the local ISI
device, but the Rx FIFO was full, resulting in a NAK.
isi_rx_under_run1OutISI Rx FIFO under run. Active high.
Indicates that a read operation was performed on an
empty FIFO. The invalid read will return the contents of
the memory location currently addressed by the FIFO
read pointer and will have no effect on the read pointer.
isi_rx_frame_error1OutISI Rx framing error. Active high.
Asserted by the ISI when a framing error is detected in
the received packet, which can be caused by an
incorrect Start or Stop field or by bit stuffing errors. The
associated packet will be dropped.
isi_rx_crc_error1OutISI Rx CRC error. Active high.
Asserted by the ISI when a CRC error is detected in an
incoming packet. Other than dropping the errored
packet ISI reception is unaffected by a CRC Error.

12.4.6.2 ISI Serial Interface Engine (isi_sie)

There are 4 instantiations of the isi_sie sub block in the ISI, 1 per ISI serial link. The isi_sie is responsible for Rx serial data sampling, Tx serial data output and bit stuffing.

Data is sampled based on a phase detection mechanism. The incoming ISI serial data stream is over sampled 5 times per ISI bit period. The phase of the incoming data is determined by detecting transitions in the ISI serial data stream, which indicates the ISI bit boundaries. An ISI bit boundary is defined as the sample phase at which a transition was detected.

The basic functional components of the isi_sie are detailed in FIG. 40. These components are simply a grouping of logical functionality and do not necessarily represent hierarchy in the design.

12.4.6.2.1 SIE Edge Detection and Data I/O

The basic structure of the data I/O and edge detection mechanism is detailed in FIG. 41.

NOTE: Serial data from the receiver in the pad MUST be synchronized to the isi_pclk domain with a 2 stage shift register external to the ISI, to reduce the risk of metastability. ser_data_out and ser_data_en should be registered externally to the ISI.

The Rx/Tx statemachine drives ser_data_en, stuff1_en and stuff0_en. The signals stuff1_en and stuff0_en cause a one or a zero to be driven on ser_data_out when they are asserted, otherwise fifo_rd_data is selected.

12.4.6.2.2 SIE Rx/Tx Statemachine

The Rx/Tx statemachine is responsible for the transmission of ISI Tx data and the sampling of ISI Rx data. Each ISI bit period is 5 isi_pclk cycles in duration.

The Tx cycle of the Rx/Tx statemachine is illustrated in FIG. 42. It generates each ISI bit that is transmitted. States tx0->tx4 represent each of the 5 isi_pclk phases that constitute a Tx ISI bit period. ser_data_en controls the tristate enable for the ISI line driver in the bidirectional pad, as shown in FIG. 41. rx_tx_cycle is asserted during both Rx and Tx states to indicate an active Rx or Tx cycle. It is primarily used to enable bit stuffing.

NOTE: All statemachine signals are assumed to be ‘0’ unless otherwise stated.

The Tx cycle for Tx bit stuffing when the Rx/Tx statemachine inserts a ‘0’ into the bitstream can be seen in FIG. 43.

NOTE: All statemachine signals are assumed to be ‘0’ unless otherwise stated

The Tx cycle for Tx bit stuffing when the RxTx statemachine inserts a ‘1’ into the bitstream can be seen in FIG. 44.

NOTE: All statemachine signals are assumed to be ‘0’ unless otherwise stated

The tx* and stuff* states are detailed separately for clarity. They could be easily combined when coding the statemachine, however it would be better for verification and debugging if they were kept separate.

The Rx cycle of the ISI Rx/Tx statemachine is detailed in FIG. 45. The Rx cycle of the Rx/Tx Statemachine, samples each ISI bit that is received. States rx0->rx4 represent each of the 5 isi_pclk phases that constitute a Rx ISI bit period.

The optimum sample position for an ideal ISI bit period is 2 isi_pclk cycles after the ISI bit boundary sample, which should result in a data sample close to the centre of the ISI bit period. rx_sample is asserted during the rx2 state to indicate a valid ISI data sample on rx_bit, unless the bit should be stripped when flagged by the bit stuffing statemachine, in which case rx_sample is not asserted during rx2 and the bit is not written to the FIFO. When edge is asserted, it resets the Rx cycle to the rx0 state, from any rx state. This is how the isi_sie tracks the phase of the incoming data. The Rx cycle will cycle through states rx0->rx4 until edge is asserted to reset the sample phase, or a tx_req is asserted indicating that the ISI needs to transmit.

Due to the 5 times oversampling a maximum phase error of 0.4 of an ISI bit period (2 isi_pclk cycles out of 5) can be tolerated.

NOTE: All statemachine signals are assumed to be ‘0’ unless otherwise stated.

An example of the Tx data generation mechanism is detailed in FIG. 46. tx_req and fifo_wr_tx are driven by the framer block.

An example of the Rx data sampling functional timing is detailed in FIG. 47. The dashed lines on the ser_data_in_ff signal indicate where the Rx/Tx statemachine perceived the bit boundary to be, based on the phase of the last ISI bit boundary. It can be seen that data is sampled during the same phase as the previous bit was, in the absence of a transition.

12.4.6.2.3 SIE Rx/Tx FIFO

The Rx/Tx FIFO is a 7×1 bit synchronous look-ahead FIFO that is shared for Tx and Rx operations. It is required to absorb any Rx/Tx latency caused by bit stripping/stuffing on a per ISI line basis, i.e. some ISI lines may require bit stripping/stuffing during an ISI bit period while the others may not, which would lead to a loss of synchronization between the data of the different ISI lines, if a FIFO were not present in each isi_sie.

The basic functional components of the FIFO are detailed in FIG. 48. tx_ready is driven by the Rx/Tx statemachine and selects which signals control the read and write operations. tx_ready=1 during ISI transmission and selects the fifo_*tx control and data signals. tx_ready=0 during ISI reception and selects the fifo_*rx control and data signals. fifo_reset is driven by the Rx/Tx statemachine. It is active high and resets the FIFO and associated logic before/after transmitting a packet to discard any residual data.

The size of the FIFO is based on the maximum bit stuffing frequency and the size of the shift register used to segment/re-assemble the multiple serial streams in the ISI framing logic. The maximum bit stuffing frequency is every 7 consecutive ones or zeroes. The shift register used is 32 bits wide. This implies that the maximum number of stuffed bits encountered in the time it takes to fill/empty the shift register if 4. This would suggest that 4×1 bit would be the minimum ideal size of the FIFO. However it is necessary to allow for different skew and phase error between the ISI lines, hence a 7×1 bit FIFO.

The FIFO is controlled by the isi_sie during packet reception and is controlled by the isi_frame block during packet transmission. This is illustrated in FIG. 49. The signal tx_ready selects which mode the FIFO control signals operate in. When tx_ready=0, i.e. Rx mode, the isi_sie control signals rx_sample, fifo_rd_rx and ser_data_in_ff are selected. When tx_ready=1, i.e. Tx mode, the sie_frame control signals fifo_wr_tx, fifo_rd_tx and fifo_wr_data_tx are selected.

12.4.6.3 Bit Stuffing

Programmable bit stuffing is implemented in the isi_sie. This is to allow the system to determine the amount of bit stuffing necessary for a specific ISI system devices. It is unlikely that bit stuffing would be required in a system using a 100 ppm rated crystal. However, a programmable bit stuffing implementation is much more versatile and robust.

The bit stuffing logic consists of a counter and a statemachine that track the number of consecutive ones or zeroes that are transmitted or received and flags the Rx/Tx statemachine when the bit stuffing limit has been reached. The counter, stuff count, is a 7 bit counter, which decrements when rx_sample is asserted on a Rx cycle or when fifo_rd_tx is asserted on a Tx cycle. The upper 4 bits of stuff_count are loaded with isi_bit_stuff_rate. The lower 3 bits of stuff_count are always loaded with b111, i.e. for isi_bit_stuff_rate=b000, the counter would be loaded with b0000111. This is to prevent bit stuffing for less than 7 consecutive ones or zeroes. This allows the bit stuffing limit to be set in the range 7->127 consecutive ones or zeroes.

NOTE: It is extremely important that a change in the bit stuffing rate, isi_bit_stuff_rate, is carefully coordinated between ISI devices in a system. It is obvious that ISI devices will not be able to communicate reliably with each other with different bit stuffing settings. It is recommended that all ISI devices in a system default to the safest bit stuffing rate (isi_bit_stuff_rate=b000) at reset. The system can then co-ordinate the change to an optimum bit stuffing rate.

The ISI bit stuffing statemachine Tx cycle is shown in FIG. 50. The counter is loaded when stuff_count_load is asserted.

NOTE: All statemachine signals are assumed to be ‘0’ unless otherwise stated.

The ISI bit stuffing statemachine Rx cycle is shown in FIG. 51. It should be noted that the statemachine enters the strip state when stuff_count=0x2. This is because the statemachine can only transition to rx0 or rx1 when rx_sample is asserted as it needs to be synchronized to changes in sampling phase introduced by the Rx/Tx statemachine. Therefore a one or a zero has already been sampled by the time it enters rx0 or rx1. This is not the case for the Tx cycle, as it will always have a stable 5 isi_pclk cycles per bit period and relies purely on the data value when entering tx0 or tx1. The Tx cycle therefore enters stuff1 or stuff0 when stuff_count=0x1.

NOTE: All statemachine signals are assumed to be ‘0’ unless otherwise stated.

12.4.6.4 ISI Framing and CRC Sub-Block (isi_frame)

12.4.6.4.1 CRC Generation/Checking

A Cyclic Redundancy Checksum (CRC) is calculated over all fields except the start and stop fields for each long or ping packet transmitted. The receiving ISI device will perform the same calculation on the received packet to verify the integrity of the packet. The procedure used in the CRC generation/checking is the same as the Frame Checking Sequence (FCS) procedure used in HDLC, detailed in ITU-T Recommendation T30[39].

For generation/checking of the CRC field, the shift register illustrated in FIG. 52 is used to perform the modulo 2 division on the packet contents by the polynomial G(x)=x16+x12+x5+1.

To generate the CRC for a transmitted packet, where T(x)=[Packet Descriptor field, Address field, Data Payload field] (a ping packet will not contain a data payload field).

    • Set the shift register to 0xFFFF.
    • Shift T(x) through the shift register, LSB first. This can occur in parallel with the packet transmission.
    • Once the each bit of T(x) has been shifted through the register, it will contain the remainder of the modulo 2 division T(x)/G(x).
    • Perform a ones complement of the register contents, giving the CRC field which is transmitted MSB first, immediately following the last bit of M(x
      • To check the CRC for a received packet, where R(x)=[Packet Descriptor field, Address field, Data Payload field, CRC field] (a ping packet will not contain a data payload field).
      • Set the shift register to 0xFFFF.
      • Shift R(x) through the shift register, LSB first. This can occur in parallel with the packet reception.
      • Once each bit of the packet has been shifted through the register, it will contain the remainder of the modulo 2 division R(x)/G(x).
      • The remainder should equal b0001110100001111, for a packet without errors.
        12.5 CTRL (Control Sub-Block)
        12.5.1 Overview

The CTRL is responsible for high level control of the SCB sub-blocks and coordinating access between them. All control and status registers for the SCB are contained within the CTRL and are accessed via the CPU interface. The other major components of the CTRL are the SCB Map logic and the DMA Manager logic.

12.5.2 SCB Mapping

In order to support maximum flexibility when moving data through a multi-SoPEC system it is possible to map any USB endpoint onto either DMAChannel within any SoPEC in the system. The SCB map, and indeed the SCB itself is based around the concept of an ISIId and an ISISubId. Each SoPEC in the system has a unique ISIId and two ISISubIds, namely ISISubId0 and ISISubId1. We use the convention that ISISubId0 corresponds to DMAChannel0 in each SoPEC and ISISubId1 corresponds to DMAChannel1. The naming convention for the ISIId is shown in Table 35 below and this would correspond to a multi-SoPEC system such as that shown in FIG. 27. We use the term ISIId instead of SoPECId to avoid confusion with the unique ChipID used to create the SoPEC_id and SoPEC_id_key (see chapter 17 and [9] for more details).

TABLE 35
ISIId naming convention
ISIIdSoPEC to which it refers
0-14Standard device ISIIds (0 is the power-on reset value)
15Broadcast ISIId

The combined ISIId and ISISubId therefore allows the ISI to address DMAChannel0 or DMAChannel1 on any SoPEC device in the system. The ISI, DMA manager and SCB map hardware use the ISIId and ISISubId to handle the different data streams that are active in a multi-SoPEC system as does the software running on the CPU of each SoPEC. In this document we will identify DMAChannels as ISIx.y where x is the ISIId and y is the ISISubId. Thus ISI2.1 refers to DMAChannel1 of ISISlave2. Any data sent to a broadcast channel, i.e. ISI15.0 or ISI15.1, are received by every ISI device in the system including the ISIMaster (which may be an ISI-Bridge). The USB device controller and software stacks however have no understanding of the ISIId and ISISubId but the Silverbrook printer driver software running on the external host does make use of the ISIId and ISISubId. USB is simply used as a data transport—the mapping of USB device endpoints onto ISIId and SubId is communicated from the external host Silverbrook code to the SoPEC Silverbrook code through USB control (or possibly bulk data) messages i.e. the mapping information is simply data payload as far as USB is concerned. The code running on SoPEC is responsible for parsing these messages and configuring the SCB accordingly.

The use of just two DMAChannels places some limitations on what can be achieved without software intervention. For every SoPEC in the system there are more potential sources of data than there are sinks. For example an ISISlave could receive both control and data messages from the ISIMaster SoPEC in addition to control and data from the external host, either specifically addressed to that particular ISISlave or over the broadcast ISI channel. However all ISISlaves only have two possible data sinks, i.e. DMAChannelz0 and DMAChannel1. Another example is the ISIMaster in a multi-SoPEC system which may receive control messages from each SoPEC in addition to control and data information from the external host (e.g. over USB). In this case all of the control messages are in contention for access to DMAChannel0. We resolve these potential conflicts by adopting the following conventions:

1) Control messages may be interleaved in a memory buffer: The memory buffer that the DMAChannel0 points to should be regarded as a central pool of control messages. Every control message must contain fields that identify the size of the message, the source and the destination of the control message. Control messages may therefore be multiplexed over a DMAChannel which allows several control message sources to address the same DMAChannel. Furthermore, if SoPEC-type control messages contain source and destination fields it is possible for the external host to send control messages to individual SoPECs over the ISI15.0 broadcast channel.

2) Data messages should not be interleaved in a memory buffer: As data messages are typically part of a much larger block of data that is being transferred it is not possible to control their contents in the same manner as is possible with the control messages. Furthermore we do not want the CPU to have to perform reassembly of data blocks. Data messages from different sources cannot be interleaved over the same DMAChannel—the SCB map must be reconfigured each time a different data source is given access to the DMAChannel.

3) Every reconfiguration of the SCB map requires the exchange of control messages: SoPEC's SCB map reset state is shown in Table and any subsequent modifications to this map require the exchange of control messages between the SoPEC and the external host. As the external host is expected to control the movement of data in any SoPEC system it is anticipated that all changes to the SCB map will be performed in response to a request from the external host. While the SoPEC could autonomously reconfigure the SCB map (this is entirely up to the software running on the SoPEC) it should not do so without informing the external host in order to avoid data being misrouted.

An example of the above conventions in operation is worked through in section 12.5.2.3.

12.5.2.1 SCB Map Rules

The operation of the SCB map is described by these 2 rules:

Rule 1: A packet is routed to the DMA manager if it originates from the USB device core and has an ISIId that matches the local SoPEC ISIId.

Rule 2: A packet is routed to the ISI if it originates from the CPU or has an ISIId that does not match the local SoPEC ISIId.

If the CPU erroneously addresses a packet to the ISIId contained in the ISIId register (i.e. the ISIId of the local SoPEC) then that packet will be transmitted on the ISI rather than be sent to the DMA manager. While this will usually cause an error on the ISI there is one situation where it could be beneficial, namely for initial dialog in a 2 SoPEC system as both devices come out of reset with an ISIId of 0.

12.5.2.2 External Host to ISIMaster SoPEC Communication

Although the SCB map configuration is independent of ISIMaster status, the following discussion on SCB map configurations assumes the ISIMaster is a SoPEC device rather than an ISI bridge chip, and that only a single USB connection to the external host is present. The information should apply broadly to an ISI-Bridge but we focus here on an ISIMaster SoPEC for clarity.

As the ISIMaster SoPEC represents the printer device on the PC USB bus it is required by the USB specification to have a dedicated control endpoint, EP0. At boot time the ISIMaster SoPEC will also require a bulk data endpoint to facilitate the transfer of program code from the external host. The simplest SCB map configuration, i.e. for a single stand-alone SoPEC, is sufficient for external host to ISIMaster SoPEC communication and is shown in Table 36.

TABLE 36
Single SoPEC SCB map configuration
SourceSink
EP0ISI0.0
EP1ISI0.1
EP2nc
EP3nc
EP4nc

In this configuration all USB control information exchanged between the external host and SoPEC over EP0 (which is the only bidirectional USB endpoint). SoPEC specific control information (printer status, DNC info etc.) is also exchanged over EP0.

All packets sent to the external host from SoPEC over EP0 must be written into the DMA mapped EP buffer by the CPU (LEON-PC dataflow in FIG. 29). All packets sent from the external host to SoPEC are placed in DRAM by the DMA Manager, where they can be read by the CPU (PC-DIU dataflow in FIG. 29). This asymmetry is because in a multi-SoPEC environment the CPU will need to examine all incoming control messages (i.e. messages that have arrived over DMAChannel0) to ascertain their source and destination (i.e. they could be from an ISISlave and destined for the external host) and so the additional overhead in having the CPU move the short control messages to the EP0 FIFO is relatively small. Furthermore we wish to avoid making the SCB more complicated than necessary, particularly when there is no significant performance gain to be had as the control traffic will be relatively low bandwidth.

The above mechanisms are appropriate for the types of communication outlined in sections 12.1.2.1.1 through 12.1.2.1.4

12.5.2.3 Broadcast Communication

The SCB configuration for broadcast communication is also the default, post power-on reset, configuration for SoPEC and is shown in Table 37.

TABLE 37
Default SoPEC SCB map configuration
SourceSink
EP0ISI0.0
EP1ISI0.1
EP2ISI15.0
EP3ISI15.1
EP4ISI1.1

USB endpoints EP2 and EP3 are mapped onto ISISubID0 and ISISubId1 of ISIId15 (the broadcast ISIId channel). EP0 is used for control messages as before and EP1 is a bulk data endpoint for the ISIMaster SoPEC. Depending on what is convenient for the boot loader software, EP1 may or may not be used during the initial program download, but EP1 is highly likely to be used for compressed page or other program downloads later. For this reason it is part of the default configuration. In this setup the USB device configuration will take place, as it always must, by exchanging messages over the control channel (EP0).

One possible boot mechanism is where the external host sends the bootloader1 program code to all SoPECs by broadcasting it over EP3. Each SoPEC in the system then authenticates and executes the bootloader1 program. The ISIMaster SoPEC then polls each ISISlave (over the ISIx.0 channel). Each ISISlave ascertains its ISIId by sampling the particular GPIO pins required by the bootloader1 and reporting its presence and status back to the ISIMaster. The ISIMaster then passes this information back to the external host over EP0. Thus both the external host and the ISIMaster have knowledge of the number of SoPECs, and their ISIIds, in the system. The external host may then reconfigure the SCB map to better optimise the SCB resources for the particular multi-SoPEC system. This could involve simplifying the default configuration to a single SoPEC system or remapping the broadcast channels onto DMAChannels in individual ISISlaves.

The following steps are required to reconfigure the SCB map from the configuration depicted in Table to one where EP3 is mapped onto ISI1.0:

    • 1) The external host sends a control message(s) to the ISIMaster SoPEC requesting that USB EP3 be remapped to ISI1.0
    • 2) The ISIMaster SoPEC sends a control message to the external host informing it that EP3 has now been mapped to ISI1.0 (and therefore the external host knows that the previous mapping of ISI15.1 is no longer available through EP3).
    • 3) The external host may now send control messages directly to ISISlave1 without requiring any CPU intervention on the ISIMaster SoPEC
      12.5.2.4 External Host to ISISlave SoPEC Communication

If the ISIMaster is configured correctly (e.g. when the ISIMaster is a SoPEC, and that SoPEC's SCB map is configured correctly) then data sent from the external host destined for an ISISlave will be transmitted on the ISI with the correct address. The ISI automatically forwards any data addressed to it (including broadcast data) to the DMA channel with the appropriate ISISubId. If the ISISlave has data to send to the external host it must do so by sending a control message to the ISIMaster identifying the external host as the intended recipient. It is then the ISIMaster's responsibility to forward this message to the external host.

With this configuration the external host can communicate with the ISISlave via broadcast messages only and this is the mechanism by which the bootloader1 program is downloaded. The ISISlave is unable to communicate with the external host (or the ISIMaster) until the bootloader1 program has successfully executed and the ISISlave has determined what its ISIId is. After the bootloader1 program (and possibly other programs) has executed the SCB map of the ISIMaster may be reconfigured to reflect the most appropriate topology for the particular multi-SoPEC system it is part of.

All communication from an ISISlave to external host is either achieved directly (if there is a direct USB connection present for example) or by sending messages via the ISIMaster. The ISISlave can never initiate communication to the external host. If an ISISlave wishes to send a message to the external host via the ISIMaster it must wait until it is pinged by the ISIMaster and then send a the message in a long packet addressed to the ISIMaster. When the ISIMaster receives the message from the ISISlave it first examines it to determine the intended destination and will then copy it into the EP0 FIFO for transmission to the external host. The software running on the ISIMaster is responsible for any arbitration between messages from different sources (including itself) that are all destined for the external host.

The above mechanisms are appropriate for the types of communication outlined in sections 12.1.2.1.5 and 12.1.2.1.6.

12.5.2.5 ISIMaster to ISISlave Communication

All ISIMaster to ISISlave communication takes place over the ISI. Immediately after reset this can only be by means of broadcast messages. Once the bootloader1 program has successfully executed on all SoPECs in a multi-SoPEC system the ISIMaster can communicate with each SoPEC on an individual basis.

If an ISISlave wishes to send a message to the ISIMaster it may do so in response to a ping packet from the ISIMaster. When the ISIMaster receives the message from the ISISlave it must interpret the message to determine if the message contains information required to be sent to the external host. In the case of the ISIMaster being a SoPEC, software will transfer the appropriate information into the EP0 FIFO for transmission to the external host.

The above mechanisms are appropriate for the types of communication outlined in sections 12.1.2.3.3 and 12.1.2.3.4.

12.5.2.6 ISISlave to ISISlave Communication

ISISlave to ISISlave communication is expected to be limited to two special cases: (a) when the PrintMaster is not the ISIMaster and (b) when a storage SoPEC is used. When the PrintMaster is not the ISIMaster then it will need to send control messages (and receive responses to these messages) to other ISISlaves. When a storage SoPEC is present it may need to send data to each SoPEC in the system. All ISISlave to ISISlave communication will take place in response to ping messages from the ISIMaster.

12.5.2.7 Use of the SCB Map in an ISISlave with a External Host Connection

After reset any SoPEC (regardless of ISIMaster/Slave status) with an active USB connection will route packets from EP0,1 to DMA channels 0,1 because the default SCB map is to map EP0 to ISIId0.0 and EP1 to ISIId0.1 and the default ISIId is 0. At some later time the SoPEC learns its true ISIId for the system it is in and re-configures its ISIId and SCB map registers accordingly. Thus if the true ISIId is 3 the external host could reconfigure the SCB map so that EP0 and EP1 (or any other endpoints for that matter) map to ISIId3.0 and 3.1 respectively. The co-ordination of the updating of the ISIId registers and the SCB map is a matter for software to take care of. While the AutoMasterEnable bit of the ISICntrl register is set the external host must not send packets down EP2-4 of the USB connection to the device intended to be an ISISlave. When AutoMasterEnable has been cleared the external host may send data down any endpoint of the USB connection to the ISISlave.

The SCB map of an ISISlave can be configured to route packets from any EP to any ISIId.ISISubId oust as an ISIMaster can). As with an ISIMaster these packets will end up in the SCBTxBuffer but while an ISIMaster would just transmit them when it got a local access slot (from ping arbitration) the ISISlave can only transmit them in response to a ping. All this would happen without CPU intervention on the ISISlave (or ISIMaster) and as long as the ping frequency is sufficiently high it would enable maximum use of the bandwidth on both USB buses.

12.5.3 DMA Manager

The DMA manager manages the flow of data between the SCB and the embedded DRAM. Whilst the CPU could be used for the movement of data in SoPEC, a DMA manager is a more efficient solution as it will handle data in a more predictable fashion with less latency and requiring less buffering. Furthermore a DMA manager is required to support the ISI transfer speed and to ensure that the SoPEC could be used with a high speed ISI-Bridge chip in the future.

The DMA manager utilizes 2 write channels (DMAChannel0, DMAChannel1) and 1 read/write channel (DMAChannel2) to provide 2 independent modes of access to DRAM via the DIU interface:

    • USBD/ISI type access.
    • USBH type access.

DIU read and write access is in bursts of 4×64 bit words. Byte aligned write enables are provided for write access. Data for DIU write accesses will be read directly from the buffers contained in the respective SCB sub-blocks. There is no internal SCB DMA buffer. The DMA manager handles all issues relating to byte/word/longword address alignment, data endianness and transaction scheduling. If a DMA channel is disabled during a DMA access, the access will be completed. Arbitration will be performed between the following DIU access requests:

    • USBD write request.
    • ISI write request.
    • USBH write request.
    • USBH read request.

DMAChannel0 will have absolute priority over any DMA requesters. In the absence of DMAChannel0 DMA requests, arbitration will be performed in a round robin manner, on a per cycle basis over the other channels.

12.5.3.1 DMA Effective Bandwidth

The DIU bandwidth available to the DMA manager must be set to ensure adequate bandwidth for all data sources, to avoid back pressure on the USB and the ISI. This is achieved by setting the output (i.e. DIU) bandwidth to be greater than the combined input bandwidths (i.e. USBD+USBH+ISI). The required bandwidth is expected to be 160 Mbits/s (1 bit/cycle @ 160 MHz). The guaranteed DIU bandwidth for the SCB is programmable and may need further analysis once there is better knowledge of the data throughput from the USB IP cores.

12.5.3.2 USBDIISI DMA Access

The DMA manager uses the two independent unidirectional write channels for this type of DMA access, one for each ISISubID, to control the movement of data. Both DMAChannel0 and DMAChannel1 only support write operation and can transfer data from any USB device DMA mapped EP buffer and from the ISI receive buffer to separate circular buffers in DRAM, corresponding to each DMA channel.

While the DMA manager performs the work of moving data the CPU controls the destination and relative timing of data flows to and from the DRAM. The management of the DRAM data buffers requires the CPU to have accurate and timely visibility of both the DMA and PEP memory usage. In other words when the PEP has completed processing of a page band the CPU needs to be aware of the fact that an area of memory has been freed up to receive incoming data. The management of these buffers may also be performed by the external host.

12.5.3.2.1 Circular Buffer Operation

The DMA manager supports the use of circular buffers for both DMAChannels. Each circular buffer is controlled by 5 registers: DMAnBottomAdr, DMAnTopAdr, DMAnMaxAdr, DMAnCurrWPtr and DMAnIntAdr. The operation of the circular buffers is shown in FIG. 53 below.

Here we see two snapshots of the status of a circular buffer with (b) occurring sometime after (a) and some CPU writes to the registers occurring in between (a) and (b). These CPU writes are most likely to be as a result of a finished band interrupt (which frees up buffer space) but could also have occurred in a DMA interrupt service routine resulting from DMAnIntAdr being hit. The DMA manager will continue filling the free buffer space depicted in (a), advancing the DMAnCurrWPtr after each write to the DIU. Note that the DMACurrWPtr register always points to the next address the DMA manager will write to. When the DMA manager reaches the address in DMAnIntAdr (i.e. DMACurrWPtr=DMAnIntAdr) it will generate an interrupt if the DMAnIntAdrMask bit in the DMAMask register is set. The purpose of the DMAnintAdr register is to alert the CPU that data (such as a control message or a page or band header) has arrived that it needs to process. The interrupt routine servicing the DMA interrupt will change the DMAnintAdr value to the next location that data of interest to the CPU will have arrived by.

In the scenario shown in FIG. 53 the CPU has determined (most likely as a result of a finished band interrupt) that the filled buffer space in (a) has been freed up and is therefore available to receive more data. The CPU therefore moves the DMAnMaxAdr to the end of the section that has been freed up and moves the DMAnIntAdr address to an appropriate offset from the DMAnMaxAdr address. The DMA manager continues to fill the free buffer space and when it reaches the address in DMAnTopAdr it wraps around to the address in DMAnBottomAdr and continues from there. DMA transfers will continue indefinitely in this fashion until the DMA manager reaches the address in the DMAnMaxAdr register.

The circular buffer is initialized by writing the top and bottom addresses to the DMAnTopAdr and DMAnBottomAdr registers, writing the start address (which does not have to be the same as the DMAnBottomAdr even though it usually will be) to the DMAnCurrWPtr register and appropriate addresses to the DMAnIntAdr and DMAnMaxAdr registers. The DMA operation will not commence until a 1 has been written to the relevant bit of the DMAChanEn register.

While it is possible to modify the DMAnTopAdr and DMAnBottomAdr registers after the DMA has started it should be done with caution. The DMAnCurrWPtr register should not be written to while the DMAChannel is in operation. DMA operation may be stalled at any time by clearing the appropriate bit of the DMAChanEn register or by disabling an SCB mapping or ISI receive operation.

12.5.3.2.2 Non-Standard Buffer Operation

The DMA manager was designed primarily for use with a circular buffer. However because the DMA pointers are tested for equality (i.e. interrupts generated when DMAnCurrWPtr=DMAIntAdr or DMAnCurrWPtr=DMAMaxAdr) and no bounds checking is performed on their values (i e. neither DMAnIntAdr nor DMAnMaxAdr are checked to see if they lie between DMAnBottomAdr and DMAnTopAdr) a number of non-standard buffer arrangements are possible. These include:

    • Dustbin buffer: If DMAnBottomAdr, DMAnTopAdr and DMAnCurrWPtr all point to the same location and both DMAnIntAdr and DMAnMaxAdr point to anywhere else then all data for that DMA channel will be dumped into the same location without ever generating an interrupt. This is the equivalent to writing to /dev/null on Unix systems.
    • Linear buffer: If DMAnMaxAdr and DMAnTopAdr have the same value then the DMA manager will simply fill from DMAnBottomAdr to DMAnTopAdr and then stop. DMAnIntAdr should be outside this buffer or have its interrupt disabled.
      12.5.3.3 USBH DMA Access

The USBH requires DMA access to DRAM in to provide a communication channel between the USB HC and the USB HCD via a shared memory resource. The DMA manager uses two independent channels for this type of DMA access, one for reads and one for writes. The DRAM addresses provided to the DIU interface are generated based on addresses defined in the USB HC core operational registers, in USBH section 12.3.

12.5.3.4 Cache Coherency

As the CPU will be processing some of the data transferred (particularly control messages and page/band headers) into DRAM by the DMA manager, care needs to be taken to ensure that the data it uses is the most recently transferred data. Because the DMA manager will be updating the circular buffers in DRAM without the knowledge of the cache controller logic in the LEON CPU core the contents of the cache can become outdated. This situation can be easily handled by software, for example by flushing the relevant cache lines, and so there is no hardware support to enforce cache coherency.

12.5.4 ISI Transmit Buffer Arbitration

The SCB control logic will arbitrate access to the ISI transmit buffer (ISITxBuffer) interface on the ISI block. There are two sources of ISI Tx packets:

    • CPUISITxBuffer, contained in the SCB control block.
    • ISI mapped USB EP OUT buffers, contained in the USB device block.

This arbitration is controlled by the ISITxBuffArb register which contains a high priority bit for both the CPU and the USB. If only one of these bits is set then the corresponding source always has priority. Note that if the CPU is given absolute priority over the USB, then the software filling the ISI transmit buffer needs to ensure that sufficient USB traffic is allowed through. If both bits of the ISITxBufferArb have the same value then arbitration will take place on a round robin basis. The control logic will use the USBEPnDest registers, as it will use the CPUISITxBuffCntrl register, to determine the destination of the packets in these buffers. When the ISITxBuffer has space for a packet, the SCB control logic will immediately seek to refill it. Data will be transferred directly from the CPUISITxBuffer and the ISI mapped USB EP OUT buffers to the ISITxBuffer without any intermediate buffering.

As the speed at which the ISITxBuffer can be emptied is at least 5 times greater than it can be filled by USB traffic, the ISI mapped USB EP OUT buffers should not overflow using the above scheme in normal operation. There are a number of scenarIOs which could lead to the USB EPs being temporarily blocked such as the CPU having priority, retransmissions on the ISI bus, channels being enabled (ChannelEn bit of the USBEPnDest register) with data already in their associated endpoint buffers or short packets being sent on the USB. Care should be taken to ensure that the USB bandwidth is efficiently utilised at all times.

12.5.5 Implementation

12.5.5.1 CTRL Sub-Block Partition

    • Block Diagram
    • Definition of I/Os
      12.5.5.2 SCB Configuration Registers

The SCB register map is listed in Table 38. Registers are grouped according to which SCB sub-block their functionality is associated. All configuration registers reside in the CTRL sub-block. The Reset values in the table indicates the 32 bit hex value that will be returned when the CPU reads the associated address location after reset. All Registers pre-fixed with Hc refer to Host Controller Operational Registers, as defined in the OHCI Spec[19].

The SCB will only allow supervisor mode accesses to data space (i.e. cpu_acode[1:0]=b11). All other accesses will result in scb_cpu_berr being asserted.

TDB: Is read access necessary for ISI Rx/Tx buffers? Could implement the ISI interface as simple FIFOs as opposed to a memory interface.

TABLE 38
SCB control block configuration registers
Address Offset
from SCB_baseRegister#BitsResetDescription
CTRL
0x000SCBResetN40x0000000FSCB software reset.
Allows individual sub-blocks to be reset
separately or together. Once a reset for
a block has been initiated, by writing a
0 to the relevant register field, it can not
be suppressed. Each field will be set
after reset. Writing 0x0 to the
SCBReset register will have the same
effect as CPR generated hardware
reset.
0x004SCBGo20x00000000SCB Go.
Allows the ISI and CTRL sub-blocks to
be selected separately or together.
When go is de-asserted for a particular
sub-block, its statemachines are reset
to their idle states and its interface
signals are de-asserted. The sub-block
counters and configuration registers
retain their values.
When go is asserted for a particular
sub-block, its counters are reset. The
sub-block configuration registers retain
their values, i.e. they don't get reset.
The sub-block statemachines and
interface signals will return to their
normal mode of operation.
The CTRL field should be de-asserted
before disabling the clock from any part
of the SCB to avoid erroneous SCB
DMA requests when the clock is
enabled again.
NOTE: This functionality has not been
provided for the USBH and USBD sub-
blocks because of the USB IP cores
that they contain. We do not have
direct control over the IP core
statemachines and counters, and it
would cause unpredictable behaviour if
the cores were disabled in this way
during operation.
0x008SCBWakeupEn20x00000000USB/ISI WakeUpEnable register
0x00CSCBISITxBufferArb20x00000000ISI transmit buffer access priority
register.
0x010SCBDebugSel[11:2]100x00000000SCB Debug select register.
0x014USBEP0Dest70x00000020This register determines which of the
data sinks the data arriving in EP0
should be routed to.
0x018USBEP1Dest70x00000021Data sink mapping for USB EP1
0x01CUSBEP2Dest70x0000003EData sink mapping for USB EP2
0x020USBEP3Dest70x0000003FData sink mapping for USB EP3
0x024USBEP4Dest70x00000023Data sink mapping for USB EP4
0x028DMA0BottomAdr[21:5]17DMAChannel0 bottom address register.
0x02CDMA0TopAdr[21:5]17DMAChannel0 top address register.
0x030DMA0CurrWPtr[21:5]17DMAChannel0 current write pointer.
0x034DMA0IntAdr[21:5]17DMAChannel0 interrupt address
register.
0x038DMA0MaxAdr[21:5]17DMAChannel0 max address register.
0x03CDMA1BottomAdr[21:5]17As per DMA0BottomAdr.
0x040DMA1TopAdr[21:5]17As per DMA0TopAdr.
0x044DMA1CurrWPtr[21:5]17As per DMA0CurrWPtr.
0x048DMA1IntAdr[21:5]17As per DMA0IntAdr.
0x04CDMA1MaxAdr[21:5]17As per DMA0MaxAdr.
0x050DMAAccessEn30x00000003DMA access enable.
0x054DMAStatus40x00000000DMA status register.
0x058DMAMask40x00000000DMA mask register.
0x05C-0x098CPUISITxBuff[7:0]32x8n/aCPU ISI transmit buffer.
32-byte packet buffer, containing the
payload of a CPU sourced packet
destined for transmission over the ISI.
The CPU has full write access to the
CPUISITxBuff.
NOTE: The CPU does not have read
access to CPUISITxBuff. This is
because the CPU is the source of the
data and to avoid arbitrating read
access between the CPU and the
CTRL sub-block. Any CPU reads from
this address space will return
0x00000000.
0x09CCPUISITxBuffCtrl90x00000000CPU ISI transmit buffer control register.
USBD
0x100USBDIntStatus190x00000000USBD Interrupt event status register.
0x104USBDISIFIFOStatus160x00000000USBD ISI mapped OUT EP packet
FIFO status register.
0x108USBDDMA0FIFO80x00000000USBD DMAChannel0 mapped OUT EP
Statuspacket FIFO status register.
0x10CUSBDDMA1FIFO80x00000000USBD DMAChannel1 mapped OUT EP
Statuspacket FIFO status register.
0x110USBDResume10x00000000USBD core resume register.
0x114USBDSetup40x00000000USBD setup/configuration register.
0x118-0x154USBDEp0InBuff[15:0]32x16n/aUSBD EP0-IN buffer.
64-byte packet buffer in the, containing
the payload of a USB packet destined
for EP0-IN.
The CPU has full write access to the
USBDEp0InBuff.
NOTE: The CPU does not have read
access to USBDEp0InBuff. This is
because the CPU is the source of the
data and to avoid arbitrating read
access between the CPU and the USB
device core. Any CPU reads from this
address space will return 0x00000000.
0x158USBDEp0InBuffCtrl10x00000000USBD EP0-IN buffer control register.
0x15C-0x198USBDEp5InBuff[15:0]32x16n/aUSBD EP5-IN buffer.
As per USBDEp0InBuff.
0x19CUSBDEp5InBuffCtrl10x00000000USBD EP5-IN buffer control register.
0x1A0USBDMask190x00000000USBD interrupt mask register.
0x1A4USBDDebug300x00000000USBD debug register.
USBH
0x200HcRevisionRefer to [19] for #Bits, Reset,
Description.
0x204HcControlRefer to [19] for #Bits, Reset,
Description.
0x208HcCommandStatusRefer to [19] for #Bits, Reset,
Description.
0x20CHcInterruptStatusRefer to [19] for #Bits, Reset,
Description.
0x210HcInterruptEnableRefer to [19] for #Bits, Reset,
Description.
0x214HcInterruptDisableRefer to [19] for #Bits, Reset,
Description.
0x218HcHCCARefer to [19] for #Bits, Reset,
Description.
0x21CHcPeriodCurrentEDRefer to [19] for #Bits, Reset,
Description.
0x220HcControlHeadEDRefer to [19] for #Bits, Reset,
Description.
0x224HcControlCurrentRefer to [19] for #Bits, Reset,
EDDescription.
0x228HcBulkHeadEDRefer to [19] for #Bits, Reset,
Description.
0x22CHcBulkCurrentEDRefer to [19] for #Bits, Reset,
Description.
0x230HcDoneHeadRefer to [19] for #Bits, Reset,
Description.
0x234HcFmIntervalRefer to [19] for #Bits, Reset,
Description.
0x238HcFmRemainingRefer to [19] for #Bits, Reset,
Description.
0x23CHcFmNumberRefer to [19] for #Bits, Reset,
Description.
0x240HcPeriodicStartRefer to [19] for #Bits, Reset,
Description.
0x244HcLSThesholdRefer to [19] for #Bits, Reset,
Description.
0x248HcRhDescriptorARefer to [19] for #Bits, Reset,
Description.
0x24CHcRhDescriptorBRefer to [19] for #Bits, Reset,
Description.
0x250HcRhStatusRefer to [19] for #Bits, Reset,
Description.
0x254HcRhPortStatus[1]Refer to [19] for #Bits, Reset,
Description.
0x258USBHStatus30x00000000USBH status register.
0x25CUSBHMask20x00000000USBH interrupt mask register.
0x260USBHDebug20x00000000USBH debug register.
ISI
0x300ISICntrl40x0000000BISI Control register
0x304ISIId40x00000000ISIId for this SoPEC.
0x308ISINumRetries40x00000002Number of ISI retransmissions register.
0x30CISIPingSchedule0150x00000000ISI Ping schedule 0 register.
0x310ISIPingSchedule1150x00000000ISI Ping schedule 1 register.
0x314ISIPingSchedule2150x00000000ISI Ping schedule 2 register.
0x318ISITotalPeriod40x0000000FReload value of the ISITotalPeriod
counter.
0x31CISILocalPeriod40x0000000FReload value of the ISILocalPeriod
counter.
0x320ISIIntStatus40x00000000ISI interrupt status register.
0x324ISITxBuffStatus270x00000000ISI Tx buffer status register.
0x328ISIRxBuffStatus270x00000000ISI Rx buffer status register.
0x32CISIMask40x00000000ISI Interrupt mask register.
0x330-0x34CISITxBuffEntry0[7:0]32x8n/aISI transmit Buff, packet entry #0.
32-byte packet entry in the ISITxBuff,
containing the payload of an ISI Tx
packet.
CPU read access to ISITxBuffEntry0 is
provided for observability only i.e. CPU
reads of the ISITxBuffEntry0 do not
alter the state of the buffer. The CPU
does not have write access to the
ISITxBuffEntry0.
0x350-0x36CISITxBuffEntry1[7:0]32x8n/aISI transmit Buff, packet entry #1.
As per ISITxBuffEntry0.
0x370-0x38CISIRxBuffEntry0[7:0]32x8n/aISI receive Buff, packet entry #0.
32-byte packet entry in the ISIRxBuff,
containing the payload of an ISI Rx
packet. Note that the only error-free
long packets are placed in the
ISIRxBuffEntry0. Both ping and ACKs
are consumed in the ISI.
CPU access to ISIRxBuffEntry0 is
provided for observability only i.e. CPU
reads of the ISIRxBuffEntry0 do not
alter the state of the buffer.
0x390-0x3ACISIRxBuffEntry1[7:0]32x8n/aISI receive Buff, packet entry #1.
As per ISIRxBuffEntry0.
0x3B0ISISubId0Seq10x00000000ISI sub ID 0 sequence bit register.
0x3B4ISISubId1Seq10x00000000ISI sub ID 1 sequence bit register.
0x3B8ISISubIdSeqMask20x00000000ISI sub ID sequence bit mask register.
0x3BCISINumPins10x00000000ISI number of pins register.
0x3C0ISITurnAround40x0000000FISI bus turn around register.
0x3C4ISITShortReplyWin50x0000001FISI short packet reply window.
0x3C8ISITLongReplyWin90x000001FFISI long packet reply window.
0x3CCISIDebug40x00000000ISI debug register.

A detailed description of each register format follows. The CPU has full read access to all registers. Write access to the fields of each register is defined as:

    • Full: The CPU has full write access to the field, i.e. the CPU can write a 1 or a 0 to each bit.
    • Clear: The CPU can clear the field by writing a 1 to each bit. Writing a 0 to this type of field will have no effect.
    • None: The CPU has no write access to the field, i.e. a CPU write will have no effect on the field.

12.5.5.2.1 SCBResetN

TABLE 39
SCBResetN register format
Field NameBit(s)write accessDescription
CTRL0Fullscb_ctrl sub-block reset.
Setting this field will reset the SCB control sub-block logic,
including all configuration registers.
0 = reset
1 = default state
ISI1Fullscb_isi sub-block reset.
Setting this field will reset the ISI sub-block logic.
0 = reset
1 = default state
USBH2Fullscb_usbh sub-block reset.
Setting this field will reset the USB host controller core
and associated logic.
0 = reset
1 = default state
USBD3Fullscb_usbd sub-block reset.
Setting this field will reset the USB device controller core
and associated logic.
0 = reset
1 = default state

12.5.5.2.2 SCBGo

TABLE 40
SCBGo register format
Field NameBit(s)write accessDescription
CTRL0Fullscb_ctrl sub-block go.
0 = halted
1 = running
ISI1Fullscb_isi sub-block go.
0 = halted
1 = running

12.5.5.2.3 SCBWakeUpEn

This register is used to gate the propagation of the USB and ISI reset signals to the CPR block.

TABLE 41
SCBWakeUpEn register format
Field NameBit(s)write accessDescription
USBWakeUpEn0Fullusb_cpr_reset_n propagation
enable.
1 = enable
0 = disable
ISIWakeUpEn1Fullisi_cpr_reset_n propagation
enable.
1 = enable
0 = disable

12.5.5.2.4 SCBISITxBufferArb

This register determines which source has priority at the ISITxBuffer interface on the ISI block. When a bit is set priority is given to the relevant source. When both bits have the same value, arbitration will be performed in a round-robin manner.

TABLE 42
SCBISITxBufferArb register format
write
Field NameBit(s)accessDescription
CPUPriority0FullCPU Priority
1 = high priority
0 = low priority
USBPriority1FullUSB Priority
1 = high priority
0 = low priority

12.5.5.2.5 SCBDebugSel

Contains address of the register selected for debug observation as it would appear on cpu_adr. The contents of the selected register are output in the scb_cpu_data bus while cpu_scb_sel is low and scb_cpu_debug_valid is asserted to indicate the debug data is valid. It is expected that a number of pseudo-registers will be made available for debug observation and these will be outlined with the implementation details.

TABLE 43
SCBDebugSel register format
write
Field NameBit(s)accessDescription
CPUAdr11:2Fullcpu_adr register address.

12.5.5.2.6 USBEPnDest

This register description applies to USBEP0Dest, USBEP1Dest, USBEP2Dest, USBEP3Dest, USBEP4Dest. The SCB has two routing options for each packet received, based on the DestISIId associated with the packets source EP:

    • To the DMA Manager
    • To the ISI

The SCB map therefore does not need special fields to identify the DMAChannels on the ISIMaster SoPEC as this is taken care of by the SCB hardware. Thus the USBEP0Dest and USBEP1Dest registers should be programmed with 0x20 and 0x21 (for ISI0.0 and ISI0.1) respectively to ensure data arriving on these endpoints is moved directly to DRAM.

TABLE 44
USBEPnDest register format
Field NameBit(s)Write accessDescription
SequenceBit0FullSequence bit for packets going
from USBEPn to
DestISIId.DestISISubId. Every
CPU write to this register
initialises the value of the
sequence bit and this is
subsequently updated by the ISI
after every successful long packet
transmission.
DestISIId4:1FullDestination ISI ID.
Denotes the ISIId of the target
SoPEC as per Table
DestISISubId5FullDestination ISI sub ID.
Indicates which DMAChannel of
the target SoPEC the endpoint
is mapped onto:
0 = DMAChannel0
1 = DMAChannel1
ChannelEn6FullCommunication channel enable bit
for EPn.
This enables/disables the
communication channel for EPn.
When disabled, the SCB will not
accept USB packets addressed to
EPn.
0 = Channel disabled
1 = Channel enabled

If the local SoPEC is connected to an external USB host, it is recommended that the EP0 communication channel should always remain enabled and mapped to DMAChannel0 on the local SoPEC, as this is intended as the primary control communication channel between the external USB host and the local SoPEC.

A SoPEC ISIMaster should map as many USB endpoints, under the control of the external host, as are required for the multi-SoPEC system it is part of. As already mentioned this mapping may be dynamically reconfigured.

12.5.5.2.7 DMAnBottomAdr

This register description applies to DMA0BottomAdr and DMA1BottomAdr.

TABLE 45
DMAnBottomAdr register format
Field NameBit(s)Write accessDescription
DMAnBottomAdr21:5FullThe 256-bit aligned DRAM
address of the bottom of the
circular buffer (inclusive)
serviced by DMAChanneln

12.5.5.2.8 DMAnTopAdr

This register description applies to DMA0TopAdr and DMA 1 TopAdr.

TABLE 46
DMAnTopAdr register format
Write
Field NameBit(s)accessDescription
DMAnTopAdr21:5FullThe 256-bit aligned DRAM address of
the top of the circular buffer (inclusive)
serviced by DMAChanneln

12.5.5.2.9 DMAnCurrWPtr

This register description applies to DMA0CurrWPtr and DMA1CurrWPtr.

TABLE 47
DMAnCurrWptr register format
Write
Field NameBit(s)accessDescription
DMAnCurrWPtr21:5FullThe 256-bit aligned DRAM address
of the next location DMAChannel0
will write to. This register is set by
the CPU at the start of a DMA
operation and dynamically updated
manager during the operation.
by the DMA

12.5.5.2.10 DMAIntAdr

This register description applies to DMA0IntAdr and DMA1IntAdr.

TABLE 48
DMAnIntAdr register format
Write
Bit(s)accessDescription
DMAnIntAdr21:5FullThe 256-bit aligned DRAM address
of the location that will trigger an
interrupt when reached by
DMAChanneln buffer.

12.5.5.2.11 DMAnMaxAdr

This register description applies to DMA0MaxAdr and DMA1MaxAdr.

TABLE 49
DMAnMaxAdr register format
Write
Field NameBit(s)accessDescription
DMAnMaxAdr21:5FullThe 256-bit aligned DRAM address of
the last free location that in the
DMAChanneln circular buffer.
DMAChannel0 transfers will stop when
it reaches this address.

12.5.5.2.12 DMAAccessEn

This register enables DMA access for the various requesters, on a per channel basis.

TABLE 50
DMAAccessEn register format
Write
Field NameBit(s)accessDescription
DMAChannel0En0FullDMA Channel #0 access enable.
This uni-directional write channel is
used by the USBD and the ISI.
1 = enable
0 = disable
DMAChannel1En1FullAs per USBDISI0En.
DMAChannel2En2FullDMA Channel #2 access enable.
This bi-directional read/write channel
is used by the USBH.
1 = enable
0 = disable

12.5.5.2.13 DMAStatus

The status bits are not sticky bits i.e. they reflect the ‘live’ status of the channel. DMAChannelNntAdrHit and DMAChannelNMaxAdrHit status bits may only be cleared by writing to the relevant DMAnintAdr or DMAnMaxAdr register.

TABLE 51
DMAStatus register format
Write
Field NameBit(s)accessDescription
DMAChannel0IntAdrHit0NoneDMA channel #0 interrupt
address hit.
1 = DMAChannel0 has
reached the address
contained in the
DMA0IntAdr register.
0 = default state
DMAChannel0MaxAdrHit1NoneDMA channel #0 max
address hit.
1 = DMAChannel0 has
reached the address
contained in the
DMA0MaxAdr register.
0 = default state
DMAChannel1IntAdrHit3NoneAs per
DMAChannel0IntAdrHit.
DMAChannel1MaxAdrHit4NoneAs per
DMAChannel0MaxAdrHit.

12.5.5.2.14 DMAMask Register

All bits of the DMAMask are both readable and writable by the CPU. The DMA manager cannot alter the value of this register. All interrupts are generated in an edge sensitive manner i.e. the DMA manager will generate a dma_icu_irq pulse each time a status bit goes high and its corresponding mask bit is enabled.

TABLE 52
DMAMask register format
Write
Field NameBit(s)accessDescription
DMAChannel0IntAdrHitIntEn0FullDMAChannel0IntAdrHit status interrupt
enable.
1 = enable
0 = disable
DMAChannel0MaxAdrHitIntEn1FullDMAChannel0MaxAdrHit status interrupt
enable.
1 = enable
0 = disable
DMAChannel1IntAdrHitIntEn2FullAs per DMAChannel0IntAdrHitIntEn
DMAChannel1MaxAdrHitIntEn3FullAs per DMAChannel0MaxAdrHitIntEn

12.5.5.2.15 CPUISITxBuffCtrl Register

TABLE 53
CPUISITxBuffCtrl register format
Write
Field NameBit(s)accessDescription
PktValid0fullThis field should be set by the CPU to
indicate the validity of the
CPUISITxBuff contents. This field will
be cleared by the SCB once the
contents of the CPUISITxBuff has been
copied to the ISITxBuff.
NOTE: The CPU should not clear this
field under normal operation. If the
CPU clears this field during a packet
transfer to the ISITxBuff, the transfer
will be aborted - this is not
recommended.
1 = valid packet.
0 = default state.
PktDesc3:1fullPktDesc field, as per Table, of the
packet contained in the CPUISITxBuff.
The CPU is responsible for maintaining
the correct sequence bit value for each
ISIId.ISISubId channel it communicates
with. Only valid when CPU-
ISITxBuffCtrl.PktValid = 1.
DestISIId7:4fullDenotes the ISIId of the target SoPEC
as per Table
DestISISubId8fullIndicates which DMAChannel of the
target SoPEC the packet in the
CPUISITxBuff is destined for.
1 = DMAChannel1
0 = DMAChannel0

12.5.5.2.16 USBDIntStatus

The USBDIntStatus register contains status bits that are related to conditions that can cause an interrupt to the CPU, if the corresponding interrupt enable bits are set in the USBDMask register. The field name extension Sticky implies that the status condition will remain registered until cleared by a CPU write of 1 to each bit of the field.

NOTE: There is no Ep0IrregPktSticky field because the default control EP will frequently receive packets that are not multiples of 32 bytes during normal operation.

TABLE 54
USBDIntStatus register format
Write
Field NameBit(s)accessDescription
CoreSuspendSticky0ClearDevice core USB suspend flag. Sticky.
1 = USB suspend state. Set when device core
udcvci_suspend signal transitions from 1 -> 0.
0 = default value.
CoreUSBResetSticky1ClearDevice core USB reset flag. Sticky.
1 = USB reset. Set when device core
udcvci_reset signal transitions from 1 -> 0.
0 = default value.
CoreUSBSOFSticky2ClearDevice core USB Start Of Frame (SOF) flag.
Sticky.
1 = USB SOF. Set when device core
udcvci_sof signal transitions from 1 -> 0
0 = default value.
CPUISITxBuffEmptySticky3ClearCPU ISI transmit buffer empty flag. Sticky.
1 = empty.
0 = default value.
CPUEp0InBuffEmptySticky4ClearCPU EP0 IN buffer empty flag. Sticky.
1 = empty.
0 = default value.
CPUEp5InBuffEmptySticky5ClearCPU EP5 IN buffer empty flag. Sticky.
1 = empty.
0 = default value.
Ep0InNAKSticky6clearEP0-IN NAK flag. Sticky
This flag is set if the USB device core issues
a read request for EP0-IN and there is not a
valid packet present in the EP0-IN buffer. The
core will therefore send a NAK response to
the IN token that was received from external
USB host. This is an indicator of any back-
pressure on the USB caused by EP0-IN.
1 = NAK sent.
0 = default value
Ep5InNAKSticky7ClearAs per Ep0InNAK.
Ep0OutNAKSticky8ClearEP0-OUT NAK flag. Sticky
This flag is set if the USB device core issues
a write request for EP0-OUT and there is no
space in the OUT EP buffer for a the packet.
The core will therefore send a NAK response
to the OUT token that was received from
external USB host. This is an indicator of any
back-pressure on the USB caused by EP0-
OUT.
1 = NAK sent.
0 = default value
Ep1OutNAKSticky9ClearAs per Ep0OutNAK.
Ep2OutNAKSticky10ClearAs per Ep0OutNAK.
Ep3OutNAKSticky11ClearAs per Ep0OutNAK.
Ep4OutNAKSticky12ClearAs per Ep0OutNAK.
Ep1IrregPktSticky13ClearEP1-OUT irregular sized packet flag. Sticky.
Indicates a packet that is not a multiple of 32
bytes in size was received by EP1-OUT.
1 = irregular sized packet received.
0 = default value.
Ep2IrregPktSticky14ClearAs per Ep1IrregPktSticky.
Ep3IrregPktSticky15ClearAs per Ep1IrregPktSticky.
Ep4IrregPktSticky16ClearAs per Ep1IrregPktSticky.
OutBuffOverFlowSticky17ClearOUT EP buffer overflow flag. Sticky.
This flag is set if the USB device core
attempted to write a packet of more than 64
bytes to the OUT EP buffer. This is a fatal
error, suggesting a problem in the USB device
IP core. The SCB will take no further action.
1 = overflow condition detected.
0 = default value.
InBuffUnderRunSticky18clearIN EP buffer underrun flag. Sticky.
This flag is set if the USB device core
attempted to read more data than was
present from the IN EP buffer. This is a fatal
error, suggesting a problem in the USB device
IP core. The SCB will take no further action.
1 = underrun condition detected.
0 = default value.

12.5.5.2.17 USBDISIFIFOStatus

This register contains the status of the ISI mapped OUT EP packet FIFO. This is a secondary status register and will not cause any interrupts to the CPU.

TABLE 55
USBDISIFIFOStatus register format
Write
Field NameBit(s)accessDescription
Entry0Valid0noneFIFO entry #0 valid field.
This flag will be set by the USBD
when the USB device core indicates
the validity of packet entry
#0 in the FIFO.
1 = valid USB packet in ISI OUT EP
buffer 0.
0 = default value.
Entry0Source3:1noneFIFO entry #0 source field.
Contains the EP associated with
packet entry #0 in the FIFO.
Binary Coded Decimal.
Only valid when ISIBuff0PktValid = 1.
Entry1Valid4noneAs per Entry0Valid.
Entry1Source7:5noneAs per Entry0Source.
Entry2Valid8noneAs per Entry0Valid.
Entry2Source11:9 noneAs per Entry0Source.
Entry3Valid12 noneAs per Entry0Valid.
Entry3Source15:13noneAs per Entry0Source.

12.5.5.2.18 USBDDMAOFIFOStatus

This register description applies to USBDDMAOFIFOStatus and USBDDMA1FIFOStatus. This register contains the status of the DMAChannelN mapped OUT EP packet FIFO. This is a secondary status register and will not cause any interrupts to the CPU.

TABLE 56
USBDDMANFIFOStatus register format
Write
Field NameBit(s)accessDescription
Entry0Valid0noneFIFO entry #0 valid field.
This flag will be set by the
USBD when the USB device core
indicates the validity of
packet entry #0 in the FIFO.
1 = valid USB packet in
ISI OUT EP buffer 0.
0 = default value.
Entry0Source3:1noneFIFO entry #0 source field.
Contains the EP associated with
packet entry #0 in the FIFO.
Binary Coded Decimal.
Only valid when Entry0Valid = 1.
Entry1Valid4noneAs per Entry0Valid.
Entry1Source7:5noneAs per Entry0Source.

12.5.5.2.19 USBDResume

This register causes the USB device core to initiate resume signalling to the external USB host. Only applicable when the device core is in the suspend state.

TABLE 57
USBDResume register format
Field NameBit(s)Write accessDescription
USBDResume0fullUSBD core resume register.
The USBD will clear this
register upon resume
notification from the device core.
1 = generate resume signalling.
0 = default value.

12.5.5.2.20 USBDSetup

This register controls the general setup/configuration of the USBD.

TABLE 58
USBDSetup register format
write
Field NameBit(s)accessDescription
Ep1IrregPktCntrl0fullEP 1 OUT irregular sized packet
control.
An irregular sized packet is
defined as a packet that is not a
multiple of 32 bytes.
1 = discard irregular sized packets.
0 = read 32 bytes from buffer,
regardless of packet size.
Ep2IrregPktCntrl1fullAs per Ep1IrregPktDiscard
Ep3IrregPktCntrl2fullAs per Ep1IrregPktDiscard
Ep4IrregPktCntrl3fullAs per Ep1IrregPktDiscard

12.5.5.2.21 USBDEpNInBuffCtrl Register

This register description applies to USBDEp0InBuffCtrl and USBDEp5InBuffCtrl.

TABLE 59
USBDEpNInBuffCtrl register format
Write
Field NameBit(s)accessDescription
PktValid0fullSetting this register validates the contents
of USBDEpNInBuff. This field will be
cleared by the SCB once the packet has
been successfully transmitted to the
external USB host.
NOTE: The CPU should not clear this
field under normal operation.
If the CPU clears this field during a packet
transfer to the USB, the transfer will
be aborted - this is not recommended.
1 = valid packet.
0 = default state.

12.5.5.2.22 USBDMask

This register serves as an interrupt mask for all USBD status conditions that can cause a CPU interrupt. Setting a field enables interrupt generation for the associated status event. Clearing a field disables interrupt generation for the associated status event. All interrupts will be generated in an edge sensitive manner, i.e. when the associated status register transitions from 0->1.

TABLE 60
USBDMask register format
Write
Field NameBit(s)accessDescription
CoreSuspendStickyEn0fullCoreSuspendSticky status interrupt enable.
CoreUSBResetStickyEn1fullCoreUSBResetSticky status interrupt enable.
CoreUSBSOFStickyEn2fullCoreUSBSOFSticky status interrupt enable.
CPUISITxBuffEmptyStickyEn3fullCPUISITxBuffEmptySticky status interrupt enable.
CPUEp0InBuffEmptyStickyEn4fullCPUEp0InBuffEmptySticky status interrupt enable.
CPUEp5InBuffEmptyStickyEn5fullCPUEp5InBuffEmptySticky status interrupt enable.
Ep0InNAKStickyEn6fullEp0InNAKSticky status interrupt enable.
Ep5InNAKStickyEn7fullEp5InNAKSticky status interrupt enable.
Ep0OutNAKStickyEn8fullEp0OutNAKSticky status interrupt enable.
Ep1OutNAKStickyEn9fullEp1OutNAKSticky status interrupt enable.
Ep2OutNAKStickyEn10fullEp2OutNAkSticky status interrupt enable.
Ep3OutNAKStickyEn11fullEp3OutNAKSticky status interrupt enable.
Ep4OutNAKStickyEn12fullEp4OutNAKSticky status interrupt enable.
Ep1IrregPktStickyEn13fullEp1IrregPktSticky status interrupt enable.
Ep2IrregPktStickyEn14fullEp2IrregPktSticky status interrupt enable.
Ep3IrregPktStickyEn15fullEp3IrregPktSticky status interrupt enable.
Ep4IrregPktStickyEn16fullEp4IrregPktSticky status interrupt enable.
OutBuffOverFlowStickyEn17fullOutBuffOverFlowSticky status interrupt enable.
InBuffUnderRunStickyEn18fullInBuffUnderRunSticky status interrupt enable.

12.5.5.2.23 USBDDebug

This register is intended for debug purposes only. Contains non-sticky versions of all interrupt capable status bits, which are referred to as dynamic in the table.

TABLE 61
USBDDebug register format
write
Field NameBit(s)accessDescription
CoreTimeStamp10:0noneUSB device core frame number.
CoreSuspend11noneDynamic version of CoreSuspendSticky.
CoreUSBRest12noneDynamic version of CoreUSBResetSticky.
CoreUSBSOF13noneDynamic version of CoreUSBSOFSticky.
CPUISITxBuffEmpty14noneDynamic version of CPUISITxBuffEmptySticky.
CPUEp0InBuffEmpty15noneDynamic version of CPUEp0InBuffEmptySticky.
CPUEp5InBuffEmpty16noneDynamic version of CPUEp5InBuffEmptySticky.
Ep0InNAK17noneDynamic version of Ep0InNAKSticky.
Ep5InNAK18noneDynamic version of Ep5InNAKSticky.
Ep0OutNAK19noneDynamic version of Ep0OutNAKSticky.
Ep1OutNAK20noneDynamic version of Ep1OutNAKSticky.
Ep2OutNAK21noneDynamic version of Ep2OutNAKSticky.
Ep3OutNAK22noneDynamic version of Ep3OutNAKSticky.
Ep4OutNAK23noneDynamic version of Ep4OutNAKSticky.
Ep1IrregPkt24noneDynamic version of Ep1IrregPktSticky.
Ep2IrregPkt25noneDynamic version of Ep2IrregPktSticky.
Ep3IrregPkt26noneDynamic version of Ep3IrregPktSticky.
Ep4IrregPkt27noneDynamic version of Ep4IrregPktSticky.
OutBuffOverFlow28noneDynamic version of OutBuffOverFlowSticky.
InBuffUnderRun29noneDynamic version of InBuffUnderRunSticky.

12.5.5.2.24 USBHStatus

This register contains all status bits associated with the USBH. The field name extension Sticky implies that the status condition will remain registered until cleared by a CPU write.

TABLE 62
USBHStatus register format
Write
Field NameBit(s)accessDescription
CoreIRQSticky0clearHC core IRQ interrupt flag. Sticky
Set when HC core UHOSTC_IrqN
output signal transitions from 0 -> 1.
Refer to OHCI spec for details on HC
interrupt processing.
1 = IRQ interrupt from core.
0 = default value.
CoreSMISticky1clearHC core SMI interrupt flag. Sticky
Set when HC core UHOSTC_SmiN
output signal transitions from 0 -> 1.
Refer to OHCI spec for details on HC
interrupt processing.
1 = SMI interrupt from HC.
0 = default value.
CoreBuffAcc2noneHC core buffer access flag.
HC core UHOSTC_BufAcc output
signal. Indicates whether the HC is
accessing a descriptor or a buffer
in shared system memory.
1 = buffer access
0 = descriptor access.

12.5.5.2.25 USBHMask

This register serves as an interrupt mask for all USBH status conditions that can cause a CPU interrupt. All interrupts will be generated in an edge sensitive manner, i.e. when the associated status register transitions from 0->1.

TABLE 63
USBHMask register format
Write
Field NameBit(s)accessDescription
CoreIRQIntEn0fullCoreIRQSticky status interrupt enable
1 = enable.
0 = disable.
CoreSMIIntEn1fullCoreSMISticky status interrupt enable.
1 = enable.
0 = disable.

12.5.5.2.26 USBHDebug

This register is intended for debug purposes only. Contains non-sticky versions of all interrupt capable status bits, which are referred to as dynamic in the table.

Field NameBit(s)write accessDescription
CoreIRQ0noneDynamic version of CoreIRQSticky.
CoreSMI1NoneDynamic version of CoreSMISticky.

12.5.5.2.27 ISICntrl

This register controls the general setup/configuration of the ISI.

Note that the reset value of this register allows the SoPEC to automatically become an ISIMaster (AutoMasterEnable=1) if any USB packets are received on endpoints 24. On becoming an ISIMaster the ISIMasterSel bit is set and any USB or CPU packets destined for other ISI devices are transmitted. The CPU can override this capability at any time by clearing the AutoMasterEnable bit.

TABLE 65
ISICntrl register format
Write
Field NameBit(s)accessDescription
TxEnable0FullISI transmit enable.
Enables ISI transmission of long or ping packets. ACKs
may still be transmitted when this bit is 0.
This is cleared by transmit errors and needs to be
restarted by the CPU.
1 = Transmission enabled
0 = Transmission disabled
RxEnable1FullISI receive enable.
Enables ISI reception. This is can only be cleared by
the CPU and it is only anticipated that reception will be
disabled when the ISI in not in use and the ISI pins are
being used by the GPIO for another purpose.
1 = Reception enabled
0 = Reception disabled
ISIMasterSel2FullISI master select.
Determines whether the SoPEC is an ISIMaster or not
1 = ISIMaster
0 = ISISlave
AutoMasterEnable3FullISI auto master enable.
Enables the device to automatically become the
ISIMaster if activity is detected on USB endpoints2-4.
1 = auto-master operation enabled
0 = auto-master operation disabled

12.5.5.2.28 ISIId

TABLE 66
ISIId register format
Write
Field NameBit(s)accessDescription
ISIId3:0FullISIId for this SoPEC.
SoPEC resets to being an ISISlave with
ISIId0. 0xF (the broadcast ISIId) is an
illegal value and should not be written
to this register.

12.5.5.2.29 ISINumRetries

TABLE 67
ISINumRetries register format
Write
Field NameBit(s)accessDescription
ISINumRetries3:0FullNumber of ISI retransmissions to
attempt in response to an inferred NAK
before aborting a long packet
transmission

12.5.5.2.30 ISIPingScheduleN

This register description applies to ISIPingSchedule0, ISIPingSchedule1 and ISIPingSchedule2.

TABLE 68
ISIPingScheduleN register format
Write
Field NameBit(s)accessDescription
ISIPingSchedule14:0FullDenotes which ISIIds will be receive
ping packets.
Note that bit0 refers to ISIId0, bit1 to
ISIId1 ...bit14 to ISIId14.

12.5.5.2.31 ISITotalPeriod

TABLE 69
ISITotalPeriod register format
Field NameBit(s)Write accessDescription
ISITotalPeriod3:0FullReload value of the ISITotalPeriod
counter

12.5.5.2.32 ISILocalPeriod

TABLE 70
ISILocalPeriod register format
Field NameBit(s)Write accessDescription
ISILocalPeriod3:0FullReload value of the ISILocalPeriod
counter

12.5.5.2.33 ISIIntStatus

The ISIIntStatus register contains status bits that are related to conditions that can cause an interrupt to the CPU, if the corresponding interrupt enable bits are set in the ISIMask register.

TABLE 71
ISIIntStatus register
Write
Field NameBit(s)accessDescription
TxErrorSticky0NoneISI transmit error flag. Sticky.
Receiving ISI device would not accept the transmitted
packet. Only set after NumRetries unsuccessful
retransmissions. (excluding ping packets).
This bit is cleared by the ISI after transmission has
been re-enabled by the CPU setting the TxEnable bit
of the ISICntrl register.
1 = transmit error.
0 = default state.
RxFrameErrorSticky1ClearISI receive framing error flag. Sticky.
This bit is set by the ISI when a framing error detected
in the received packet, which can be caused by an
incorrect Start or Stop field or by bit stuffing errors.
1 = framing error detected.
0 = default state.
RxCRCErrorSticky2ClearISI receive CRC error flag.
This bit is set by the ISI when a CRC error is detected
in an incoming packet. Other than dropping the
errored packet ISI reception is unaffected by a CRC
Error.
1 = CRC error
0 = default state.
RxBuffOverFlowSticky3ClearISI receive buffer over flow flag. Sticky.
An overflow has occurred in the ISI receive buffer and
a packet had to be dropped.
1 = over flow condition detected.
0 = default state.

12.5.5.2.34 ISITxBuffStatus

The ISITxBuffStatus register contains status bits that are related to the ISI Tx buffer. This is a secondary status register and will not cause any interrupts to the CPU.

TABLE 72
ISITxBuffStatus register format
Write
Field NameBit(s)accessDescription
Entry0PktValid0NoneISI Tx buffer entry #0 packet valid flag.
This flag will be set by the ISI when a valid ISI packet is
written to entry #0 in the ISITxBuff for transmission over the
ISI bus. A Tx packet is considered valid when it is 32 bytes
in size and the ISI has written the packet header information
to Entry0PktDesc, Entry0DestISIId and Entry0DestISISubId.
1 = packet valid.
0 = default value.
Entry0PktDesc3:1NoneISI Tx buffer entry #0 packet descriptor.
PktDesc field as per Table for the packet entry #0 in the
ISITxBuff. Only valid when Entry0PktValid = 1.
Entry0DestISIId7:4NoneISI Tx buffer entry #0 destination ISI ID.
Denotes the ISIId of the target SoPEC as per Table . Only
valid when Entry0PktValid = 1.
Entry0DestISISubId8NoneISI Tx buffer entry #0 destination ISI sub ID.
Indicates which DMAChannel on the target SoPEC that
packet entry #0 in the ISITxBuff is destined for. Only valid
when Entry0PktValid = 1.
1 = DMAChannel1
0 = DMAChannel0
Entry1PktValid9NoneAs per Entry0PktValid.
Entry1PktDesc12:10NoneAs per Entry0PktDesc.
Entry1DestISIId16:13NoneAs per Entry0DestISIId.
Entry1DestISISubId17 NoneAs per Entry0DestISISubId.

12.5.5.2.35 ISIRxBuffStatus

The ISIRxBuffStatus register contains status bits that are related to the ISI Rx buffer. This is a secondary status register and will not cause any interrupts to the CPU.

TABLE 73
ISIRxBuffStatus register format
Write
Field NameBit(s)accessDescription
Entry0PktValid0NoneISI Rx buffer entry #0 packet valid flag.
This flag will be set by the ISI when a valid ISI packet is
received and written to entry #0 of the ISIRxBuff. A Rx
packet is considered valid when it is 32 bytes in size and
no framing or CRC errors were detected.
1 = valid packet
0 = default value
Entry0PktDesc3:1NoneISI Rx buffer entry #0 packet descriptor.
PktDesc field as per Table for packet entry #0 of the
ISIRxBuff. Only valid when Entry0PktValid = 1.
Entry0DestISIId7:4NoneISI Rx buffer 0 destination ISI ID.
Denotes the ISIId of the target SoPEC as per Table . This
should always correspond to the local SoPEC ISIId. Only
valid when Entry0PktValid = 1.
Entry0DestISISubId8NoneISI Rx buffer 0 destination ISI sub ID.
Indicates which DMAChannel on the target SoPEC that
entry #0 of the ISIRxBuff is destined for. Only valid when
Entry0PktValid = 1.
1 = DMAChannel1
0 = DMAChannel0
Entry1PktValid9NoneAs per Entry0PktValid.
Entry1PktDesc12:10NoneAs per Entry0PktDesc.
Entry1DestISIId16:13NoneAs per Entry0DestISIId.
Entry1DestISISubId17 NoneAs per Entry0DestISISubId.

12.5.5.2.36 ISIMask Register

An interrupt will be generated in an edge sensitive manner i.e. the ISI will generate an isi_icu_irq pulse each time a status bit goes high and the corresponding bit of the ISIMask register is enabled.

TABLE 74
ISIMask register
Write
Field NameBit(s)accessDescription
TxErrorIntEn0FullTxErrorSticky status
interrupt enable.
1 = enable.
0 = disable.
RxFrameErrorIntEn1FullRxFrameErrorSticky status
interrupt enable.
1 = enable.
0 = disable.
RxCRCErrorIntEn2FullRxCRCErrorSticky status
interrupt enable.
1 = enable.
0 = disable.
RxBuffOverFlowIntEn3FullRxBuffOverFlowSticky status
interrupt enable.
1 = enable.
0 = disable.

12.5.5.2.37 ISISubIdNSeq

This register description applies to ISISubId0Seq and ISISubId0Seq.

TABLE 75
ISISubIdNSeq register format
Write
Field NameBit(s)accessDescription
ISISubIdNSeq0FullISI sub ID channel N sequence bit.
This bit may be initialised by the CPU
but is updated by the ISI each time
an error-free long packet is received.

12.5.5.2.38 ISISubIdSeqMask

TABLE 76
ISISubIdSeqMask register format
Write
Field NameBit(s)accessDescription
ISISubIdSeq0Mask0FullISI sub ID channel 0 sequence
bit mask.
Setting this bit ensures that the
sequence bit will be ignored for
incoming packets for the ISISubId.
1 = ignore sequence bit.
0 = default state.
ISISubIdSeq1Mask1FullAs per ISISubIdSeq0Mask.

12.5.5.2.39 ISINumPins

TABLE 77
ISINumPins register format
Field NameBit(s)Write accessDescription
ISINumPins0FullSelect number of active ISI pins.
1 = 4 pins
0 = 2 pins

12.5.5.2.40 ISITurnAround

The ISI bus turnaround time will reset to its maximum value of 0xF to provide a safer starting mode for the ISI bus. This value should be set to a value that is suitable for the physical implementation of the ISI bus, i.e. the lowest turn around time that the physical implementation will allow without significant degradation of signal integrity.

TABLE 78
ISITurnAround register format
Field NameBit(s)Write accessDescription
ISITurnAround3:0FullISI bus turn around time in ISI
clock cycles (32 MHz).

12.5.5.2.41 ISIShortReplyWin

The ISI short packet reply window time will reset to its maximum value of 0x1F to provide a safer starting mode for the ISI bus. This value should be set to a value that will allow for expected frequency of bit stuffing and receiver response timing.

TABLE 79
ISIShortReplyWin register format
Field NameBit(s)Write accessDescription
ISIShortReplyWin4:0FullISI long packet reply window
in ISI clock cycles (32 MHz).

12.5.5.2.42 ISILongReplyWin

The ISI long packet reply window time will reset to its maximum value of 0x1FF to provide a safer starting mode for the ISI bus. This value should be set to a value that will allow for expected frequency of bit stuffing and receiver response timing.

TABLE 80
ISILongReplyWin register format
Write
Field NameBit(s)accessDescription
ISILongReplyWin8:0FullISI long packet reply window in
ISI clock cycles (32 MHz).

12.5.5.2.43 ISIDebug

This register is intended for debug purposes only. Contains non-sticky versions of all interrupt capable status bits, which are referred to as dynamic in the table.

TABLE 81
ISIDebug register format
Field NameBit(s)Write accessDescription
TxError0NoneDynamic version of
TxErrorSticky.
RxFrameError1NoneDynamic version of
RxFrameErrorSticky.
RxCRCError2NoneDynamic version of
RxCRCErrorSticky.
RxBuffOverFlow3NoneDynamic version of
RxBuffOverFlowSticky.

12.5.5.3 CPU Bus Interface
12.5.5.4 Control Core Logic
12.5.5.5 DIU Bus Interface
12.6 DMA Regs

All of the circular buffer registers are 256-bit word aligned as required by the DIU. The DMAnBottomAdr and DMAnTopAdr registers are inclusive i.e. the addresses contained in those registers form part of the circular buffer. The DMAnCurrWPtr always points to the next location the DMA manager will write to so interrupts are generated whenever the DMA manager reaches the address in either the DMAnIntAdr or DMAnMaxAdr registers rather than when it actually writes to these locations. It therefore can not write to the location in the DMAnMaxAdr register.

SCB Map Regs

The SCB map is configured by mapping a USB endpoint on to a data sink. This is performed on a endpoint basis i.e. each endpoint has a configuration register to allow its data sink be selected. Mapping an endpoint on to a data sink does not initiate any data flow—each endpoint/data sink needs to be enabled by writing to the appropriate configuration registers for the USBD, ISI and DMA manager.

13. General Purpose IO (GPIO)

13.1 Overview

The General Purpose IO block (GPIO) is responsible for control and interfacing of GPIO pins to the rest of the SoPEC system. It provides easily programmable control logic to simplify control of GPIO functions. In all there are 32 GPIO pins of which any pin can assume any output or input function. Possible output functions are

    • 4 Stepper Motor control Outputs
    • 12 Brushless DC Motor Control Output (total of 2 different controllers each with 6 outputs)
    • 4 General purpose high drive pulsed outputs capable of driving LEDs.
    • 4 Open drain IOs used for LSS interfaces
    • 4 Normal drive low impedance IOs used for the ISI interface in Multi-SoPEC mode

Each of the pins can be configured in either input or output mode, each pin is independently controlled. A programmable de-glitching circuit exists for a fixed number of input pins. Each input is a schmidt trigger to increase noise immunity should the input be used without the de-glitch circuit. The mapping of the above functions and their alternate use in a slave SoPEC to GPIO pins is shown in Table 82 below.

TABLE 82
GPIO pin type
GPIO pin(s)Pin IO TypeDefault Function
gpio[3:0]Normal drive, low impedance IOPins 1 and 0 in ISI
(35 Ohm), Integrated pull-upMode, pins 2 and 3 in
resistorinput mode
gpio[7:4]High drive, normal impedance IOInput Mode
(65 Ohm), intended for LED
drivers
gpio[31:8]Normal drive, normal impedanceInput Mode
IO (65 Ohm), no pull-up

13.2 Stepper Motor Control

The motor control pins can be directly controlled by the CPU or the motor control logic can be used to generate the phase pulses for the stepper motors. The controller consists of two central counters from which the control pins are derived. The central counters have several registers (see Table) used to configure the cycle period, the phase, the duty cycle, and counter granularity.

There are two motor master counters (0 and 1) with identical features. The period of the master counters are defined by the MotorMasterClkPeriod[1:0] and MotorMasterClkSrc registers i.e. both master counters are derived from the same MotorMasterClkSrc. The MotorMasterClkSrc defines the timing pulses used by the master counters to determine the timing period. The MotorMasterClkSrc can select clock sources of 1 μs, 100 μs, 10 ms and pclk timing pulses.

The MotorMasterClkPeriod[1:0] registers are set to the number of timing pulses required before the timing period re-starts. Each master counter is set to the relevant MotorMasterClkPeriod value and counts down a unit each time a timing pulse is received.

The master counters reset to MotorMasterClkPeriod value and count down. Once the value hits zero a new value is reloaded from the MotorMasterClkPeriod[1:0] registers. This ensures that no master clock glitch is generated when changing the clock period.

Each of the IO pins for the motor controller are derived from the master counters. Each pin has independent configuration registers. The MotorMasterClkSelect[3:0] registers define which of the two master counters to use as the source for each motor control pin. The master counter value is compared with the configured MotorCtrlLow and MotorCtrlHigh registers (bit fields of the MotorCtrlConfig register). If the count is equal to MotorCtrlHigh value the motor control is set to 1, if the count is equal to MotorCtrlLow value the motor control pin is set to 0.

This allows the phase and duty cycle of the motor control pins to be varied at pclk granularity. The motor control generators keep a working copy of the MotorCtrlLow, MotorCtrlHigh values and update the configured value to the working copy when it is safe to do so. This allows the phase or duty cycle of a motor control pin to be safely adjusted by the CPU without causing a glitch on the output pin.

Note that when reprogramming the MotorCtrlLow, MotorCtrlHigh registers to reorder the sequence of the transition points (e.g changing from low point less than high point to low point greater than high point and vice versa) care must still taken to avoid introducing glitching on the output pin.

13.3 LED Control

LED lifetime and brightness can be improved and power consumption reduced by driving the LEDs with a pulsed rather than a DC signal. The source clock for each of the LED pins is a 7.8 kHz (128 μs period) clock generated from the 1 μs clock pulse from the Timers block. The LEDDutySelect registers are used to create a signal with the desired waveform. Unpulsed operation of the LED pins can be achieved by using CPU IO direct control, or setting LEDDutySelect to 0. By default the LED pins are controlled by the LED control logic.

13.4 LSS Interface via GPIO

In some SoPEC system configurations one or more of the LSS interfaces may not be used. Unused LSS interface pins can be reused as general IO pins by configuring the IOModeSelect registers. When a mode select register for a particular GPIO pin is set to 23,22,21,20 the GPIO pin is connected to LSS control IOs 3 to 0 respectively.

13.5 ISI Interface via GPIO

In Multi-SoPEC mode the SCB block (in particular the ISI sub-block) requires direct access to and from the GPIO pins. Control of the ISI interface pins is determined by the IOModeSelect registers. When a mode select register for a particular GPIO pin is set to 27,26,25,24 the GPIO pin connected to the ISI control bits 3 to 0 respectively. By default the GPIO pins 1 to 0 are directly controlled by the ISI block.

In single SoPEC systems the pins can be re-used by the GPIO.

13.6 CPU GPIO Control

The CPU can assume direct control of any (or all) of the IO pins individually. On a per pin basis the CPU can turn on direct access to the pin by configuring the IOModeSelect register to CPU direct mode. Once set the IO pin assumes the direction specified by the CpuIODirection register. When in output mode the value in register CpuIOOut will be directly reflected to the output driver. When in input mode the status of the input pin can be read by reading CpuIOIn register. When writing to the CpuIOOut register the value being written is XORed with the current value in CpuIOOut. The CPU can also read the status of the 10 selected de-glitched inputs by reading the CpuIOInDeGlitch register.

13.7 Programmable De-Glitching Logic

Each IO pin can be filtered through a de-glitching logic circuit, the pin that the de-glitching logic is connected to is configured by the InputPinSelect registers. There are IO de-glitching circuits, so a maximum of IO input pin can be de-glitched at anytime.

The de-glitch circuit can be configured to sample the IO pin for a predetermined time before concluding that a pin is in a particular state. The exact sampling length is configurable, but each de-glitch circuit must use one of two possible configured values (selected by DeGlitchSelect). The sampling length is the same for both high and low states. The DeGlitchCount is programmed to the number of system time units that a state must be valid for before the state is passed on. The time units are selected by DeGlitchClkSel and can be one of 1 μs, 100 μs, 10 ms and pclk pulses.

For example if DeGlitchCount is set to 10 and DeGlitchClkSel set to 3, then the selected input pin must consistently retain its value for 10 system clock cycles (pclk) before the input state will be propagated from CpuIOIn to CpuIOInDeglitch.

13.8 Interrupt Generation

Any of the selected input pins (selected by InputPinSelect) can generate an interrupt from the raw or deglitched version of the input pin. There are IO possible interrupt sources from the GPIO to the interrupt controller, one interrupt per input pin. The InterruptSrcSelect register determines whether the raw input or the deglitched version is used as the interrupt source.

The interrupt type, masking and priority can be programmed in the interrupt controller.

13.9 Frequency Analyser

The frequency analyser measures the duration between successive positive edges on a selected input pin (selected by InputPinSelect) and reports the last period measured (FreqAnaLastPeriod) and a running average period (FreqAnaAverage).

The running average is updated each time a new positive edge is detected and is calculated by FreqAnaAverage=(FreqAnaAverage/8)*7+FreqAnaLastPeriod/8.

The analyser can be used with any selected input pin (or its deglitched form), but only one input at a time can be selected. The input is selected by the FreqAnaPinSelect (range of 0 to 9) and its deglitched form can be selected by FreqAnaPinFormSelect.

13.10 Brushless DC (BLDC) Motor Controllers

The GPIO contains 2 brushless DC (BLDC) motor controllers. Each controller consists of 3 hall inputs, a direction input, and six possible outputs. The outputs are derived from the input state and a pulse width modulated (PWM) input from the Stepper Motor controller, and is given by the truth table in Table 83.

TABLE 83
Truth Table for BLDC Motor Controllers
directionhchbhaq6q5q4q3q2q1
00010001PWM0
0011PWM00100
0010PWM00001
011000PWM001
010001PWM000
01010100PWM0
0000000000
0111000000
100100PWM001
1011PWM00001
1010PWM00100
11100001PWM0
11000100PWM0
110101PWM000
1000000000
1111000000

All inputs to a BLDC controller must be de-glitched. Each controller has its inputs hardwired to de-glitch circuits. Controller 1 hall inputs are de-glitched by circuits 2 to 0, and its direction input is de-glitched by circuit 3. Controller 2 inputs are de-glitched by circuits 6 to 4 for hall inputs and 7 for direction input.

Each controller also requires a PWM input. The stepper motor controller outputs are reused, output 0 is connected to BLDC controller 1, and output 1 to BLDC controller 2.

The controllers have two modes of operation, internal and external direction control (configured by BLDCMode). If a controller is in external direction mode the direction input is taken from a de-glitched circuit, if it is in internal direction mode the direction input is configured by the BLDCDirection register.

The BLDC controller outputs are connected to the GPIO output pins by configuring the IOModeSelect register for each pin. e.g Setting the mode register to 8 will connect q1 Controller 1 to drive the pin.

13.11 Implementation

13.11.1 Definitions of I/O

TABLE 84
I/O definition
Port namePinsI/ODescription
Clocks and Resets
Pclk1InSystem Clock
prst_n1InSystem reset, synchronous active low
tim_pulse[2:0]3InTimers block generated timing pulses.
0 - 1 μs pulse
1 - 100 μs pulse
2 - 10 ms pulse
CPU Interface
cpu_adr[8:2]8InCPU address bus. Only 7 bits are required to
decode the address space for this block
cpu_dataout[31:0]32InShared write data bus from the CPU
gpio_cpu_data[31:0]32OutRead data bus to the CPU
cpu_rwn1InCommon read/not-write signal from the CPU
cpu_gpio_sel1InBlock select from the CPU. When cpu_gpio_sel is
high both cpu_adr and cpu_dataout are valid
gpio_cpu_rdy1OutReady signal to the CPU. When gpio_cpu_rdy is
high it indicates the last cycle of the access. For a
write cycle this means cpu_dataout has been
registered by the GPIO block and for a read cycle
this means the data on gpio_cpu_data is valid.
gpio_cpu_berr1OutBus error signal to the CPU indicating an invalid
access.
gpio_cpu_debug_valid1OutDebug Data valid on gpio_cpu_data bus. Active high
cpu_acode[1:0]2InCPU Access Code signals. These decode as
follows:
00 - User program access
01 - User data access
10 - Supervisor program access
11 - Supervisor data access
IO Pins
gpio_o[31:0]32OutGeneral purpose IO output to IO driver
gpio_i[31:0]32InGeneral purpose IO input from IO receiver
gpio_e[31:0]32OutGeneral purpose IO output control. Active high
driving
GPIO to LSS
lss_gpio_dout[1:0]2InLSS bus data output
Bit 0 - LSS bus 0
Bit 1 - LSS bus 1
gpio_lss_din[1:0]2OutLSS bus data input
Bit 0 - LSS bus 0
Bit 1 - LSS bus 1
lss_gpio_e[1:0]2InLSS bus data output enable, active high
Bit 0 - LSS bus 0
Bit 1 - LSS bus 1
lss_gpio_clk[1:0]2InLSS bus clock output
Bit 0 - LSS bus 0
Bit 1 - LSS bus 1
GPIO to ISI
gpio_isi_din[1:0]2OutInput data from IO receivers to ISI.
isi_gpio_dout[1:0]2InData output from ISI to IO drivers
isi_gpio_e[1:0]2InGPIO ISI pins output enable (active high) from ISI
interface
usbh_gpio_power_en1InPort Power enable from the USB host core, active
high
gpio_usbh_over_current1OutOver current detect to the USB host core, active
high
Miscellaneous
gpio_icu_irq[9:0]10OutGPIO pin interrupts
gpio_cpr_wakeup1OutSoPEC wakeup to the CPR block active high.
Debug
debug_data_out[31:0]32InOutput debug data to be muxed on to the GPIO pins
debug_cntrl[31:0]32InControl signal for each GPIO bound debug data line
indicating whether or not the debug data should be
selected by the pin mux

13.11.2 Configuration Registers

The configuration registers in the GPIO are programmed via the CPU interface. Refer to section 11.4.3 on page 69 for a description of the protocol and timing diagrams for reading and writing registers in the GPIO. Note that since addresses in SoPEC are byte aligned and the CPU only supports 32-bit register reads and writes, the lower 2 bits of the CPU address bus are not required to decode the address space for the GPIO. When reading a register that is less than 32 bits wide zeros should be returned on the upper unused bit(s) of gpio_cpu_data. Table 85 lists the configuration registers in the GPIO block

TABLE 85
GPIO Register Definition
Address
GPIO_base+Register#bitsResetDescription
0x000-0x07CIOModeSelect[31:0]32x5SeeSpecifies the mode of operation for each
Table forGPIO pin. One 5 bit bus per pin.
default valuesPossible assignment values and correspond
controller outputs are as follows
Value - Controlled by
3 to 0 - Output, LED controller 4 to 1
7 to 4 - Output Stepper Motor control 4-1
13 to 8 - Output BLDC 1 Motor control 6-1
19 to 14 - Output BLDC 2 Motor control 6-1
23 to 20 - LSS control 4-1
27 to 24 - ISI control 4-1
28 - CPU Direct Control
29 - USB power enable output
30 - Input Mode
0x080-0xA4InputPinSelect[9:0]10x50x00Specifies which pins should be selected as
inputs. Used to select the pin source to the
DeGlitch Circuits.
CPU IO Control
0x0B0CpuIOUserModeMask320x0000_0000User Mode Access Mask to CPU GPIO
control register. When 1 user access is
enabled. One bit per gpio pin. Enables
access to CpuIODirection, CpuIOOut and
CpuIOIn in user mode.
0x0B4CpuIOSuperModeMask320xFFFF_FFFFSupervisor Mode Access Mask to CPU
GPIO control register. When 1 supervisor
access is enabled. One bit per gpio pin.
Enables access to CpuIODirection,
CpuIOOut and CpuIOIn in supervisor mode.
0x0B8CpuIODirection320x0000_0000Indicates the direction of each IO pin, when
controlled by the CPU
0 - Indicates Input Mode
1 - Indicates Output Mode
0x0BCCpuIOOut320x0000_0000Value used to drive output pin in CPU direct
mode.
bits31:0 - Value to drive on output GPIO
pins
When written to the register assumes the
new value XORed with the current value.
0x0C0CpuIOIn32External pinValue received on each input pin regardless
valueof mode. Read Only register.
0x0C4CpuDeGlitchUserModeMask100x000User Mode Access Mask to
CpuIOInDeglitch control register. When 1
user access is enabled, otherwise bit reads
as zero.
0x0C8CpuIOInDeglitch100x000Deglitched version of selected input pins.
The input pins are selected by the
InputPinSelect register.
Note that after reset this register will reflect
the external pin values 256 pclk cycles after
they have stabilized. Read Only register.
Deglitch control
0x0D0-0x0D4DeGlitchCount[1:0]2x80xFFDeglitch circuit sample count in
DeGlitchClkSrc selected units.
0x0D8-0x0DCDeGlitchClkSrc2x20x3Specifies the unit use of the GPIO deglitch
[1:0]circuits:
0 - 1 μs pulse
1 - 100 μs pulse
2 - 10 ms pulse
3 - pclk
0x0E0DeGlitchSelect100x000Specifies which deglitch count
(DeGlitchCount) and unit select
(DeGlitchClkSrc) should be used with each
de-glitch circuit
0 - Specifies DeGlitchCount[0] and
DeGlitchClkSrc[0]
1 - Specifies DeGlitchCount[1] and
DeGlitchClkSrc[1]
Motor Control
0x0E4MotorCtrlUser10x0User Mode Access enable to Motor control
ModeEnableconfiguration registers. When 1 user access
is enabled.
Enables user access to
MotorMasterClkPeriod, MotorMasterClkSrc,
MotorDutySelect, MotorPhaseSelect,
MotorMasterClockEnable, Motor-
MasterClkSelect, BLDCMode and
BLDCDirection registers
0x0E8-0x0ECMotorMasterClkPeriod[1:0]2x160x0000Specifies the motor controller master clock
periods in MotorMasterClkSrc selected units
0x0F0MotorMasterClkSrc20x0Specifies the unit use by the motor controller
master clock generator:
0 - 1 μs pulse
1 - 100 μs pulse
2 - 10 ms pulse
3 - pclk
0x0F4-0x100MotorCtrlConfig4x320x0000_0000Specifies the transition points in the clock
[3:0]period for each motor control pin. One
register per pin
bits 15:0 - MotorCtrlLow, high to low
transition point
bits 31:16 - MotorCtrlHigh, low to high
transition point
0x104MotorMasterClkSelect40x0Specifies which motor master clock should
be used as a pin generator source
0 - Clock derived from MotorMasterClockPeriod
[0]
1 - Clock derived from MotorMasterClockPeriod
[1]
0x108MotorMasterClockEnable20x0Enable the motor master clock counter.
When 1 count is enabled
Bit 0 - Enable motor master clock 0
Bit 1 - Enable motor master clock 1
BLDC Motor Controllers
0x10CBLDCMode20x0Specifies the Mode of operation of the
BLDC Controller. One bit per Controller.
0- External direction control
1- Internal direction control
0x110BLDCDirection20x0Specifies the direction input of the BLDC
controller. Only used when BLDC controller
is an internal direction control mode. One bit
per controller.
LED control
0x114LEDCtrlUserModeEnable40x0User Mode Access enable to LED control
configuration registers. When 1 user access
is enabled.
One bit per LEDDutySelect select register.
0x118-0x124LEDDutySelect4x30x0Specifies the duty cycle for each LED
[3:0]control output. See FIG. 54 for encoding
details. The LEDDutySelect[3:0] registers
determine the duty cycle of the LED
controller outputs
Frequency Analyser
0x130FreqAnaUserModeEnable10x0User Mode Access enable to Frequency
analyser configuration registers. When 1
user access is enabled. Controls access to
FreqAnaPinFormSelect,
FreqAnaLastPeriod, FreqAnaAverage and
FreqAnaCountInc.
0x134FreqAnaPinSelect40x00Selects which selected input should be used
for the frequency analyses.
0x138FreqAnaPinFormSelect10x0Selects if the frequency analyser should use
the raw input or the deglitched form.
0 - Deglitched form of input pin
1 - Raw form of input pin
0x13CFreqAnaLastPeriod160x0000Frequency Analyser last period of selected
input pin.
0x140FreqAnaAverage160x0000Frequency Analyser average period of
selected input pin.
0x144FreqAnaCountInc200x0000 0Frequency Analyser counter increment
amount. For each clock cycle no edge is
detected on the selected input pin the
accumulator is incremented by this amount.
0x148FreqAnaCount320x0000_0000Frequency Analyser running counter
(Working register)
Miscellaneous
0x150InterruptSrcSelect100x3FFInterrupt source select.1 bit per selected
input. Determines whether the interrupt
source is direct form the selected input pin
or the deglitched version. Input pins are
selected by the DeGlitchPinSelect register.
0 - Selected input direct
1 - Deglitched selected input
0x154DebugSelect[8:2]70x00Debug address select. Indicates the address
of the register to report on the
gpio_cpu_data bus when it is not otherwise
being used.
0x158-0x15CMotorMasterCount[1:0]2x160x0000Motor master clock counter values.
Bus 0 - Master clock count 0
Bus 1 - Master clock count 1
Read Only registers
0x160WakeUpInputMask100x000Indicates which deglitched inputs should be
considered to generate the CPR wakeup.
Active high
0x164WakeUpLevel10Defines the level to detect on the masked
GPIO inputs to generate a wakeup to the
CPR
0 - Level 0
1 - Level 1
0x168USBOverCurrentPinSelect40x00Selects which deglitched input should be
used for the USB over current detect.

13.11.2.1 Supervisor and User Mode Access

The configuration registers block examines the CPU access type (cpu_acode signal) and determines if the access is allowed to that particular register, based on configured user access registers. If an access is not allowed the GPIO will issue a bus error by asserting the gpio_cpu_berr signal.

All supervisor and user program mode accesses will result in a bus error.

Access to the CpuIODirection, CpuIOOut and CpuIOIn is filtered by the CpuIOUserModeMask and CpuIOSuperModeMask registers. Each bit masks access to the corresponding bits in the CpuIO* registers for each mode, with CpuIOUserModeMask filtering user data mode access and CpuIOSuperModeMask filtering supervisor data mode access.

The addition of the CpuIOSuperModeMask register helps prevent potential conflicts between user and supervisor code read modify write operations. For example a conflict could exist if the user code is interrupted during a read modify write operation by a supervisor ISR which also modifies the CpuIO* registers.

An attempt to write to a disabled bit in user or supervisor mode will be ignored, and an attempt to read a disabled bit returns zero. If there are no user mode enabled bits then access is not allowed in user mode and a bus error will result. Similarly for supervisor mode.

When writing to the CpuIOOut register, the value being written is XORed with the current value in the CpuIOOut register, and the result is reflected on the GPIO pins.

The pseudocode for determining access to the CpuIOOut register is shown below. Similar code could be shown for the CpuIODirection and CpuIOIn registers. Note that when writing to CpuIODirection data is deposited directly and not XORed with the existing data (as in the CpuIOOut case).

if (cpu_acode == SUPERVISOR_DATA_MODE) then
// supervisor mode
if (CpuIOSuperModeMask[31:0] == 0 ) then
// access is denied, and bus error
gpio_cpu_berr = 1
elsif (cpu_rwn == 1) then
// read mode (no filtering needed)
gpio_cpu_data[31:0] = CpuIOOut[31:0]
else
// write mode,filtered by mask
mask[31:0] = (cpu_dataout[31:0] &
CpuIOSuperModeMask[31:0])
CpuIOOut[31:0] = (cpu_dataout[31:0] {circumflex over ( )} mask[31:0] )
//bitwise XOR operator
elsif (cpu_acode == USER_DATA_MODE) then
// user datamode
if (CpuIOUserModeMask[31:0] == 0 ) then
// access is denied, and bus error
gpio_cpu_berr = 1
elsif (cpu_rwn == 1) then
// read mode, filtered by mask
gpio_cpu_data = ( CpuIOOut[31:0] &
CpuIOUserModeMask[31:0])
else
// write mode,filtered by mask
mask[31:0] = (cpu_dataout[31:0] &
CpuIOUserModeMask[31:0])
CpuIOOut[31:0] = (cpu_dataout[31:0] {circumflex over ( )} mask[31:0] )
//bitwise XOR operator
else
// access is denied, bus error
gpio_cpu_berr = 1

Table 86 details the access modes allowed for registers in the GPIO block. In supervisor mode all registers are accessible. In user mode forbidden accesses will result in a bus error (gpio_cpu_berr asserted).

TABLE 86
GPIO supervisor and user access modes
Register AddressRegistersAccess Permitted
0x000-0x07CIOModeSelect[31:0]Supervisor data mode only
0x080-0x94InputPinSelect[9:0]Supervisor data mode only
CPU IO Control
0x0B0CpuIOUserModeMaskSupervisor data mode only
0x0B4CpuIOSuperModeMaskSupervisor data mode only
0x0B8CpuIODirectionCpuIOUserModeMask and
CpuIOSuperModeMask filtered
0x0BCCpuIOOutCpuIOUserModeMask and
CpuIOSuperModeMask filtered
0x0C0CpuIOInCpuIOUserModeMask and
CpuIOSuperModeMask filtered
0x0C4CpuDeGlitchUserModeMaskSupervisor data mode only
0x0C8CpuIOInDeglitchCpuDeGlitchUserModeMask filtered.
Unrestricted Supervisor data mode
access
Deglitch control
0x0D0-0x0D4DeGlitchCount[1:0]Supervisor data mode only
0x0D8-0x0DCDeGlitchClkSrc[1:0]Supervisor data mode only
0x0E0DeGlitchSelectSupervisor data mode only
Motor Control
0x0E4MotorCtrlUserModeEnableSupervisor data mode only
0x0E8-0x0ECMotorMasterClkPeriod[1:0]MotorCtrlUserModeEnable enabled.
0x0F0MotorMasterClkSrcMotorCtrlUserModeEnable enabled.
0x0F4-0x100MotorCtrlConfig[3:0]MotorCtrlUserModeEnable enabled
0x104MotorMasterClkSelectMotorCtrlUserModeEnable enabled
0x108MotorMasterClockEnableMotorCtrlUserModeEnable enabled
BLDC Motor Controllers
0x10CBLDCModeMotorCtrlUserModeEnable Enabled
0x110BLDCDirectionMotorCtrlUserModeEnable Enabled
LED control
0x114LEDCtrlUserModeEnableSupervisor data mode only
0x118-0x124LEDDutySelect[3:0]LEDCtrlUserModeEnable[3:0]
enabled
Frequency Analyser
0x130FreqAnaUserModeEnableSupervisor data mode only
0x134FreqAnaPinSelectFreqAnaUserModeEnable enabled
0x138FreqAnaPinFormSelectFreqAnaUserModeEnable enabled
0x13CFreqAnaLastPeriodFreqAnaUserModeEnable enabled
0x140FreqAnaAverageFreqAnaUserModeEnable enabled
0x144FreqAnaCountIncFreqAnaUserModeEnable enabled
0x148FreqAnaCountFreqAnaUserModeEnable enabled
Miscellaneous
0x150InterruptSrcSelectSupervisor data mode only
0x154DebugSelect[8:2]Supervisor data mode only
0x158-0x15CMotorMasterCount[1:0]Supervisor data mode only
0x160WakeUpInputMaskSupervisor data mode only
0x164WakeUpLevelSupervisor data mode only
0x168USBOverCurrentPinSelectSupervisor data mode only

13.11.3 GPIO Partition
13.11.4 IO Control

The IO control block connects the IO pin drivers to internal signalling based on configured setup registers and debug control signals.

// Output Control
for (i=0; i<32 ; i++) {
if (debug_cntrl[i] == 1) then // debug mode
gpio_e[i] = 1;gpio_o[i] =debug_data_out[i]
else // normal mode
case io_mode_select[i] is
0 : gpio_e[i] =1 ;gpio_o[i] =led_ctrl[0] // LED
output 1
1 : gpio_e[i] =1 ;gpio_o[i] =led_ctrl[1] // LED
output 2
2 : gpio_e[i] =1 ;gpio_o[i] =led_ctrl[2] // LED
output 3
3 : gpio_e[i] =1 ;gpio_o[i] =led_ctrl[3] // LED
output 4
4 : gpio_e[i] =1 ;gpio_o[i] =motor_ctrl[0] // Stepper
Motor Control 1
5 : gpio_e[i] =1 ;gpio_o[i] =motor_ctrl[1] // Stepper
Motor Control 2
6 : gpio_e[i] =1 ;gpio_o[i] =motor_ctrl[2] // Stepper
Motor Control 3
7 : gpio_e[i] =1 ;gpio_o[i] =motor_ctrl[3] // Stepper
Motor Control 4
8 : gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[0][0] // BLDC
Motor Control 1,output 1
9 : gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[0][1] // BLDC
Motor Control 1,output 2
10: gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[0][2] // BLDC
Motor Control 1,output 3
11: gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[0][3] // BLDC
Motor Control 1,output 4
12: gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[0][4] // BLDC
Motor Control 1,output 5
13: gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[0][5] // BLDC
Motor Control 1,output 6
14: gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[1][0] // BLDC
Motor Control 2,output 1
15: gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[1][1] // BLDC
Motor Control 2,output 2
16: gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[1][2] // BLDC
Motor Control 2,output 3
17: gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[1][3] // BLDC
Motor Control 2,output 4
18: gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[1][4] // BLDC
Motor Control 2,output 5
19: gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[1][5] // BLDC
Motor Control 2,output 6
20: gpio_e[i] =1 ;gpio_o[i] =lss_gpio_clk[0] // LSS Clk
0
21: gpio_e[i] =1 ;gpio_o[i] =lss_gpio_clk[1] // LSS Clk
1
22: gpio_e[i] =lss_gpio_e[0] ;gpio_o[i]
=lss_gpio_dout[0]; // LSS Data 0
gpio_lss_din[0] = gpio_i[i]
23: gpio_e[i] =lss_gpio_e[1] ;gpio_o[i]
=lss_gpio_dout[1]; // LSS Data 1
gpio_lss_din[1] = gpio_i[i]
24: gpio_e[i] =isi_gpio_e[0] ;gpio_o[i]
=isi_gpio_dout[0]; // ISI Control 1
gpio_isi_din[0] = gpio_i[i]
25: gpio_e[i] =isi_gpio_e[1] ;gpio_o[i]
=isi_gpio_dout[1]; // ISI Control 2
gpio_isi_din[1] = gpio_i[i]
26: gpio_e[i] =isi_gpio_e[2] ;gpio_o[i]
=isi_gpio_dout[2]; // ISI Control 3
gpio_isi_din[2] = gpio_i[i]
27: gpio_e[i] =isi_gpio_e[3] ;gpio_o[i]
=isi_gpio_dout[3]; // ISI Control 4
gpio_isi_din[3] = gpio_i[i]
28: gpio_e[i] =cpu_io_dir[i] ;gpio_o[i] =cpu_io_out[i];
// CPU Direct
29: gpio e[i] =1 ;gpio o[i] =usbh gpio power en
// USB host power enable
30: gpio e[i] =0 ;gpio o[i] =0
// Input only mode
end case
// all gpio are always readable by the CPU
cpu_io_in[i] = gpio_i[i];
}

The input selection pseudocode, for determining which pin connects to which de-glitch circuit.

for( i=0 ;i < 10 ; i++) {
pin_num= input_pin_select[i]
deglitch_input[i]= gpio_i[pin_num]
}

The gpio_usbh_over_current output to the USB core is driven by a selected deglitched input (configured by the USBOverCurrentPinSelect register).

    • index=USBOverCurrentPinSelect
    • gpio_usbh_over_current=cpu_io_in_deglitch[index]
      13.11.5 Wakeup Generator

The wakeup generator compares the deglitched inputs with the configured mask (WakeUpInputMask) and level (WakeUpLevel), and determines whether to generate a wakeup to the CPR block.

for (i =0;i<10; i++) {
if (wakeup_level = 0) then// level 0 active
wakeup  =  wakeup  OR  wakeup_input_mask[i]  ANDNOT
cpu_io_in_deglitch[i]
else// level 1 active
wakeup = wakeup OR wakeup_input_mask[i]AND
cpu_io_in_deglitch[i]
}
// assign the output
gpio_cpr_wakeup = wakeup

13.11.6 LED Pulse Generator

The pulse generator logic consists of a 7-bit counter that is incremented on a 1 μs pulse from the timers block (tim_pulse[0]). The LED control signal is generated by comparing the count value with the configured duty cycle for the LED (led_duty_sel).

The logic is given by:

for (i=0 i<4 ;i++) { // for each LED pin
// period divided into 8 segments
period_div8 = cnt[6:4];
if (period_div8 < led_duty_sel[i]) then
led_ctrl[i] = 1
else
led_ctrl[i] = 0
}
// update the counter every 1us pulse
if (tim_pulse[0] == 1) then
cnt ++

13.11.7 Stepper Motor Control

The motor controller consists of 2 counters, and 4 phase generator logic blocks, one per motor control pin. The counters decrement each time a timing pulse (cnt_en) is received. The counters start at the configured clock period value (motor_mas_clk_period) and decrement to zero. If the counters are enabled (via motor_mas_clk_enable), the counters will automatically restart at the configured clock period value, otherwise they will wait until the counters are re-enabled.

The timing pulse period is one of pclk, 1 μs, 100 μs, 1 ms depending on the motor_mas_clk_sel signal. The counters are used to derive the phase and duty cycle of each motor control pin.

// decrement logic
if (cnt_en == 1) then
if ((mas_cnt == 0) AND (motor_mas_clk_enable == 1)) then
mas_cnt = motor_mas_clk_period[15:0]
elsif ((mas_cnt == 0) AND (motor_mas_clk_enable == 0)) then
mas_cnt = 0
else
mas_cnt −−
else // hold the value
mas_cnt = mas_cnt

The phase generator block generates the motor control logic based on the selected clock generator (motor_mas_clk_sel) the motor control high transition point (curr_motor_ctrl_high) and the motor control low transition point (curr_motor_ctrl_low).

The phase generator maintains current copies of the motor_ctrl_config configuration value (motor_ctrl_config[31:16] becomes curr_motor_ctrl_high and motor_ctrl_config[15:0] becomes curr_motor_ctrl_low). It updates these values to the current register values when it is safe to do so without causing a glitch on the output motor pin.

Note that when reprogramming the motor_ctrl_config register to reorder the sequence of the transition points (e.g changing from low point less than high point to low point greater than high point and vice versa) care must taken to avoid introducing glitching on the output pin.

There are 4 instances one per motor control pin.

The logic is given by:

// select the input counter to use
if (motor_mas_clk_sel == 1) then
count = mas_cnt[1]
else
count = mas_cnt[0]
// Generate the phase and duty cycle
if (count == curr_motor_ctrl_low) then
motor_ctrl = 0
elsif (count == curr_motor_ctrl_high) then
motor_ctrl = 1
else
motor_ctrl = motor_ctrl // remain the same
// update the current registers at period boundary
if (count == 0) then
curr_motor_ctrl_high = motor_ctrl_config[31:16]//
update to new high value
curr_motor_ctrl_low = motor_ctrl_config[15:0]//
update to new high value

13.11.8 Input Deglitch

The input deglitch logic rejects input states of duration less than the configured number of time units (deglitch_cnt), input states of greater duration are reflected on the output cpu_io_in_deglitch. The time units used (either pclk, 1 μs, 100 μs, 1 ms) by the deglitch circuit is selected by the deglitch_clk_src bus.

There are 2 possible sets of deglitch_cnt and deglitch_clk_src that can be used to deglitch the input pins. The values used are selected by the deglitch_sel signal.

There are 10 deglitch circuits in the GPIO. Any GPIO pin can be connected to a deglitch circuit. Pins are selected for deglitching by the InputPinSelect registers.

Each selected input can be used to generate an interrupt. The interrupt can be generated from the raw input signal (deglitch_input) or a deglitched version of the input (cpu_io_in_deglitch). The interrupt source is selected by the interrupt_src_select signal.

The counter logic is given by

if (deglitch_input != deglitch_input_delay) then
cnt = deglitch_cnt
output_en = 0
elsif (cnt == 0 ) then
cnt = cnt
output_en = 1
elsif (cnt_en == 1) then
cnt −−
output_en = 0

13.11.9 Frequency Analyser

The frequency analyser block monitors a selected deglitched input (cpu_io_in_deglitch) or a direct selected input (deglitch_input) and detects positive edges. The selected input is configured by FreqAnaPinSelect and FreqAnaPinFormSel registers. Between successive positive edges detected on the input it increments a counter (FreqAnaCount) by a programmed amount (FreqAnaCountInc) on each clock cycle. When a positive edge is detected the FreqAnaLastPeriod register is updated with the top 16 bits of the counter and the counter is reset. The frequency analyser also maintains a running average of the FreqAnaLastPeriod register. Each time a positive edge is detected on the input the FreqAnaAverage register is updated with the new calculated FreqAnaLastPeriod. The average is calculated as ⅞ the current value plus ⅛ of the new value. The FreqAnaLastPeriod, FreqAnaCount and FreqAnaAverage registers can be written to by the CPU.

The pseudocode is given by

if ((pin == 1) AND pin_delay ==0 ))then // positive edge
detected
freq_ana_lastperiod[15:0] = freq_ana_count[31:16]
freq_ana_average[15:0] = freq_ana_average[15:0] −
freq_ana_average[15:3]
+
freq_ana_lastperiod[15:3]
freq_ana_count[15:0] = 0
else
freq_ana_count[31:0] = freq_ana_count[31:0] +
freq_ana_count_inc[19:0]
// implement the configuration register write
if (wr_last_en == 1) then
freq_ana_lastperiod = wr_data
elsif (wr_average_en == 1 ) then
freq_ana_average = wr_data
elsif (wr_freq_count_en == 1) then
freq_ana_count = wr_data

13.11.10 BLDC Motor Controller

The BLDC controller logic is identical for both instances, only the input connections are different. The logic implements the truth table shown in Table. The six q outputs are combinationally based on the direction, ha, hb, hc and pwm inputs. The direction input has 2 possible sources selected by the mode, the pseudocode is as follows

// determine if in internal or external direction mode
if (mode == 1) then// internal mode
direction = int_direction
else// external mode
direction = ext_direction

14 Interrupt Controller Unit (ICU)

The interrupt controller accepts up to N input interrupt sources, determines their priority, arbitrates based on the highest priority and generates an interrupt request to the CPU. The ICU complies with the interrupt acknowledge protocol of the CPU. Once the CPU accepts an interrupt (i.e. processing of its service routine begins) the interrupt controller will assert the next arbitrated interrupt if one is pending.

Each interrupt source has a fixed vector number N, and an associated configuration register, IntReg[N]. The format of the IntReg[N] register is shown in Table 87 below.

TABLE 87
IntReg[N] register format
Fieldbit(s)Description
Priority3:0Interrupt priority
Type5:4Determines the triggering conditions for the interrupt
00 - Positive edge
10 - Negative edge
01 - Positive level
11 - Negative level
Mask6Mask bit.
1 - Interrupts from this source are enabled,
0 - Interrupts from this source are disabled.
Note that there may be additional masks in operation at
the source of the interrupt.
Reserved31:7 Reserved. Write as 0.

Once an interrupt is received the interrupt controller determines the priority and maps the programmed priority to the appropriate CPU priority levels, and then issues an interrupt to the CPU. The programmed interrupt priority maps directly to the LEON CPU interrupt levels. Level 0 is no interrupt. Level 15 is the highest interrupt level.

14.1 Interrupt Preemption

With standard LEON pre-emption an interrupt can only be pre-empted by an interrupt with a higher priority level. If an interrupt with the same priority level (1 to 14) as the interrupt being serviced becomes pending then it is not acknowledged until the current service routine has completed. Note that the level 15 interrupt is a special case, in that the LEON processor will continue to take level 15 interrupts (i.e re-enter the ISR) as long as level 15 is asserted on the icu_cpu_ilevel. Level 0 is also a special case, in that LEON consider level 0 interrupts as no interrupt, and will not issue an acknowledge when level 0 is presented on the icu_cpu_ilevel bus.

Thus when pre-emption is required, interrupts should be programmed to different levels as interrupt priorities of the same level have no guaranteed servicing order. Should several interrupt sources be programmed with the same priority level, the lowest value interrupt source will be serviced first and so on in increasing order.

The interrupt is directly acknowledged by the CPU and the ICU automatically clears the pending bit of the lowest value pending interrupt source mapped to the acknowledged interrupt level.

All interrupt controller registers are only accessible in supervisor data mode. If the user code wishes to mask an interrupt it must request this from the supervisor and the supervisor software will resolve user access levels.

14.2 Interrupt Sources

The mapping of interrupt sources to interrupt vectors (and therefore IntReg[N] registers) is shown in Table 88 below. Please refer to the appropriate section of this specification for more details of the interrupt sources.

TABLE 88
Interrupt sources vector table
VectorSourceDescription
 0TimersWatchDog Timer Update request
 1TimersGeneric Timer 1 interrupt
 2TimersGeneric Timer 2 interrupt
 3PCUPEP Sub-system Interrupt- TE finished band
 4PCUPEP Sub-system Interrupt- LBD finished band
 5PCUPEP Sub-system Interrupt- CDU finished band
 6PCUPEP Sub-system Interrupt- CDU error
 7PCUPEP Sub-system Interrupt- PCU finished band
 8PCUPEP Sub-system Interrupt- PCU Invalid address
interrupt
 9PHIPEP Sub-system Interrupt- PHI Line Sync Interrupt
10PHIPEP Sub-system Interrupt- PHI Buffer underrun
11PHIPEP Sub-system Interrupt- PHI Page finished
12PHIPEP Sub-system Interrupt- PHI Print ready
13SCBUSB Host interrupt
14SCBUSB Device interrupt
15SCBISI interrupt
16SCBDMA interrupt
17LSSLSS interrupt, LSS interface 0 interrupt request
18LSSLSS interrupt, LSS interface 1 interrupt request
19-28GPIOGPIO general purpose interrupts
29TimersGeneric Timer 3 interrupt

14.3 Implentation

14.3.1 Definitions of I/O

TABLE 89
Interrupt Controller Unit I/O definition
Port namePinsI/ODescription
Clocks and Resets
Pclk1InSystem Clock
prst_n1InSystem reset, synchronous active low
CPU interface
cpu_adr[7:2]6InCPU address bus. Only 6 bits are required to
decode the address space for the ICU block
cpu_dataout[31:0]32InShared write data bus from the CPU
icu_cpu_data[31:0]32OutRead data bus to the CPU
cpu_rwn1InCommon read/not-write signal from the CPU
cpu_icu_sel1InBlock select from the CPU. When cpu_icu_sel is
high both cpu_adr and cpu_dataout are valid
icu_cpu_rdy1OutReady signal to the CPU. When icu_cpu_rdy is
high it indicates the last cycle of the access. For
a write cycle this means cpu_dataout has been
registered by the ICU block and for a read cycle
this means the data on icu_cpu_data is valid.
icu_cpu_ilevel[3:0]4OutIndicates the priority level of the current active
interrupt.
cpu_iack1InInterrupt request acknowledge from the LEON
core.
cpu_icu_ilevel[3:0]4InInterrupt acknowledged level from the LEON
core
icu_cpu_berr1OutBus error signal to the CPU indicating an invalid
access.
cpu_acode[1:0]2InCPU Access Code signals. These decode as
follows:
00 - User program access
01 - User data access
10 - Supervisor program access
11 - Supervisor data access
icu_cpu_debug_valid1OutDebug Data valid on icu_cpu_data bus. Active
high
Interrupts
tim_icu_wd_irq1InWatchdog timer interrupt signal from the Timers
block
tim_icu_irq[2:0]3InGeneric timer interrupt signals from the Timers
block
gpio_icu_irq[9:0]10InGPIO pin interrupts
usb_icu_irq[1:0]2InUSB host and device interrupts from the SCB
Bit 0 - USB Host interrupt
Bit 1 - USB Device interrupt
isi_icu_irq1InISI interrupt from the SCB
dma_icu_irq1InDMA interrupt from the SCB
lss_icu_irq[1:0]2InLSS interface interrupt request
cdu_finishedband1InFinished band interrupt request from the CDU
cdu_icu_jpegerror1InJPEG error interrupt from the CDU
lbd_finishedband1InFinished band interrupt request from the LBD
te_finishedband1InFinished band interrupt request from the TE
pcu_finishedband1InFinished band interrupt request from the PCU
pcu_icu_address_invalid1InInvalid address interrupt request from the PCU
phi_icu_underrun1InBuffer underrun interrupt request from the PHI
phi_icu_page_finish1InPage finished interrupt request from the PHI
phi_icu_print_rdy1InPrint ready interrupt request from the PHI
phi_icu_linesync_int1InLine sync interrupt request from the PHI

14.3.2 Configuration Registers

The configuration registers in the ICU are programmed via the CPU interface. Refer to section 11.4 on page 69 for a description of the protocol and timing diagrams for reading and writing registers in the ICU. Note that since addresses in SoPEC are byte aligned and the CPU only supports 32-bit register reads and writes, the lower 2 bits of the CPU address bus are not required to decode the address space for the ICU. When reading a register that is less than 32 bits wide zeros should be returned on the upper unused bit(s) of icu_pcu_data. Table 90 lists the configuration registers in the ICU block.

The ICU block will only allow supervisor data mode accesses (i.e. cpu_acode[1:0]=SUPERVISOR_DATA). All other accesses will result in icu_cpu_berr being asserted.

TABLE 90
ICU Register Map
Address
ICU_base+Register#bitsResetDescription
0x00-0x74IntReg[29:0]30x70x00Interrupt vector configuration register
0x88IntClear300x0000_0000Interrupt pending clear register. If written with a
one it clears corresponding interrupt
Bits[30:0] - Interrupts sources 30 to 0
(Reads as zero)
0x90IntPending300x0000_0000Interrupt pending register. (Read Only)
Bits[30:0]- Interrupts sources 30 to 0
0xA0IntSource 50x1FIndicates the interrupt source of the last acknowledged
interrupt. The NoInterrupt value is defined
as all bits set to one.
(Read Only)
0xC0DebugSelect[7:2] 60x00Debug address select. Indicates the address of
the register to report on the icu_cpu_data bus
when it is not otherwise being used.

14.3.3 ICU Partition
114.3.4 Interrupt Detect

The ICU contains multiple instances of the interrupt detect block, one per interrupt source. The interrupt detect block examines the interrupt source signal, and determines whether it should generate request pending (int_pend) based on the configured interrupt type and the interrupt source conditions. If the interrupt is not masked the interrupt will be reflected to the interrupt arbiter via the int_active signal. Once an interrupt is pending it remains pending until the interrupt is accepted by the CPU or it is level sensitive and gets removed. Masking a pending interrupt has the effect of removing the interrupt from arbitration but the interrupt will still remain pending.

When the CPU accepts the interrupt (using the normal ISR mechanism), the interrupt controller automatically generates an interrupt clear for that interrupt source (cpu_int_clear). Alternatively if the interrupt is masked, the CPU can determine pending interrupts by polling the IntPending registers. Any active pending interrupts can be cleared by the CPU without using an ISR via the IntClear registers.

Should an interrupt clear signal (either from the interrupt clear unit or the CPU) and a new interrupt condition happen at the same time, the interrupt will remain pending. In the particular case of a level sensitive interrupt, if the level remains the interrupt will stay active regardless of the clear signal.

The logic is shown below:

mask = int_config[6]
type = int_config[5:4]
int_pend = last_int_pend // the last pending
interrupt
// update the pending FF
// test for interrupt condition
if (type == NEG_LEVEL) then
int_pend = NOT(int_src)
elsif (type == POS_LEVEL)
int_pend = int_src
elsif ((type == POS_EDGE ) AND (int_src == 1) AND
(last_int_src == 0))
int_pend = 1
elsif ((type == NEG_EDGE ) AND (int_src == 0) AND
(last_int_src == 1))
int_pend = 1
elsif ((int_clear == 1 )OR (cpu_int_clear==1)) then
int_pend = 0
else
int_pend = last_int_pend // stay the same as before
// mask the pending bit
if (mask == 1) then
int_active = int_pend
else
int_active = 0
// assign the registers
last_int_src = int_src
last_int_pend = int_pend

14.3.5 Interrupt Arbiter

The interrupt arbiter logic arbitrates a winning interrupt request from multiple pending requests based on configured priority. It generates the interrupt to the CPU by setting icu_cpu_ilevel to a non-zero value. The priority of the interrupt is reflected in the value assigned to icu_cpu_ilevel, the higher the value the higher the priority, 15 being the highest, and 0 considered no interrupt.

// arbitrate with the current winner
int_ilevel = 0
for (i=0;i<30;i++) {
if ( int_active[i] == 1) then {
if (int_config[i][3:0] > win_int_ilevel[3:0] ) then
win_int_ilevel[3:0] = int_config[i][3:0]
}
}
}
// assign the CPU interrupt level
int_ilevel = win_int_ilevel[3:0]

14.3.6 Interrupt Clear Unit

The interrupt clear unit is responsible for accepting an interrupt acknowledge from the CPU, determining which interrupt source generated the interrupt, clearing the pending bit for that source and updating the IntSource register.

When an interrupt acknowledge is received from the CPU, the interrupt clear unit searches through each interrupt source looking for interrupt sources that match the acknowledged interrupt level (cpu_icu_ilevel) and determines the winning interrupt (lower interrupt source numbers have higher priority). When found the interrupt source pending bit is cleared and the IntSource register is updated with the interrupt source number.

The LEON interrupt acknowledge mechanism automatically disables all other interrupts temporarily until it has correctly saved state and jumped to the ISR routine. It is the responsibility of the ISR to re-enable the interrupts. To prevent the IntSource register indicating the incorrect source for an interrupt level, the ISR must read and store the IntSource value before re-enabling the interrupts via the Enable Traps (ET) field in the Processor State Register (PSR) of the LEON.

See section 11.9 on page 104 for a complete description of the interrupt handling procedure. After reset the state machine remains in Idle state until an interrupt acknowledge is received from the CPU (indicated by cpu_iack). When the acknowledge is received the state machine transitions to the Compare state, resetting the source counter (cnt) to the number of interrupt sources.

While in the Compare state the state machine cycles through each possible interrupt source in decrementing order. For each active interrupt source the programmed priority (int_priority[cnt][3:0]) is compared with the acknowledged interrupt level from the CPU (cpu_icu_ilevel), if they match then the interrupt is considered the new winner. This implies the last interrupt source checked has the highest priority, e.g interrupt source zero has the highest priority and the first source checked has the lowest priority. After all interrupt sources are checked the state machine transitions to the IntClear state, and updates the int_source register on the transition.

Should there be no active interrupts for the acknowledged level (e.g. a level sensitive interrupt was removed), the IntSource register will be set to NoInterrupt. NoInterrupt is defined as the highest possible value that IntSource can be set to (in this case 0x1F), and the state machine will return to Idle.

The exact number of compares performed per clock cycle is dependent the number of interrupts, and logic area to logic speed trade-off, and is left to the implementer to determine. A comparison of all interrupt sources must complete within 8 clock cycles (determined by the CPU acknowledge hardware).

When in the IntClear state the state machine has determined the interrupt source to clear (indicated by the int_source register). It resets the pending bit for that interrupt source, transitions back to the Idle state and waits for the next acknowledge from the CPU.

The minimum time between successive interrupt acknowledges from the CPU is 8 cycles.

15 Timers Block (TIM)

The Timers block contains general purpose timers, a watchdog timer and timing pulse generator for use in other sections of SoPEC.

15.1 Watchdog Timer

The watchdog timer is a 32 bit counter value which counts down each time a timing pulse is received. The period of the timing pulse is selected by the WatchDogUnitSel register. The value at any time can be read from the WatchDogTimer register and the counter can be reset by writing a non-zero value to the register. When the counter transitions from 1 to 0, a system wide reset will be triggered as if the reset came from a hardware pin.

The watchdog timer can be polled by the CPU and reset each time it gets close to 1, or alternatively a threshold (WatchDogIntThres) can be set to trigger an interrupt for the watchdog timer to be serviced by the CPU. If the WatchDogIntThres is set to N, then the interrupt will be triggered on the N to N−1 transition of the WatchDogTimer. This interrupt can be effectively masked by setting the threshold to zero. The watchdog timer can be disabled, without causing a reset, by writing zero to the WatchDogTimer register.

15.2 Timing Pulse Generator

The timing block contains a timing pulse generator clocked by the system clock, used to generate timing pulses of programmable periods. The period is programmed by accessing the TimerStartValue registers. Each pulse is of one system clock duration and is active high, with the pulse period accurate to the system clock frequency. The periods after reset are set to 1 us, 100 us and 100 ms.

The timing pulse generator also contains a 64-bit free running counter that can be read or reset by accessing the FreeRunCount registers. The free running counter can be used to determine elapsed time between events at system clock accuracy or could be used as an input source in low-security random number generator.

15.3 Generic Timers

SoPEC contains 3 programmable generic timing counters, for use by the CPU to time the system. The timers are programmed to a particular value and count down each time a timing pulse is received. When a particular timer decrements from 1 to 0, an interrupt is generated. The counter can be programmed to automatically restart the count, or wait until re-programmed by the CPU. At any time the status of the counter can be read from GenCntValue, or can be reset by writing to GenCntValue register. The auto-restart is activated by setting the GenCntAuto register, when activated the counter restarts at GenCntStartValue. A counter can be stopped or started at any time, without affecting the contents of the GenCntValue register, by writing a 1 or 0 to the relevent GenCntEnable register.

15.4 Implementation

15.4.1 Definitions of I/O

TABLE 91
Timers block I/O definition
Port namePinsI/ODescription
Clocks and Resets
Pclk1InSystem Clock
prst_n1InSystem reset, synchronous active low
tim_pulse[2:0]3OutTimers block generated timing pulses, each one pclk
wide
0 - Nominal 1 μs pulse
1 - Nominal 100 μs pulse
2 - Nominal 10 ms pulse
CPU interface
cpu_adr[6:2]5InCPU address bus. Only 5 bits are required to decode
the address space for the ICU block
cpu_dataout[31:0]32InShared write data bus from the CPU
tim_cpu_data[31:0]32OutRead data bus to the CPU
cpu_rwn1InCommon read/not-write signal from the CPU
cpu_tim_sel1InBlock select from the CPU. When cpu_tim_sel is high
both cpu_adr and cpu_dataout are valid
tim_cpu_rdy1OutReady signal to the CPU. When tim_cpu_rdy is high
it indicates the last cycle of the access. For a write
cycle this means cpu_dataout has been registered by
the TIM block and for a read cycle this means the
data on tim_cpu_data is valid.
tim_cpu_berr1OutBus error signal to the CPU indicating an invalid
access.
cpu_acode[1:0]2InCPU Access Code signals. These decode as follows:
00 - User program access
01 - User data access
10 - Supervisor program access
11 - Supervisor data access
tim_cpu_debug_valid1OutDebug Data valid on tim_cpu_data bus. Active high
Miscellaneous
tim_icu_wd_irq1OutWatchdog timer interrupt signal to the ICU block
tim_icu_irq[2:0]3OutGeneric timer interrupt signals to the ICU block
tim_cpr_reset_n1OutWatch dog timer system reset.

15.4.2 Timers Sub-Block Partition
15.4.3 Watchdog Timer

The watchdog timer counts down from pre-programmed value, and generates a system wide reset when equal to one. When the counter passes a pre-programmed threshold (wdog_tim_thres) value an interrupt is generated (tim_icu_wd_irq) requesting the CPU to update the counter. Setting the counter to zero disables the watchdog reset. In supervisor mode the watchdog counter can be written to or read from at any time, in user mode access is denied. Any accesses in user mode will generate a bus error.

The counter logic is given by

if (wdog_wen == 1) then
wdog_tim_cnt = write_data// load new data
elsif ( wdog_tim_cnt == 0) then
wdog_tim_cnt = wdog_tim_cnt// count disabled
elsif ( cnt_en == 1 ) then
wdog_tim_cnt−−
else
wdog_tim_cnt = wdog_tim_cnt

if (( wdog_tim_cnt == wdog_tim_thres) AND (wdog_tim_cnt != 0
)AND (cnt_en == 1)) then
tim_icu_wd_irq = 1
else
tim_icu_wd_irq = 0
// reset generator logic
if (wdog_tim_cnt == 1) AND (cnt_en == 1) then
tim_cpr_reset_n = 0
else
tim_cpr_reset_n = 1

15.4.4 Generic Timers

The generic timers block consists of 3 identical counters. A timer is set to a pre-configured value (GenCntStartValue) and counts down once per selected timing pulse (gen_unit_sel). The timer can be enabled or disabled at any time (gen_tim_en), when disabled the counter is stopped but not cleared. The timer can be set to automatically restart (gen_tim_auto) after it generates an interrupt. In supervisor mode a timer can be written to or read from at any time, in user mode access is determined by the GenCntUserModeEnable register settings.

The counter logic is given by

if (gen_wen == 1) then
gen_tim_cnt = write_data
elsif (( cnt_en == 1 )AND (gen_tim_en == 1 )) then
if ( gen_tim_cnt == 1) OR
( gen_tim_cnt == 0)  then  //
counter may need re-starting
if (gen_tim_auto == 1) then
gen_tim_cnt = gen_tim_cnt_st_value
else
gen_tim_cnt = 0 // hold
count at zero
else
gen_tim_cnt−−
else
gen_tim_cnt = gen_tim_cnt

if (gen_tim_cnt == 1)AND ( cnt_en == 1 )AND (gen_tim_en == 1
) then
tim_icu_irq = 1
else
tim_icu_irq = 0

15.4.5 Timing Pulse Generator

The timing pulse generator contains a general free running 64-bit timer and 3 timing pulse generators producing timing pulses of one cycle duration with a programmable period. The period is programmed by changed the TimerStartValue registers, but have a nominal starting period of 1 μs, 100 μs and 1 ms. In supervisor mode the free running timer register can be written to or read from at any time, in user mode access is denied. The status of each of the timers can be read by accessing the PulseTimerStatus registers in supervisor mode. Any accesses in user mode will result in a bus error.

15.4.5.1 Free Run Timer

The increment logic block increments the timer count on each clock cycle. The counter wraps around to zero and continues incrementing if overflow occurs. When the timing register (FreeRunCount) is written to, the configuration registers block will set the free_run_wen high for a clock cycle and the value on write_data will become the new count value. If free_run_wen[1] is 1 the higher 32 bits of the counter will be written to, otherwise if free_run_wen[0] the lower 32 bits are written to. It is the responsibility of software to handle these writes in a sensible manner.

The increment logic is given by

if (free_run_wen[1] == 1) then
free_run_cnt[63:32] = write_data
elsif (free_run_wen[0] == 1) then
free_run_cnt[31:0] = write_data
else
free_run_cnt ++

15.4.5.2 Pulse Timers

The pulse timer logic generates timing pulses of 1 clock cycle length and programmable period. Nominally they generate pulse periods of 1 μs, 100 μs and 1 ms. The logic for timer 0 is given by:

// Nominal 1us generator
if (pulse_0_cnt == 0 ) then
pulse_0_cnt = timer_start_value[0]
tim_pulse[0]= 1
else
pulse_0_cnt −−
tim_pulse[0]= 0

The logic for timer 1 is given by:

// 100us generator
if ((pulse_1_cnt == 0) AND (tim_pulse[0] == 1)) then
pulse_1_cnt = timer_start_value[1]
tim_pulse[1]= 1
elsif (tim_pulse[0] == 1) then
pulse_1_cnt −−
tim_pulse[1]= 0
else
pulse_1_cnt = pulse_1_cnt
tim_pulse[1]= 0

The logic for the timer 2 is given by:

// 10ms generator
if ((pulse_2_cnt == 0 ) AND (tim_pulse[1] == 1)) then
pulse_2_cnt = timer_start_value[2]
tim_pulse[2]= 1
elsif (tim_pulse[1] == 1) then
pulse_2_cnt −−
tim_pulse[2]= 0
else
pulse_2_cnt = pulse_2_cnt
tim_pulse[2]= 0

15.4.6 Configuration Registers

The configuration registers in the TIM are programmed via the CPU interface. Refer to section 11.4.3 on page 69 for a description of the protocol and timing diagrams for reading and writing registers in the TIM. Note that since addresses in SoPEC are byte aligned and the CPU only supports 32-bit register reads and writes, the lower 2 bits of the CPU address bus are not required to decode the address space for the TIM. When reading a register that is less than 32 bits wide zeros should be returned on the upper unused bit(s) of tim_pcu_data. Table 92 lists the configuration registers in the TIM block.

TABLE 92
Timers Register Map
Address TIM_base+Register#bitsResetDescription
0x00WatchDogUnitSel 20x0Specifies the units used for the
watchdog timer:
0 - Nominal 1 μs pulse
1 - Nominal 100 μs pulse
2 - Nominal 10 ms pulse
3 - pclk
0x04WatchDogTimer320xFFFF_FFFFSpecifies the number of units to count
before watchdog timer triggers.
0x08WatchDogIntThres320x0000_0000Specifies the threshold value below
which the watchdog timer issues an
interrupt
0x0C-0x10FreeRunCount[1:0]2x320x0000_0000Direct access to the free running
counter register.
Bus 0 - Access to bits 31-0
Bus 1 - Access to bits 63-32
0x14 to 0x1CGenCntStartValue[2:0]3x320x0000_0000Generic timer counter start value,
number of units to count before event
0x20 to 0x28GenCntValue[2:0]3x320x0000_0000Direct access to generic timer counter
registers
0x2C to 0x34GenCntUnitSel[2:0]3x20x0Generic counter unit select. Selects
the timing units used with
corresponding counter:
0 - Nominal 1 μs pulse
1 - Nominal 100 μs pulse
2 - Nominal 10 ms pulse
3 - pclk
0x38 to 0x40GenCntAuto[2:0]3x10x0Generic counter auto re-start select.
When high timer automatically
restarts, otherwise timer stops.
0x44 to 0x4CGenCntEnable[2:0]3x10x0Generic counter enable.
0 - Counter disabled
1 - Counter enabled
0x50GenCntUserMode 30x0User Mode Access enable to generic
Enabletimer configuration register. When 1
user access is enabled.
Bit 0 - Generic timer 0
Bit 1 - Generic timer 1
Bit 2 - Generic timer 2
0x54 to 0x5CTimerStartValue[2:0]3x80x7F,Timing pulse generator start value.
0x63,Indicates the start value for each
0x63timing pulse timers. For timer 0 the
start value specifies the timer period
in pclk cycles −1.
For timer 1 the start value specifies
the timer period in timer 0 intervals −1.
For timer 2 the start value specifies
the timer period in timer 1 intervals −1.
Nominally the timers generate pulses
at 1 us, 100 us and 10 ms intervals
respecitively.
0x60DebugSelect[6:2] 50x00Debug address select. Indicates the
address of the register to report on
the tim_cpu_data bus when it is not
otherwise being used.
Read Only
Registers
0x64PulseTimerStatus240x00Current pulse timer values, and
pulses
7:0 - Timer 0 count
15:8 - Timer 1 count
23:16 - Timer 2 count
24 - Timer 0 pulse
25 - Timer 1 pulse
26 - Timer 2 pulse

15.4.6.1 Supervisor and User Mode Access

The configuration registers block examines the CPU access type (cpu_acode signal) and determines if the access is allowed to that particular register, based on configured user access registers. If an access is not allowed the block will issue a bus error by asserting the tim_cpu_berr signal.

The timers block is fully accessible in supervisor data mode, all registers can written to and read from. In user mode access is denied to all registers in the block except for the generic timer configuration registers that are granted user data access. User data access for a generic timer is granted by setting corresponding bit in the GenCntUserModeEnable register. This can only be changed in supervisor data mode. If a particular timer is granted user data access then all registers for configuring that timer will be accessible. For example if timer 0 is granted user data access the GenCntStartValue[0], GenCntUnitSel[0], GenCntAuto[0], GenCntEnable[0] and GenCntValue[0] registers can all be written to and read from without any restriction.

Attempts to access a user data mode disabled timer configuration register will result in a bus error. Table 93 details the access modes allowed for registers in the TIM block. In supervisor data mode all registers are accessable. All forbidden accesses will result in a bus error (tim_cpu_berr asserted).

TABLE 93
TIM supervisor and user access modes
Register
AddressRegistersAccess Permission
0x00WatchDogUnitSelSupervisor data mode only
0x04WatchDogTimerSupervisor data mode only
0x08WatchDogIntThresSupervisor data mode only
0x0C-0x10FreeRunCountSupervisor data mode only
0x14GenCntStartValue[0]GenCntUserModeEnable[0]
0x18GenCntStartValue[1]GenCntUserModeEnable[1]
0x1CGenCntStartValue[2]GenCntUserModeEnable[2]
0x20GenCntValue[0]GenCntUserModeEnable[0]
0x24GenCntValue[1]GenCntUserModeEnable[1]
0x28GenCntValue[2]GenCntUserModeEnable[2]
0x2CGenCntUnitSel[0]GenCntUserModeEnable[0]
0x30GenCntUnitSel[1]GenCntUserModeEnable[1]
0x34GenCntUnitSel[2]GenCntUserModeEnable[2]
0x38GenCntAuto[0]GenCntUserModeEnable[0]
0x3CGenCntAuto[1]GenCntUserModeEnable[1]
0x40GenCntAuto[2]GenCntUserModeEnable[2]
0x44GenCntEnable[0]GenCntUserModeEnable[0]
0x48GenCntEnable[1]GenCntUserModeEnable[1]
0x4CGenCntEnable[2]GenCntUserModeEnable[2]
0x50GenCntUserModeEnableSupervisor data mode only
0x54-0x5CTimerStartValue[2:0]Supervisor data mode only
0x60DebugSelectSupervisor data mode only
0x64PulseTimerStatusSupervisor data mode only

16 Clocking, Power and Reset (CPR)

The CPR block provides all of the clock, power enable and reset signals to the SoPEC device.

16.1 Powerdown Modes

The CPR block is capable of powering down certain sections of the SoPEC device. When a section is powered down (i.e. put in sleep mode) no state is retained (except the PSS storage), the CPU must re-initialize the section before it can be used again.

For the purpose of powerdown the SoPEC device is divided into sections:

TABLE 94
Powerdown sectioning
SectionBlock
Print Engine PipelinePCU
SubSystem (Section 0)
CDU
CFU
LBD
SFU
TE
TFU
HCU
DNC
DWU
LLU
PHI
CPU-DRAM (Section 1)DRAM
CPU/MMU
DIU
TIM
ROM
LSS
PSS
ICU
ISI Subsystem (Section 2)ISI (SCB)
DMA Ctrl (SCB)
GPIO
USB Subsystem (Section 3)USB (SCB)

Note that the CPR block is not located in any section. All configuration registers in the CPR block are clocked by an ungateable clock and have special reset conditions.

Note that the CPR block is not located in any section. All configuration registers in the CPR block are clocked by an ungateable clock and have special reset conditions.

16.1.1 Sleep Mode

Each section can be put into sleep mode by setting the corresponding bit in the SleepModeEnable register. To re-enable the section the sleep mode bit needs to be cleared and then the section should be reset by writing to the relevant bit in the ResetSection register. Each block within the section should then be re-configured by the CPU.

If the CPU system (section 1) is put into sleep mode, the SoPEC device will remain in sleep mode until a system level reset is initiated from the reset pin, or a wakeup reset by the SCB block as a result of activity on either the USB or ISI bus. The watchdog timer cannot reset the device as it is in section 1 also, and will be in sleep mode.

If the CPU and ISI subsystem are in sleep mode only a reset from the USB or a hardware reset will re-activate the SoPEC device.

If all sections are put into sleep mode, then only a system level reset initiated by the reset pin will re-activate the SoPEC device.

Like all software resets in SoPEC the ResetSection register is active-low i e. a 0 should be written to each bit position requiring a reset. The ResetSection register is self-reseting.

16.1.2 Sleep Mode Powerdown Procedure

When powering down a section, the section may retain it's current state (although not gauranteed to). It is possible when powering back up a section that inconsistencies between interface state machines could cause incorrect operation. In order to prevent such condition from happening, all blocks in a section must be disabled before powering down. This will ensure that blocks are restored in a benign state when powered back up.

In the case of PEP section units setting the Go bit to zero will disable the block. The DRAM subsystem can be effectively disabled by setting the RotationSync bit to zero, and the SCB system disabled by setting the DMAAccessEn bits to zero turning off the DMA access to DRAM. Other CPU subsystem blocks without any DRAM access do not need to be disabled.

16.2 Reset Source

The SoPEC device can be reset by a number of sources. When a reset from an internal source is initiated the reset source register (ResetSrc) stores the reset source value. This register can then be used by the CPU to determine the type of boot sequence required.

16.3 Clock Relationship

The crystal oscillator excites a 32 MHz crystal through the xtalin and xtalout pins. The 32 MHz output is used by the PLL to derive the master VCO frequency of 960 MHz. The master clock is then divided to produce 320 MHz clock (clk320), 160 MHz clock (clk160) and 48 MHz (clk48) clock sources.

The phase relationship of each clock from the PLL will be defined. The relationship of internal clocks clk320, clk48 and clk160 to xtalin will be undefined.

At the output of the clock block, the skew between each pclk domain (pclk_section[2:0] and jclk) should be within skew tolerances of their respective domains (defined as less than the hold time of a D-type flip flop).

The skew between doclk and pclk should also be less than the skew tolerances of their respective domains.

The usbclk is derived from the PLL output and has no relationship with the other clocks in the system and is considered asynchronous.

16.4 PLL Control

The PLL in SoPEC can be adjusted by programming the PLLRangeA, PLLRangeB, PLLTunebits and PLLMult registers. If these registers are changed by the CPU the values are not updated until the PLLUpdate register is written to. Writing to the PLLUpdate register triggers the PLL control state machine to update the PLL configuration in a safe way. When an update is active (as indicated by PLLUpdate register) the CPU must not change any of the configuration registers, doing so could cause the PLL to lose lock indefintely, requiring a hardware reset to recover. Configuring the PLL registers in an inconsistent way can also cause the PLL to lose lock, care must taken to keep the PLL configuration within specified parameters.

The VCO frequency of the PLL is calculated by the number of divider in the feedback path. PLL output A is used as the feedback source.
VCOfreq=REFCLK×PLLMult×PLLRangeA×External divider
VCOfreq=32×3×10×1=960 Mhz.

In the default PLL setup, PLLMult is set to 3, PLLRangeA is set to 3 which corresponds to a divide by 10, PLLRangeB is set to 5 which corresponds to a divide by 3.
PLLouta=VCOfreq/PLLRangeA=960 Mhz/10=96 Mhz
PLLoutb=VCOfreq/PLLRangeB=960 Mhz/3=320 Mhz

See [16] for complete PLL setup parameters.

16.5 Implementation

16.5.1 Definitions of I/O

TABLE 95
CPR I/O definition
Port namePinsI/ODescription
Clocks and Resets
Xtalin1InCrystal input, direct from IO pin.
Xtalout1InoutCrystal output, direct to IO pin.
pclk_section[3:0]4OutSystem clocks for each section
Doclk1OutData out clock (2x pclk) for the PHI block
Jclk1OutGated version of system clock used to clock the
JPEG decoder core in the CDU
Usbclk1OutUSB clock, nominally at 48 Mhz
jclk_enable1InGating signal for jclk. When 1 jclk is enabled
reset_n1InReset signal from the reset_n pin
usb_cpr_reset_n1InReset signal from the USB block
isi_cpr_reset_n1InReset signal from the ISI block
tim_cpr_reset_n1InReset signal from watch dog timer.
gpio_cpr_wakeup1InSoPEC wake up from the GPIO, active high.
prst_n_section[3:0]4OutSystem resets for each section, synchronous
active low
dorst_n1OutReset for PHI block, synchronous to doclk
jrst_n1OutReset for JPEG decoder core in CDU block,
synchronous to jclk
usbrst_n1OutReset for the USB block, synchronous to usbclk
CPU interface
cpu_adr[5:2]3InCPU address bus. Only 4 bits are required to
decode the address space for the CPR block
cpu_dataout[31:0]32InShared write data bus from the CPU
cpr_cpu_data[31:0]32OutRead data bus to the CPU
cpu_rwn1InCommon read/not-write signal from the CPU
cpu_cpr_sel1InBlock select from the CPU. When cpu_cpr_sel is
high both cpu_adr and cpu_dataout are valid
cpr_cpu_rdy1OutReady signal to the CPU. When cpr_cpu_rdy is
high it indicates the last cycle of the access. For a
write cycle this means cpu_dataout has been
registered by the block and for a read cycle this
means the data on cpr_cpu_data is valid.
cpr_cpu_berr1OutBus error signal to the CPU indicating an invalid
access.
cpu_acode[1:0]2InCPU Access Code signals. These decode as
follows:
00 - User program access
01 - User data access
10 - Supervisor program access
11 - Supervisor data access
cpr_cpu_debug_valid1OutDebug Data valid on cpr_cpu_data bus. Active
high

16.5.2 Configuration Registers

The configuration registers in the CPR are programmed via the CPU interface. Refer to section 11.4 on page 69 for a description of the protocol and timing diagrams for reading and writing registers in the CPR. Note that since addresses in SoPEC are byte aligned and the CPU only supports 32-bit register reads and writes, the lower 2 bits of the CPU address bus are not required to decode the address space for the CPR. When reading a register that is less than 32 bits wide zeros should be returned on the upper unused bit(s) of cpr_pcu_data. Table 96 lists the configuration registers in the CPR block.

The CPR block will only allow supervisor data mode accesses (i.e. cpu_acode[1:0]=SUPERVISOR_DATA). All other accesses will result in cpr_cpu_berr being asserted.

TABLE 96
CPR Register Map
Address
CPR_base+Register#bitsResetDescription
0x00SleepModeEnable40x0aSleep Mode enable, when high a section
of logic is put into powerdown.
Bit 0 - Controls section 0
Bit 1 - Controls section 1
Bit 2 - Controls section 2
Bit 3 - Controls section 3
Note that the SleepModeEnable register
has special reset conditions. See
Section 16.5.6 for details
0x04ResetSrc50x1aReset Source register, indicating the
source of the last reset (or wake-up)
Bit 0 - External Reset
Bit 1 - USB wakeup reset
Bit 2 - ISI wakeup reset
Bit 3 - Watchdog timer reset
Bit 4 - GPIO wake-up
(Read Only Register)
0x08ResetSection40xFActive-low synchronous reset for each
section, self-resetting.
Bit 0 - Controls section 0
Bit 1 - Controls section 1
Bit 2 - Controls section 2
Bit 3 - Controls section 3
0x0CDebugSelect[5:2]40x0Debug address select. Indicates the
address of the register to report on the
cpr_cpu_data bus when it is not
otherwise being used.
PLL Control
0x10PLLTuneBits100x3BCPLL tuning bits
0x14PLLRangeA40x3PLLOUT A frequency selector (defaults
to 60 Mhz to 125 Mhz)
0x18PLLRangeB30x5PLLOUT B frequency selector (defaults
to 200 Mhz to 400 Mhz)
0x1CPLLMultiplier50x03PLL multiplier selector, defaults to
refclk × 3
0x20PLLUpdate10x0PLL update control. A write (of any
value) to this register will cause the
PLL to lose lock for ˜100 us. Reading
the register indicates the status of the
update.
0 - PLL update complete
1 - PLL update active
No writes to
PLLTuneBits, PLLRangeA, PLL-
RangeB, PLLMultiplier or PLLUpdate
are allowed while the PLL update is
active.

aReset value depends on reset source. External reset shown.
    • a. Reset value depends on reset source. External reset shown.
      16.5.3 CPR Sub-Block Partition
      16.5.4 Reset_n deglitch

The external reset_n signal is deglitched for about 1 μs. reset_n must maintain a state for 1 us second before the state is passed into the rest of the device. All deglitch logic is clocked on bufrefclk.

16.5.5 Sync Reset

The reset synchronizer retimes an asynchronous reset signal to the clock domain that it resets. The circuit prevents the inactive edge of reset occurring when the clock is rising

16.5.6 Reset Generator Logic

The reset generator logic is used to determine which clock domains should be reset, based on configured reset values (reset_section_n), the external reset (reset_n), watchdog timer reset (tim_cpr_reset_n), the USB reset (usb_cpr_reset_n), the GPIO wakeup control (gpio_cpr_wakeup) and the ISI reset (isi_cpr_reset_n). The reset direct from the IO pin (reset_n) is synchronized and de-glitched before feeding the reset logic.

All resets are lengthened to at least 16 pclk cycles, regardless of the duration of the input reset. The clock for a particular section must be running for the reset to have an effect. The clocks to each section can be enabled/disabled using the SleepModeEnable register.

Resets from the ISI or USB block reset everything except its own section (section 2 or 3).

TABLE 97
Reset domains
Reset signalDomain
reset_dom[0]Section 0 pclk domain (PEP)
reset_dom[1]Section 1 pclk domain (CPU)
reset_dom[2]Section 2 pclk domain (ISI)
reset_dom[3]Section 3 usbclk/pclk domain
(USB)
reset_dom[4]doclk domain
reset_dom[5]jclk domain

The logic is given by

if (reset_dg_n == 0) then
reset_dom[5:0]= 0x00// reset everything
reset_src[4:0]= 0x01
cfg_reset_n= 0
sleep_mode_en[3:0]= 0x0// re-awaken all sections
elsif (tim_cpr_reset_n == 0) then
reset_dom[5:0] = 0x00// reset everything except
CPR config
reset_src[4:0]= 0x08
cfg_reset_n= 1// CPR config stays the same
sleep_mode_en[1]  = 0// re-awaken section 1 only
(awake already)
elsif (usb_cpr_reset_n == 0) then
reset_dom[5:0] = 0x08// all except USB domain +
CPR config
reset_src[4:0]= 0x02
cfg_reset_n= 1// CPR config stays the same
sleep_mode_en[1]= 0// re-awaken section 1 only,
section 3 is awake
elsif (isi_cpr_reset_n == 0) then
reset_dom[5:0] = 0x04// all except ISI domain +
CPR config
reset_src[4:0]= 0x04
cfg_reset_n= 1// CPR config stays the same
sleep_mode_en[1]= 0// re-awaken section 1 only,
section 2 is awake
elsif (gpio_cpr_wakeup = 1) then
reset_dom[5:0]= 0x3C// PEP and CPU sections only
reset_src[4:0]= 0x10
cfg_reset_n= 1// CPR config stays the same
sleep_mode_en[1]= 0// re-awaken section 1 only,
section 2 is awake
else
// propagate resets from reset section register
reset_dom[5:0]= 0x3F // default to on
cfg_reset_n   = 1 // CPR cfg
registers are not in any section
sleep_mode_en[3:0] = sleep_mode_en[3:0] // stay
the same
by default
if (reset_section_n[0] == 0) then
reset_dom[5] = 0// jclk domain
reset_dom[4] = 0// doclk domain
reset_dom[0] = 0// pclk section 0 domain
if (reset_section_n[1] == 0) then
reset_dom[1] = 0// pclk section 1 domain
if (reset_section_n[2] == 0) then
reset_dom[2] = 0// pclk section 2 domain
(ISI)
if (reset_section_n[3] == 0) then
reset_dom[3] = 0// USB domain

16.5.7 Sleep Logic

The sleep logic is used to generate gating signals for each of SoPECs clock domains. The gate enable (gate_dom) is generated based on the configured sleep_mode_en and the internally generated jclk_enable signal.

The logic is given by

// clock gating for sleep modes
gate_dom[5:0] = 0x0 // default to all clocks
on
if (sleep_mode_en[0] == 1) then// section 0 sleep
gate_dom[0] = 1// pclk section 0
gate_dom[4] = 1// doclk domain
gate_dom[5] = 1// jclk domain
if (sleep_mode_en[1] == 1) then // section 1 sleep
gate_dom[1] = 1// pclk section 1
if (sleep_mode_en[2] == 1) then // section 2 sleep
gate_dom[2] = 1// pclk section 2
if (sleep_mode_en[3] == 1) then // section 3 sleep
gate_dom[3] = 1// usb section 3
// the jclk can be turned off by CDU signal
if (jclk_enable == 0) then
gate_dom[5] = 1

The clock gating and sleep logic is clocked with the master_pclk clock which is not gated by this logic, but is synchronous to other pclk_section and jclk domains.

Once a section is in sleep mode it cannot generate a reset to restart the device. For example if section 1 is in sleep mode then the watchdog timer is effectively disabled and cannot trigger a reset.

16.5.8 Clock Gate Logic

The clock gate logic is used to safely gate clocks without generating any glitches on the gated clock. When the enable is high the clock is active otherwise the clock is gated

16.5.9 Clock Generator Logic

The clock generator block contains the PLL, crystal oscillator, clock dividers and associated control logic. The PLL VCO frequency is at 960 MHz locked to a 32 MHz refclk generated by the crystal oscillator. In test mode the xtalin signal can be driven directly by the test clock generator, the test clock will be reflected on the refclk signal to the PLL.

16.5.9.1 Clock Divider A

The clock divider A block generates the 48 MHz clock from the input 96 MHz clock (pllouta) generated by the PLL. The divider is enabled only when the PLL has acquired lock.

16.5.9.2 Clock Divider B

The clock divider B block generates the 160 MHz clocks from the input 320 MHz clock (plloutb) generated by the PLL. The divider is enabled only when the PLL has acquired lock.

16.5.9.3 PLL Control State Machine

The PLL will go out of lock whenever pll_reset goes high (the PLL reset is the only active high reset in the device) or if the configuration bits pll_rangea, pll_rangeb, pll_mult, pll_tune are changed. The PLL control state machine ensures that the rest of the device is protected from glitching clocks while the PLL is being reset or it's configuration is being changed.

In the case of a hardware reset (the reset is deglitched), the state machine first disables the output clocks (via the clk_gate signal), it then holds the PLL in reset while its configuration bits are reset to default values. The state machine then releases the PLL reset and waits approx. 100 us to allow the PLL to regain lock. Once the lock time has elapsed the state machine re-enables the output clocks and resets the remainder of the device via the reset_dg_n signal.

When the CPU changes any of the configuration registers it must write to the PLLupdate register to allow the state machine to update the PLL to the new configuration setup. If a PLLUpdate is detected the state machine first gates the output clocks. It then holds the PLL in reset while the PLL configuration registers are updated. Once updated the PLL reset is released and the state machine waits approx 100 us for the PLL to regain lock before re-enabling the output clocks. Any write to the PLLUpdate register will cause the state machine to perform the update operation regardless of whether the configuration values changed or not.

All logic in the clock generator is clocked on bufrefclk which is always an active clock regardless of the state of the PLL.

17 ROM Block

17.1 Overview

The ROM block interfaces to the CPU bus and contains the SoPEC boot code. The ROM block consists of the CPU bus interface, the ROM macro and the ChipID macro. The current ROM size is 16 KBytes implemented as a 4096×32 macro. Access to the ROM is not cached because the CPU enjoys fast (no more than one cycle slower than a cache access), unarbitrated access to the ROM. Each SoPEC device is required to have a unique ChipID which is set by blowing fuses at manufacture. IBM's 300 mm ECID macro and a custom 112-bit ECID macro are used to implement the ChipID offering 224-bits of laser fuses. The exact number of fuse bits to be used for the ChipID will be determined later but all bits are made available to the CPU. The ECID macros allows all 224 bits to be read out in parallel and the ROM block will make all 224 bits available in the FuseChipID[N] registers which are readable by the CPU in supervisor mode only.

17.2 Boot Operation

The are two boot scenarIOs for the SoPEC device namely after power-on and after being awoken from sleep mode. When the device is in sleep mode it is hoped that power will actually be removed from the DRAM, CPU and most other peripherals and so the program code will need to be freshly downloaded each time the device wakes up from sleep mode. In order to reduce the wakeup boot time (and hence the perceived print latency) certain data items are stored in the PSS block (see section 18). These data items include the SHA-1 hash digest expected for the program(s) to be downloaded, the master/slave SoPEC id and some configuration parameters. All of these data items are stored in the PSS by the CPU prior to entering sleep mode. The SHA-1 value stored in the PSS is calculated by the CPU by decrypting the signature of the downloaded program using the appropriate public key stored in ROM. This compute intensive decryption only needs to take place once as part of the power-on boot sequence—subsequent wakeup boot sequences will simply use the resulting SHA-1 digest stored in the PSS. Note that the digest only needs to be stored in the PSS before entering sleep mode and the PSS can be used for temporary storage of any data at all other times.

The CPU is expected to be in supervisor mode for the entire boot sequence described by the pseudocode below. Note that the boot sequence has not been finalised but is expected to be close to the following:

if (ResetSrc == 1) then // Reset was a power-on reset
configure_sopec // need to configure peris (USB, ISI,
DMA, ICU etc.)
// Otherwise reset was a wakeup reset so peris etc. were
already configured
PAUSE: wait until IrqSemaphore != 0 // i.e. wait until an
interrupt has been serviced
if (IrqSemaphore == DMAChan0Msg) then
parse_msg(DMAChan0MsgPtr) // this routine will parse the
message and take any
// necessary action e.g. programming
the DMAChannel1 registers
elsif (IrqSemaphore == DMAChan1Msg) then // program has
been downloaded
CalculatedHash = gen_sha1(ProgramLocn, ProgramSize)
if (ResetSrc == 1) then
ExpectedHash = sig_decrypt(ProgramSig,public_key)
else
ExpectedHash = PSSHash
if (ExpectedHash == CalculatedHash) then
jmp(PrgramLocn) // transfer control to the downloaded
program
else
send_host_msg(“Program Authentication Failed”)
goto PAUSE:
elsif (IrqSemaphore == timeout) then // nothing has
happened
if (ResetSrc == 1) then
sleep_mode( ) // put SoPEC into sleep mode to be woken
up by USB/ISI activity
else // we were woken up but nothing happened
reset_sopec(PowerOnReset)
else
goto PAUSE

The boot code places no restrictions on the activity of any programs downloaded and authenticated by it other than those imposed by the configuration of the MMU i.e. the principal function of the boot code is to authenticate that any programs downloaded by it are from a trusted source. It is the responsibility of the downloaded program to ensure that any code it downloads is also authenticated and that the system remains secure. The downloaded program code is also responsible for setting the SoPEC ISIId (see section 12.5 for a description of the ISIID) in a multi-SoPEC system. See the “SoPEC Security Overview” document [9] for more details of the SoPEC security features.

17.3 Implementation

17.3.1 Definitions of I/O

TABLE 98
ROM Block I/O
Port namePinsI/ODescription
Clocks and Resets
prst_n1InGlobal reset. Synchronous to pclk,
active low.
Pclk1InGlobal clock
CPU Interface
cpu_adr[14:2]13InCPU address bus. Only 13 bits are
required to decode the address
space for this block.
rom_cpu_data[31:0]32OutRead data bus to the CPU
cpu_rwn1InCommon read/not-write signal
from the CPU
cpu_acode[1:0]2InCPU Access Code signals. These
decode as follows:
00 - User program access
01 - User data access
10 - Supervisor program access
11 - Supervisor data access
cpu_rom_sel1InBlock select from the CPU. When
cpu_rom_sel is high cpu_adr
is valid
rom_cpu_rdy1OutReady signal to the CPU. When
rom_cpu_rdy is high it indicates
the last cycle of the access. For
a read cycle this means the data on
rom_cpu_data is valid.
rom_cpu_berr1OutROM bus error signal to the CPU
indicating an invalid access.

17.3.2 Configuration Registers

The ROM block will only allow read accesses to the FuseChipID registers and the ROM with supervisor data space permissions (i.e. cpu_acode[1:0]=11). Write accesses with supervisor data space permissions

will have no effect. All other accesses with will result in rom_cpu_berr being asserted. The CPU subsystem bus slave interface is described in more detail in section 9.4.3.

TABLE 99
ROM Block Register Map
Address
ROM_base+Register#bitsResetDescription
0x4000FuseChipID032n/aValue of corresponding fuse
bits 31 to 0 of the IBM
112-bit ECID macro. (Read
only)
0x4004FuseChipID132n/aValue of corresponding fuse
bits 63 to 32 of the IBM
112-bit ECID macro. (Read
only)
0x4008FuseChipID232n/aValue of corresponding fuse
bits 95 to 64 of the IBM
112-bit ECID macro. (Read
only)
0x400CFuseChipID316n/aValue of corresponding fuse
bits 111 to 96 of the IBM
112-bit ECID macro. (Read
only)
0x4010FuseChipID432n/aValue of corresponding fuse
bits 31 to 0 of the Custom
112-bit ECID macro. (Read
only)
0x4014FuseChipID532n/aValue of corresponding fuse
bits 63 to 32 of the Custom
112-bit ECID macro. (Read
only)
0x4018FuseChipID632n/aValue of corresponding fuse
bits 95 to 64 of the Custom
112-bit ECID macro. (Read
only)
0x401CFuseChipID716n/aValue of corresponding fuse
bits 111 to 96 of the Custom
112-bit ECID macro. (Read
only)

17.3.3 Sub-Block Partition

IBM offer two variants of their ROM macros; A high performance version (ROMHD) and a low power version (ROMLD). It is likely that the low power version will be used unless some implementation issue requires the high performance version. Both versions offer the same bit density. The sub-block partition diagram below does not include the clocking and test signals for the ROM or ECID macros. The CPU subsystem bus interface is described in more detail in section 11.4.3.

17.3.4

TABLE 100
ROM Block internal signals
Port nameWidthDescription
Clocks and Resets
prst_n1Global reset. Synchronous to pclk, active
low.
Pclk1Global clock
Internal Signals
rom_adr[11:0]12ROM address bus
rom_sel1Select signal to the ROM macro
instructing it to access the location at
rom_adr
rom_oe1Output enable signal to the ROM block
rom_data[31:0]32Data bus from the ROM macro to the CPU
bus interface
rom_dvalid1Signal from the ROM macro indicating
that the data on rom_data is valid for the
address on rom_adr
fuse_data[31:0]32Data from the FuseChipID[N] register
addressed by fuse_reg_adr
fuse_reg_adr[2:0]3Indicates which of the FuseChipID
registers is being addressed

Sub-Block Signal Definition
18 Power Safe Storage (PSS) Block
18.1 Overview

The PSS block provides 128 bytes of storage space that will maintain its state when the rest of the SoPEC device is in sleep mode. The PSS is expected to be used primarily for the storage of decrypted signatures associated with downloaded programmed code but it can also be used to store any information that needs to survive sleep mode (e.g. configuration details). Note that the signature digest only needs to be stored in the PSS before entering sleep mode and the PSS can be used for temporary storage of any data at all other times.

Prior to entering sleep mode the CPU should store all of the information it will need on exiting sleep mode in the PSS. On emerging from sleep mode the boot code in ROM will read the ResetSrc register in the CPR block to determine which reset source caused the wakeup. The reset source information indicates whether or not the PSS contains valid stored data, and the PSS data determines the type of boot sequence to execute. If for any reason a full power-on boot sequence should be performed (e.g. the printer driver has been updated) then this is simply achieved by initiating a full software reset.

Note that a reset or a powerdown (powerdown is implemented by clock gating) of the PSS block will not clear the contents of the 128 bytes of storage. If clearing of the PSS storage is required, then the CPU must write to each location individually.

18.2 Implementation

The storage area of the PSS block will be implemented as a 128-byte register array. The array is located from PSS_base through to PSS_base+0x7F in the address map. The PSS block will only allow read or write accesses with supervisor data space permissions (i.e. cpu_acode[1:0]=11). All other accesses will result in pss_cpu_berr being asserted. The CPU subsystem bus slave interface is described in more detail in section 11.4.3.

18.2.1 Definitions of I/O

TABLE 101
PSS Block I/O
Port namePinsI/ODescription
Clocks and Resets
prst_n1InGlobal reset. Synchronous to pclk,
active low.
Pclk1InGlobal clock
CPU Interface
cpu_adr[6:2]5InCPU address bus. Only 5 bits are
required to decode the address
space for this block.
cpu_dataout[31:0]32InShared write data bus from the CPU
pss_cpu_data[31:0]32OutRead data bus to the CPU
cpus_rwn1InCommon read/not-write signal from
the CPU
cpu_acode[1:0]2InCPU Access Code signals. These
decode as follows:
00 - User program access
01 - User data access
10 - Supervisor program access
11 - Supervisor data access
cpu_pss_sel1InBlock select from the CPU. When
cpu_pss_sel is high both cpu_adr
and cpu_dataout are valid
pss_cpu_rdy1OutReady signal to the CPU. When
pss_cpu_rdy is high it indicates
the last cycle of the access. For a read
cycle this means the data on
pss_cpu_data is valid.
pss_cpu_berr1OutPSS bus error signal to the CPU
indicating an invalid access.

19 Low Speed Serial Interface (LSS)
19.1 Overview

The Low Speed Serial Interface (LSS) provides a mechanism for the internal SoPEC CPU to communicate with external QA chips via two independent LSS buses. The LSS communicates through the GPIO block to the QA chips. This allows the QA chip pins to be reused in multi-SoPEC environments. The LSS Master system-level interface is illustrated in FIG. 75. Note that multiple QA chips are allowed on each LSS bus.

19.2 QA Communication

The SoPEC data interface to the QA Chips is a low speed, 2 pin, synchronous serial bus. Data is transferred to the QA chips via the lss_data pin synchronously with the lss_clk pin. When the lss_clk is high the data on lss_data is deemed to be valid. Only the LSS master in SoPEC can drive the lss_clk pin, this pin is an input only to the QA chips. The LSS block must be able to interface with an open-collector pull-up bus. This means that when the LSS block should transmit a logical zero it will drive 0 on the bus, but when it should transmit a logical 1 it will leave high-impedance on the bus (i.e. it doesn't drive the bus). If all the agents on the LSS bus adhere to this protocol then there will be no issues with bus contention.

The LSS block controls all communication to and from the QA chips. The LSS block is the bus master in all cases. The LSS block interprets a command register set by the SoPEC CPU, initiates transactions to the QA chip in question and optionally accepts return data. Any return information is presented through the configuration registers to the SoPEC CPU. The LSS block indicates to the CPU the completion of a command or the occurrence of an error via an interrupt. The LSS protocol can be used to communicate with other LSS slave devices (other than QA chips). However should a LSS slave device hold the clock low (for whatever reason), it will be in violation of the LSS protocol and is not supported. The LSS clock is only ever driven by the LSS master.

19.2.1 Start and Stop Conditions

All transmissions on the LSS bus are initiated by the LSS master issuing a START condition and terminated by the LSS master issuing a STOP condition. START and STOP conditions are always generated by the LSS master. As illustrated in FIG. 76, a START condition corresponds to a high to low transition on lss_data while lss_clk is high. A STOP condition corresponds to a low to high transition on lss_data while lss_clk is high.

19.2.2 Data Transfer

Data is transferred on the LSS bus via a byte orientated protocol. Bytes are transmitted serially. Each byte is sent most significant bit (MSB) first through to least significant bit (LSB) last. One clock pulse is generated for each data bit transferred. Each byte must be followed by an acknowledge bit.

The data on the lss_data must be stable during the HIGH period of the lss_clk clock. Data may only change when lss_clk is low. A transmitter outputs data after the falling edge of lss_clk and a receiver inputs the data at the rising edge of lss_clk. This data is only considered as a valid data bit at the next lss_clk falling edge provided a START or STOP is not detected in the period before the next lss_clk falling edge. All clock pulses are generated by the LSS block. The transmitter releases the lss_data line (high) during the acknowledge clock pulse (ninth clock pulse). The receiver must pull down the lss_data line during the acknowledge clock pulse so that it remains stable low during the HIGH period of this clock pulse.

Data transfers follow the format shown in FIG. 77. The first byte sent by the LSS master after a START condition is a primary id byte, where bits 7-2 form a 6-bit primary id (0 is a global id and will address all QA Chips on a particular LSS bus), bit 1 is an even parity bit for the primary ID, and bit 0 forms the read/write sense. Bit 0 is high if the following command is a read to the primary id given or low for a write command to that id. An acknowledge is generated by the QA chip(s) corresponding to the given id (if such a chip exists) by driving the lss_data line low synchronous with the LSS master generated ninth lss_clk.

19.2.3 Write Procedure

The protocol for a write access to a QA Chip over the LSS bus is illustrated in FIG. 79 below. The LSS master in SoPEC initiates the transaction by generating a START condition on the LSS bus. It then transmits the primary id byte with a 0 in bit 0 to indicate that the following command is a write to the primary id. An acknowledge is generated by the QA chip corresponding to the given primary id. The LSS master will clock out M data bytes with the slave QA Chip acknowledging each successful byte written. Once the slave QA chip has acknowledged the Mth data byte the LSS master issues a STOP condition to complete the transfer. The QA chip gathers the M data bytes together and interprets them as a command. See QA Chip Interface Specification for more details on the format of the commands used to communicate with the QA chip[8]. Note that the QA chip is free to not acknowledge any byte transmitted. The LSS master should respond by issuing an interrupt to the CPU to indicate this error. The CPU should then generate a STOP condition on the LSS bus to gracefully complete the transaction on the LSS bus.

19.2.4 Read Procedure

The LSS master in SoPEC initiates the transaction by generating a START condition on the LSS bus. It then transmits the primary id byte with a 1 in bit 0 to indicate that the following command is a read to the primary id. An acknowledge is generated by the QA chip corresponding to the given primary id. The LSS master releases the lss_data bus and proceeds to clock the expected number of bytes from the QA chip with the LSS master acknowledging each successful byte read. The last expected byte is not acknowledged by the LSS master. It then completes the transaction by generating a STOP condition on the LSS bus. See QA Chip Interface Specification for more details on the format of the commands used to communicate with the QA chip[8].

19.3 Implementation

A block diagram of the LSS master is given in FIG. 80. It consists of a block of configuration registers that are programmed by the CPU and two identical LSS master units that generate the signalling protocols on the two LSS buses as well as interrupts to the CPU. The CPU initiates and terminates transactions on the LSS buses by writing an appropriate command to the command register, writes bytes to be transmitted to a buffer and reads bytes received from a buffer, and checks the sources of interrupts by reading status registers.

19.3.1 Definitions of IO

TABLE 102
LSS IO pins definitions
Port namePinsI/ODescription
Clocks and Resets
Pclk1InSystem Clock
prst_n1InSystem reset, synchronous active low
CPU Interface
cpu_rwn1InCommon read/not-write signal from the CPU
cpu_adr[6:2]5InCPU address bus. Only 5 bits are required to
decode the address space for this block
cpu_dataout[31:0]32InShared write data bus from the CPU
cpu_acode[1:0]2InCPU access code signals.
cpu_acode[0] - Program (0)/Data (1) access
cpu_acode[1] - User (0)/Supervisor (1) access
cpu_lss_sel1InBlock select from the CPU. When cpu_lss_sel is
high both cpu_adr and cpu_dataout are valid
lss_cpu_rdy1OutReady signal to the CPU. When lss_cpu_rdy is high
it indicates the last cycle of the access. For a write
cycle this means cpu_dataout has been registered
by the LSS block and for a read cycle this means
the data on lss_cpu_data is valid.
lss_cpu_berr1OutLSS bus error signal to the CPU.
lss_cpu_data[31:0]32OutRead data bus to the CPU
lss_cpu_debug_valid1OutActive high. Indicates the presence of valid debug
data on lss_cpu_data.
GPIO for LSS buses
lss_gpio_dout[1:0]2OutLSS bus data output
Bit 0 - LSS bus 0
Bit 1 - LSS bus 1
gpio_lss_din[1:0]2InLSS bus data input
Bit 0 - LSS bus 0
Bit 1 - LSS bus 1
lss_gpio_e[1:0]2OutLSS bus data output enable, active high
Bit 0 - LSS bus 0
Bit 1 - LSS bus 1
lss_gpio_clk[1:0]2OutLSS bus clock output
Bit 0 - LSS bus 0
Bit 1 - LSS bus 1
ICU interface
lss_icu_irq[1:0]2OutLSS interrupt requests
Bit 0 - interrupt associated with LSS bus 0
Bit 1 - interrupt associated with LSS bus 1

19.3.2 Configuration Registers

The configuration registers in the LSS block are programmed via the CPU interface. Refer to section 11.4 on page 69 for the description of the protocol and timing diagrams for reading and writing registers in the LSS block. Note that since addresses in SoPEC are byte aligned and the CPU only supports 32-bit register reads and writes, the lower 2 bits of the CPU address bus are not required to decode the address space for the LSS block. Table 103 lists the configuration registers in the LSS block. When reading a register that is less than 32 bits wide zeros should be returned on the upper unused bit(s) of lss_cpu_data.

The input cpu_acode signal indicates whether the current CPU access is supervisor, user, program or data. The configuration registers in the LSS block can only be read or written by a supervisor data access, i.e. when cpu_acode equals b11. If the current access is a supervisor data access then the LSS responds by asserting lss_cpu_rdy for a single clock cycle.

If the current access is anything other than a supervisor data access, then the LSS generates a bus error by asserting lss_cpu_berr for a single clock cycle instead of lss_cpu_rdy as shown in section 11.4 on page 69. A write access will be ignored, and a read access will return zero.

TABLE 103
LSS Control Registers
Address
(LSS_base+)Register#bitsResetDescription
Control registers
0x00Reset10x1A write to this register causes a reset of the
LSS.
0x04LssClockHighLow-160x00C8Lss_clk has a 50:50 duty cycle, this register
Durationdefines the period of lss_clk by means of
specifying the duration (in pclk cycles) that
lss_clk is low (or high).
The reset value specifies transmission over
the LSS bus at a nominal rate of 400 kHz,
corresponding to a low (or high) duration of
200 pclk (160 Mhz) cycles.
Register should not be set to values less
than 8.
0x08LssClocktoDataHold60x3Specifies the number of pclk cycles that Data
must remain valid for after the falling edge of
lss_clk.
Minimum value is 3 cycles, and must to
programmed to be less than
LssClockHighLowDuration.
LSS bus 0 registers
0x10Lss0IntStatus30x0LSS bus 0 interrupt status registers
Bit 0 - command completed successfully
Bit 1 - error during processing of command,
not-acknowledge received after
transmission
of primary id byte on LSS bus 0
Bit 2 - error during processing of command,
not-acknowledge received after
transmission
of data byte on LSS bus 0
All the bits in Lss0IntStatus are cleared when
the Lss0Cmd register gets written to.
(Read only register)
0x14Lss0CurrentState40x0Gives the current state of the LSS bus 0
state machine. (Read only register).
(Encoding will be specified upon state
machine implementation)
0x18Lss0Cmd210x00_0000Command register defining sequence of
events to perform on LSS bus 0 before
interrupting CPU.
A write to this register causes all the bits in
the Lss0IntStatus register to be cleared as
well as generating a lss0_new_cmd pulse.
0x1C-0x2CLss0Buffer[4:0]5x320x0000_0000LSS Data buffer. Should be filled with
transmit data before transmit command, or
read data bytes received after a valid read
command.
LSS bus 1 registers
0x30Lss1IntStatus30x0LSS bus 1 interrupt status registers
Bit 0 - command completed successfully
Bit 1 - error during processing of command,
not-acknowledge received after
transmission
of primary id byte on LSS bus 1
Bit 2 - error during processing of command,
not-acknowledge received after
transmission
of data byte on LSS bus 1
All the bits in Lss1IntStatus are cleared when
the Lss1Cmd register gets written to.
(Read only register)
0x34Lss1CurrentState40x0Gives the current state of the LSS bus 1
state machine. (Read only register)
(Encoding will be specified upon state
machine implementation)
0x38Lss1Cmd210x00_0000Command register defining sequence of
events to perform on LSS bus 1 before
interrupting CPU.
A write to this register causes all the bits in
the Lss1IntStatus register to be cleared as
well as generating a lss1_new_cmd pulse.
0x3C-0x4CLss1Buffer[4:0]5x320x0000_0000LSS Data buffer. Should be filled with
transmit data before transmit command, or
read data bytes received after a valid read
command.
Debug registers
0x50LssDebugSel[6:2]50x00Selects register for debug output. This value
is used as the input to the register decode
logic instead of cpu_adr[6:2] when the LSS
block is not being accessed by the CPU, i.e.
when cpu_lss_sel is 0.
The output lss_cpu_debug_valid is asserted
to indicate that the data on lss_cpu_data is
valid debug data. This data can be
mutliplexed onto chip pins during debug
mode.

19.3.2.1 LSS Command Registers

The LSS command registers define a sequence of events to perform on the respective LSS bus before issuing an interrupt to the CPU. There is a separate command register and interrupt for each LSS bus. The format of the command is given in Table 104. The CPU writes to the command register to initiate a sequence of events on an LSS bus. Once the sequence of events has completed or an error has occurred, an interrupt is sent back to the CPU.

Some example commands are:

    • a single START condition (Start=1, IdByteEnable=0, RdWrEnable=0, Stop=0)
    • a single STOP condition (Start=0, IdByteEnable=0, RdWrEnable=0, Stop=1)
    • a START condition followed by transmission of the id byte (Start=1, IdByteEnable=1, RdWrEnable=0, Stop=0, IdByte contains primary id byte)
    • a write transfer of 20 bytes from the data buffer (Start=0, IdByteEnable=0, RdWrEnable=1, RdWrSense=0, Stop=0, TxRxByteCount=20)
    • a read transfer of 8 bytes into the data buffer (Start=0, IdByteEnable=0, RdWrEnable=1, RdWrSense=1, ReadNack=0, Stop=0, TxRxByteCount=8)
    • a complete read transaction of 16 bytes (Start=1, IdByteEnable=1, RdWrEnable=1, RdWrSense=1, ReadNack=1, Stop=1, IdByte contains primary id byte, TxRxByteCount=16), etc.

The CPU can thus program the number of bytes to be transmitted or received (up to a maximum of 20) on the LSS bus before it gets interrupted. This allows it to insert arbitrary delays in a transfer at a byte boundary. For example the CPU may want to transmit 30 bytes to a QA chip but insert a delay between the 20th and 21st bytes sent. It does this by first writing 20 bytes to the data buffer. It then writes a command to generate a START condition, send the primary id byte and then transmit the 20 bytes from the data buffer. When interrupted by the LSS block to indicate successful completion of the command the CPU can then write the remaining 10 bytes to the data buffer. It can then wait for a defined period of time before writing a command to transmit the 10 bytes from the data buffer and generate a STOP condition to terminate the transaction over the LSS bus.

An interrupt to the CPU is generated for one cycle when any bit in LssNIntStatus is set. The CPU can read LssNIntStatus to discover the source of the interrupt. The LssNIntStatus registers are cleared when the CPU writes to the LssNCmd register. A null command write to the LssNCmd register will cause the LssNIntStatus registers to clear and no new command to start. A null command is defined as Start, IdbyteEnable, RdWrEnable and Stop all set to zero.

TABLE 104
LSS command register description
bit(s)nameDescription
0StartWhen 1, issue a START condition on the LSS bus.
1IdByteEnableID byte transmit enable:
1 - transmit byte in IdByte field
0 - ignore byte in IdByte field
2RdWrEnableRead/write transfer enable:
0 - ignore settings of RdWrSense, ReadNack and
TxRxByteCount
1 - if RdWrSense is 0, then perform a write transfer of
TxRxByteCount bytes from the
data buffer.
if RdWrSense is 1, then perform a read transfer of
TxRxByteCount bytes into the
data buffer. Each byte should be acknowledged and
the last byte received is
acknowledged/not-acknowledged according to the setting of
ReadNack.
3RdWrSenseRead/write sense indicator:
0 - write
1 - read
4ReadNackIndicates, for a read transfer, whether to issue an
acknowledge or a not-acknowledge after the last byte
received (indicated by TxRxByteCount).
0 - issue acknowledge after last byte received
1 - issue not-acknowledge after last byte received.
5StopWhen 1, issue a STOP condition on the LSS bus.
7:6reservedMust be 0
15:8 IdByteByte to be transmitted if IdByteEnable is 1. Bit 8
corresponds to the LSB.
20:16TxRxByteCountNumber of bytes to be transmitted from the data buffer or
the number of bytes to be received into the data buffer.
The maximum value that should be programmed is 20, as
the size of the data buffer is 20 bytes. Valid values are 1
to 20, 0 is valid when RdWrEnable = 0, other cases are invalid
andundefined.

The data buffer is implemented in the LSS master block. When the CPU writes to the LssNBuffer registers the data written is presented to the LSS master block via the lssN_buffer_wrdata bus and configuration registers block pulses the lssN_buffer_wen bit corresponding to the register written. For example if LssNBuffer[2] is written to lssN_buffer_wen[2] will be pulsed. When the CPU reads the LssNBuffer registers the configuration registers block reflect the lssN_buffer_rdata bus back to the CPU.

19.3.3 LSS Master Unit

The LSS master unit is instantiated for both LSS bus 0 and LSS bus 1. It controls transactions on the LSS bus by means of the state machine shown in FIG. 83, which interprets the commands that are written by the CPU. It also contains a single 20 byte data buffer used for transmitting and receiving data.

The CPU can write data to be transmitted on the LSS bus by writing to the LssNBuffer registers. It can also read data that the LSS master unit receives on the LSS bus by reading the same registers. The LSS master always transmits or receives bytes to or from the data buffer in the same order.

For a transmit command, LssNBuffer[0][7:0] gets transmitted first, then LssNBuffer[0][15:8], LssNBuffer[0][23:16], LssNBuffer[0][31:24], LssNBuffer[1][7:0] and so on until TxRxByteCount number of bytes are transmitted. A receive command fills data to the buffer in the same order. Each new command the buffer start point is reset.

All state machine outputs, flags and counters are cleared on reset. After a reset the state machine goes to the Reset state and initialises the LSS pins (lss_clk is set to 1, lss_data is tristated and allowed to be pulled up to 1). When the reset condition is removed the state machine transitions to the Wait state.

It remains in the Wait state until lss_new_cmd equals 1. If the Start bit of the command is 0 the state machine proceeds directly to the CheckIdByteEnable state. If the Start bit is 1 it proceeds to the GenerateStart state and issues a START condition on the LSS bus.

In the CheckIdByteEnable state, if the IdByteEnable bit of the command is 0 the state machine proceeds directly to the CheckRdWrEnable state. If the IdByteEnable bit is 1 the state machine enters the SendIdByte state and the byte in the IdByte field of the command is transmitted on the LSS. The WaitForIdAck state is then entered. If the byte is acknowledged, the state machine proceeds to the CheckRdWrEnable state. If the byte is not-acknowledged, the state machine proceeds to the GenerateInterrupt state and issues an interrupt to indicate a not-acknowledge was received after transmission of the primary id byte.

In the CheckRdWrEnable state, if the RdWrEnable bit of the command is 0 the state machine proceeds directly to the CheckStop state. If the RdWrEnable bit is 1, count is loaded with the value of the TxRxByteCount field of the command and the state machine enters either the ReceiveByte state if the RdWrSense bit of the command is 1 or the TransmitByte state if the RdWrSense bit is 0.

For a write transaction, the state machine keeps transmitting bytes from the data buffer, decrementing count after each byte transmitted, until count is 1. If all the bytes are successfully transmitted the state machine proceeds to the CheckStop state. If the slave QA chip not-acknowledges a transmitted byte, the state machine indicates this error by issuing an interrupt to the CPU and then entering the GenerateInterrupt state.

For a read transaction, the state machine keeps receiving bytes into the data buffer, decrementing count after each byte transmitted, until count is 1. After each byte received the LSS master must issue an acknowledge. After the last expected byte (i.e. when count is 1) the state machine checks the ReadNack bit of the command to see whether it must issue an acknowledge or not-acknowledge for that byte. The CheckStop state is then entered.

In the CheckStop state, if the Stop bit of the command is 0 the state machine proceeds directly to the GenerateInterrupt state. If the Stop bit is 1 it proceeds to the GenerateStop state and issues a STOP condition on the LSS bus before proceeding to the GenerateInterrupt state. In both cases an interrupt is issued to indicate successful completion of the command.

The state machine then enters the Wait state to await the next command. When the state machine reenters the Wait state the output pins (lss_and lss_clk) are not changed, they retain the state of the last command. This allows the possibility of multi-command transactions. The CPU may abort the current transfer at any time by performing a write to the Reset register of the LSS block.

19.3.3.1 START and STOP Generation

START and STOP conditions, which signal the beginning and end of data transmission, occur when the LSS master generates a falling and rising edge respectively on the data while the clock is high.

In the GenerateStart state, lss_gpio_clk is held high with lss_gpio_e remaining deasserted (so the data line is pulled high externally) for LssClockHighLowDuration pclk cycles. Then lss_gpio_e is asserted and lss_gpio_dout is pulled low (to drive a 0 on the data line, creating a falling edge) with lss_gpio_clk remaining high for another LssClockHighLowDuration pclk cycles. In the GenerateStop state, both lss_gpio_clk and lss_gpio_dout are pulled low followed by the assertion of lss_gpio_e to drive a 0 while the clock is low. After LssClockHighLowDuration pclk cycles, lss_gpio_clk is set high. After a further LssClockHighLowDuration pclk cycles, lss_gpio_e is deasserted to release the data bus and create a rising edge on the data bus during the high period of the clock.

If the bus is not in the required state for start and stop generation (lss_clk=1, lss_data=1 for start, and lss_clk=1, lss_data=0), the state machine moves the bus to the correct state and proceeds as described above. FIG. 82 shows the transition timing from any bus state to start and stop generation

19.3.3.2 Clock Pulse Generation

The LSS master holds lss_gpio_clk high while the LSS bus is inactive. A clock pulse is generated for each bit transmitted or received over the LSS bus. It is generated by first holding lss_gpio_clk low for LssClockHighLowDuration pclk cycles, and then high for LssClockHighLowDuration pclk cycles.

19.3.3.3 Data De-Glitching

When data is received in the LSS block it is passed to a de-glitching circuit. The de-glitch circuit samples the data 3 times on pclk and compares the samples. If all 3 samples are the same then the data is passed, otherwise the data is ignored.

Note that the LSS data input on SoPEC is double registered in the GPIO block before being passed to the LSS.

19.3.3.4 Data Reception

The input data, gpio_lss_di, is first synchronised to the pclk domain by means of two flip-flops clocked by pclk (the double register resides in the GPIO block). The LSS master generates a clock pulse for each bit received. The output lss_gpio_e is deasserted LssClockToDataHold pclk cycles after the falling edge of lss_gpio_clk to release the data bus. The value on the synchronised gpio_lss_di is sampled Tstrobe number of clock cycles after the rising edge of lss_gpio_clk (the data is de-glitched over a further 3 stage register to avoid possible glitch detection). See FIG. 84 for further timing information.

In the ReceiveByte state, the state machine generates 8 clock pulses. At each Tstrobe time after the rising edge of lss_gpio_clk the synchronised gpio_lss_di is sampled. The first bit sampled is LssNBuffer[0][7], the second LssNBuffer[0][6], etc to LssNBuffer[0][0]. For each byte received the state machine either sends an NAK or an ACK depending on the command configuration and the number of bytes received.

In the SendNack state the state machine generates a single clock pulse. lss_gpio_e is deasserted and the LSS data line is pulled high externally to issue a not-acknowledge.

In the SendAck state the state machine generates a single clock pulse. lss_gpio_e is asserted and a 0 driven on lss_gpio_dout after lss_gpio_clk falling edge to issue an acknowledge.

19.3.3.5 Data Transmission

The LSS master generates a clock pulse for each bit transmitted. Data is output on the LSS bus on the falling edge of lss_gpio_clk.

When the LSS master drives a logical zero on the bus it will assert lss_gpio_e and drive a 0 on lss_gpio_dout after lss_gpio_clk falling edge. lss_gpio_e will remain asserted and lss_gpio_dout will remain low until the next lss_clk falling edge.

When the LSS master drives a logical one lss_gpio_e should be deasserted at lss_gpio_clk falling edge and remain deasserted at least until the next lss_gpio_clk falling edge. This is because the LSS bus will be externally pulled up to logical one via a pull-up resistor.

In the SendId byte state, the state machine generates 8 clock pulses to transmit the byte in the IdByte field of the current valid command. On each falling edge of lss_gpio_clk a bit is driven on the data bus as outlined above. On the first falling edge IdByte[7] is driven on the data bus, on the second falling edge IdByte[6] is driven out, etc.

In the TransmitByte state, the state machine generates 8 clock pulses to transmit the byte at the output of the transmit FIFO. On each falling edge of lss_gpio_clk a bit is driven on the data bus as outlined above. On the first falling edge LssNBuffer[0][7] is driven on the data bus, on the second falling edge LssNBuffer[0][6] is driven out, etc on to LssNBuffer[0][7] bits.

In the WaitForAck state, the state machine generates a single clock pulse. At Tstrobe time after the rising edge of lss_gpio_clk the synchronized gpio_lss_di is sampled. A 0 indicates an acknowledge and ack_detect is pulsed, a 1 indicates a not-acknowledge and nack_detect is pulsed.

19.3.3.6 Data Rate Control

The CPU can control the data rate by setting the clock period of the LSS bus clock by programming appropriate value in LssClockHighLowDuration. The default setting for the register is 200 (pclk cycles) which corresponds to transmission rate of 400 kHz on the LSS bus (the lss_clk is high for LssClockHighLowDuration cycles then low for LssClockHighLowDuration cycles). The lss_clk will always have a 50:50 duty cycle. The LssClockHighLowDuration register should not be set to values less than 8.

The hold time of lss_data after the falling edge of lss_clk is programmable by the LssClocktoDataHold register. This register should not be programmed to less than 2 or greater than the LssClockHighLowDuration value.

19.3.3.7 LSS Master Timing Parameters

The LSS master timing parameters are shown in FIG. 84 and the associated values are shown in Table 105.

TABLE 105
LSS master timing parameters
ParameterDescriptionminnommaxunit
LSS Master Driving
TpLSS clock period divided by 28200FFFFpclk cycles
Tstart_delayTime to start data edge from risingTp + LssClocktoDataHoldpclk cycles
clock edge
Tstop_delayTime to stop data edge from risingTp + LssClocktoDataHoldpclk cycles
clock edge
Tdata_setupTime from data setup to rising clockTp − 2 − LssClocktoDataHoldpclk cycles
edge
Tdata_holdTime from falling clock edge to dataLssClocktoDataHoldpclk cycles
hold
Tack_setupTime that outgoing (N)Ack is setupTp − 2 − LssClocktoDataHoldpclk cycles
before lss_clk rising edge
Tack_holdTime that outgoing (N)Ack is heldLssClocktoDataHoldpclk cycles
after lss_clk falling edge
LSS Master Sampling
TstrobeLSS master strobe point forTp −2Tp −2pclk cycles
incoming data and (N)Ack values

DRAM Subsystem

20 DRAM Interface Unit (DIU)

20.1 Overview

FIG. 85 shows how the DIU provides the interface between the on-chip 20 Mbit embedded DRAM and the rest of SoPEC. In addition to outlining the functionality of the DIU, this chapter provides a top-level overview of the memory storage and access patterns of SoPEC and the buffering required in the various SoPEC blocks to support those access requirements.

The main functionality of the DIU is to arbitrate between requests for access to the embedded DRAM and provide read or write accesses to the requesters. The DIU must also implement the initialisation sequence and refresh logic for the embedded DRAM.

The arbitration scheme uses a fully programmable timeslot mechanism for non-CPU requesters to meet the bandwidth and latency requirements for each unit, with unused slots re-allocated to provide best effort accesses. The CPU is allowed high priority access, giving it minimum latency, but allowing bounds to be placed on its bandwidth consumption.

The interface between the DIU and the SoPEC requesters is similar to the interface on PEC1 i.e. separate control, read data and write data busses.

The embedded DRAM is used principally to store:

    • CPU program code and data.
    • PEP (re)programming commands.
    • Compressed pages containing contone, bi-level and raw tag data and header information.
    • Decompressed contone and bi-level data.
    • Dotline store during a print.
    • Print setup information such as tag format structures, dither matrices and dead nozzle information.
      20.2 IBM Cu-11 Embedded DRAM
      20.2.1 Single Bank

SoPEC will use the 1.5 V core voltage option in IBM's 0.13 μm class Cu-11 process.

The random read/write cycle time and the refresh cycle time is 3 cycles at 160 MHz [16]. An open page access will complete in 1 cycle if the page mode select signal is clocked at 320 MHz or 2 cycles if the page mode select signal is clocked every 160 MHz cycle. The page mode select signal will be clocked at 160 MHz in SoPEC in order to simplify timing closure. The DRAM word size is 256 bits.

Most SoPEC requesters will make single 256 bit DRAM accesses (see Section 20.4). These accesses will take 3 cycles as they are random accesses i.e. they will most likely be to a different memory row than the previous access.

The entire 20 Mbit DRAM will be implemented as a single memory bank. In Cu-11, the maximum single instance size is 16 Mbit. The first 1 Mbit tile of each instance contains an area overhead so the cheapest solution in terms of area is to have only 2 instances. 16 Mbit and 4 Mbit instances would together consume an area of 14.63 mm2 as would 2 times 10 Mbit instances. 4 times 5 Mbit instances would require 17.2 mm2.

The instance size will determine the frequency of refresh. Each refresh requires 3 clock cycles. In Cu-11 each row consists of 8 columns of 256-bit words. This means that 10 Mbit requires 5120 rows. A complete DRAM refresh is required every 3.2 ms. Two times 10 Mbit instances would require a refresh every 100 clock cycles, if the instances are refreshed in parallel.

The SoPEC DRAM will be constructed as two 10 Mbit instances implemented as a single memory bank.

20.3 SoPEC Memory Usage Requirements

The memory usage requirements for the embedded DRAM are shown in Table 106.

TABLE 106
Memory Usage Requirements
BlockSizeDescription
Compressed page2048KbytesCompressed data page store for Bi-
storelevel
and contone data
Decompressed108Kbyte13824 lines with scale factor 6 = 2304
Contone Storepixels, store 12 lines, 4 colors = 108 kB
13824 lines with scale factor 5 = 2765
pixels, store 12 lines, 4 colors = 130 kB
Spot line store5.1Kbyte13824 dots/line so 3 lines is 5.1 kB
Tag Format StructureTypically 12Kbyte (2.5 mm55 kB in for 384 dot line tags
tags @ 800 dpi)2.5 mm tags (1/10th inch) @ 1600 dpi
require 160 dot lines = 160/384 ×55 or
23 kB
2.5 mm tags (1/10th inch) @ 800 dpi
require 80/384 ×55 = 12 kB
Dither Matrix store4Kbytes64×64 dither matrix is 4 kB
128×128 dither matrix is 16 kB
256×256 dither matrix is 64 kB
DNC Dead Nozzle1.4KbytesDelta encoded, (10 bit delta position + 6
Tabledead nozzle mask) x % Dnozzle
5% dead nozzles requires (10 + 6)×692
Dnozzles = 1.4 Kbytes
Dot-line store369.6KbytesAssume each color row is separated
by 5 dot lines on the print head
The dot line store will be
0+5+10...50+55 = 330 half dot lines + 48
extra half dot lines (4 per dot row) + 60
extra half dot lines estimated to
account for printhead misalignment = 438
half dot lines.
438 half dot lines of 6912 dots = 369.6 Kbytes
PCU Program code8Kbytes1024 commands of 64 bits = 8 kB
CPU64KbytesProgram code and data
TOTAL2620Kbytes (12 Kbyte TFS
storage)

Note:

Total storage is fixed to 2560 Kbytes to align to 20 Mbit DRAM. This will mean that less space than noted in Table may be available for the compressed band store.

20.4 SoPEC Memory Access Patterns

Table 107 shows a summary of the blocks on SoPEC requiring access to the embedded DRAM and their individual memory access patterns. Most blocks will access the DRAM in single 256-bit accesses. All accesses must be padded to 256-bits except for 64-bit CDU write accesses and CPU write accesses. Bits which should not be written are masked using the individual DRAM bit write inputs or byte write inputs, depending on the foundry. Using single 256-bit accesses means that the buffering required in the SoPEC DRAM requesters will be minimized.

TABLE 107
Memory access patterns of SoPEC DRAM Requesters
DRAM requesterDirectionMemory access pattern
CPURSingle 256-bit reads.
WSingle 32-bit, 16-bit or 8-bit writes.
SCBRSingle 256-bit reads.
WSingle 256-bit writes, with byte enables.
CDURSingle 256-bit reads of the compressed contone data.
WEach CDU access is a write to 4 consecutive DRAM words in the
same row but only 64 bits of each word are written with the remaining
bits write masked.
The access time for this 4 word page mode burst is 3 + 2 + 2 + 2 = 9
cycles if the page mode select signal is clocked at 160 MHz.
CFURSingle 256 bit reads.
LBDRSingle 256 bit reads.
SFURSeparate single 256 bit reads for previous and current line but sharing
the same DIU interface
WSingle 256 bit writes.
TE(TD)RSingle 256 bit reads. Each read returns 2 times 128 bit tags.
TE(TFS)RSingle 256 bit reads. TFS is 136 bytes. This means there is unused
data in the fifth 256 bit read. A total of 5 reads is required.
HCURSingle 256 bit reads. 128 × 128 dither matrix requires 4 reads per line
with double buffering. 256 × 256 dither matrix requires 8 reads at the
end of the line with single buffering.
DNCRSingle 256 bit dead nozzle table reads. Each dead nozzle table read
contains 16 dead-nozzle tables entries each of 10 delta bits plus 6
dead nozzle mask bits.
DWUWSingle 256 bit writes since enable/disable DRAM access per color
plane.
LLURSingle 256 bit reads since enable/disable DRAM access per color
plane.
PCURSingle 256 bit reads. Each PCU command is 64 bits so each 256 bit
word can contain 4 PCU commands.
PCU reads from DRAM used for reprogramming PEP should be
executed with minimum latency.
If this occurs between pages then there will be free bandwidth as most
of the other SoPEC Units will not be requesting from DRAM. If this
occurs between bands then the LDB, CDU and TE bandwidth will be
free. So the PCU should have a high priority to access to any spare
bandwidth.
RefreshSingle refresh.

20.5 Buffering Required in SoPEC DRAM Requesters

If each DIU access is a single 256-bit access then we need to provide a 256-bit double buffer in the DRAM requester. If the DRAM requester has a 64-bit interface then this can be implemented as an 8×64-bit FIFO.

TABLE 108
Buffer sizes in SoPEC DRAM requesters
Buffering required in
DRAM RequesterDirectionAccess patternsblock
CPURSingle 256-bit reads.Cache.
WSingle 32-bit writes but allowing 16-bit orNone.
byte addressable writes.
SCBRSingle 256-bit reads.Double 256-bit buffer.
WSingle 256-bit writes, with byte enables.Double 256-bit buffer.
CDURSingle 256-bit reads of the compressedDouble 256-bit buffer.
contone data.
WEach CDU access is a write to 4Double half JPEG block
consecutive DRAM words in the samebuffer.
row but only 64 bits of each word are
written with the remaining bits write
masked.
CFURSingle 256 bit reads.Triple 256-bit buffer.
LBDRSingle 256 bit reads.Double 256-bit buffer.
SFURSeparate single 256 bit reads forDouble 256-bit buffer for
previous and current line but sharingeach read channel.
the same DIU interface
WSingle 256 bit writes.Double 256-bit buffer.
TE(TD)RSingle 256 bit reads.Double 256-bit buffer.
TE(TFS)RSingle 256 bit reads. TFS is 136 bytes.Double line-buffer for
This means there is unused data in the136 bytes implemented
fifth 256 bit read. A total of 5 reads isin TE.
required.
HCURSingle 256 bit reads. 128 × 128 ditherConfigurable between
matrix requires 4 reads per line withdouble 128 byte buffer
double buffering. 256 × 256 dither matrixand
requires 8 reads at the end of the linesingle 256 byte buffer.
with single buffering.
DNCRSingle 256 bit readsDouble 256-bit buffer.
Deeper buffering could
be specified to cope with
local clusters of dead
nozzles.
DWUWSingle 256 bit writes per enabledDouble 256-bit buffer per
odd/even color plane.color plane.
LLURSingle 256 bit reads per enabledDouble 256-bit buffer per
odd/even color plane.color plane.
PCURSingle 256 bit reads. Each PCUSingle 256-bit buffer.
command is 64 bits so each 256 bit
DRAM read can contain 4 PCU commands.
Requested command is read
from DRAM together with the next 3
contiguous 64-bits which are cached to
avoid unnecessary DRAM reads.
RefreshSingle refresh.None.

20.6 SoPEC DIU Bandwidth Requirements

TABLE 109
SoPEC DIU Bandwidth Requirements
Number of
cycles betweenPeak
eachBandwidthExample
256-bit DRAMwhich must beAveragenumber of
access to meetsuppliedBandwidthallocated
Block NameDirectionpeak bandwidth(bits/cycle)(bits/cycle)timeslots1
CPUR
W
SCBR
W34820.7340.39331
CDUR128 (SF = 4), 28864/n2 (SF = n),32/10 * n2 (SF = n),1 (SF = 6)
(SF = 6), 1:11.8 (SF = 6),0.09 (SF = 6),2 (SF = 4)
compression44 (SF = 4)0.2 (SF = 4)
(1:1(10:1
compression)compression)5
WFor individual64/n2 (SF = n),32/n2 (SF = n)7,2 (SF = 6)8
accesses: 161.8 (SF = 6),0.9 (SF = 6),4 (SF = 4)
cycles (SF = 4), 364 (SF = 4)2 (SF = 4)
cycles (SF = 6), n2
cycles (SF = n).
Will be
implemented as a
page mode burst of
4 accesses every
64 cycles (SF = 4),
144 (SF = 6), 4 * n2
(SF = n) cycles6
CFUR32 (SF = 4), 48 (SF = 6)932/n (SF = n),32/n (SF = n),6 (SF = 6)
5.4 (SF = 6),5.4 (SF = 6),8 (SF = 4)
8 (SF = 4)8 (SF = 4)
LBDR256 (1:11 (1:10.1 (10:11
compression)10compression)compression)11
SFUR12812222
W25613111
TE(TD)R252141.021.021
TE(TFS)R5 reads per line150.0930.0930
HCUR4 reads per line for0.0740.0740
128 × 128 dither
matrix16
DNCR106 (5% dead-2.4 (clump of0.8 (equally3
nozzles 10-bit deltadead nozzles)spaced dead
encoded)17nozzles)
DWUW6 writes every666
25618
LLUR8 reads every868
25619
PCUR25620111
Refresh100212.562.563 (effective)
TOTALSF = 6: 34.9SF = 6: 27.5SF = 6: 36
SF = 4: 41.9SF = 4: 31.2excluding CPU.
excluding CPUexcluding CPUSF = 4: 41
excluding CPU

Notes:

1The number of allocated timeslots is based on 64 timeslots each of 1 bit/cycle but broken down to a granularity of 0.25 bit/cycle. Bandwidth is allocated based on peak bandwidth.

2: Wire-speed bandwidth for a 4 wire SCB configuration is 32 Mbits/s for each wire plus 12 Mbit/s for USB. This is a maximum of 138 Mbit/s. The maximum effective data rate is 26 Mbits/s for each wire plus 8 Mbit/s for USB. This is 112 Mbit/s. 112 Mbit/s is 0.734 bits/cycle or 256 bits every 348 cycles.

3: Wire-speed bandwidth for a 2 wire SCB configuration is 32 Mbits/s for each wire plus 12 Mbit/s for USB. This is a maximum of 74 Mbit/s. The maximum effective data rate is 26 Mbits/s for each wire plus 8 Mbit/s for USB. This is 60 Mbit/s. 60 Mbit/s is 0.393 bits/cycle or 256 bits every 650 cycles.

4: At 1:1 compression CDU must read a 4 color pixel (32 bits) every SF2 cycles.

5: At 10:1 average compression CDU must read a 4 color pixel (32 bits) every 10 * SF2 cycles.

6: 4 color pixel (32 bits) is required, on average, by the CFU every SF2 (scale factor) cycles. The time available to write the data is a function of the size of the buffer in DRAM. 1.5 buffering means 4 color pixel (32 bits) must be written every SF2/2 (scale factor) cycles. Therefore, at a scale factor of SF, 64 bits are required every SF2 cycles. Since 64 valid bits are written per 256-bit write (Figure on page379 on page Error! Bookmark
# not defined.) then the DRAM is accessed every SF2 cycles i.e. at SF4 an access every 16 cycles, at SF6 an access every 36 cycles. If a page mode burst of 4 accesses is used then each access takes (3 + 2 + 2 + 2) equals 9 cycles. This means at SF, a set of 4 back-to-back accesses must occur every 4 * SF2 cycles. This assumes the page mode select signal is clocked at 160 MHz. CDU timeslots therefore take 9 cycles.
# For scale factors lower than 4 double buffering will be used.

7: The peak bandwidth is twice the average bandwidth in the case of 1.5 buffering.

8: Each CDU(W) burst takes 9 cycles instead of 4 cycles for other accesses so CDU timeslots are longer.

9: 4 color pixel (32 bits) read by CFU every SF cycles. At SF4, 32 bits is required every 4 cycles or 256 bits every 32 cycles. At SF6, 32bits every 6 cycles or 256 bits every 48 cycles.

10: At 1:1 compression require 1 bit/cycle or 256 bits every 256 cycles.

11: The average bandwidth required at 10:1 compression is 0.1 bits/cycle.

12: Two separate reads of 1 bit/cycle.

13: Write at 1 bit/cycle.

14: Each tag can be consumed in at most 126 dot cycles and requires 128 bits. This is a maximum rate of 256 bits every 252 cycles.

15: 17 × 64 bit reads per line in PEC1 is 5 × 256 bit reads per line in SoPEC. Double-line buffered storage.

16: 128 bytes read per line is 4 × 256 bit reads per line. Double-line buffered storage.

17: 5% dead nozzles 10-bit delta encoded stored with 6-bit dead nozzle mask requires 0.8 bits/cycle read access or a 256-bit access every 320 cycles. This assumes the dead nozzles are evenly spaced out. In practice dead nozzles are likely to be clumped. Peak bandwidth is estimated as 3 times average bandwidth.

18: 6 bits/cycle requires 6 × 256 bit writes every 256 cycles.

19: 6 bits/160 MHz SoPEC cycle average but will peak at 2 × 6 bits per 106 MHz print head cycle or 8 bits/SoPEC cycle. The PHI can equalise the DRAM access rate over the line so that the peak rate equals the average rate of 6 bits/cycle. The print head is clocked at an effective speed of 106 MHz.

20: Assume one 256 read per 256 cycles is sufficient i.e. maximum latency of 256 cycles per access is allowable.

21: Refresh must occur every 3.2 ms. Refresh occurs row at a time over 5120 rows of 2 parallel 10 Mbit instances. Refresh must occur every 100 cycles. Each refresh takes 3 cycles.

20.7 DIU BUS Topology

20.7.1 Basic Topology

TABLE 110
SoPEC DIU Requesters
ReadWriteOther
CPUCPURefresh
SCBSCB
CDUCDU
CFUSFU
LBDDWU
SFU
TE(TD)
TE(TFS)
HCU
DNC
LLU
PCU

Table 110 shows the DIU requesters in SoPEC. There are 12 read requesters and 5 write requesters in SoPEC as compared with 8 read requesters and 4 write requesters in PEC1. Refresh is an additional requester.

In PEC1, the interface between the DIU and the DIU requesters had the following main features:

    • separate control and address signals per DIU requester multiplexed in the DIU according to the arbitration scheme,
    • separate 64-bit write data bus for each DRAM write requester multiplexed in the DIU,
    • common 64-bit read bus from the DIU with separate enables to each DIU read requester.

Timing closure for this bussing scheme was straight-forward in PEC1. This suggests that a similar scheme will also achieve timing closure in SoPEC. SoPEC has 5 more DRAM requesters but it will be in a 0.13 um process with more metal layers and SoPEC will run at approximately the same speed as PEC1.

Using 256-bit busses would match the data width of the embedded DRAM but such large busses may result in an increase in size of the DIU and the entire SoPEC chIP. The SoPEC requestors would require double 256-bit wide buffers to match the 256-bit busses. These buffers, which must be implemented in flip-flops, are less area efficient than 8-deep 64-bit wide register arrays which can be used with 64-bit busses. SoPEC will therefore use 64-bit data busses. Use of 256-bit busses would however simplify the DIU implementation as local buffering of 256-bit DRAM data would not be required within the DIU.

20.7.1.1 CPU DRAM Access

The CPU is the only DIU requestor for which access latency is critical. All DIU write requesters transfer write data to the DIU using separate point-to-point busses. The CPU will use the cpu_dataout[31:0] bus. CPU reads will not be over the shared 64-bit read bus. Instead, CPU reads will use a separate 256-bit read bus.

20.7.2 Making More Efficient Use of DRAM Bandwidth

The embedded DRAM is 256-bits wide. The 4 cycles it takes to transfer the 256-bits over the 64-bit data busses of SoPEC means that effectively each access will be at least 4 cycles long. It takes only 3 cycles to actually do a 256-bit random DRAM access in the case of IBM DRAM.

20.7.2.1 Common Read Bus

If we have a common read data bus, as in PEC1, then if we are doing back to back read accesses the next DRAM read cannot start until the read data bus is free. So each DRAM read access can occur only every 4 cycles. This is shown in FIG. 86 with the actual DRAM access taking 3 cycles leaving 1 unused cycle per access.

20.7.2.2 Interleaving CPU and Non-CPU Read Accesses

The CPU has a separate 256-bit read bus. All other read accesses are 256-bit accesses are over a shared 64-bit read bus. Interleaving CPU and non-CPU read accesses means the effective duration of an interleaved access timeslot is the DRAM access time (3 cycles) rather than 4 cycles.

FIG. 87 shows interleaved CPU and non-CPU read accesses.

20.7.2.3 Interleaving Read and Write Accesses

Having separate write data busses means write accesses can be interleaved with each other and with read accesses. So now the effective duration of an interleaved access timeslot is the DRAM access time (3 cycles) rather than 4 cycles. Interleaving is achieved by ordering the DIU arbitration slot allocation appropriately.

FIG. 88 shows interleaved read and write accesses. FIG. 89 shows interleaved write accesses.

256-bit write data takes 4 cycles to transmit over 64-bit busses so a 256-bit buffer is required in the DIU to gather the write data from the write requester. The exception is CPU write data which is transferred in a single cycle.

FIG. 89 shows multiple write accesses being interleaved to obtain 3 cycle DRAM access. Since two write accesses can overlap two sets of 256-bit write buffers and multiplexors to connect two write requestors simultaneously to the DIU are required.

Write requestors only require approximately one third of the total non-CPU bandwidth. This means that a rule can be introduced such that non-CPU write requestors are not allocated adjacent timeslots. This means that a single 256-bit write buffer and multiplexor to connect the one write requestor at a time to the DIU is all that is required.

Note that if the rule prohibiting back-to-back non-CPU writes is not adhered to, then the second write slot of any attempted such pair will be disregarded and re-allocated under the unused read round-robin scheme.

20.7.3 Bus Widths Summary

TABLE 111
SoPEC DIU Requesters Data Bus Width
ReadBus access widthWriteBus access width
CPU256 (separate)CPU32
SCB 64 (shared)SCB64
CDU 64 (shared)CDU64
CFU 64 (shared)SFU64
LBD 64 (shared)DWU64
SFU 64 (shared)
TE(TD) 64 (shared)
TE(TFS) 64 (shared)
HCU 64 (shared)
DNC 64 (shared)
LLU 64 (shared)
PCU 64 (shared)

20.7.4 Conclusions

Timeslots should be programmed to maximise interleaving of shared read bus accesses with other accesses for 3 cycle DRAM access. The interleaving is achieved by ordering the DIU arbitration slot allocation appropriately. CPU arbitration has been designed to maximise interleaving with non-CPU requesters

20.8 SoPEC DRAM Addressing Scheme

The embedded DRAM is composed of 256-bit words. However the CPU-subsystem may need to write individual bytes of DRAM. Therefore it was decided to make the DIU byte addressable. 22 bits are required to byte address 20 Mbit of DRAM.

Most blocks read or write 256 bit words of DRAM. Therefore only the top 17 bits i.e. bits 21 to 5 are required to address 256-bit word aligned locations.

The exceptions are

    • CDU which can write 64-bits so only the top 19 address bits i.e. bits 21-3 are required.
    • CPU writes can be 8, 16 or 32-bits. The cpu_diu_wmask[1:0] pins indicate whether to write 8, 16 or 32 bits.

All DIU accesses must be within the same 256-bit aligned DRAM word. The exception is the CDU write access which is a write of 64-bits to each of 4 contiguous 256-bit DRAM words.

20.8.1 Write Address Constaints Specific to the CDU

Note the following conditions which apply to the CDU write address, due to the four masked page-mode writes which occur whenever a CDU write slot is arbitrated.

    • The CDU address presented to the DIU is cdu_diu_wadr[21:3].
    • Bits [4:3] indicate which 64-bit segment out of 256 bits should be written in 4 successive masked page-mode writes.
    • Each 10-Mbit DRAM macro has an input address port of width [15:0]. Of these bits, [2:0] are the “page address”. Page-mode writes, where you just vary these LSBs (i.e. the “page” or column address), but keep the rest of the address constant, are faster than random writes. This is taken advantage of for CDU writes.
    • To guarantee against trying to span a page boundary, the DIU treats “cdu_diu_wadr[6:5]” as being fixed at “00”.
    • From cdu_diu_wadr[21:3], a initial address of cdu_diu_wadr[21:7], concatenated with “00”, is used as the starting location for the first CDU write. This address is then auto-incremented a further three times.
      20.9 DIU Protocols

The DIU protocols are

    • Pipelined i.e. the following transaction is initiated while the previous transfer is in progress.
    • Split transaction i.e. the transaction is split into independent address and data transfers.
      20.9.1 Read Protocol Except CPU

The SoPEC read requestors, except for the CPU, perform single 256-bit read accesses with the read data being transferred from the DIU in 4 consecutive cycles over a shared 64-bit read bus, diu_data[63:0]. The read address <unit>_diu_radr[21:5] is 256-bit aligned.

The read protocol is:

    • <unit>_diu_rreq is asserted along with a valid <unit>_diu_radr[21:5].
    • The DIU acknowledges the request with diu_<unit>_rack. The request should be deasserted. The minimum number of cycles between <unit>_diu_rreq being asserted and the DIU generating an diu_<unit>_rack strobe is 2 cycles (1 cycle to register the request, 1 cycle to perform the arbitration—see Section 20.14.10).
    • The read data is returned on diu_data[63:0] and its validity is indicated by diu_<unit>_rvalid. The overall 256 bits of data are transferred over four cycles in the order: [63:0]->[127:64]->[191:128]->[255:192].
    • When four diu_<unit>_rvalid pulses have been received then if there is a further request <unit>_diu_rreq should be asserted again. diu_<unit>_rvalid will be always be asserted by the DIU for four consecutive cycles. There is a fixed gap of 2 cycles between diu_<unit>_rack and the first diu_<unit>_rvalid pulse. For more detail on the timing of such reads and the implications for back-to-back sequences, see Section 20.14.10.
      20.9.2 Read Protocol for CPU

The CPU performs single 256-bit read accesses with the read data being transferred from the DIU over a dedicated 256-bit read bus for DRAM data, dram_cpu_data[255.0]. The read address cpu_adr[21:5] is 256-bit aligned.

The CPU DIU read protocol is:

    • cpu_diu_rreq is asserted along with a valid cpu_adr[21:5].
    • The DIU acknowledges the request with diu_cpu_rack. The request should be deasserted. The minimum number of cycles between cpu_diu_rreq being asserted and the DIU generating a cpu_diu_rack strobe is 1 cycle (1 cycle to perform the arbitration—see Section 20.14.10).
    • The read data is returned on dram_cpu_data[255:0] and its validity is indicated by diu_cpu_rvalid.
    • When the diu_cpu_rvalid pulse has been received then if there is a further request cpu_diu_rreq should be asserted again. The diu_cpu_rvalid pulse with a gap of 1 cycle after rack (1 cycle for the read data to be returned from the DRAM—see Section 20.14.10).
      20.9.3 Write Protocol Except CPU and CDU

The SoPEC write requestors, except for the CPU and CDU, perform single 256-bit write accesses with the write data being transferred to the DIU in 4 consecutive cycles over dedicated point-to-point 64-bit write data busses. The write address <unit>_diu_wadr[21:5] is 256-bit aligned.

The write protocol is:

    • <unit>_diu_wreq is asserted along with a valid <unit>_diu_wadr[21:5].
    • The DIU acknowledges the request with diu_<unit>_wack. The request should be deasserted. The minimum number of cycles between <unit>_diu_wreq being asserted and the DIU generating an diu_<unit>_wack strobe is 2 cycles (1 cycle to register the request, 1 cycle to perform the arbitration—see Section 20.14.10).
    • In the clock cycles following diu_<unit>_wack the SoPEC Unit outputs the 15<unit>_diu_data[63:0], asserting <unit>_diu_wvalid. The first <unit>_diu_wvalid pulse can occur the clock cycle after diu_<unit>_wack. <unit>_diu_wvalid remains asserted for the following 3 clock cycles. This allows for reading from an SRAM where new data is available in the clock cycle after the address has changed e.g. the address for the second 64-bits of write data is available the cycle after diu_<unit>_wack meaning the second 64-bits of write data is a further cycle later. The overall 256 bits of data is transferred over four cycles in the order: [63:0]->[127:64]->[191:128]->[255:192].
    • Note that for SCB writes, each 64-bit quarter-word has an 8-bit byte enable mask associated with it. A different mask is used with each quarter-word. The 4 mask values are transferred along with their associated data, as shown in FIG. 92.
    • If four consecutive <unit>_diu_wvalid pulses are not provided by the requester, then the arbitration logic will disregard the write and re-allocate the slot under the unused read round-robin scheme.

Once all the write data has been output then if there is a further request <unit>_diu_wreq should be asserted again.

20.9.4 CPU Write Protocol

The CPU performs single 128-bit writes to the DIU on a dedicated write bus, cpu_diu_wdata[127:0]. There is an accompanying write mask, cpu_diu_wmask[15:0], consisting of 16 byte enables and the CPU also supplies a 128-bit aligned write address on cpu_diu_wadr[21:4]. Note that writes are posted by the CPU to the DIU and stored in a 1-deep buffer. When the DAU subsequently arbitrates in favour of the CPU, the contents of the buffer are written to DRAM.

The CPU write protocol, illustrated in FIG. 93, is as follows:—

    • The DIU signals to the CPU via diu_cpu_write_rdy that its write buffer is empty and that the CPU may post a write whenever it wishes.
    • The CPU asserts cpu_diu_wdatavalid to enable a write into the buffer and to confirm the validity of the write address, data and mask.
    • The DIU de-asserts diu_cpu_write_rdy in the following cycle to indicate that its buffer is full and that the posted write is pending execution.
    • When the CPU is next awarded a DRAM access by the DAU, the buffer's contents are written to memory. The DIU re-asserts diu_cpu_write_rdy once the write data has been captured by DRAM, namely in the “MSN1” DCU state.
    • The CPU can then, if it wishes, asynchronously use the new value of .diu_cpu_write_rdy to enable a new posted write in the same “MSN1” cycle.
      20.9.5 CDU Write Protocol

The CDU performs four 64-bit word writes to 4 contiguous 256-bit DRAM addresses with the first address specified by cdu_diu_wadr[21:3]. The write address cdu_diu_wadr[21:5] is 256-bit aligned with bits cdu_diu_wadr[4:3] allowing the 64-bit word to be selected.

The write protocol is:

    • cdu_diu_wdata is asserted along with a valid cdu_diu_wadr[21:3].
    • The DIU acknowledges the request with diu_cdu_wack. The request should be deasserted. The minimum number of cycles between cdu_diu_wreq being asserted and the DIU generating an diu_cdu_wack strobe is 2 cycles (1 cycle to register the request, 1 cycle to perform the arbitration—see Section 20.14.10).
    • In the clock cycles following diu_cdu_wack the CDU outputs the cdu_diu_data[63:0], together with asserted cdu_diu_wvalid. The first cdu_diu_wvalid pulse can occur the clock cycle after diu_cdu_wack. cdu_diu_wvalid remains asserted for the following 3 clock cycles. This allows for reading from an SRAM where new data is available in the clock cycle after the address has changed e.g. the address for the second 64-bits of write data is available the cycle after diu_cdu_wack meaning the second 64-bits of write data is a further cycle later. Data is transferred over the 4-cycle window in an order, such that each successive 64 bits will be written to a monotonically increasing (by 1 location) 256-bit DRAM word.
    • If four consecutive cdu_diu_wvalid pulses are not provided with the data, then the arbitration logic will disregard the write and re-allocate the slot under the unused read round-robin scheme.
    • Once all the write data has been output then if there is a further request cdu_diu_wreq should be asserted again.
      20.10 DIU Arbitration Mechanism

The DIU will arbitrate access to the embedded DRAM. The arbitration scheme is outlined in the next sections.

20.10.1 Timeslot Based Arbitration Scheme

Table summarised the bandwidth requirements of the SoPEC requestors to DRAM. If we allocate the DIU requestors in terms of peak bandwidth then we require 35.25 bits/cycle (at SF=6) and 40.75 bits/cycle (at SF=4) for all the requestors except the CPU.

A timeslot scheme is defined with 64 main timeslots. The number of used main timeslots is programmable between 1 and 64.

Since DRAM read requesters, except for the CPU, are connected to the DIU via a 64-bit data bus each 256-bit DRAM access requires 4 pclk cycles to transfer the read data over the shared read bus. The timeslot rotation period for 64 timeslots each of 4 pclk cycles is 256 pclk cycles or 1.6 μs, assuming pclk is 160 MHz. Each timeslot represents a 256-bit access every 256 pclk cycles or 1 bit/cycle. This is the granularity of the majority of DIU requesters bandwidth requirements in Table.

The SoPEC DIU requesters can be represented using 4 bits (Table n page 288 on page 268). Using 64 timeslots means that to allocate each timeslot to a requester, a total of 64×5-bit configuration registers are required for the 64 main timeslots.

Timeslot based arbitration works by having a pointer point to the current timeslot. When re-arbitration is signaled the arbitration winner is the current timeslot and the pointer advances to the next timeslot. Each timeslot denotes a single access. The duration of the timeslot depends on the access.

Note that advancement through the timeslot rotation is dependent on an enable bit, RotationSync, being set. The consequences of clearing and setting this bit are described in section 20.14.12.2.1 on page 295.

If the SoPEC Unit assigned to the current timeslot is not requesting then the unused timeslot arbitration mechanism outlined in Section 20.10.6 is used to select the arbitration winner.

Note that there is always an arbitration winner for every slot. This is because the unused read re-allocation scheme includes refresh in its round-robin protocol. If all other blocks are not requesting, an early refresh will act as fall-back for the slot.

20.10.2 Separate Read and Write Arbitration Windows

For write accesses, except the CPU, 256-bits of write data are transferred from the SoPEC DIU write requestors over 64-bit write busses in 4 clock cycles. This write data transfer latency means that writes accesses, except for CPU writes and also the CDU, must be arbitrated 4 cycles in advance. (The CDU is an exception because CDU writes can start once the first 64-bits of write data have been transferred since each 64-bits is associated with a write to a different 256-bit word).

Since write arbitration must occur 4 cycles in advance, and the minimum duration of a timeslot duration is 3 cycles, the arbitration rules must be modified to initiate write accesses in advance. Accordingly, there is a write timeslot lookahead pointer shown in FIG. 96 two timeslots in advance of the current timeslot pointer.

The following examples illustrate separate read and write timeslot arbitration with no adjacent write timeslots. (Recall rule on adjacent write timeslots introduced in Section 20.7.2.3 on page 238.)

In FIG. 97 writes are arbitrated two timeslots in advance. Reads are arbitrated in the same timeslot as they are issued. Writes can be arbitrated in the same timeslot as a read. During arbitration the command address of the arbitrated SoPEC Unit is captured.

Other examples are shown in FIG. 98 and FIG. 99. The actual timeslot order is always the same as the programmed timeslot order i.e. out of order accesses do not occur and data coherency is never an issue.

Each write must always incur a latency of two timeslots.

Startup latency may vary depending on the position of the first write timeslot. This startup latency is not important.

Table 112 shows the 4 scenarIOs depending on whether the current timeslot and write timeslot lookahead pointers point to read or write accesses.

TABLE 112
Arbitration with separate windows for read and write accesses
write timeslot
lookahead
current timeslot pointerpointeractions
ReadwriteInitiate DRAM read,
Initiate write arbitration
Read1read2Initiate DRAM read1.
Write1write2Initiate write2 arbitration.
Execute DRAM write1.
WritereadExecute DRAM write.

If the current timeslot pointer points to a read access then this will be initiated immediately. If the write timeslot lookahead pointer points to a write access then this access is arbitrated immediately, or immediately after the read access associated with the current timeslot pointer is initiated.

When a write access is arbitrated the DIU will capture the write address. When the current timeslot pointer advances to the write timeslot then the actual DRAM access will be initiated. Writes will therefore be arbitrated 2 timeslots in advance of the DRAM write occurring.

At initialisation, the write lookahead pointer points to the first timeslot. The current timeslot pointer is invalid until the write lookahead pointer advances to the third timeslot when the current timeslot pointer will point to the first timeslot. Then both pointers advance in tandem.

CPU write accesses are excepted from the lookahead mechanism.

If the selected SoPEC Unit is not requesting then there will be separate read and write selection for unused timeslots. This is described in Section 20.10.6.

20.10.3 Arbitration of CPU Accesses

What distinguishes the CPU from other SoPEC requesters, is that the CPU requires minimum latency DRAM access i.e. preferably the CPU should get the next available timeslot whenever it requests.

The minimum CPU read access latency is estimated in Table 113. This is the time between the CPU making a request to the DIU and receiving the read data back from the DIU.

TABLE 113
Estimated CPU read access latency ignoring caching
CPU read access latencyDuration
CPU cache miss1cycle
CPU MMU logic issues request and1cycle
DIU arbitration completes
Transfer the read address to the DRAM1cycle
DRAM read latency1cycle
Register the read data in CPU bridge1cycle
Register the read data in CPU1cycle
CPU cache miss1cycle
CPU MMU logic issues request and1cycle
DIU arbitration completes
TOTAL gap between requests6cycles

If the CPU, as is likely, requests DRAM access again immediately after receiving data from the DIU then the CPU could access every second timeslot if the access latency is 6 cycles. This assumes that interleaving is employed so that timeslots last 3 cycles. If the CPU access latency were 7 cycles, then the CPU would only be able to access every third timeslot.

If a cache hit occurs the CPU does not require DRAM access. For its next DIU access it will have to wait for its next assigned DIU slot. Cache hits therefore will reduce the number of DRAM accesses but not speed up any of those accesses.

To avoid the CPU having to wait for its next timeslot it is desirable to have a mechanism for ensuring that the CPU always gets the next available timeslot without incurring any latency on the non-CPU timeslots.

This can be done by defining each timeslot as consisting of a CPU access preceding a non-CPU access. Each timeslot will last 6 cycles i.e. a CPU access of 3 cycles and a non-CPU access of 3 cycles. This is exactly the interleaving behaviour outlined in Section 20.7.2.2. If the CPU does not require an access, the timeslot will take 3 or 4 and the timeslot rotation will go faster. A summary is given in Table 114.

TABLE 114
Timeslot access times.
AccessDurationExplanation
CPU access +3 + 3 = 6cyclesInterleaved access
non-CPU access
non-CPU access4cyclesAccess and preceding
access both to shared
read bus
non-CPU access3cyclesAccess and preceding
access not both to
shared read bus
CDU write access3+2+2+2 = 9cyclesPage mode select
signal is clocked
at 160 MHz

CDU write accesses require 9 cycles. CDU write accesses preceded by a CPU access require 12 cycles. CDU timeslots therefore take longer than all other DIU requestors timeslots.

With a 256 cycle rotation there can be 42 accesses of 6 cycles.

For low scale factor applications, it is desirable to have more timeslots available in the same 256 5 cycle rotation. So two counters of 4-bits each are defined allowing the CPU to get a maximum of (CPUPreAccessTimeslots+1) pre-accesses for every (CPUTotalTimeslots+1) main slots. A timeslot counter starts at CPUTotalTimeslots and decrements every timeslot, while another counter starts at CPUPreAccessTimeslots and decrements every timeslot in which the CPU uses its access. When the CPU pre-access counter goes to zero before CPUTotalTimeslots, no further CPU accesses are allowed. When the CPUTotalTimeslots counter reaches zero both counters are reset to their respective initial values.

The CPU is not included in the list of SoPEC DIU requesters, Table, for the main timeslot allocations. The CPU cannot therefore be allocated main timeslots. It relies on pre-accesses in advance of such slots as the sole method for DRAM transfers.

CPU access to DRAM can never be fully disabled, since to do so would render SoPEC inoperable. Therefore the CPUPreAccessTimeslots and CPUTotalTimeslots register values are interpreted as follows: In each succeeding window of (CPUTotalTimeslots+1) slots, the maximum quota of CPU pre-accesses allowed is (CPUPreAccessTimeslots+1). The “+1” implementations mean that the CPU quota cannot be made zero.

The various modes of operation are summarised in Table 115 with a nominal rotation period of 256 cycles.

TABLE 115
CPU timeslot allocation modes with nominal rotation period of 256 cycles
Nominal
TimeslotNumber of
Access TypedurationtimeslotsNotes
CPU Pre-access6 cycles  42 timeslotsEach access is CPU + non-CPU.
i.e.If CPU does not use a timeslot then
CPUPreAccessTimeslots = CPUTotalTimeslotsrotation is faster.
Fractional CPU Pre-4 or 642-64 timeslotsEach CPU + non-CPU access
accesscyclesrequires a 6 cycle
i.e.timeslot.
CPUPreAccessTimeslots < CPUTotalTimeslots
Individual non-CPU timeslots take 4
cycles if
current access and preceding
access are both
to shared read bus.
Individual non-CPU timeslots take 3
cycles if
current access and preceding
access are not both
to shared read bus.

20.10.4 CDU Accesses

As indicated in Section 20.10.3, CDU write accesses require 9 cycles. CDU write accesses preceded by a CPU access require 12 cycles. CDU timeslots therefore take longer than all other DIU requestors timeslots. This means that when a write timeslot is unused it cannot be re-allocated to a CDU write as CDU accesses take 9 cycles. The write accesses which the CDU write could otherwise replace require only 3 or 4 cycles.

Unused CDU write accesses can be replaced by any other write access according to 20.10.6.1 Unused write timeslots allocation on page 247.

20.10.5 Refresh Controller

Refresh is not included in the list of SoPEC DIU requesters, Table, for the main timeslot allocations. Timeslots cannot therefore be allocated to refresh.

The DRAM must be refreshed every 3.2 ms. Refresh occurs row at a time over 5120 rows of 2 parallel 10 Mbit instances. A refresh operation must therefore occur every 100 cycles. The refresh_period register has a default value of 99. Each refresh takes 3 cycles.

A refresh counter will count down the number of cycles between each refresh. When the down-counter reaches 0, the refresh controller will issue a refresh request and the down-counter is reloaded with the value in refresh_period and the count-down resumes immediately. Allocation of main slots must take into account that a refresh is required at least once every 100 cycles. Refresh is included in the unused read and write timeslot allocation. If unused timeslot allocation results in refresh occurring early by N cycles, then the refresh counter will have counted down to N. In this case, the refresh counter is reset to refresh_period and the count-down recommences. Refresh can be preceded by a CPU access in the same way as any other access. This is controlled by the CPUPreAccessTimeslots and CPUTotalTimeslots configuration registers. Refresh will therefore not affect CPU performance. A sequence of accesses including refresh might therefore be CPU, refresh, CPU, actual timeslot.

20.10.6 Allocating Unused Timeslots

Unused slots are re-allocated separately depending on whether the unused access was a read access or a write access. This is best-effort traffic. Only unused non-CPU accesses are re-allocated.

20.10.6.1 Unused Write Timeslots Allocation

Unused write timeslots are re-allocated according to a fixed priority order shown in Table 116.

TABLE 116
Unused write timeslot priority order
Priority
NameOrder
SCB(W)1
SFU(W)2
DWU3
Unused read timeslot allocation4

CDU write accesses cannot be included in the unused timeslot allocation for write as CDU accesses take 9 cycles. The write accesses which the CDU write could otherwise replace require only 3 or 4 cycles.

Unused write timeslot allocation occurs two timeslots in advance as noted in Section 20.10.2. If the units at priorities 1-3 are not requesting then the timeslot is re-allocated according to the unused read timeslot allocation scheme described in Section 20.10.6.2. However, the unused read timeslot allocation will occur when the current timeslot pointer of FIG. 96 reaches the timeslot i.e. it will not occur in advance.

20.10.6.2 Unused Read Timeslots Allocation

Unused read timeslots are re-allocated according to a two level round-robin scheme. The SoPEC Units included in read timeslot re-allocation is shown in Table 117.

TABLE 117
Unused read timeslot allocation
Name
SCB(R)
CDU(R)
CFU
LBD
SFU(R)
TE(TD)
TE(TFS)
HCU
DNC
LLU
PCU
CPU
Refresh

Each SoPEC requestor has an associated bit, ReadRoundRobinLevel, which indicates whether it is in level 1 or level 2 round-robin.

TABLE 118
Read round-robin level selection
LevelAction
ReadRoundRobinLevel = 0Level 1
ReadRoundRobinLevel = 1Level 2

A pointer points to the most recent winner on each of the round-robin levels. Re-allocation is carried out by traversing level 1 requesters, starting with the one immediately succeeding the last level 1 winner. If a requesting unit is found, then it wins arbitration and the level 1 pointer is shifted to its position. If no level 1 unit wants the slot, then level 2 is similarly examined and its pointer adjusted.

Since refresh occupies a (shared) position on one of the two levels and continually requests access, there will always be some round-robin winner for any unused slot.

20.10.6.2.1 Shared CPU/Refresh Round-Robin Position

Note that the CPU can conditionally be allowed to take part in the unused read round-robin scheme. Its participation is controlled via the configuration bit EnableCPURoundRobin. When this bit is set, the CPU and refresh share a joint position in the round-robin order, shown in Table. When cleared, the position is occupied by refresh alone.

If the shared position is next in line to be awarded an unused non-CPU read/write slot, then the CPU will have first option on the slot. Only if the CPU doesn't want the access, will it be granted to refresh. If the CPU is excluded from the round robin, then any awards to the position benefit refresh.

20.11 Guidelines for Programming the DIU

Some guidelines for programming the DIU arbitration scheme are given in this section together with an example.

20.11.1 Circuit Latency

Circuit latency is a fixed service delay which is incurred, as and from the acceptance by the DIU arbitration logic of a block's pending read/write request. It is due to the processing time of the request, readying the data, plus the DRAM access time. Latencies differ for read and write requests. See Tables 79 and 80 for respective breakdowns.

If a requesting block is currently stalled, then the longest time it will have to wait between issuing a new request for data and actually receiving it would be its timeslot period, plus the circuit latency overhead, along with any intervening non-standard slot durations, such as refresh and CDU(W). In any case, a stalled block will always incur this latency as an additional overhead, when coming out of a stall.

In the case where a block starts up or unstalls, it will start processing newly-received data at a time beyond its serviced timeslot equivalent to the circuit latency. If the block's timeslots are evenly spaced apart in time to match its processing rate, (in the hope of minimising stalls,) then the earliest that the block could restall, if not re-serviced by the DIU, would be the same latency delay beyond its next timeslot occurrence. Put another way, the latency incurred at start-up pushes the potential DIU-induced stall point out by the same fixed delta beyond each successive timeslot allocated to the block. This assumes that a block re-requests access well in advance of its upcoming timeslots. Thus, for a given stall-free run of operation, the circuit latency overhead is only incurred inititially when unstalling.

While a block can be stalled as a result of how quickly the DIU services its DRAM requests, it is also prone to stalls caused by its upstream or downstream neighbours being able to supply or consume data which is transferred between the blocks directly, (as opposed to via the DIU). Such neighbour-induced stalls, often occurring at events like end of line, will have the effect that a block's DIU read buffer will tend to fill, as the block stops processing read data. Its DIU write buffer will also tend to fill, unable to despatch to DRAM until the downstream block frees up shared-access DRAM locations. This scenario is beneficial, in that when a block unstalls as a result of its neighbour releasing it, then that block's read/write DIU buffers will have a fill state less likely to stall it a second time, as a result of DIU service delays.

A block's slots should be scheduled with a service guarantee in mind. This is dictated by the block's processing rate and hence, required access to the DRAM. The rate is expressed in terms of bits per cycle across a processing window, which is typically (though not always) 256 cycles. Slots should be evenly interspersed in this window (or “rotation”) so that the DIU can fulfill the block's service needs.

The following ground rules apply in calculating the distribution of slots for a given non-CPU block:—

    • The block can, at maximum, suffer a stall once in the rotation, (i.e. unstall and restall) and hence incur the circuit latency described above.

This rule is, by definition, always fulfilled by those blocks which have a service requirement of only

    • 1 bit/cycle (equivalent to 1 slot/rotation) or fewer. It can be shown that the rule is also satisfied by those blocks requiring more than 1 bit/cycle. See Section 20.12.1 Slot Distributions and Stall Calculations for Individual Blocks, on page 255.
    • Within the rotation, certain slots will be unavailable, due to their being used for refresh. (See Section 20.11.2 Refresh latencies)
    • In programming the rotation, account must be taken of the fact that any CDU(W) accesses will consume an extra 6 cycles/access, over and above the norm, in CPU pre-access mode, or 5 cycles/access without pre-access.
    • The total delay overhead due to latency, refreshes and CDU(W) can be factored into the service guarantee for all blocks in the rotation by deleting once, (i.e. reducing the rotation window,) that number of slots which equates to the cumulative duration of these various anomalies.
    • The use of lower scale factors will imply a more frequent demand for slots by non-CPU blocks. The percentage of slots in the overall rotation which can therefore be designated as CPU pre-access ones should be calculated last, based on what can be accommodated in the light of the non-CPU slot need.

Read latency is summarised below in Table 119.

TABLE 119
Read latency
Non-CPU read access latencyDuration
non-CPU read requestor internally1cycle
generates DIU request
register the non-CPU read request1cycle
complete the arbitration of the request1cycle
transfer the read address to the DRAM1cycle
DRAM read latency1cycle
register the DRAM read data in DIU1cycle
register the 1st 64-bits of read data in1cycle
requester
register the 2nd 64-bits of read data in1cycle
requester
register the 3rd 64-bits of read data in1cycle
requester
register the 4th 64-bits of read data in1cycle
requester
TOTAL10cycles

Write latency is summarised in Table 120.

TABLE 120
Write latency
Non-CPU write access latencyDuration
non-CPU write requestor internally generates DIU request1 cycle
register the non-CPU write request1 cycle
complete the arbitration of the request1 cycle
transfer the acknowledge to the write requester1 cycle
transfer the 1st 64 bits of write data to the DIU1 cycle
transfer the 2nd 64 bits of write data to the DIU1 cycle
transfer the 3rd 64 bits of write data to the DIU1 cycle
transfer the 4th 64 bits of write data to the DIU1 cycle
Write to DRAM with locally registered write data1 cycle
TOTAL9 cycles

Timeslots removed to allow for read latency will also cover write latency, since the former is the larger of the two.

20.11.2 Refresh Latencies

The number of allocated timeslots for each requester needs to take into account that a refresh must occur every 100 cycles. This can be achieved by deleting timeslots from the rotation since the number of timeslots is made programmable.

Refresh is preceded by a CPU access in the same way as any other access. This is controlled by the CPUPreAccessTimeslots and CPUTotalTimeslots configuration registers. Refresh will therefore not affect CPU performance.

As an example, in CPU pre-access mode each timeslot will last 6 cycles. If the timeslot rotation has 50 timeslots then the rotation will last 300 cycles. The refresh controller will trigger a refresh every 100 cycles. Up to 47 timeslots can be allocated to the rotation ignoring refresh. Three timeslots deleted from the 50 timeslot rotation will allow for the latency of a refresh every 100 cycles.

20.11.3 Ensuring Sufficient DNC and PCU Access

PCU command reads from DRAM are exceptional events and should complete in as short a time as possible. Similarly, we must ensure there is sufficient free bandwidth for DNC accesses e.g. when clusters of dead nozzles occur. In Table DNC is allocated 3 times average bandwidth. PCU and DNC can also be allocated to the level 1 round-robin allocation for unused timeslots so that unused timeslot bandwidth is preferentially available to them.

20.11.4 Basing Timeslot Allocation on Peak Bandwidths

Since the embedded DRAM provides sufficient bandwidth to use 1:1 compression rates for the CDU and LBD, it is possible to simplify the main timeslot allocation by basing the allocation on peak bandwidths. As combined bi-level and tag bandwidth at 1:1 scaling is only 5 bits/cycle, we will usually only consider the contone scale factor as the variable in determining timeslot allocations.

If slot allocation is based on peak bandwidth requirements then DRAM access will be guaranteed to all SoPEC requesters. If we do not allocate slots for peak bandwidth requirements then we can also allow for the peaks deterministically by adding some cycles to the print line time.

20.11.5 Adjacent Timeslot Restrictions

20.11.5.1 Non-CPU Write Adjacent Timeslot Restrictions

Non-CPU write requesters should not be assigned adjacent timeslots as described in Section 20.7.2.3. This is because adjacent timeslots assigned to non-CPU requestors would require two sets of 256-bit write buffers and multiplexors to connect two write requestors simultaneously to the DIU. Only one 256-bit write buffer and multiplexor is implemented. Recall from section 20.7.2.3 on page 238 that if adjacent non-CPU writes are attempted, that the second write of any such pair will be disregarded and re-allocated under the unused read scheme.

20.11.5.2 Same DIU Requestor Adjacent Timeslot Restrictions

All DIU requesters have state-machines which request and transfer the read or write data before requesting again. From FIG. 90 read requests have a minimum separation of 9 cycles. From FIG. 92 write requests have a minimum separation of 7 cycles. Therefore adjacent timeslots should not be assigned to a particular DIU requester because the requester will not be able to make use of all these slots.

In the case that a CPU access precedes a non-CPU access timeslots last 6 cycles so write and read requesters can only make use of every second timeslot. In the case that timeslots are not preceded by CPU accesses timeslots last 4 cycles so the same write requester can use every second timeslot but the same read requestor can use only every third timeslot. Some DIU requestors may introduce additional pipeline delays before they can request again. Therefore timeslots should be separated by more than the minimum to allow a margin.

20.11.6 Line Margin

The SFU must output 1 bit/cycle to the HCU. Since HCUNumDots may not be a multiple of 256 bits the last 256-bit DRAM word on the line can contain extra zeros. In this case, the SFU may not be able to provide 1 bit/cycle to the HCU. This could lead to a stall by the SFU. This stall could then propagate if the margins being used by the HCU are not sufficient to hide it. The maximum stall can be estimated by the calculation: DRAM service period—X scale factor * dots used from last DRAM read for HCU line.

Similarly, if the line length is not a multiple of 256-bits then e.g. the LLU could read data from DRAM which contains padded zeros. This could lead to a stall. This stall could then propagate if the page margins cannot hide it.

A single addition of 256 cycles to the line time will suffice for all DIU requesters to mask these stalls.

20.12 Example Outline DIU Programming

TABLE 121
Timeslot allocation based on peak bandwidth
Peak Bandwidth
which must be
BlocksuppliedMainTimeslots
NameDirection(bits/cycle)allocated
SCBR
W0.73471
CDUR0.9 (SF = 6),1(SF = 6)
2 (SF = 4)2(SF = 4)
W1.8 (SF = 6),82(SF = 6)
4 (SF = 4)4(SF = 4)
CFUR5.4 (SF = 6),6(SF = 6)
8 (SF = 4)8(SF = 4)
LBDR11
SFUR22
W11
TE(TD)R1.021
TE(TFS)R0.0930
HCUR0.0740
DNCR2.43
DWUW66
LLUR88
PCUR11
TOTAL33(SF = 6) 
38(SF = 4) 

7The SCB figure of 0.734 bits/cycle applies to multi-SoPEC systems. For single-SoPEC systems, the figure is 0.050 bits/cycle.

8Bandwidth for CDU(W) is peak value. Because of 1.5 buffering in DRAM, peak CDU(W) b/w equals 2 × average CDU(W) b/w. For CDU(R), peak b/w = average CDU(R) b/w.

Table 121 shows an allocation of main timeslots based on the peak bandwidths of Table The bandwidth required for each unit is calculated allowing extra cycles for read and write circuit latency for each access requiring a bandwidth of more than 1 bit/cycle. Fractional bandwidth is supplied via unused read slots.

The timeslot rotation is 256 cycles. Timeslots are deleted from the rotation to allow for circuit latencies for accesses of up to 1 bit per cycle i.e. 1 timeslot per rotation.

EXAMPLE 1

Scale-Factor=6

Program the MainTimeslot configuration register (Table) for peak required bandwidths of SoPEC Units according to the scale factor.

Program the read round-robin allocation to share unused read slots. Allocate PCU, DNC, HCU and TFS to level 1 read round-robin.

    • Assume scale-factor of 6 and peak bandwidths from Table
      • Assign all DIU requestors except TE(TFS) and HCU to multiples of 1 timeslot, as indicated in Table, where each timeslot is 1 bit/cycle. This requires 33 timeslots.
      • No timeslots are explicitly allocated for the fractional bandwidth requirements of TE(TFS) and HCU accesses. Instead, these units are serviced via unused read slots.
      • Allow 3 timeslots to allow for 3 refreshes in the rotation.
      • Therefore, 36 scheduled slots are used in the rotation for main timeslots and refreshes, some or all of which may be able to have a CPU pre-access, provided they fit in the rotation window.
      • Each of the 2 CDU(W) accesses requires 9 cycles. Per access, this implies an overhead of 1 slot (12 cycles instead of 6) in pre-access mode, or 1.25 slots (9 cycles instead of 4) for no pre-access. The cumulative overhead of the two accesses is either 2 slots (pre-access) or 3 slots (no pre-access).
      • Assuming all blocks require a service guarantee of no more than a single stall across 256 bits, allow 10 cycles for read latency, which also takes care of 9-cycle write latency. This can be accounted for by reserving 2 six-cycle slots (CPU pre-access) or 3 four-cycle slots (no pre-access).
    • Assume a 256 cycle timeslot rotation.
    • CDU(W) and read latency reduce the number of available cycles in a rotation to: 256−2×6−2×6=232 cycles (CPU pre-access) or 256−3×4−3×4=232 cycles (no pre-access).
    • As a result, 232 cycles available for 36 accesses implies each access can take 232/36=6.44 cycles maximum. So, all accesses can have a pre-access.
    • Therefore the CPU achieves a pre-access ratio of 36/36=100% of slots in the rotation.

EXAMPLE 2

Scale-Factor=4

Program the MainTimeslot configuration register (Table) for peak required bandwidths of SoPEC Units according to the scale factor. Program the read round-robin allocation to share unused read slots. Allocate PCU, DNC, HCU and TFS to level 1 read round-robin.

    • Assume scale-factor of 4 and peak bandwidths from Table
    • Assign all DIU requestors except TE(TFS) and HCU multiples of 1 timeslot, as indicated in Table, where each timeslot is 1 bit/cycle. This requires 38 timeslots.
    • No timeslots are explicitly allocated for the fractional bandwidth requirements of TE(TFS) and HCU accesses. Instead, these units are serviced via unused read slots.
    • Allow 3 timeslots to allow for 3 refreshes in the rotation.
    • Therefore, 41 scheduled slots are used in the rotation for main timeslots and refreshes, some or all of which can have a CPU pre-access, provided they fit in the rotation window.
    • Each of the 4 CDU(W) accesses requires 9 cycles. Per access, this implies an overhead of 1 slot (12 cycles instead of 6) for pre-access mode, or 1.25 slots (9 cycles instead of 4) for no pre-access. The cumulative overhead of the four accesses is either 4 slots (pre-access) or 5 slots (no pre-access).
    • Assuming all blocks require a service guarantee of no more than a single stall across 256 bits, allow 10 cycles for read latency, which also takes care of 9-cycle write latency. This can be accounted for by reserving 2 six-cycle slots (CPU pre-access) or 3 four-cycle slots (no pre-access).
    • Assume a 256 cycle timeslot rotation.
    • CDU(W) and read latency reduce the number of available cycles in a rotation to: 256−4×6−2×6=220 cycles (CPU pre-access) or 256−5×4−3×4=224 cycles (no pre-access).
    • As a result, between 220 and 224 cycles are available for 41 accesses, which implies each access can take between 220/41=5.36 cycles and 224/41=5.46 cycles.
    • Work out how many slots can have a pre-access: For the lower number of 220 cycles, this implies (41−n)*6+n*4<=220, where n=number of slots with no pre-access cycle. Solving the equation gives n>=13. Check answer: 28*6+0.13*4=220.
    • So 28 slots out of the 41 in the rotation can have CPU pre-accesses.
    • The CPU thus achieves a pre-access ratio of 28/41=68.3% of slots in the rotation.
      20.12.1 Slot Distributions and Stall Calculations for Individual Blocks

The following sections show how the slots for blocks with a service requirement greater than 1 bit/cycle should be distributed. Calculations are included to check that such blocks will not suffer more than one stall per rotation.

20.12.1.1 SFU

This has 2 bits/cycle on read but this is two separate channels of 1 bit/cycle sharing the same DIU interface so it is effectively 2 channels each of 1 bit/cycle so allowing the same margins as the LBD will work.

20.12.1.2 DWU

The DWU has 12 double buffers in each of the 6 colour planes, odd and even. These buffers are filled by the DNC and will request DIU access when double buffers fill. The DNC supplies 6 bits to the DWU every cycle (6 odd in one cycle, 6 even in the next cycle). So the service deadline is 512 cycles, given 6 accesses per 256-cycle rotation.

20.12.1.3 CFU

Here the requirement is that the DIU stall should be less than the time taken for the CFU to consume one third of its triple buffer. The total DIU stall=refresh latency+extra CDU(W) latency+read circuit latency=3+5 (for 4 cycle timeslots)+10=18 cycles. The CFU can consume its data at 8 bits/cycle at SF=4. Therefore 256 bits of data will last 32 cycles so the triple buffer is safe. In fact we only need an extra 144 bits of buffering or 3×64 bits. But it is safer to have the full extra 256 bits or 4×64 bits of buffering.

20.12.1.4 LLU

The LLU has 2 channels, each of which could request at 6 bits/106 MHz channel or 4 bits/160 MHz cycle, giving a total of 8 bits/160 MHz cycle. The service deadline for each channel is 256×106 MHz cycles, i.e. all 6 colours must be transferred in 256 cycles to feed the printhead. This equates to 384×160 MHz cycles.

Over a span of 384 cycles, there will be 6 CDU(W) accesses, 4 refreshes and one read latency encountered at most. Assuming CPU pre-accesses for these occurrences, this means the number of available cycles is given by 384−6×6−4×6−10=314 cycles.

For a CPU pre-access slot rate of 50%, 314 cycles implies 31 CPU and 63 non-CPU accesses (31×6+32×4=314). For 12 LLU accesses interspersed amongst these 63 non-CPU slots, implies an LLU allocation rate of approximately one slot in 5.

If the CPU pre-access is 100% across all slots, then 314 cycles gives 52 slots each to CPU and non-CPU accesses, (52×6=312 cycles). Twelve accesses spread over 52 slots, implies a 1-in-4 slot allocation to the LLU.

The same LLU slot allocation rate (1 slot in 5, or 1 in 4) can be applied to programming slots across a 256-cycle rotation window. The window size does not affect the occurrence of LLU slots, so the 384-cycle service requirement will be fulfilled.

20.12.1.5 DNC

This has a 2.4 bits/cycle bandwidth requirement. Each access will see the DIU stall of 18 cycles. 2.4 bits/cycle corresponds to an access every 106 cycles within a 256 cycle rotation. So to allow for DIU latency we need an access every 106-18 or 88 cycles. This is a bandwidth of 2.9 bits/cycle, requiring 3 timeslots in the rotation.

20.12.1.6 CDU

The JPEG decoder produces 8 bits/cycle. Peak CDUR[ead] bandwidth is 4 bits/cycle (SF=4), peak CDUW[rite] bandwidth is 4 bits/cycle (SF=4). both with 1.5 DRAM buffering.

The CDU(R) does a DIU read every 64 cycles at scale factor 4 with 1.5 DRAM buffering. The delay in being serviced by the DIU could be read circuit latency (10)+refresh (3)+extra CDU(W) cycles (6)=19 cycles. The JPEG decoder can consume each 256 bits of DIU-supplied data at 8 bits/cycle, i.e. in 32 cycles. If the DIU is 19 cycles late (due to latency) in supplying the read data then the JPEG decoder will have finished processing the read data 32+19=49 cycles after the DIU access. This is 64-49=15 cycles in advance of the next read. This 15 cycles is the upper limit on how much the DIU read service can further be delayed, without causing a stall. Given this margin, a stall on the read side will not occur.

On the write side, for scale factor 4, the access pattern is a DIU writes every 64 cycles with 1.5 DRAM buffereing. The JPEG decoder runs at 8 bits cycle and consumes 256 bits in 32 cycles. The CDU will not stall if the JPEG decode time (32)+DIU stall (19)<64, which is true.

20.13 CPU DRAM Access Performance

The CPU's share of the timeslots can be specified in terms of guaranteed bandwidth and average bandwidth allocations.

    • The CPU's access rate to memory depends on the CPU read access latency i.e. the time between the CPU making a request to the DIU and receiving the read data back from the DIU.
    • how often it can get access to DIU timeslots.

Table estimated the CPU read latency as 6 cycles.

How often the CPU can get access to DIU timeslots depends on the access type. This is summarised in Table 122.

TABLE 122
CPU DRAM access performance
Nominal
AccessTimeslotCPU DRAM
TypeDurationaccess rateNotes
CPU Pre-6 cyclesLower boundCPU can access every timeslot.
access(guaranteed bandwidth)
is 160 MHz/6 = 26.27 MHz
Fractional4 or 6cyclesLower boundCPU accesses precede a fraction
CPU(guaranteed bandwidth)N of timeslots
Pre-accessis (160 MHz * N/P)where N = C/T.
C = CPUPreAccessTimeslots
T = CPUTotalTimeslots
P = (6 * C + 4 * (T − C))/T

In both CPU Pre-access and Fractional CPU Pre-access modes, if the CPU is not requesting the timeslots will have a duration of 3 or 4 cycles depending on whether the current access and preceding access are both to the shared read bus. This will mean that the timeslot rotation will run faster and more bandwidth is available.

If the CPU runs out of its instruction cache then instruction fetch performance is only limited by the on-chip bus protocol. If data resides in the data cache then 160 MHz performance is achieved. Accessing memory mapped registers, PSS or ROM with a 3 cycle bus protocol (address cycle+data cycle) gives 53 MHz performance.

Due to the action of CPU caching, some bandwidth limiting of the CPU in Fractional CPU Pre-access mode is expected to have little or no impact on the overall CPU performance.

20.14 Implementation

The DRAM Interface Unit (DIU) is partitioned into 2 logical blocks to facilitate design and verification.

a. The DRAM Arbitration Unit (DAU) which interfaces with the SoPEC DIU requesters.

b. The DRAM Controller Unit (DCU) which accesses the embedded DRAM.

The basic principle in design of the DIU is to ensure that the eDRAM is accessed at its maximum rate while keeping the CPU read access latency as low as possible.

The DCU is designed to interface with single bank 20 Mbit IBM Cu-11 embedded DRAM performing random accesses every 3 cycles. Page mode burst of 4 write accesses, associated with the CDU, are also supported.

The DAU is designed to support interleaved accesses allowing the DRAM to be accessed every 3 cycles where back-to-back accesses do not occur over the shared 64-bit read data bus.

20.14.1 DIU Partition

20.14.2 Definition of DCU IO

TABLE 123
DCU interface
Port NamePinsI/ODescription
Clocks and Resets
pclk1InSoPEC Functional clock
dau_dcu_reset_n1InActive-low, synchronous reset in pclk domain.
Incorporates DAU hard and soft resets.
Inputs from DAU
dau_dcu_msn2stall1InSignal indicating from DAU Arbitration Logic
which when asserted stalls DCU in MSN2
state.
dau_dcu_adr[21:5]17InSignal indicating the address for the DRAM
access. This is a 256-bit aligned DRAM
address.
dau_dcu_rwn1InSignal indicating the direction for the DRAM
access (1=read, 0=write).
dau_dcu_cduwpage1InSignal indicating if access is a CDU write
page mode access (1=CDU page mode,
0=not CDU page mode).
dau_dcu_refresh1InSignal indicating that a refresh command is to
be issued. If asserted day_dcu_adr,
dau_dcu_rwn and dau_dcu_cduwpage are
ignored.
dau_dcu_wdata256In256-bit write data to DCU
dau_dcu_wmask32InByte encoded write data mask for 256-bit
dau_dcu_wdata to DCU
Polarity: A “1” in a bit field of
dau_dcu_wmask means that the
corresponding byte in the 256-bit
dau_dcu_wdata is written to DRAM.
Outputs to DAU
dcu_dau_adv1OutSignal indicating to DAU to supply next
command to DCU
dcu_dau_wadv1OutSignal indicating to DAU to initiate next non-
CPU write
dcu_dau_refreshcomplete1OutSignal indicating that the DCU has completed
a refresh.
dcu_dau_rdata256Out256-bit read data from DCU.
dcu_dau_rvalid1OutSignal indicating valid read data on
dcu_dau_rdata.

20.14.3 DRAM Access Types

The DRAM access types used in SoPEC are summarised in Table 124. For a refresh operation the DRAM generates the address internally.

TABLE 124
SoPEC DRAM access types
TypeAccess
ReadRandom 256-bit read
WriteRandom 256-bit write with byte write masking
Page mode write for burst of 4 256-bit
words with byte write masking
RefreshSingle refresh

20.14.4 Constructing the 20 Mbit DRAM From Two 10 Mbit Instances

The 20 Mbit DRAM is constructed from two 10 Mbit instances. The address ranges of the two instances are shown in Table 125.

TABLE 125
Address ranges of the two 10 Mbit instances
in the 20 Mbit DRAM
Hex 256-bitBinary 256-bit
InstanceAddressword addressword address
Instance0First word in000000 0000 0000 0000 0000
lower 10 Mbit
Instance0Last word in09FFF0 1001 1111 1111 1111
lower 10 Mbit
Instance1First word in0A0000 1010 0000 0000 0000
upper 10 Mbit
Instance1Last word in13FFF1 0011 1111 1111 1111
upper 10 Mbit

There are separate macro select signals, inst0_MSN and inst1_MSN, for each instance and separate dataout busses inst0_DO and inst1_DO, which are multiplexed in the DCU. Apart from these signals both instances share the DRAM output pins of the DCU.

The DRAM Arbitration Unit (DAU) generates a 17 bit address, dau_dcu_adr[21:5], sufficient to address all 256-bit words in the 20 Mbit DRAM. The upper 5 bits are used to select between the two memory instances by gating their MSN pins. If instance1 is selected then the lower 16-bits are translated to map into the 10 Mbit range of that instance. The multiplexing and address translation rules are shown in Table 126.

In the case that the DAU issues a refresh, indicated by dau_dcu_refresh, then both macros are selected. The other control signals

TABLE 126
Instance selection and address translation
DAU Address bitsInstance
dau_dcu_refreshdau_dcu_adr[21:17]selectedinst0_MSNinst1_MSNAddress translation
0  <01010Instance0MSN1A[15:0] =
dau_dcu_adr[20:5]
>=01010Instance11MSNA[15:0] =
dau_dcu_adr[21:5] −
hA000
1Instance0MSNMSN
and
Instance1

dau_dcu_adr[21:5], dau_dcu_rwn and dau_dcu_cduwpage are ignored.

The instance selection and address translation logic is shown in FIG. 102.

The address translation and instance decode logic also increments the address presented to the DRAM in the case of a page mode write. Pseudo code is given below.

if rising_edge(dau_dcu_valid) then
//capture the address from the DAU
next_cmdadr[21:5] = dau_dcu_adr[21:5]
elsif pagemode_adr_inc == 1 then
//increment the address
next_cmdadr[21:5] = cmdadr[21:5] + 1
else
next_cmdadr[21:5] = cmdadr[21:5]
if rising_edge(dau_dcu_valid) then
//capture the address from the DAU
adr_var[21:5] := dau_dcu_adr[21:5]
else
adr_var[21:5] := cmdadr[21:5]
if adr_var[21:17] < 01010 then
//choose instance0
instance_sel = 0
A[15:0] = adr_var[20:5]
else
//choose instance1
instance_sel = 1
A[15:0] = adr_var[21:5] − hA000

Pseudo code for the select logic, SEL0, for DRAM Instance0 is given below.

//instance0 selected or refresh
if instance_sel == 0 OR dau_dcu_refresh == 1 then
inst0_MSN = MSN
else
inst0_MSN = 1

Pseudo code for the select logic, SEL1, for DRAM instance1 is given below.

//instance1 selected or refresh
if instance_sel == 1 OR dau_dcu_refresh == 1 then
inst1_MSN = MSN
else
inst1_MSN = 1

During a random read, the read data is returned, on dcu_dau_rdata, after time Tacc, the random access time, which varies between 3 and 8 ns (see Table). To avoid any metastability issues the read data must be captured by a flip-flop which is enabled 2 pclk cycles or 12.5 ns after the DRAM access has been started. The DCU generates the enable signal dcu_dau_rvalid to capture dcu_dau_rdata.

The byte write mask dau_dcu_wmask[31:0] must be expanded to the bit write mask bitwritemask[255:0 needed by the DRAM.

20.14.5 DAU-DCU Interface Description

The DCU asserts dcu_dau_adv in the MSN2 state to indicate to the DAU to supply the next command. dcu_dau_adv causes the DAU to perform arbitration in the MSN2 cycle. The resulting command is available to the DCU in the following cycle, the RST state. The timing is shown in FIG. 103. The command to the DRAM must be valid in the RST and MSN1 states, or at least meet the hold time requirement to the MSN falling edge at the start of the MSN1 state.

Note that the DAU issues a valid arbitration result following every dcu_dau_adv pulse. If no unit is requesting DRAM access, then a fall-back refresh request will be issued. When dau_dcu_refresh is asserted the operation is a refresh and dau_dcu_adr, dau_dcu_rwn and dau_dcu_cduwpage are ignored.

The DCU generates a second signal, dcu_dau_wadv, which is asserted in the RST state. This indicates to the DAU that it can perform arbitration in advance for non-CPU writes. The reason for performing arbitration in advance for non-CPU writes is explained in “Command Multiplexor Sub-block

TABLE 136
Command Multiplexor Sub-block IO Definition
Port namePinsI/ODescription
Clocks and Resets
pclk1InSystem Clock
prst_n1InSystem reset, synchronous active low
DIU Read Interface to SoPEC Units
<unit>_diu_radr[21:5]17InRead address to DIU
17 bits wide (256-bit aligned word).
diu_<unit>_rack1OutAcknowledge from DIU that read request has been
accepted and new read address can be placed on
<unit>_diu_radr
DIU Write Interface to SoPEC Units
<unit>_diu_wadr[21:5]17InWrite address to DIU except CPU, SCB, CDU
17 bits wide (256-bit aligned word)
cpu_diu_wadr[21:4]]22InCPU Write address to DIU
(128-bit aligned address.)
cpu_diu_wmask16InByte enables for CPU write.
cdu_diu_wadr[21:3]19InCDU Write address to DIU
19 bits wide (64-bit aligned word)
Addresses cannot cross a 256-bit word DRAM boundary.
diu_<unit>_wack1OutAcknowledge from DIU that write request has been
accepted and new write address can be placed on
<unit>_diu_wadr
Outputs to CPU Interface and Arbitration Logic sub-block
re_arbitrate1OutSignalling telling the arbitration logic to choose the next
arbitration winner.
re_arbitrate_wadv1OutSignal telling the arbitration logic to choose the next
arbitration winner for non-CPU writes 2 timeslots in
advance
Debug Outputs to CPU Configuration and Arbitration Logic Sub-block
write_sel5OutSignal indicating the SoPEC Unit for which the current
write transaction is occurring. Encoding is described in
Table .
write_complete1OutSignal indicating that write transaction to SoPEC Unit indicated
by write_sel is complete.
Inputs from CPU Interface and Arbitration Logic sub-block
arb_gnt1InSignal lasting 1 cycle which indicates arbitration has
occurred and arb_sel is valid.
arb_sel5InSignal indicating which requesting SoPEC Unit has won
arbitration. Encoding is described in Table .
dir_sel2InSignal indicating which sense of access associated with
arb_sel
00: issue non-CPU write
01: read winner
10: write winner
11: refresh winner
Inputs from Read Write Multiplexor Sub-block
write_data_valid2InSignal indicating that valid write data is available for the
current command.
00=not valid
01=CPU write data valid
10=non-CPU write data valid
11=both CPU and non-CPU write data Valid
wdata256In256-bit non-CPU write data
cpu_wdata32In32-bit CPU write data
Outputs to Read Write Multiplexor Sub-block
write_data_accept2OutSignal indicating the Command Multiplexor has accepted
the write data from the write multiplexor
00=not valid
01=accepts CPU write data
10=accepts non-CPU write data
11=not valid
Inputs from DCU
dcu_dau_adv1InSignal indicating to DAU to supply next command to DCU
dcu_dau_wadv1InSignal indicating to DAU to initiate next non-CPU write
Outputs to DCU
dau_dcu_adr[21:5]17OutSignal indicating the address for the DRAM access. This is
a 256-bit aligned DRAM address.
dau_dcu_rwn1OutSignal indicating the direction for the DRAM access
(1=read, 0=write).
dau_dcu_cduwpage1OutSignal indicating if access is a CDU write page mode
access (1=CDU page mode, 0 = not CDU page mode).
dau_dcu_refresh1OutSignal indicating that a refresh command is to be issued. If
asserted dau_dcu_adr, dau_dcu_rwn and
dau_dcu_cduwpage are ignored.
dau_dcu_wdata256Out256-bit write data to DCU
dau_dcu_wmask32OutByte encoded write data mask for 256-bit dau_dcu_wdata
to DCU

The DCU state-machine can stall in the MSN2 state when the signal dau_dcu_msn2stall is asserted by the DAU Arbitration Logic,

The states of the DCU state-machine are summarised in Table 127.

TABLE 127
States of the DCU state-machine
StateDescription
RSTRestore state
MSN1Macro select state 1
MSN2Macro select state 2

20.14.6 DCU State Machines

The IBM DRAM has a simple SRAM like interface. The DRAM is accessed as a single bank. The state machine to access the DRAM is shown in FIG. 104.

The signal pagemode_adr_inc is exported from the DCU as dcu_dau_cduwaccept. dcu_dau_cduwaccept tells the DAU to supply the next write data to the DRAM

20.14.7 CU-11DRAM Timing Diagrams

The IBM Cu-11 embedded DRAM datasheet is referenced as [16].

Table 128 shows the timing parameters which must be obeyed for the IBM embedded DRAM.

TABLE 128
1.5 V Cu-11 DRAM a.c. parameters
SymbolParameterMinMaxUnits
TsetInput setup to MSN/PGN1ns
ThldInput hold to MSN/PGN2ns
TaccRandom access time38  ns
TactMSN active time8100kns
TresMSN restore time4ns
TcycRandom R/W cycle time12ns
TrfcRefresh cycle time12ns
TaccpPage mode access time13.9ns
TpaPGN active time1.6ns
TprPGN restore time1.6ns
TpcycPGN cycle time4ns
TmprdMSN to PGN restore delay6ns
TactpMSN active for page mode12ns
TrefRefresh period3.2ms
TpamrPage active to MSN restore4ns

The IBM DRAM is asynchronous. In SoPEC it interfaces to signals clocked on pclk. The following timing diagrams show how the timing parameters in Table 129 are satisfied in SoPEC.

20.14.8 Definition of DAU IO

TABLE 129
DAU interface
Port NamePinsI/ODescription
Clocks and Resets
pclk1InSoPEC Functional clock
prst_n1InActive-low, synchronous reset in pclk domain
dau_dcu_reset_n1OutActive-low, synchronous reset in pclk domain. This
reset signal, exported to the DCU, incorporates the
locally captured DAU version of hard reset (prst_n) and
the soft reset configuration register bit “Reset”.
CPU Interface
cpu_adr22InCPU address bus for both DRAM and configuration
register access.
9 bits (bits 10:2) are required to decode the
configuration register address space.
22 bits can address the DRAM at byte level. DRAM
addresses cannot cross a 256-bit word DRAM
boundary.
cpu_dataout32InShared write data bus from the CPU for DRAM and
configuration data
diu_cpu_data32OutConfiguration, status and debug read data bus to the
CPU
diu_cpu_debug_valid1OutSignal indicating the data on the diu_cpu_data bus is
valid debug data.
cpu_rwn1InCommon read/not-write signal from the CPU
cpu_acode2InCPU access code signals.
cpu_acode[0] - Program (0)/Data (1) access
cpu_acode[1] - User (0)/Supervisor (1) access
The DAU will only allow supervisor mode accesses to
data space.
cpu_diu_sel1InBlock select from the CPU. When cpu_diu_sel is high
both cpu_adr and cpu_dataout are valid
diu_cpu_rdy1OutReady signal to the CPU. When diu_cpu_rdy is high it
indicates the last cycle of the access. For a write cycle
this means cpu_dataout has been registered by the
block and for a read cycle this means the data on
diu_cpu_data is valid.
diu_cpu_berr1OutBus error signal to the CPU indicating an invalid
access.
DIU Read Interface to SoPEC Units
<unit>_diu_rreq1InSoPEC unit requests DRAM read. A read request must
be accompanied by a valid read address.
<unit>_diu_radr[21:5]17InRead address to DIU
17 bits wide (256-bit aligned word).
Note: “<unit>” refers to non-CPU requesters only.
CPU addresses are provided via “cpu_adr”.
diu_<unit>_rack1OutAcknowledge from DIU that read request has been
accepted and new read address can be placed on
<unit>_diu_radr
diu_data64OutData from DIU to SoPEC Units except CPU.
First 64-bits is bits 63:0 of 256 bit word
Second 64-bits is bits 127:64 of 256 bit word
Third 64-bits is bits 191:128 of 256 bit word
Fourth 64-bits is bits 255:192 of 256 bit word
dram_cpu_data256Out256-bit data from DRAM to CPU.
diu_<unit>_rvalid1OutSignal from DIU telling SoPEC Unit that valid read data
is on the diu_data bus
DIU Write Interface to SoPEC Units
<unit>_diu_wreq1InSoPEC unit requests DRAM write. A write request
must be accompanied by a valid write address.
Note: “<unit>” refers to non-CPU requesters only.
<unit>_diu_wadr[21:5]17InWrite address to DIU except CPU, CDU
17 bits wide (256-bit aligned word)
Note: “<unit>” refers to non-CPU requesters,
excluding the CDU.
scb_diu_wmask[7:0]8InByte write enables applicable to a given 64-bit quarter-
word transferred from the SCB. Note that different
mask values are used with each quarter-word.
Requirement for the USB host core.
diu_cpu_write_rdy1OutFlag indicating that the CPU posted write buffer is
empty.
cpu_diu_wdatavalid1InWrite enable for the CPU posted write buffer. Also
confirms that the CPU write data, address and mask
are valid.
cpu_diu_wdata128InCPU write data which is loaded into the posted write
buffer.
cpu_diu_wadr[21:4]18In128-bit aligned CPU write address.
cpu_diu_wmask[15:0]16InByte enables for 128-bit CPU posted write.
cdu_diu_wadr[21:3]19InCDU Write address to DIU
19 bits wide (64-bit aligned word)
Addresses cannot cross a 256-bit word DRAM
boundary.
diu_<unit>_wack1OutAcknowledge from DIU that write request has been
accepted and new write address can be placed on
<unit>_diu_wadr
<unit>_diu_data[63:0]64InData from SoPEC Unit to DIU except CPU.
First 64-bits is bits 63:0 of 256 bit word
Second 64-bits is bits 127:64 of 256 bit word
Third 64-bits is bits 191:128 of 256 bit word
Fourth 64-bits is bits 255:192 of 256 bit word
Note: “<unit>” refers to non-CPU requesters only.
<unit>_diu_wvalid1InSignal from SoPEC Unit indicating that data on
<unit>_diu_data is valid.
Note: “<unit>” refers to non-CPU requesters only.
Outputs to DCU
dau_dcu_msn2stall1OutSignal indicating from DAU Arbitration Logic which
when de-asserted stalls DCU in MSN2 state.
dau_dcu_adr[21:5]17OutSignal indicating the address for the DRAM access.
This is a 256-bit aligned DRAM address.
dau_dcu_rwn1OutSignal indicating the direction for the DRAM access
(1=read, 0=write).
dau_dcu_cduwpage1OutSignal indicating if access is a CDU write page mode
access (1=CDU page mode, 0=not CDU page mode).
dau_dcu_refresh1OutSignal indicating that a refresh command is to be
issued. If asserted dau_dcu_cmd_adr, dau_dcu_rwn
and dau_dcu_cduwpage are ignored.
dau_dcu_wdata256Out256-bit write data to DCU
dau_dcu_wmask32OutByte-encoded write data mask for 256-bit
dau_dcu_wdata to DCU
Polarity: A “1” in a bit field of dau_dcu_wmask means
that the corresponding byte in the 256-bit
dau_dcu_wdata is written to DRAM.
Inputs from DCU
dcu_dau_adv1InSignal indicating to DAU to supply next command to
DCU
dcu_dau_wadv1InSignal indicating to DAU to initiate next non-CPU write
dcu_dau_refreshcomplete1InSignal indicating that the DCU has completed a
refresh.
dcu_dau_rdata256In256-bit read data from DCU.
dcu_dau_rvalid1InSignal indicating valid read data on dcu_dau_rdata.

The CPU subsystem bus interface is described in more detail in Section 11.4.3. The DAU block will only allow supervisor-mode accesses to update its configuration registers (i.e. cpu_acode[1:0]=b11). All other accesses will result in diu_cpu_berr being asserted.

20.14.9 DAU Configuration Registers

TABLE 130
DAU configuration registers
Address
(DIU_base+)Register#bitsResetDescription
Reset
0x00Reset10x1A write to this register causes a reset
of the DIU.
This register can be read to indicate
the reset state:
0 - reset in progress
1 - reset not in progress
Refresh
0x04RefreshPeriod90x063Refresh controller.
When set to 0 refresh is off, otherwise
the value indicates the number of
cycles, less one, between each
refresh. [Note that for a system clock
frequency of 160 MHz, a value
exceeding 0x63 (indicating a 100-cycle
refresh period) should not be
programmed, or the DRAM will
malfunction.]
Timeslot allocation and control
0x08NumMainTimeslots60x01Number of main timeslots (1-64) less
one
0x0CCPUPreAccessTimes40x0(CPUPreAccessTimeslots + 1) main
lotsslots out of a total of
(CPUTotalTimeslots + 1) are preceded
by a CPU access.
0x10CPUTotalTimeslots40x0(CPUPreAccessTimeslots + 1) main
slots out of a total of
(CPUTotalTimeslots + 1) are preceded
by a CPU access.
0x100-0x1FCMainTimeslot[63:0]64x4[63:1][3:0] = 0x0Programmable main timeslots (up to
[0][3:0] = 0xE64 main timeslots).
0x200ReadRoundRobinLevel120x000For each read requester plus refresh
0 = level1 of round-robin
1 = level2 of round-robin
The bit order is defined in Table .
0x204EnableCPURound10x1Allows the CPU to particpate in the
Robinunused read round-robin scheme. If
disabled, the shared CPU/refresh
round-robin position is dedicated
solely to refresh.
0x208RotationSync10x1Writing 0, followed by 1 to this bit
allows the timeslot rotation to advance
on a cycle basis which can be
determined by the CPU.
0x20CminNonCPUReadAdr120x80012 MSBs of lowest DRAM address
which may be read by non-CPU
requesters.
0x210minDWUWriteAdr120x80012 MSBs of lowest DRAM address
which may be written to by the DWU.
0x214minNonCPUWriteAdr120x80012 MSBs of lowest DRAM address
which may be written to by non-CPU
requesters other than the DWU.
Debug
0x300DebugSelect[11:2]100x304Debug address select. Indicates the
address of the register to report on the
diu_cpu_data bus when it is not
otherwise being used.
When this signal carries debug
information the signal
diu_cpu_debug_valid will be asserted.
Debug: arbitration and performance
0x304ArbitrationHistory22Bit 0 = arb_gnt
Bit 1 = arb_executed
Bit 6:2 = arb_sel[4:0]
Bit 12:7 = timeslot_number[5:0]
Bit 15:13 = access_type[2:0]
Bit 16 = back2back_non_cpu_write
Bit 17 = sticky_back2back_non_cpu_write
(Sticky version of same, cleared on
reset.)
Bit 18 = rotation_sync
Bit 20:19 = rotation_state
Bit 21 = sticky_invalid_non_cpu_adr
See Section 20.14.9.2 DIU Debug for
a description of the fields.
Read only register.
0x308DIUPerformance31Bit 0 = cpu_diu_rreq
Bit 1 = scb_diu_rreq
Bit 2 = cdu_diu_rreq
Bit 3 = cfu_diu_rreq
Bit 4 = lbd_diu_rreq
Bit 5 = sfu_diu_rreq
Bit 6 = td_diu_rreq
Bit 7 = tfs_diu_rreq
Bit 8 = hcu_diu_rreq
Bit 9 = dnc_diu_rreq
Bit 10 = llu_diu_rreq
Bit 11 = pcu_diu_rreq
Bit 12 = cpu_diu_wreq
Bit 13 = scb_diu_wreq
Bit 14 = cdu_diu_wreq
Bit 15 = sfu_diu_wreq
Bit 16 = dwu_diu_wreq
Bit 17 = refresh_req
Bit 22:18 = read_sel[4:0]
Bit 23 = read_complete
Bit 28:24 = write_sel[4:0]
Bit 29 = write_complete
Bit 30 = dcu_dau_refreshcomplete
See Section 20.14.9.2 DIU Debug for
a description of the fields.
Read only register.
Debug DIU read requesters interface signals
0x30CCPUReadInterface25Bit 0 = cpu_diu_rreq
Bit 22:1 = cpu_adr[21:0]
Bit 23 = diu_cpu_rack
Bit 24 = diu_cpu_rvalid
Read only register.
0x310SCBReadInterface20Bit 0 = scb_diu_rreq
Bit 17:1 = scb_diu_radr[21:5]
Bit 18 = diu_scb_rack
Bit 19 = diu_scb_rvalid
Read only register.
0x314CDUReadInterface20Bit 0 = cdu_diu_rreq
Bit 17:1 = cdu_diu_radr[21:5]
Bit 18 = diu_cdu_rack
Bit 19 = diu_cdu_rvalid
Read only register.
0x318CFUReadInterface20Bit 0 = cfu_diu_rreq
Bit 17:1 = cfu_diu_radr[21:5]
Bit 18 = diu_cfu_rack
Bit 19 = diu_cfu_rvalid
Read only register.
0x31CLBDReadInterface20Bit 0 = lbd_diu_rreq
Bit 17:1 = lbd_diu_radr[21:5]
Bit 18 = diu_lbd_rack
Bit 19 = diu_lbd_rvalid
Read only register.
0x320SFUReadInterface20Bit 0 = sfu_diu_rreq
Bit 17:1 = sfu_diu_radr[21:5]
Bit 18 = diu_sfu_rack
Bit 19 = diu_sfu_rvalid
Read only register.
0x324TDReadInterface20Bit 0 = td_diu_rreq
Bit 17:1 = td_diu_radr[21:5]
Bit 18 = diu_td_rack
Bit 19 = diu_td_rvalid
Read only register.
0x328TFSReadInterface20Bit 0 = tfs_diu_rreq
Bit 17:1 = tfs_diu_radr[21:5]
Bit 18 = diu_tfs_rack
Bit 19 = diu_tfs_rvalid
Read only register.
0x32CHCUReadInterface20Bit 0 = hcu_diu_rreq
Bit 17:1 = hcu_diu_radr[21:5]
Bit 18 = diu_hcu_rack
Bit 19 = diu_hcu_rvalid
Read only register.
0x330DNCReadInterface20Bit 0 = dnc_diu_rreq
Bit 17:1 = dnc_diu_radr[21:5]
Bit 18 = diu_dnc_rack
Bit 19 = diu_dnc_rvalid
Read only register.
0x334LLUReadInterface20Bit 0 = llu_diu_rreq
Bit 17:1 = lluu_diu_radr[21:5]
Bit 18 = diu_llu_rack
Bit 19 = diu_llu_rvalid
Read only register.
0x338PCUReadInterface20Bit 0 = pcu_diu_rreq
Bit 17:1 = pcu_diu_radr[21:5]
Bit 18 = diu_pcu_rack
Bit 19 = diu_pcu_rvalid
Read only register.
Debug DIU write requesters interface signals
0x33CCPUWriteInterface27Bit 0 = cpu_diu_wreq
Bit 22:1 = cpu_adr[21:0]
Bit 24:23 = cpu_diu_wmask[1:0]
Bit 25 = diu_cpu_wack
Bit 26 = cpu_diu_wvalid
Read only register.
0x340SCBWriteInterface20Bit 0 = scb_diu_wreq
Bit 17:1 = scb_diu_wadr[21:5]
Bit 18 = diu_scb_wack
Bit 19 = scb_diu_wvalid
Read only register.
0x344CDUWriteInterface22Bit 0 = cdu_diu_wreq
Bit 19:1 = cdu_diu_wadr[21:3]
Bit 20 = diu_cdu_wack
Bit 21 = cdu_diu_wvalid
Read only register.
0x348SFUWriteInterface20Bit 0 = sfu_diu_wreq
Bit 17:1 = sfu_diu_wadr[21:5]
Bit 18 = diu_sfu_wack
Bit 19 = sfu_diu_wvalid
Read only register.
0x34CDWUWriteInterface20Bit 0 = dwu_diu_wreq
Bit 17:1 = dwu_diu_wadr[21:5]
Bit 18 = diu_dwu_wack
Bit 19 = dwu_diu_wvalid
Read only register.
Debug DAU-DCU interface signals
0x350DAU-DCUInterface25Bit 16:0 = dau_dcu_adr[21:5]
Bit 17 = dau_dcu_rwn
Bit 18 = dau_dcu_cduwpage
Bit 19 = dau_dcu_refresh
Bit 20 = dau_dcu_msn2stall
Bit 21 = dcu_dau_adv
Bit 22 = dcu_dau_wadv
Bit 23 = dcu_dau_refreshcomplete
Bit 24 = dcu_dau_rvalid
Read only register.

Each main timeslot can be assigned a SoPEC DIU requestor according to Table 131.

TABLE 131
SoPEC DIU requester encoding for main timeslots.
NameIndex (binary)Index (HEX)
Write
SCB(W)b0_00000x00
CDU(W)b00010x1
SFU(W)b00100x2
DWUb00110x3
Read
SCB(R)b01000x4
CDU(R)b01010x5
CFUb01100x6
LBDb01110x7
SFU(R)b10000x8
TE(TD)b10010x9
TE(TFS)b10100xA
HCUb10110xB
DNCb11000xC
LLUb11010xD
PCUb11100xE

ReadRoundRobinLevel and ReadRoundRobinEnable registers are encoded in the bit order defined in Table 132.

TABLE 132
Read round-robin registers bit order
NameBit index
SCB(R)0
CDU(R)1
CFU2
LBD3
SFU(R)4
TE(TD)5
TE(TFS)6
HCU7
DNC8
LLU9
PCU10
CPU/11
Refresh

20.14.9.1 Configuration Register Reset State

The RefreshPeriod configuration register has a reset value of 0x063 which ensures that a refresh will occur every 100 cycles and the contents of the DRAM will remain valid.

The CPUPreAccessTimeslots and CPUTotalTimeslots configuration registers both have a reset value of 0x0. Matching values in these two registers means that every slot has a CPU pre-acess. NumMainTimeslots is reset to 0x1, so there are just 2 main timeslots in the rotation initially. These slots alternate between SCB writes and PCU reads, as defined by the reset value of MainTimeslot[63:0], thus respecting at reset time the general rule that adjacent non-CPU writes are not permitted.

The first access issued by the DIU after reset will be a refresh.

20.14.9.2 DIU Debug

External visibility of the DIU must be provided for debug purposes. To facilitate this debug registers are added to the DIU address space.

The DIU CPU system data bus diu_cpu_data[31:0] returns configuration and status register information to the CPU. When a configuration or status register is not being read by the CPU debug data is returned on diu_cpu_data[31:0] instead. An accompanying active high diu_cpu_debug_valid signal is used to indicate when the data bus contains valid debug data. The DIU features a DebugSelect register that controls a local multiplexor to determine which register is output on diu_cpu_data[31:0].

Three kinds of debug information are gathered:

a. The order and access type of DIU requesters winning arbitration.

This information can be obtained by observing the signals in the ArbitrationHistory debug register at DIU_Base+0x304 described in Table 133.

TABLE 133
ArbitrationHistory debug register description, DIU_base+0x304
Field nameBitsDescription
arb_gnt1Signal lasting 1 cycle which is asserted in the cycle following a main
arbitration or pre-arbitration.
arb_executed1Signal lasting 1 cycle which indicates that an arbitration result has
actually been executed. Is used to differentiate between *pre*-arbitration
and *main* arbitration, both of which cause arb_gnt to be asserted. If
arb_executed and arb_gnt are both high, then a main (executed)
arbitration is indicated.
arb_sel5Signal indicating which requesting SoPEC Unit has won arbitration.
Encoding is described in Table . Refresh winning arbitration is
indicated by access_type.
timeslot_number6Signal indicating which main timeslot is either currently being serviced,
or about to be serviced. The latter case applies where a main slot is pre-
empted by a CPU pre-access or a scheduled refresh.
access_type3Signal indicating the origin of the winning arbitration
000 = Standard CPU pre-access.
001 = Scheduled refresh.
010 = Standard non-CPU timeslot.
011 = CPU access via unused read/write slot, re-allocated by round
robin.
100 = Non-CPU write via unused write slot, re-allocated at pre-
arbitration.
101 = Non-CPU read via unused read/write slot, re-allocated by round
robin.
110 = Refresh via unused read/write slot, re-allocated by round robin.
111 = CPU/Refresh access due to RotationSync = 0.
back2back_non_cpu_write1Instantaneous indicator of attempted illegal back-to-back non-CPU
write. (Recall from section 20.7.2.3 on page 212 that the second write of
any such pair is disregarded and re-allocated via the unused read
round-robin scheme.)
sticky_back2back_non_cpu_write1Sticky version of same, cleared on reset.
rotation_sync1Current value of the RotationSync configuration bit.
rotation_state2These bits indicate the current status of pre-arbitation and main timeslot
rotation, as a result of the RotationSync setting.
00 = Pre-arb enabled, rotation enabled.
01 = Pre-arb disabled, rotation enabled.
10 = Pre-arb disabled, rotation disabled.
11 = Pre-arb enabled, rotation disabled.
00 is the normal functional setting when RotationSync is 1.
01 indicates that pre-arbitration has halted at the end of its rotation
because of RotationSync having been cleared. However the main
arbitration has yet to finish its current rotation.
10 indicates that both pre-arb and the main rotation have halted, due to
RotationSync being 0 and that only CPU accesses and refreshes are
allowed.
11 indicates that RotationSync has just been changed from 0 to 1 and
that pre-arbitration is being given a head start to look ahead for non-
CPU writes, in advance of the main rotation starting up again.
sticky_invalid_non_cpu_adr1Sticky bit to indicate an attempted non-CPU access with an invalid
address. Cleared by reset or by an explicit write by the CPU.

TABLE 134
arb_sel, read_sel and write_sel encoding
NameIndex (binary)Index (HEX)
Write
SCB(W)b0_00000x00
CDU(W)b0_00010x01
SFU(W)b0_00100x02
DWUb0_00110x03
Read
SCB(R)b0_01000x04
CDU(R)b0_01010x05
CFUb0_01100x06
LBDb0_01110x07
SFU(R)b0_10000x08
TE(TD)b0_10010x09
TE(TFS)b0_10100x0A
HCUb0_10110x0B
DNCb0_11000x0C
LLUb0_11010x0D
PCUb0_11100x0E
Refresh
Refreshb0_11110x0F
CPU
CPU(R)b1_00000x10
CPU(W)b1_00010x11

The encoding for arb_sel is described in Table 134.

b. The time between a DIU requester requesting an access and completing the access. This information can be obtained by observing the signals in the DIUPerformance debug register at DIU_Base+0x308 described in Table 135. The encoding for read_sel and write_sel is described in Table. The data collected from DIUPerformance can be post-processed to count the number of cycles between a unit requesting DIU access and the access being completed.

TABLE 135
DIUPerformance debug register description, DIU_base+0x308
Field nameBitsDescription
<unit>_diu_rreq12Signal indicating that SoPEC unit requests DRAM read.
<unit>_diu_wreq5Signal indicating that SoPEC unit requests DRAM write.
refresh_req1Signal indicating that refresh has requested a DIU access.
read_sel[4:0]5Signal indicating the SoPEC Unit for which the current read
transaction is occurring. Encoding is described in Table
read_complete1Signal indicating that read transaction to SoPEC Unit indicated by
read_sel is complete i.e. that the last read data has been output
by the DIU.
write_sel[4:0]5Signal indicating the SoPEC Unit for which the current write
transaction is occurring. Encoding is described in Table
write_complete1Signal indicating that write transaction to SoPEC Unit indicated
by write_sel is complete i.e. that the last write data has been
transferred to the DIU.
dcu_refresh_complete1Signal indicating that refresh has completed.

c. Interface signals to DIU requestors and DAU-dCU interface.

All interface signals with the exception of data busses at the interfaces between the DAU and DCU and DIU write and read requestors can be monitored in debug mode by observing debug registers DIU_Base+0x314 to DIU_Base+0x354.

20.14.10 DRAM Arbitration Unit (DAU)

The DAU is shown in FIG. 101.

The DAU is composed of the following sub-blocks

a. CPU Configuration and Arbitration Logic sub-block.

b. Command Multiplexor sub-block.

c. Read and Write Data Multiplexor sub-block.

The function of the DAU is to supply DRAM commands to the DCU.

    • The DCU requests a command from the DAU by asserting dcu_dau_adv.
    • The DAU Command Multiplexor requests the Arbitration Logic sub-block to arbitrate the next DRAM access. The Command Multiplexor passes dcu_dau_adv as the re_arbitrate signal to the Arbitration Logic sub-block.
    • If the RotationSync bit has been cleared, then the arbitration logic grants exclusive access to the CPU and scheduled refreshes. If the bit has been set, regular arbitration occurs. A detailed description of RotationSync is given in section 20.14.12.2.1 on page 295.
    • Until the Arbitration Logic has a valid result it stalls the DCU by asserting dau_dcu_msn2stall. The Arbitration Logic then returns the selected arbitration winner to the Command Multiplexor which issues the command to the DRAM. The Arbitration Logic could stall for example if it selected a shared read bus access but the Read Multiplexor indicated it was busy by de-asserting read_cmd_rdy[1].
    • In the case of a read command the read data from the DRAM is multiplexed back to the read requestor by the Read Multiplexor. In the case of a write operation the Write Multiplexor multiplexes the write data from the selected DIU write requester to the DCU before the write command can occur. If the write data is not available then the Command Multiplexor will keep dau_dcu_valid de-asserted. This will stall the DCU until the write command is ready to be issued.
    • Arbitration for non-CPU writes occurs in advance. The DCU provides a signal dcu_dau_wadv which the Command Multiplexor issues to the Arbitrate Logic as re_arbitrate_wadv. If arbitration is blocked by the Write Multiplexor being busy, as indicated by write_cmd_rdy[1] being de-asserted, then the Arbitration Logic will stall the DCU by asserting dau_dcu_msn2stall until the Write Multiplexor is ready.
      20.14.10.1 Read Accesses

The timing of a non-CPU DIU read access are shown in FIG. 109. Note re_arbitrate is asserted in the MSN2 state of the previous access.

Note the fixed timing relationship between the read acknowledgment and the first rvalid for all non-CPU reads. This means that the second and any later reads in a back-to-back non-CPU sequence have their acknowledgments asserted one cycle later, i.e. in the “MSN1” DCU state. The timing of a CPU DIU read access is shown in FIG. 110. Note re_arbitrate is asserted in the MSN2 state of the previous access.

Some points can be noted from FIG. 109 and FIG. 110.

DIU requests:

    • For non-CPU accesses the <unit>_diu_rreq signals are registered before the arbitration can occur.
    • For CPU accesses the cpu_diu_rreq signal is not registered to reduce CPU DIU access latency.

Arbitration occurs when the dcu_dau_adv signal from the DCU is asserted. The DRAM address for the arbitration winner is available in the next cycle, the RST state of the DCU.

The DRAM access starts in the MSN1 state of the DCU and completes in the RST state of the DCU.

Read data is available:

    • In the MSN2 cycle where it is output unregistered to the CPU
    • In the MSN2 cycle and registered in the DAU before being output in the next cycle to all other read requesters in order to ease timing.

The DIU protocol is in fact:

    • Pipelined i.e. the following transaction is initiated while the previous transfer is in progress.
    • Split transaction i.e. the transaction is split into independent address and data transfers.

Some general points should be noted in the case of CPU accesses:

    • Since the CPU request is not registered in the DIU before arbitration, then the CPU must generate the request, route it to the DAU and complete arbitration all in 1 cycle. To facilitate this CPU access is arbitrated late in the arbitration cycle (see Section 20.14.12.2).
    • Since the CPU read data is not registered in the DAU and CPU read data is available 8 ns after the start of the access then 4.5 ns are available for routing and any shallow logic before the CPU read data is captured by the CPU (see Section 20.14.4).

The phases of CPU DIU read access are shown in FIG. 111. This matches the timing shown in Table 135.

20.14.10.2 Write Accesses

CPU writes are posted into a 1-deep write buffer in the DIU and written to DRAM as shown below in FIG. 112.

The sequence of events is as follows:—

    • [1] The DIU signals that its buffer for CPU posted writes is empty (and has been for some time in the case shown).
    • [2] The CPU asserts “cpu_diu_wdatavalid” to enable a write to the DIU buffer and presents valid address, data and write mask. The CPU considers the write posted and thus complete in the cycle following [2] in the diagram below.
    • [3] The DIU stores the address/data/mask in its buffer and indicates to the arbitration logic that a posted write wishes to participate in any upcoming arbitration.
    • [4] Provided the CPU still has a pre-access entitlement left, or is next in line for a round-robin award, a slot is arbitrated in favour of the posted write. Note that posted CPU writes have higher arbitration priority than simultaneous CPU reads.
    • [5] The DRAM write occurs.
    • [6] The earliest that “diu_cpu_write_rdy” can be re-asserted in the “MSN1” state of the DRAM write. In the same cycle, having seen the re-assertion, the CPU can asynchronously turn around “cpu_diu_wdatavalid” and enable a subsequent posted write, should it wish to do so. The timing of a non-CPU/non-CDU DIU write access is shown below in FIG. 113.

Compared to a read access, write data is only available from the requester 4 cycles after the address. An extra cycle is used to ensure that data is first registered in the DAU, before being despatched to DRAM. As a result, writes are pre-arbitrated 5 cycles in advance of the main arbitration decision to actually write the data to memory.

The diagram above shows the following sequence of events:—

    • [1] A non-CPU block signals a write request.
    • [2] A registered version of this is available to the DAU arbitration logic.
    • [3] Write pre-arbitration occurs in favour of the requester.
    • [4] A write acknowledgment is returned by the DIU.
    • [5] The pre-arbitration will only be upheld if the requester supplies 4 consecutive write data quarter-words, qualified by an asserted wvalid flag.
    • [6] Provided this has happened, the main arbitration logic is in a position at [6] to reconfirm the pre-arbitration decision. Note however that such reconfirmation may have to wait a further one or two DRAM accesses, if the write is pre-empted by a CPU pre-access and/or a scheduled refresh.
    • [7] This is the earliest that the write to DRAM can occur.
    • Note that neither the arbitration at [8] nor the pre-arbitration at [9] can award its respective slot to a non-CPU write, due to the ban on back-to-back accesses.

The timing of a CDU DIU write access is shown overleaf in FIG. 114.

This is simular to a regular non-CPU write access, but uses page mode to carry out 4 consecutive DRAM writes to contiguous addresses. As a consequence, subsequent accesses are delayed by 6 cycles, as shown in the diagram. Note that a new write can be pre-arbitrated at [10] in FIG. 114.

20.14.11 Command Multiplexor Sub-Block

TABLE 136
Command Multiplexor Sub-block IO Definition
Port namePinsI/ODescription
Clocks and Resets
pclk1InSystem Colck
prst_n1InSystem reset, synchronous active low
DIU Read Interface to SoPEC Units
<unit>_diu_radr[21:5]17InRead address to DIU
17 bits wide (256-bit aligned word).
diu_<unit>_rack1OutAcknowledge from DIU that read request has been
accepted and new read address can be placed on
<unit>_diu_radr
DIU Write Interface to SoPEC Units
<unit>_diu_wadr[21:5]17InWrite address to DIU except CPU, SCB, CDU
17 bits wide (256-bit aligned word)
cpu_diu_wadr[21:4]]22InCPU Write address to DIU
(128-bit aligned address.)
cpu_diu_wmask16InByte enables for CPU write.
cdu_diu_wadr[21:3]19InCDU Write address to DIU
19 bits wide (64-bit aligned word)
Addresses cannot cross a 256-bit word DRAM boundary.
diu_<unit>_wack1OutAcknowledge from DIU that write request has been
accepted and new write address can be placed on
<unit>_diu_wadr
Outputs to CPU Interface and Arbitration Logic sub-block
re_arbitrate1OutSignalling telling the arbitration logic to choose the next
arbitration winner.
re_arbitrate_wadv1OutSignal telling the arbitration logic to choose the next
arbitration winner for non-CPU writes 2 timeslots in
advance
Debug Outputs to CPU Configuration and Arbitration Logic Sub-block
write_sel5OutSignal indicating the SoPEC Unit for which the current