Title:
Foldover packages and manufacturing and test methods therefor
Kind Code:
A1


Abstract:
A microelectronic fold package is formed from an in-process unit including an internal unit such as a chip and a tape defining a bottom run extending beneath the internal unit, a top run extending above the internal unit and a fold connecting said top and bottom runs. The in-process unit is engaged between a pair of elements having flat surfaces so that these elements form the top and bottom runs to a substantially flat condition at least in regions between the internal unit and the fold and so that the engagement elements form the fold to a height equal to the height of the internal unit.



Inventors:
Thompson, Jesse Burl (Brentwood, CA, US)
Alfonso, Jennifer Fosberry (Santa Clara, CA, US)
Urbish, Glenn (Coral Springs, FL, US)
Osborn, Philip R. (Mountain View, CA, US)
Chau, Ellis (San Jose, CA, US)
Application Number:
10/969527
Publication Date:
07/14/2005
Filing Date:
10/20/2004
Assignee:
Tessera, Inc. (San Jose, CA, US)
Primary Class:
Other Classes:
257/E23.065, 257/E25.023, 206/832
International Classes:
B65D85/30; H01L23/498; H01L25/10; (IPC1-7): B65D85/30
View Patent Images:
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Primary Examiner:
ARBES, CARL J
Attorney, Agent or Firm:
LERNER DAVID, LITENBERG, KRUMHOLZ & MENTLIK (600 SOUTH AVENUE WEST, WESTFIELD, NJ, 07090, US)
Claims:
1. A method of making a fold package comprising the steps of: (a) providing an in-process unit including one or more internal elements defining a internal unit and a carrier including a tape having a dielectric layer, said tape defining a bottom run extending beneath the internal unit, a top run extending above the internal unit and a fold connecting said top and bottom runs; and (b) engaging the in-process unit between a pair of engagement elements having flat surfaces so that said engagement elements form said top and bottom runs to a substantially flat condition at least in regions between said internal unit and said fold and so that said engagement elements form said fold to a height equal to the height of said internal unit.

2. A method as claimed in claim 1 further comprising the step of leaving said fold unconstrained with respect to horizontal movement towards or away from said internal unit during said engaging step.

3. A method as claimed in claim 1 wherein said internal unit includes at least one adhesive layer in contact with at least one of said runs, the method further comprising the step of curing said at least one adhesive layer during said engaging step.

4. A method as claimed in claim 3 wherein said internal unit includes at least one microelectronic element and a said at least one adhesive layer includes a top adhesive layer disposed between a surface of said microelectronic element and said top run, said step of curing said at least one adhesive layer including the step of curing said top adhesive layer.

5. A method as claimed in claim 1 wherein said step of providing said in-process unit includes mounting said microelectronic element above a first mounting portion of said tape so that a fold portion and a second mounting portion of said tape project in a lengthwise direction beyond a first edge of said microelectronic element and then bending fold portion so that said second mounting portion of said tape overlies said microelectronic element and forms at least a part of said top run.

6. A method as claimed in claim 5, said step of providing said in-process unit further comprising the step of temporarily attaching said top run to said microelectronic element so that said temporary attachment holds said top run in place between said bending step and said engagement step.

7. A method as claimed in claim 6 wherein said step of providing said in process unit includes the step of providing a tacky top adhesive layer disposed between said microelectronic element and said top run before completion of said bending step, said step of temporarily attaching including tacking said top run to said microelectronic element using said top adhesive layer.

8. A method as claimed in claim 7 further comprising curing said top adhesive layer during said engaging step.

9. A method as claimed in claim 5 wherein said tape includes a first set of electrically conductive elements on said first mounting portion and a second set of electrically conductive elements on said second mounting portion, said bending step being performed so as to place said second set of electrically conductive elements in a preselected spatial relation with said first set of conductive elements.

10. A method as claimed in claim 9 wherein said tape includes a first set of registration features on said first mounting portion and a second set of registration features on said second mounting portion, said bending step including controlling the positions of said mounting portions using said registration features.

11. A method as claimed in claim 10 wherein said registration features include holes extending through tape, said controlling step including engaging said holes on one or pins.

12. A method as claimed in claim 1 wherein said tape includes electrically conductive traces extending between said top and bottom runs by way of said fold.

13. A method as claimed in claim 1 wherein the entirety of said top run and the entirety of said bottom run are engaged with said flat surfaces during said engagement step.

14. A group comprising a plurality of fold packages, each said package having: (a) a internal unit including one or more internal elements, said internal elements including at least one microelectronic element; (b) a tape having a bottom run extending beneath said internal unit, a top run extending above said internal unit and a fold interconnecting said top and bottom runs, said fold being offset from said internal unit by an offset distance in a horizontal direction, said tape having a first set of electrically conductive elements on said bottom run, a second set of electrically conductive elements on said top run and electrically conductive traces extending between said top and bottom runs by way of said fold; and the microelectronic element, first set of conductive elements and second set of conductive elements in each one of said fold packages being identical in function to the corresponding elements in other ones of said fold packages, the internal units in different ones of said fold packages having different heights, the offset distances in different ones of said fold packages differing from one another such that fold packages having greater internal unit heights have lesser offset distances.

15. A group as claimed in claim 14 wherein, in each said fold package, the top and bottom runs are substantially flat and parallel to one another.

16. A group as claimed in claim 14 wherein, in each said fold package, the tape has an inner surface facing inwardly toward the internal unit in and an outer surface facing away from the internal unit, and the first and second sets of conductive elements include first and second sets of terminals exposed at the outer surface of the tape.

17. An assembly including a group of fold packages as claimed in claim 16, wherein said fold packages are mechanically and electrically connected to one another.

18. An assembly as claimed in claim 17 wherein said fold packages are stacked one atop the other whereby said stacked fold packages define interfaces between adjacent ones of said fold packages, the top run of one said fold packages confronting the bottom run of another one of said fold packages at each said interface, the terminals on said confronting runs being connected to one another.

19. An assembly as claimed in claim 16 wherein, in each said fold package, the first and second sets of terminals are disposed in substantially identical arrays aligned with one another.

20. A method of testing a fold package including a tape and an internal unit, a tape having a bottom run disposed below said internal unit, a top run disposed above said internal unit and a fold interconnecting said top and bottom runs offset from said internal unit in a horizontal direction, the method including the step of advancing a test fixture toward the package so that the fixture engages the fold and displaces the fold toward said internal unit.

21. A method as claimed in claim 20 wherein the test fixture has an elongated edge and said advancing step is performed so that said edge extends in a vertical direction and so that said edge engages the fold.

22. A method as claimed in claim 20 wherein said advancing step is performed so as to apply a predetermined force to the fold.

23. A method as claimed in claim 20 wherein said advancing step is performed so as to apply a predetermined displacement to the fold.

Description:

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of the filing date of U.S. Provisional Patent Application 60/515,313, filed Oct. 29, 2004, the disclosure of which is hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to microelectronic packaging and more particularly relates to fold packages for microelectronic elements, methods of making such packages and methods of testing the same.

Microelectronic elements such as semiconductor chips commonly are provided in packages which protect the chip or other element from physical damage, and which facilitate mounting of the chip on a circuit panel or other element. One type of microelectronic package includes a substrate, also referred to as a “tape” incorporating a dielectric layer such as a layer of a polyimide, BT resin or other polymeric material with electrically conductive features such as terminals on the dielectric element. The chip is mounted on the substrate so that a face of the chip confronts the substrate, typically with a layer of a die attach adhesive between the chip and the substrate. The terminals are exposed at an outer surface of the substrate, but are electrically connected to contacts on the die itself. A protective material commonly referred to as an overmolding may surround the die itself, but desirably does not cover the terminals. Such a package can be mounted on a circuit board with the outer surface of the substrate facing toward the circuit board, and with the terminals aligned with contact pads on the circuit board. Conductive bonding materials such as solder balls can be used to bond the terminals to the contact pads, so as to physically mount the package in place on the board and connect the terminals to the circuitry of the board, thereby connecting the die to the circuitry. When the package is mounted to the circuit board, the substrate lies beneath the die, between the die and the circuit board.

As disclosed, for example, in co-pending, commonly assigned U.S. patent application Ser. Nos. 10/077,388; 10/281,550; 10/654,375; 60/408,644 and 60/443,438, the disclosures of which are hereby incorporated by reference herein, and in commonly assigned PCT International Application PCT/US03/25256, the disclosure of which is also incorporated by reference herein, a package referred to herein as a “fold” package incorporates a generally similar substrate or tape. However, the substrate or tape in a fold package is folded around the die so as to define a pair of opposed runs extending in generally parallel planes. One such run extends below the die, in the position occupied by the substrate of the conventional package, whereas the other run extends above the die, with the die disposed between the runs. The bottom run typically bears terminals used to mount the package to a circuit panel or other larger substrate. In some variants of the fold package, electrically conductive components on the top run include terminals exposed at the outer surface (the surface facing upwardly away from the die and away from the bottom run), so that other packaged or unpackaged microelectronic elements can be mounted on the top run of the fold package. Fold packages of this type can be stacked, one on top of the other. The features on the top run are interconnected with the terminals or other electrically-conductive features on the bottom run by traces extending along the dielectric element. These traces extend around the fold formed in the dielectric element.

In a further variant, two or more microelectronic elements such as two or more semiconductor chips are mounted in the space between the top and bottom runs.

Still other fold packages combine these approaches, so that two or more microelectronic elements are disposed in the space between the top and bottom runs of the package, and the package has exposed terminals on both the top run and the bottom run, and hence can be stacked or otherwise combined with additional packages of the same or different types and/or with additional microelectronic elements.

Fold packages provide certain significant advantages. The traces which extend between the top and bottom runs can be formed in the normal tape-fabrication process at little additional cost, so as to provide low-cost, reliable interconnections between the two runs.

However, fabrication of foldover packages presents certain additional challenges, particularly under mass-production conditions. The folding process should be controlled so as to provide a repeatable, controlled alignment between electrically conductive features on the top run of a package and features on the bottom run of the same package, and should make the top and bottom runs parallel to one another. Also, the folding process should be relatively simple.

Moreover, the package must have high reliability. In particular, the traces on the tape must remain continuous after folding and after exposure to repeated stresses in service and/or in assembly processes using the package, such as reflow soldering of the package to the circuit board and reflow soldering of other elements to the package. As described, for example, in the aforementioned Ser. No. 10/654,375 application, it has been proposed to fold the tape using a fixture such as a die having a preselected radius so as to form folds of a constant, predetermined shape and size. This makes a fold with a predetermined height. Where the fold is precisely semicircular, the height of the fold (the distance between the top and bottom runs at the fold) is equal to twice the radius of the fold.

However, the collection of elements mounted between the runs, referred to herein as the “internal unit,” tends to vary in height. For example, the internal unit typically includes a layer of a die attach adhesive between a die and the bottom run and a layer of encapsulant or adhesive covering a die surface facing the top run. In other variants, the internal unit may include two or more dies with two or more layers of adhesive or encapsulant. Factors such as differences in the thickness of the dies and differences in the thickness of the layers of encapsulant can cause variations in the height of the internal unit. Where the fold is formed by a process which bends the tape using a die or other tool to provide a predetermined bend radius, variations in internal unit height can cause a mismatch between the internal unit height and the bend radius.

SUMMARY OF THE INVENTION

One aspect of the present invention incorporates the realization that such a mismatch can reduce the reliability of the package. Although the present invention is not limited by any theory of operation, it is believed that when a tape is formed to a controlled bend radius and hence to a controlled height and the internal unit height is greater than the height of the fold, small, localized bends will be formed at the edges of the internal unit, typically in close proximity to relatively sharp edges on the die or dies. It is believed that such bends and the proximity of the die edges to these bends contribute to premature failure of the traces under conditions involving thermal cycling. If the internal unit height is substantially less than the fold height, it is believed that there will also be small, localized bends in each of the top and bottom runs adjacent the edges of the internal unit. Localized bends of this type are believed to cause high stress levels in the adhesive which bonds the runs of the tape to the internal unit. This, in turn, can lead to premature failure of the bond between the adhesive and the tape runs, or in the bond between the adhesive and the die. Also, where the internal unit height does not match the fold height, the top and bottom runs tend to be non-planar, so that they bulge or droop in the regions between the internal unit and the fold.

One aspect of the present invention provides a manufacturing process which meets the needs for a controlled configuration and controlled alignment between the runs, but which avoids these difficulties. A related aspect of the invention provides assemblages of plural fold packages.

Moreover, it would be desirable to provide a simple method for testing the adhesion between the folded tape and the internal unit. Yet another aspect of the invention provides such a test.

These and other features and advantages of the present invention will be more readily apparent from the detailed description set forth below, taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic plan view of a tape used in a process according to one embodiment of the invention.

FIG. 2 is a diagrammatic sectional view of the tape of FIG. 1 in conjunction with a semiconductor chip.

FIG. 3 is a diagrammatic sectional view of the tape and chip of FIG. 2 during one stage of a process according to an embodiment of the invention.

FIG. 4 is a view similar to FIG. 3 but depicting the tape and chip in a later stage of the process.

FIG. 5 is a diagrammatic elevational view depicting an assembly including a group of packages made according to the process of FIGS. 3 and 4.

FIG. 6 is a diagrammatic elevational view of a package and testing tool during a test method according to a further embodiment of the invention.

FIG. 7 is a diagrammatic plan view of the package and tool shown in FIG. 6.

FIG. 8 is a diagrammatic elevational view of a package according to a further embodiment of the invention.

DETAILED DESCRIPTION

A process in accordance with one embodiment of the invention utilizes a tape 10 having a first mounting region 12, a second mounting region 14 and a fold region 16 disposed between these end regions. The term “lengthwise direction” is used herein as referring to the direction along the tape between mounting regions 12 and 14, i.e., the direction L from one mounting region to the other across fold region 16. The “widthwise direction” as referred to herein is the direction transverse to the lengthwise direction. Although the terms lengthwise and widthwise are used herein as referring to these directions, this does not imply that the dimension of the tape in the lengthwise direction L must be greater than the dimension of the tape in the widthwise direction.

The tape includes a dielectric layer having an inner side 18, visible in FIG. 1, and an opposite, outer side 20 (FIG. 2). The dielectric layer may be formed from any material suitable for forming a circuit panel and suitable for bending in the manner discussed below as, for example, from the material commonly used in forming flexible circuit panels such as polyimide or BT resin. Most typically, the dielectric layer is on the order of 15-100 microns thick. A first set of electrically conductive features 22 is provided in the first mounting region 12 of the tape, whereas a second set of electrically conductive features 24 is provided in the second mounting region 14. In the particular embodiment depicted, the conductive features of the first and second sets are terminals disposed in identical arrays, but this is not essential; the conductive features in the first and second sets may be different from one another, and may include features other than terminals. Merely by way of example, the conductive features in one or both sets may include, or may consist entirely of, features such as bonding pads or lead portions adapted to make electrical connection with a chip or other microelectronic element to be incorporated in the completed package. The electrically conductive features of the two sets are interconnected to one another by traces 26 extending across the fold region 16.

As used in this disclosure, when a conductive feature or tape is said to be “on” a dielectric element, the conductive element need not be disposed on a surface of the dielectric, but instead, may be disposed within the dielectric. That is, the word “on” does not imply location at a surface of a dielectric. The particular embodiment of the tape depicted in FIGS. 1 and 2 is a “circuits-in” tape, having conductive features 22 and 24 and traces 26 disposed on the inner surface 18 of the dielectric layer. However, the circuits in arrangement shown in FIGS. 1 and 2 are depicted for purposes of illustration. A “circuits-out” arrangement, in which the conductive features and traces are disposed on the outer side of the dielectric layer, may be employed. Also, the conductive features and traces may be disposed within the dielectric layer. That is, the dielectric layer itself may be formed from two or more sublayers, some or all of the electrically conductive elements disposed between the sublayers and exposed at the surfaces as needed through holes in one or more of the sublayers. Also, the tape may include additional layers such as a solder mask layer or coating overlying parts or all of the conductive features and traces, as well as adhesive layers (not shown) to provide a physical interconnection between the conductive features and the dielectric layer.

The terminals in set 22 are exposed at the outer surface 20 of the dielectric layer through holes 28 aligned with the terminals, and the terminals of set 24 are exposed at surface 20 through similar holes 30. As used in this disclosure, a terminal or other conductive feature is regarded as “exposed at” a surface of a dielectric element where the terminal is arranged so that all or part of the conductive feature can be seen by looking at such surface. Thus, a conductive feature which is exposed at a surface of a dielectric element may project from such surface; may be flush with such surface; or may be recessed from such surface and exposed through an opening extending entirely or partially through the dielectric element.

The tape may be fabricated in a conventional manner using procedures commonly employed for making flexible circuit panels as, for example, by providing a lamination including a sheet of metal and the dielectric layer and selectively etching the metal sheet so as to leave the traces and other conductive features, or by an additive process in which some or all of the traces or conductive features are formed by electroplating or other deposition processes. The traces and conductive features may be formed from one or more metals, as, for example, copper or copper alloys and gold. Most typically, the metallic traces and features are about 5-25 microns thick, although any thickness compatible with the bending procedures discussed below may be used.

Tape 10 has registration features 32 in the first mounting region 12. These registration features lie in a predetermined spatial relationship to the conductive features 22 of the first set. That is, the locations of the conductive features 22 in the lengthwise and widthwise directions along the tape are fixed during the manufacturing process and controlled to within a reasonable tolerance. A second set of registration features 34 is provided in the second end region 14, these features being in a predetermined spatial relationship with the conductive features 24 of the second set. In the particular embodiment illustrated, registration features 32 and 24 are rows of sprocket holes 32 and 34. Where tape 10 is formed as part of a larger tape, the sprocket holes may be used to feed such larger tape or sheet through the various steps of the fabrication process. For example, the larger tape may have numerous sections, each corresponding to one tape 10, these regions being disposed side-by-side with one another, so that the widthwise directions W of adjacent sections extend along the length of the larger tape and hence the rows of sprocket holes 32 and 34 also extend along the length of the larger tape.

In a manufacturing process according to one embodiment of the invention, a set of interior elements is mounted to the inner side of the tape. The interior elements in this embodiment include a semiconductor chip 36. Chip 36 overlies first mounting region 12 and is electrically connected to the conductive features 22 of the first set, and hence to traces 26, in any suitable manner. Merely for purposes of illustration, the chip is depicted as directly connected to the terminals in set 22 by bonding the contacts 40 of the chip directly to the terminals. However, any suitable way of electrically connecting the chip to the electrically conductive features and/or to the traces may be employed. The chip can be connected to the traces or to other electrically conductive features by leads formed integrally with the traces or other features; by wire bonds; by solder bonds; by a layer of an anisotropic conductive adhesive; or in any other suitable manner.

Chip 36 is a solid body having a front or contact-bearing face 42 having contacts 40 thereon; a rear face 44 opposite to the front face; and edges extending between these faces. The chip may include an overmold compound (not shown) covering the actual semiconductor element at the rear face and edges. The chip is mounted on the tape so that a first edge 46 of the chip extends in the widthwise direction W (FIG. 1) of the tape, i.e., into and out of the plane of the drawing, as seen in FIG. 2. The fold region 16 and the second mounting region 14 of the tape project beyond first edge 46 of the chip.

The internal elements also include a layer of adhesive 48 disposed between chip 36 and the tape, as well as another layer of adhesive 50 disposed in the second region of the tape. As discussed below, adhesive layer 50 ultimately will be engaged with the rear surface 44 of chip 36. In an alternate arrangement, adhesive layer 50 may be applied on the rear surface 44 of the chip.

In the next stage of the process, the tape is folded generally around a widthwise folding axis 52 overlying the fold region 16 of the tape, so as to form fold region 16 into a bend or bight 16′ extending around this axis, and so as to provide a first or bottom run 12′ incorporating the first mounting region of the tape and a second or top run 14′ incorporating the second mounting region. As used in this disclosure, directional terms such as “vertical,” “horizontal,” “up” and “down” should be understood as referring to the frame of reference of the elements constituting the package, rather than to the normal gravitational frame of reference.

During this step, the two runs are brought into a predetermined alignment with one another in the horizontal directions (the directions to the left and right, and into and out of the plane of the drawing in FIG. 3) by aligning the registration features 32 and 34 with one another as, for example, by aligning these features using one or more pins 56 extending through one or more of the registration features in each set. This serves to align the electrically conductive features 24 of the second set in a predetermined position, in the horizontal directions, relative to the conductive features 22 of the first set. At this stage of the process, the second run 14′ is at least partially adhered to the chip 36 by adhesive layer 50, so that the two runs are at least temporarily held in position relative to one another by the stacked internal elements. Most preferably, adhesive layer 50 has “tack” properties. That is, the adhesive layer at this stage typically is not fully cured. However, even in a partially cured or uncured condition, the adhesive layer has sufficient adhesion to hold the tape in the folded condition temporarily. Also, at this stage, the internal unit, including adhesive layers 48 and chip 36, lies between the two runs, with an edge 46 of the internal unit, defined by the edge of the chip facing toward the fold or bight 16′.

In the next stage of the process (FIG. 4), the assembly is squeezed between a pair of forming elements or plates 58 and 60 having flat engage surfaces which abut the upper run 14′ and lower run 12′. The engaging surfaces are advanced with sufficient pressure to flatten the upper and lower runs. The pressure exerted by the engaging elements may deform the adhesive layers 48 and 50 slightly, depending upon the state of cure of the adhesives and the properties of the particular adhesives, and hence may squeeze the upper and lower runs slightly towards one another. However, a principal effect of the engagement elements is to flatten the upper and lower runs. In particular, those portions of the upper and lower runs extending in the vicinity of edge 46, and those portions extending beyond such edge in the horizontal direction towards fold 16′ (to the right, as seen in FIG. 4) and the immediately adjacent portions of the upper and lower runs, just to the left of edge 46, are brought to a substantially flat condition. While the unit is engaged between element 58 and 60, the adhesive in layers 48 and 50 is cured. Depending upon the composition of the adhesive, it may be desirable to apply heat during the curing process as, for example, by applying heat through the engagement elements 58 and 60 or by conducting this step in a heated chamber.

During the flattening and curing process, the fold or bight 16′ is not constrained. In effect, the fold “finds” its appropriate bend configuration and bend radius compatible with the flattened runs. Variations in the chip 36; in the adhesive layers 48 and 50; and, in some cases, variations in the height of the bonds connecting the chip contacts with the conductive elements, will cause some variation in the height Hs of the internal unit in the as-cured condition. These variations in the height of the internal unit will not affect the flatness of the runs. Instead, these variations in internal unit height will be reflected as variations in the distance DF between the edge of the internal unit and the fold. Stated another way, the radius of fold 16′ will vary depending upon the internal unit height HS. Because only a fixed amount of material is available to form the fold and to form those portions of the runs extending between the edge of the internal unit and the fold, such variations will be reflected as changes in DF. Thus, as the internal unit height increases, DF will decrease and vice versa.

The process produces fold packages with substantially flat runs at least in the vicinity of the first edge and the fold, and substantially free of localized deformations at the edge of the internal unit. Although the present invention is not limited by any theory of operation, it is believed that the enhanced flatness in the areas adjacent the edge of the internal unit, and the absence of localized deformations in this area, tends to increase reliability. In particular, units formed in the manner tend to resist breakage or peeling of the adhesive bonds 48 and 50 and also tend to resist breakage of the traces at the edge of the internal unit. Although the process according to this aspect of the present invention improves the reliability of the adhesive bonds, other factors which contribute to making a reliable adhesive bond should not be neglected. For example, as in any adhesive bonding process, the elements to be joined should be cleaned thoroughly. For example, where the chip has an overmold layer, such layer may be contaminated by mold release compounds used in the molding process used to form such a layer. A plasma cleaning process using, for example, repeated or prolonged exposure to an argon and oxygen plasma converts such contaminants to ash, which can then be removed by washing with liquids such as methyl ethyl ketone and water under ultrasonic agitation. Also, the adhesives should be selected to provide good bond strength. Suitable adhesives include those sold under the designation HS 232 by the Hitachi Chemical Company. Other suitable adhesives include those sold under the designations Dexter QMI 536 and Ablestick. The time and temperature conditions used in the tacking step and during final cure will depend on the adhesive used; the HS 232 material develops some surface tack when the tape is pressed against the adhesive at room temperature under a pressure of 200 pounds per square inch (psi) for 30 seconds. A stronger tack is developed at 93° C. using the same temperature and time. Final cure can be achieved in 15-60 minutes at 200 psi and a curing temperature of about 175° C.

Moreover, the flat configuration of the runs facilitates handling of the packages in production operation and, particularly, stacking of the packages on one another so as to form a larger assembly. This effect is illustrated schematically in FIG. 5, showing an assembly including a group of three packages 102, 104 and 106 having different internal unit heights HS and, hence, different fold projection distances DE. As used in this disclosure, reference to a “group” of plural packages should be understood as referring to a collection of packages without regard to whether the packages are physically or electrically connected to one another, whereas references to an “assembly” of plural packages should be understood as referring to a structure including plural packages which are physically or electrically connected to one another. In each of packages 102, 104 and 106, the upper and lower runs remain flat and parallel to one another, without localized deformation. Also, in each of these packages, the conductive elements on the two runs of the package are in the same predetermined alignment with one another. Therefore, these packages can be stacked and assembled with one another as, for example, using conductive bonding materials such as solder balls 108 and 110 to connect mutually facing runs of adjacent packages to one another. Such an assembly of stacked packages can be attached to a circuit board using further solder balls 112 to connect the conductive elements on the bottom run of lower-most package 106 to a circuit panel 114. A larger group of packages may be provided as an article of commerce with the packages constituting the group being provided in a box or other container. Such a group of packages may be used as an input to an assembly process in which sets of packages are assembled to form assemblies of plural packages, or an assembly process in which individual packages are assembled to circuit boards. Here again, the configuration of the packages with flat upper and lower runs, and with good, repeatable alignment between the conductive features on the upper and lower runs of each package, facilitates the assembly process.

A further aspect of the present invention provides methods of testing the adhesive bonds and other features in a fold package. In FIGS. 6 and 7, the package being tested is a fold package 202 having an internal unit 236 and a tape defining a bottom run 212, top run 214 and fold 216. Here again, the runs are adhesively bonded to the chip included in the internal unit. The fold 216 extends around a horizontal fold axis 252 extending in the widthwise direction of the tape, parallel to an edge 246 of the internal unit. A test fixture 280 in the form of a blade defining an edge 284 is positioned relative to the package, so that the edge 284 extends vertically, transverse to the fold axis. While maintaining the fixture in this orientation, the fixture is advanced with a predetermined force toward the package, so that the edge engages the outer surface of the fold and crushes the fold inwardly, in the horizontal direction toward internal unit 236 (to the left as seen in FIGS. 6 and 7). In this embodiment, the edge 284 of the fixture engages the fold at only one location along the widthwise extent of the tape, i.e., at one location along fold axis 252. Most preferably, this location is near the edge of the tape, i.e., adjacent a corner 286 of the package defined by the fold. The edge crushes the fold towards the internal unit, so that those portions of the top and bottom runs 214 and 212 extending between the internal unit and the fold are bent outwardly, as seen in broken lines in FIG. 6 at 214′ and 212′, at least in the vicinity of the fixture. This places a significant peeling stress on the adhesive bonds between the runs and the chip. After engaging the fold with the test fixture, the fixture is removed and the adhesive bonds are inspected as, for example, by microscopic examination. If no separation of the adhesive bonds is detected, this indicates that the bonds have sufficient strength. Separation of the adhesive bonds indicates a failure. Provided that the applied force and the dimensions and orientation of the fixture are well-controlled, this test provides a repeatable measure of bond strength which can be applied easily and quickly in a mass-production environment.

The particular fixture shown in FIGS. 6 and 7 has a rounded edge 284. However, the edge may be flat or sharp, provided the same configuration is used in all repetitions. Also, the edge need not be defined by a blade; a vertically-extending wire or rod defines a similar edge. In a further variant, the text fixture may be a flat plate or other shape such that the test fixture engages the fold over most or all of the widthwise extent of the tape, i.e., at most or all locations along fold axis 252. In further variants of this test, the fixture may be advanced through a predetermined distance from the point where the fixture engages the fold, or to a predetermined distance from the edge 246 of the internal unit facing the fold.

The features described above have been illustrated with reference to fold packages incorporating only one fold. However, the present invention may be employed with packages having plural folds as, for example, a package 302 (FIG. 8) having a tape defining two folds 316 and 317 extending around opposite edges of the internal unit 336. Moreover, the internal unit in a fold package may include two or more chips or other elements stacked atop one another or disposed side-by-side. Also, the particular orientation of the chip shown in FIGS. 2-4, with the front or contact-bearing surface facing downwardly toward the bottom run, is not essential. Merely by way of example, the chip may have a contact-bearing surface facing upwardly, with the contacts connected to the bottom run by wire bonds which are covered by the overmolding, or may have an upwardly facing contact-bearing surface which is connected to traces on the top run. Also, the tape may include additional conductive features such as planar conductive elements to serve as ground or power distribution elements or as a shield to block electromagnetic radiation.

As these and other variations of the features discussed above may be employed, the foregoing description of the preferred embodiments should be taken by way of illustration rather than as limiting the present invention.