DESCRIPTION OF THE PREFERRED EMBODIMENT

[0034] FIG. 2 is a schematic block diagram of the preferred embodiment of an electronic still camera in accordance with the principals of the invention. Referring to FIG. 2 , an image optical pick-up element 1 , which for example could be a Charge Coupled Device (CCD) (or an Infrared (IR) or Ultraviolet (UV) sensor), converts a still image of an object into an electric signal when a picture “shoot” command is initiated by the operator via control panel 2 . When taking a picture, focusing and shutter speed are controlled by a lens system and shutter speed selection mechanism under control of the digital control unit 9 . The camera, like other still video cameras, employs an electronic shutter system that controls a charge storage time in a CCD array onto which an image of an object is focused through the lens system.

[0035] When the “shoot” control 6 is half depressed (see FIG. 6 ), a power supply voltage is supplied from the rechargeable batteries 4 to the electronic circuits and digital control unit 9 , control panel 2 , and the disk drive assembly 5 . The exposure control circuitry not shown generates appropriate horizontal and vertical transfer pulses as well as field shift pulses under control of the reference clock timing and control signals provided by the digital control unit 9 type for driving the CCD device and pre-processing circuitry. This design may be of any type well known in the art for example those cited in U.S. Pat. Nos. 4,131,919 and 4,456,931 and any similar designs well known in the prior art.

[0036] An alternate embodiment of the present invention that provides remote operation of the camera is shown in FIG. 6C . When remote “Shoot” control 30 is activated by any means for example manually, or by radiant, or electronic energy, a control signal is generated and routed through the external jack 31 , located on the external camera body. The external control 30 is electrically connected to the external jack 31 by a twisted-pair conductive cable assembly that is familiar to those skilled in the art. Upon receipt of the externally generated “shoot” command, the relay switch 32 is activated and provides internal switch closure. This closure of switch 32 then initiates the process previously described and provides the half V+ voltage previously described. The full V+ is provided via the fixed delay 33 , the value chosen to allow the diskette drive assembly 5 ( FIG. 2 ) and associated control circuitry to initialize prior to receiving image data.

[0037] When the “shoot” control is fully depressed in either embodiment, the shutter controller 15 ( FIG. 6 ) generates a shutter pulse that generates control signals for the A/D converters 8 allowing the image/picture data signal in the sample and hold circuitry of the pixel multiplexer 7 to be converted into a digital signal. Control and address instructions of the type well known in the art are generated from the digital control unit 9 to facilitate the storage of the digital image data within the pixel buffer 10 and frame buffer 11 . Upon completion of image conversion, the contents of the frame buffer are transferred to the compression processor 12 which for example may be of the many versions currently offered commercially such as C-Cube's (San Jose, Calif.) four chip Application Specific Integrated Circuit (ASIC) set. In the compression processor 12 , the Joint Photographic Experts Group (JPEG), a part of the International Standards Organization (ISO) which is a subset of the International Telegraph and Telephone Committee (CCITT), image compression algorithm fully described in Report # JTC1/SC2/WG8 dated 1985 is performed under control of the digital control unit 9 to compress the size of the image. A variable selectable compression ratio of up to 50:1 is performed on the digital image frame. Other compression ratios are operator selectable via the control panel 2 switches 14 A and 14 B ( FIG. 6 ). The compressed digital frame is then formatted into either an IBM PC/Clone (such as GIFF) or Apple Macintosh (such as PICT II) image file format depending on the setting selected by the operator for a user switch 17 ( FIG. 6 ) position on the control panel 2 . After formatting, the file is written into a temporary memory buffer within the disk input/output (I/O) interface circuit 13 which, under the command of the digital control unit 9 , controls the high density (1.4 Mbyte storage capacity) disk drive unit 5 . Following file transfer to the diskette e.g., the frame counter display 22 on the control panel 2 is updated by appropriate control signals and the camera is ready to undergo the same procedure for the next image. Power to the electronic circuits and disk drive system is terminated following release of the “shoot” control switch 6 .

[0038] In accordance with the preferred embodiment of this invention, it is permissible for the user to select various resolution quality image recording levels with the higher levels being at the expense of memory diskette storage capacity. The position of switches 14 A and 14 B for example could represent a unique digital mark or word that denotes the respective switch position and is sensed during initial power application and periodically during operation. FIG. 6A illustrates typical logic AND gate circuits 60 a and 60 b utilizable in conjunction with switches 14 A and 14 B or switch 17 to generate appropriate signals to designate respective switch positions and generate appropriate control signals from. The switch positioned in the High position for high resolution allows only four to five images to be stored, while Med. switch position for medium resolution allows approximately twenty five images to be stored, and Low for low resolution allows up to fifty images to be stored on a single diskette. Also, by selecting black and white mode instead of color via switch 14 B, the operator may select additional storage capacity since storage is increased by a factor greater than three (one element per pixel versus three for color). Various image resolution combinations are permissible because the operator can select a different resolution and mode setting for each image prior to image signal capture. This is accomplished by marking or “tagging” each image frame data information signal with the resolution and mode of each image as it is written onto the memory diskette in any suitable manner, for example as shown in FIG. 2A . With reference to FIG. 2 A, diskette 50 has tracks 51 a , 52 b , . . . 52 n . With reference to track 52 b there is shown a representative portion of segment 53 depicting a typical image file information format having digital bit 54 depicting color mode, and digital bits 55 representing compression resolution level markings or tags. With reference to color mode tag 54 it can be seen that if switch 14 B is in the color position tag 54 is recorded as a logical “one” or true-conversely if bit 54 is recorded as a logical “zero” it corresponds to the black and white position of switch 14 B. Similarly as shown switch 14 A would record in memory position 55 a binary “zero” for low resolution, a binary “one” for medium resolution and a binary “two” for high resolution selections by the operator. By incorporating this “tagging” approach, it is possible for the decompression algorithm, loaded into any PC prior to use or written onto the memory storage diskette along with the image data, to automatically determine the appropriate level of compression associated with image file and execute decompression efficiently.

[0039] Still another alternate embodiment in accordance with this invention incorporates an acoustic digitizer circuit which digitizes sound. There are several digitizers commercially available such as the Apple Computer Inc. Musical Instrument Data Interface (MIDI) adaptor. The output of this digitizer may be selectively connected to the CPU 20 ( FIG. 7 ) via an additional I/O interface similar to the auxiliary I/O interface 80 . The sound or audio associated with each image can be recorded, digitized, and stored on the diskette device on available tracks in an identical manner previously described ( FIG. 2A ). An image file in accordance with this embodiment would be appropriately marked or tagged with the corresponding digitized audio file 56 ( FIG. 2A ). Upon playback on a sound configured PC, both the image and the corresponding audio would then be viewed and heard simultaneously.

[0040] It should be noted that a major advantage a camera in accordance with the present invention has over conventional still video cameras is that a camera according to this invention is capable of storing multiple digital images in semiconductor memory temporarily at a rapid rate while, simultaneously, the image compression processor 12 , file formatter software algorithm, and disk I/O interface 13 that stores formatted files continue to function in concert together at a slower rate. This efficient design coupled with VLSI low power, high speed semiconductor memory devices ( 10 & 11 FIG. 5A and 24 FIG. 7 ) allows this operational capability.

[0041] Like most other still video and conventional film cameras, when the “shoot” control 6 ( FIG. 6 ) is fully depressed, a control signal is generated from the digital control unit 9 that generates a trigger signal on the control panel 2 to cause a flash unit 16 ( FIG. 6 ) to irradiate a flash of light onto the subject image.

[0042] During initial camera operation, the user first inserts a diskette such as a standard three and a half inch or similar storage medium. Various memory diskette sizes and formats are suitable for the invention. However, for the preferred embodiment either a double-density (800 Kbytes of storage) or a high-density (1.4 Mbytes of storage) diskette in a three and a half inch format which are readily available from various commercial sources such as Sony, Maxell, and Verbatim. The user must then select the desired PC format (IBM PC/Clone or Apple Macintosh, etc.) via switch 17 ( FIG. 6 ) on the control panel 2 . As shown in FIG. 3 ; after turning on the power switch or inserting a diskette 50 , the digital control unit 9 performs a self test of all internal circuitry, battery, disk drive unit, and control panel. Should any failures be detected, an appropriate error indicator is illuminated on the control panel. During the power-on sequence (see FIG. 3 and FIG. 12 ), the inserted diskette 50 is automatically checked for formatting consistencies in accordance with the format selected by the format switch 17 on the control panel 2 (IBM/Apple/etc.) and for available storage space by checking the boot block on the diskette, a technique that will be familiar to those skilled in the art. Should any inconsistencies be detected, an error indicator is illuminated on the control panel (ie, disk full, unformatted, etc.). The operator frame counter display 22 ( FIG. 6 ) is then updated to show the maximum number of pictures available based upon indicated operator selections (color/black and white), diskette type (double versus high density), and capacity (partially full versus empty diskette). During operation, the operator can selectively erase a frame and record over it if desired by selecting the erase mode of operation from the control panel and toggling the forward/reverse control.

[0043] The optics for the preferred embodiment of the invention is a commercially available one-half inch (½″) color CCD device having a pixel grid array of 780×488 as pictorially depicted in FIG. 4 . This results in 380,640 pixel elements which results in a commercially acceptable quality resolution image as will be understood by those skilled in the art. In a color imaging device (CCD array) photoelectric elements, such as photodiodes, are arranged in a two dimensional array with optical filters for R (red), G (green), and B (blue). Various arrangements of optical filters are well known and the arrangement of optical filters is not limited to a particular one with this invention. During operation each pixel stores a charge corresponding to the amount of incident light. The RGB components of each pixel's charge is sequentially read out via a horizontal/vertical addressing scheme that will be familiar to those skilled in the art.

[0044] As shown in FIG. 5A ; each charge, when addressed, is amplified and processed in a sample and hold (S/H) circuit 18 . The analog voltage in each S/H circuit is digitized by an associated analog to digital (A/D) converter 8 . The digital values are routed and collected in the pixel buffer 10 . Following completion of discrete pixel element conversion and subsequent formatting in the pixel buffer which is under Control Processor Unit (CPU) 20 software control, the output of the full pixel buffer is routed to the frame buffer 11 by digital control unit 9 . This process continues until a complete frame is collected within the frame buffer. The general digital logic and timing and control signals for this circuitry is shown in FIG. 5B . The timing is provided by a master clock that is an integral part of the CPU microprocessor. For example, the MOTOROLA 68040 microprocessor has a clock speed of approximately 40 Megahertz (MHZ) which results in a clock period of 25 nanoseconds (nsec.). This clock pulse is used by the function and address decoder 19 ( FIG. 6 ) to generate the address and control signals shown in FIG. 5B as would be understood by those skilled in the art. The circuit of the present invention may be designed by one skilled in the art to function with a variety of microprocessor architectures and is not limited to any one in particular. One can see from the timing chart that the S/H circuit is allowed (via the SE command) to charge to a voltage level indicative of the analog voltage impinging upon the pixel element (via the PS command). After a fixed time period, the A/D converters are enabled(via the CE command) to begin conversion of the analog voltage value on the S/H. Upon completion of conversion, a conversion completion signal (CC) is generated by the A/D and routed back to the S/H circuit (via the SC command which is generated by the function and address controller 19 ) to discharge the stored analog voltage in anticipation of the next pixel element conversion process. Next, the output of the A/D converter 8 is clocked into the pixel buffer 10 (via the PB command). When the pixel buffer 10 is full, the output is clocked out to the frame buffer 11 (via the FB command) and the pixel multiplexer address circuitry selects the next pixel for conversion. Reset signals (RST) are sent to all circuit elements to allow these devices to reset prior to receiving the next analog value.

[0045] Another novel concept of the present invention as illustrated in FIGS. 5A and 5B utilizes a technique of paralleling the S/H and A/D devices for each pixel element thus accelerating the image signal analog-to-digital conversion process. This is accomplished by eliminating the serial S/H and A/D path typical of prior art still video camera designs. In addition, high-speed, low-power devices available from Sony, Burr-Brown, Datel, Analog Devices, and others facilitate the increased conversion throughput of the S/H and A/D circuits with pixel conversion times of less than 150 nanoseconds (nsec.). For example, Sony's video A/D converter Device part number CXA1016P/K performs up to 50 million samples per second or 20 nsec. per conversion. This device, or similar, may be used in the preferred embodiment of the present invention. As explained previously, prior art still video camera designs multiplex each signal component into a common/singular A/D path to reduce the number of components and power consumption. However, in accordance with another aspect of the present invention components such as CMOS and ECL devices coupled with miniaturized packaging techniques such as surface mount devices (SMD) and ASIC technology make it feasible to incorporate these devices in a parallel design in order to realize a substantial increase in conversion speed with no appreciable increase in power consumption. Therefore, this design approach provides significant conversion throughput increases over previous designs.

[0046] The extremely high conversion speed in accordance with another concept of the present invention makes multiple high-speed camera operation possible in an alternate embodiment. For example, total conversion time required for the aforementioned CCD array utilizing the circuit of the present invention ( FIG. 5A ) requires approximately 380,640×150 nsec. or 38 milliseconds (msec.). Additional time (approximately 5 msec.) is required for timing and control signal latency. Thus, total conversion time for a complete image frame prior to compression processing and logging to the memory storage diskette 50 is less than fifty msec. This allows for approximately 20 images to be captured in a one second period. By adding additional RAM 11 A ( FIG. 13 ) or other forms of commercially available random access memory to the frame buffer 11 , image frames could be “pushed” onto a semiconductor memory stack for temporary storage allowing the compression processor and data interface circuitry to perform their respective functions at a slower rate. As shown in FIG. 13 , each unprocessed image frame would be recorded or “pulled” from the stack on a “First-In, First-Out” (FIFO) manner until all images in the stack queue were processed and written to the storage diskette via the disk I/O circuitry 13 .

[0047] As shown in FIG. 6 , control panel settings are monitored by the CPU 20 , a microprocessor, thus allowing the appropriate timing, control, and signal processing to be effected properly. The microprocessor 20 may be of the type 68040 manufactured by MOTOROLA, Intel's 80386 series, or equivalent microprocessors which specifications are commercially available and are incorporated herein by reference. The microprocessor utilization of this invention, which is in the digital control unit 9 , transmits commands and status to specific controls, functions, and displays in the control panel as well as receiving both circuit status/control data and operator commands through polling the operator switch settings 14 A, 14 B, and 17 via the bidirectional function and address decoder 19 . This approach allows the user to know immediately how much storage capacity remains in the image storage diskette 50 as well as the camera's overall operational and functional status through the use of status displays 21 , 22 , and 23 and ongoing software self-tests running in the background as depicted in FIG. 3 . An example of this would be a low battery situation. First, the digital control unit 9 would detect a failure in the self-test mode. Next, the self-test light emitting diode 21 ( FIG. 6 ) would be illuminated and an appropriate error display would be illuminated in the status display 22 thus providing the user with an exact indication of the error. Another example illustrating the operation of this embedded microprocessor type of control approach is the format switch 17 ( FIG. 6 ). The position of the format switch 17 is sensed upon power application. Following diskette insertion, the boot block on the diskette is compared with the format switch 17 setting (IBM/clone or Apple) and if the format does not match or if the disk 50 is unformatted, the disk format status light emitting diode 23 would be illuminated and an appropriate error display would be illuminated in the status display 22 thus prompting the user to take appropriate corrective measures.

[0048] An alternate embodiment of the present invention involves adding an auxiliary I/O interface circuit or port to the digital control unit 9 . As shown if FIG. 7 , the auxiliary I/O port 80 connects in a manner similar to the Disk I/O interface 13 . This additional I/O channel provides for external control and monitor of all timing and control signals internal to the camera. In addition, it allows for the image data to be routed past or around the compression processor out to any additional internal or external device such as an optical disk storage device, digital analyzer, or other data processors that might be desired.

[0049] FIG. 7 shows the digital control unit 9 . The microprocessor 20 architecture here is typical to one familiar with the art. The frame buffer 11 ( FIG. 5A ) receives and stores the outputs of the pixel buffer 10 until a complete frame of image data is received. Then, the CPU 20 , under software control, issues a control signal to the optics logic in the shutter and control circuitry 15 ( FIG. 6 ) thus resetting those functions for future image recording. The full frame buffer 11 , upon command from the CPU 20 , transfers it's data into the compression processor 12 ( FIG. 2 ) which performs thousands of levels of parallel pipeline processing on the image data. The compressed image frame is then written out to the mass memory RAM (Random Access Memory) 24 where it is temporarily stored until transferred to the disk drive assembly 5 via the disk I/O interface circuitry 13 .

[0050] Referring to FIG. 8, a flowchart shows the steps involved in the image compression process performed by the image compression processor 12 ( FIG. 2 ) in accordance with the preferred embodiment of the present invention. The output of the frame buffer 11 is transferred into the input of the image compression processor 12 under the control of the digital control unit 9 . As previously described, the setting of switch 14 A ( FIG. 6 ) is read by the CPU 20 ( FIG. 7 ) to determine the image resolution quality desired. Depending on the operator selected setting of switch 14 A, the unique digital word generated by the AND gate 60 a - b ( FIG. 6A ) which is activated by the selected position of switch 14 A is routed to image compression processor 12 via CPU 20 ( FIG. 7 ) which selects for example a predetermined digital memory location containing the appropriate corresponding compression ratio parameters under program control. The compression processor uses this command value for example to establish the size of the covariance matrix and a threshold for acceptance for the variances produced by the Discrete Cosine Transformation (DCT) transform coefficients. Next, the digital image signals are converted from the RGB format previously discussed in connection with FIGS. 2, 5 , and 6 into luminance and chrominance signals. The luminance and chrominance signals subsequently undergo a DCT. The cosine transformed signals are then quantized and are then processed for Huffman coding. The Huffman coded image signals are then formatted into a form that facilitates format processing into various PC compatible formats (GIFF, PICT2, etc.). For a more complete understanding of the image compression process reference may be made to I.E.E.E. Catalog No. EH0231-1, Library of Congress No. 85-60384 published by the I.E.E.E. Society dated 1985 and incorporated herein by reference.

[0051] Of the two traditional classes of image compression techniques, spatial coding and transform coding, transform coding techniques lend themselves well for this application due to computational simplicity. Transform coding techniques that provide good visual fidelity include: Karhunen-Loeve transform (KLT), Fourier, cosine, sine, and Hadamard. The KLT algorithm offers the best visual fidelity but suffers from serious computational complications due to extremely large matrix size. Several alternate algorithms that offer reasonable visual fidelity that are computationally feasible for this invention include the Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT), and Discrete Sine Transform (DST). The DCT was adopted by the JPEG as the preferred algorithm due to computational simplicity and performance.

[0052] It should be noted that the Joint Photographic Experts Group (JPEG) (composed of experts from many companies including IBM, AT&T, Digital Equipment Corp, and INTEL) compression/decompression standard was developed in 1985 in response to the lack of interoperability between image and processing equipment due to numerous proprietary standards held by each manufacturer. The JPEG standard provides image compression effectively up to 75 times or greater depending on the visual fidelity desired. The JPEG standard is widely used in industry as an alternative to proprietary algorithms such as Intel's own proprietary standard called DVI which was initially developed by RCA before being sold to INTEL, the integrated Circuit manufacturer. INTEL offers it's own firmware compression processor incorporating their DVI standard delivering compression ratios in excessive of 100:1. However, a new international standard called MPEG is due to be announced in the 1991 time frame from the JPEG and should offer compression ratios of 275:1 and greater. In the preferred embodiment of the present invention, the JPEG standard is the preferred algorithm chosen with the incorporation of the the MPEG standard or other similar standard in the future when available commercially. An alternate embodiment of the present invention would be the incorporation of various proprietary compression algorithm standards such as DVI.

[0053] The compression/decompression algorithm firmware implementation of the JPEG algorithm is available commercially from various sources including C-Cube, Electronics for imaging, Storm Technology, Burr-Brown, Spectral Innovations Inc., INTEL, and others. The implementation of this algorithm for the present invention may incorporate the integrated circuit set commercially available from C-Cube. Their four chip ASIC JPEG algorithm implementation is performed in three basic steps: first, the image is divided into 8-by-8 pixel squares and applies a discrete cosine transform (DCT) to each square resulting in 64 frequency values; second, these frequencies are put through a quantization algorithm to eliminate unimportant frequencies; third, the remaining values are run through a Huffman coding scheme to encode the most frequently occurring values using the fewest bits. A compatible software implementation of the JPEG algorithm is available commercially from Aladdin Systems, Radius Inc., Kodak, and others.

[0054] Those skilled in the art will be familiar with the process and the commercially available software and firmware chipsets that are currently available on the market. The present invention incorporates both available firmware chipsets in the camera and software for use in the PC for decompression. The decompression algorithm can be written onto the camera's diskette 50 prior to any image data recording. This allows the PC user to take the diskette 50 to a PC and directly incorporate the image data because the image file selected by the user is automatically decompressed transparent to the user. The algorithm can be written onto an unused track 52 or sector combination on the diskette as shown on FIG. 2A . Alternatively, the decompression algorithm can be loaded onto a PC before inserting a diskette 50 containing compressed image data. In the latter embodiment the resolution and mode values 54 and 55 ( FIG. 2A .) for each representative image would be read from diskette 50 in order to appropriately control the selection and activation of the appropriate corresponding decompression algorithm.

[0055] As shown in FIG. 7 , the output of the image compression processor 12 is routed to the RAM memory 24 where the compressed image is formatted for either the PICT II or GIFF format depending on the setting of format switch 17 ( FIG. 6 ). It should be noted that a large number of image formats for PCs exist. PICT and GIFF are the most common for the Apple and IBM PC's and are therefore the preferred formats for the present invention although other formats can be easily incorporated into the design by changing the software format routines. These software image formats are commercially available from many sources most notably Apple computers for PICT and IBM for GIFF. An example of the PICT format is pictorially shown in FIG. 6B as will be familiar to those skilled in the computer arts. Once formatting is complete, the formatted image data is transferred to the disk I/O interface 13 for transfer to the magnetic recording diskette 50 .

[0056] FIG. 9 and FIG. 10 illustrate the preferred embodiment of the video format translator device in accordance with another aspect of this invention that converts other still video camera formats for example on two inch video diskette to this invention's selectable PC compatible digital format. The general concept of operation is shown in FIG. 10 . In FIG. 9 correspond parts and subassemblies in translator 40 are shown with like numbers corresponding to FIGS. 2 and 6 having a 40 hyphenation prefix designation and such parts and subassemblies perform similar functions to those described above with reference to FIGS. 2 and 6 . Referring again to FIG. 9 , the translator 40 incorporates the same components utilized in the digital circuit card assembly which houses both the digital control unit 9 and optics processing circuits (pixel multiplexer 7 , A/D 8 , etc. 10 - 13 ). The major difference is that the CCD array 1 is replaced with an input disk drive 25 , for example a two inch (2″) video disk drive assembly, and an NTSC video format decoder 26 which converts the composite video signal to an RGB format for processing as described previously.

[0057] FIG. 11 displays an alternate embodiment of the video format translator device 40 of the present invention that shows optional inputs 27 and outputs 28 and 29 . The exact same circuitry is utilized that was used for the translator device 40 as shown in FIG. 9 except that inputs 27 for either an NTSC/PAL format or RGB format video signal is provided. This allows video signals from other sources such as a cable TV, CAMCORDER, or other video signal source to be digitized and archived in a PC compatible format. Also, provisions for video output jacks 28 are made to allow either viewing of the image/video source prior to or during image recording. Finally, provisions are made to provide a data output 29 to allow connection to other PC peripherals such as a communications modem, larger/smaller disk drive assembly, optical disk, specialty display or signal processor/analyzer. Either a standard serial, parallel, or Small Computer Standard Interface (SCSI) data port can be readily connected to the auxiliary I/O interface 80 .

[0058] FIG. 12 depicts an alternate feature of an embodiment of the present invention that shows how an inserted diskette 50 that is either unformatted or formatted for a undesired (e.g., not corresponding to the setting of switch 17 — FIG. 6 ) PC configuration would be automatically properly formatted for use with a camera in accordance with another aspect of this invention. This capability allows the user of this invention to forego the requirement to pre-format the storage medium (diskette) on a PC prior to using it in the camera operated in accordance with the present invention. With reference to FIG. 3 the power-on sequence process would result in an abnormal diskette format error if the format of an inserted diskette 50 did not correspond to the operator selected format switch 17 ( FIG. 6 ). In accordance with the automatic diskette format option, CPU 20 of digital control unit 9 in response to the abnormal diskette format error would initiate the diskette format process illustrated in FIG. 12 . Upon completion of the diskette format process illustrated in FIG. 12 , the power-on sequence illustrated in FIG. 3 would continue from step B.

[0059] Referring now to FIG. 14 A, there is shown a schematic block diagram of the format selection logic in accordance with another aspect of the present invention. During the power-on sequence as described in connection with FIGS. 3 and 12 , processor 20 of control unit 9 initiates a format selection switch sample and test routine as more fully described in the flow diagram illustrated in FIG. 14B . Switch 17 is illustrated in FIG. 14A in the Apple PC position and logic level v1 is applied as inputs to logic gates 60 c and 60 d . As illustrated in FIG. 2 A, the format signals 57 for the Apple PC format is a logic “zero” and conversely the format signal or tag 57 if the format switch 17 were in the IBM PC or other computer type position would be a logic “one” and “two” respectively. In response to the logic “zero” indicating Apple PC format, processor 20 accesses a unique memory location XY of format memory 20 - 2 which for example may comprise any random access memory with two megabytes storage capacity. The data format for the operator selectable predetermined number of computer architectures, similar in content and arrangement to those illustrated in FIG. 6B for an Apple PC would be stored in memory 20 - 2 which would be addressed in response to the other operator selectable position of switch 17 to generate the other unique codes 57 as shown in FIG. 2A . Processor 20 in response to a stored format subroutine more particularly shown in FIG. 14B contains the allocation of data memory addresses in disk input/output interface unit 13 in accordance with the picture image file format as illustrated in FIG. 6B . Thus the digital video data information signals generated by compression processor 12 are appropriately formatted and stored in memory storage disk drive 5 to insure compatibility with the format selected by the operator by selectively positioning switch 17 .

[0060] Those skilled in the art will recognize the many alterations, additions or changes of the preferred embodiment may be made without departing from the scope of the following claims.