BEST MODE FOR CARRYING OUT THE PRESENT INVENTION

[0100] The best mode for carrying out the present invention is now discussed, referring to the embodiments together with the drawings. In each of the following embodiments, the electrooptical device of the present invention is employed in a liquid crystal device.

[0101] (First Embodiment)

[0102] An electrooptical device of the first embodiment is now discussed, referring to FIG. 1 through FIG. 16 .

[0103] The construction and operation of the electrooptical device of the present invention are discussed, referring to FIG. 1 through FIG. 9 . FIG. 1 is an equivalent circuit diagram of a variety of elements and wiring formed in each of a plurality of pixels arranged in a matrix forming an image display area of the electrooptical device of a first embodiment of the present invention. FIG. 2 is a plan view showing a plurality of pixel groups adjacent to each other in a TFT array substrate in which a data line, a scanning line, a pixel electrode, and a light shield layer are formed. FIG. 3 is an enlarged view showing the formation area of the pixel electrodes in the TFT array substrate. FIG. 4 is an enlarged view showing the formation area of the scanning line and the data line in the TFT array substrate. FIG. 5 is an enlarged view showing the formation area of a semiconductor layer for forming a TFT in the TFT array substrate. FIG. 6 is a cross-sectional view showing the TFT array substrate taken along line A-A′, line B-B′, and line C-C′. FIG. 7 is an enlarged view showing the formation area of a drain electrode in the TFT array substrate. FIG. 8 is an enlarged view showing a first light shield layer and the formation area of a side wall formation trench in the TFT array substrate. FIG. 9 is an enlarged view showing the first light shield layer and the formation area of the side wall formation trench in the TFT array substrate. As shown, layers and members are not necessarily drawn to equal scale to show the layers and members in easy-to-identify sizes.

[0104] Referring to FIG. 1 , each of a plurality of pixels arranged in a matrix forming an image display area of the electrooptical device of this embodiment includes pixel electrodes 9 a and TFT 30 s for controlling the pixel electrodes 9 a , and data lines 6 a for supplying image signals are electrically connected to the sources of the TFT 30 s . Image signals S 1 , S 2 , . . . , Sn may subsequently be supplied to the data lines 6 a on one line at a time basis or may be supplied to a plurality of adjacent data lines 6 a on a group by group basis. Scanning lines 3 a are respectively electrically connected to the gates of the TFTs 30 , and are supplied with scanning signals G 1 , G 2 , . . . , Gm in a pulse form, in this order, on one line at a time basis. The pixel electrodes 9 a are electrically connected to the drains of the TFTs 30 , and turn on the TFTs 30 as switching elements for a predetermined period, thereby writing the image signals S 1 , S 2 , . . . , Sn supplied from the data lines 6 a , in each pixel at a predetermined timing.

[0105] The image signals S 1 , S 2 , . . . , Sn at a predetermined level written through pixel electrodes 9 a on the liquid crystal as one example of electrooptical material are held with respect to a counter electrode formed on a counter substrate, to be discussed later. The electrooptical device modulates light to present a gradation display by changing the orientation or order of a set of molecules with an applied voltage level. In the normally white mode, transmittance ratio to incident light drops in response to the applied voltage while in the normally black mode, the transmittance ratio to the incident light rises in response to the applied voltage. The liquid-crystal display device outputs light having a contrast responsive to the image signal.

[0106] To prevent the stored image signal from being leaked, a storage capacitor 70 may be added in parallel with a capacitance of the liquid crystal formed between the pixel electrode 9 a and the counter electrode. For example, the voltage at the pixel electrode 9 a is maintained by the storage capacitor 70 for a period of time three orders of magnitude longer than the period throughout which the source voltage is applied. The voltage holding characteristic of the pixel is thus improved, and a high-contrast electrooptical device 100 can be achieved.

[0107] Referring to FIG. 2 , the TFT array substrate of the electrooptical device includes a matrix of transparent pixel electrodes 9 a in each pixel. The formation area of the pixel electrode 9 a is a rectangular area hatched with upwardly inclined lines in an enlarged view in FIG. 3 .

[0108] The data line 6 a , and the scanning line 3 a run, respectively, vertically and horizontally along the border area of each pixel electrode 9 a , but unlike conventional electrooptical devices, no dedicated capacitive lines are formed.

[0109] The formation area of the data line 6 a is represented by an area hatched with downwardly inclined lines in the enlarged view in FIG. 4 . Both edge portions of the data line 6 a overlap the edge of each pixel electrode 9 a . The formation area of the scanning line 3 a is represented by an area hatched with upwardly inclined lines in the enlarged view in FIG. 4 , and both edge portions of the scanning line 3 a overlap the edge of each pixel electrode 9 a.

[0110] In this embodiment, the data line 6 a is electrically connected to the source region, to be discussed later, of a semiconductor layer 1 a formed of a polysilicon layer through a contact hole 5 , and the pixel electrode 9 a is electrically connected to the drain region, to be discussed later, of the semiconductor layer 1 a through contact holes 81 and 82 . The scanning line 3 a (a gate electrode) runs facing the channel formation region, to be discussed later, of the semiconductor layer 1 a.

[0111] The formation area of the semiconductor layer 1 a is represented by an area hatched with upwardly inclined lines in the enlarged view in FIG. 5 .

[0112] In this embodiment, the data line 6 a is formed of a conductive layer having a light shield property and extending in a line having an equal line width, such as a metal layer of aluminum and an alloy layer of metal silicide. The semiconductor layer 1 a is formed beneath the data line 6 a and within the formation area of the data line 6 a . Specifically, the semiconductor layer 1 a is arranged in the border area running vertically and horizontally between the pixel electrodes 9 a .

[0113] Referring to FIG. 6 , the electrooptical device 100 includes a TFT array substrate 10 (a first substrate) and a counter substrate 20 (a second substrate) opposed to the TFT array substrate 10 . The TFT array substrate 10 is fabricated of a quartz substrate, for instance, and the counter substrate 20 is fabricated of a glass substrate or a quartz substrate, for instance. The TFT array substrate 10 is provided with the pixel electrodes 9 a , and arranged on top of them is an alignment layer (not shown) which has been subjected to a predetermined alignment process such as a rubbing process. The pixel electrode 9 a is fabricated of a transparent conductive thin film, such as an ITO (Indium Tin Oxide) film. The alignment layer is fabricated of an organic thin film, such as a polyimide thin film.

[0114] The TFT array substrate 10 includes a pixel switching TFT 30 for performing switching control of each pixel electrode 9 a , formed right below the data line 6 a . The TFT 30 has an LDD (Lightly Doped Drain) structure and includes the scanning line 3 a (the gate electrode), the channel region 1 a ′ of the semiconductor layer 1 a in which a channel is formed by the electric field of the scanning signals supplied from the scanning line 3 a , a dual-structured gate insulator 2 for insulating the scanning line 3 a from the semiconductor layer 1 a , the data line 6 a (a source electrode), the lightly doped source region 1 b (a source LDD region) and the lightly doped drain region 1 c (a drain LDD region) of the semiconductor layer 1 a , and the heavily doped source region 1 d and the heavily doped drain region 1 e of the semiconductor layer 1 a . A corresponding one of the plurality of pixel electrodes 9 a is electrically connected to the heavily doped drain region 1 e.

[0115] The source regions 1 b and 1 d as well as the drain regions 1 c and 1 e are doped with a n-type dopant or a p-type dopant, depending on which of the two channels, a n-channel or a p-channel, is produced in the semiconductor layer 1 a . The n-channel TFT provides a fast operational speed and is frequently used as a pixel switching TFT.

[0116] The TFT 30 preferably has the above-mentioned LDD structure. Alternatively, the TFT 30 may have an offset structure in which no impurity ion implantation is performed on the regions corresponding to the lightly doped source region 1 b and the lightly doped drain region 1 c . The TFT 30 may also have a self-aligned type TFT in which a high dose impurity ion is implanted with a part of the gate electrode 3 a being used as a mask, to form heavily doped source and drain regions in a self-alignment process. In this embodiment, the gate electrode (the data line 3 a ) of the TFT 30 is of a single gate structure in which a gate electrode is interposed between the source and drain regions 1 b and 1 e , but alternatively, more than one gate electrode may be interposed therebetween. In this case, the same signal is applied to the gate electrodes. With dual gates (double gates) or triple gates employed in a TFT, photocurrent leakage at junctions between the channel region and the source region as well as between the channel region and the drain region are prevented, and thereby a current during off period is reduced. If at least one of the gate electrodes has a LDD structure or an offset structure, the off current is reduced even more, and a reliable switching element can be achieved.

[0117] In this embodiment, the data line 6 a (the source electrode) is formed of a metal layer of aluminum, or an alloy layer of metal silicide.

[0118] Arranged over the scanning line 3 a (the gate electrode) and the gate insulator 2 is a first interlayer insulator 4 through which a contact hole 5 leading to the heavily doped source region 1 d and a contact hole 81 leading to the heavily doped drain region 1 e are formed. A second interlayer insulator 7 a is arranged over the interlayer insulator 4 , and a third interlayer insulator 7 b is formed over the second interlayer insulator 7 a . The data line 6 a (the source electrode) is formed on the second interlayer insulator 7 a , and is electrically connected to the heavily doped source region 1 d through the contact hole 5 .

[0119] The pixel electrode 9 a is formed on the third insulator 7 b . In this embodiment, to electrically connect the pixel electrode 9 a to the heavily doped drain region 1 e of the TFT 30 , a drain electrode 11 is formed on the surface of the first interlayer insulator 4 , the drain electrode 11 is electrically connected to the heavily doped drain region 1 e of the TFT 30 through the contact hole 81 in the first interlayer insulator 4 , a contact hole 82 is drilled through the second interlayer insulator 7 a and the third interlayer insulator 7 b , and the pixel electrode 9 a is thus electrically connected to the drain electrode 11 through the contact hole 82 . The pixel electrode 9 a is electrically connected to the heavily doped drain region 1 e of the TFT 30 through the drain electrode 11 .

[0120] In this embodiment, the drain electrode 11 is fabricated of a conductive layer having a light shield property, such as a doped silicon layer (a polysilicon intermediary electrode) which is formed to fully cover the heavily doped drain region 1 e and the channel region 1 a from above. As represented by an area hatched with upwardly inclined lines in FIG. 7 , the formation area of the drain electrode 11 extends along the data line 6 a and the scanning line 3 a in a cross configuration in the border area of each pixel electrode 9 a from the intersection of the data line 6 a and the scanning line 3 a.

[0121] Referring to FIG. 6 , in this embodiment, a thin insulator 12 is deposited on the top surface of the drain electrode 11 , and a first light shield layer 13 is laminated between the thin insulator 12 and the second interlayer insulator 7 a , covering the channel region 1 a ′ of the TFT 30 . In this embodiment, the first light shield layer 13 is formed of a metal layer, an alloy layer, a metal silicide layer, each of which layers contains at least either one of titanium, chromium, tungsten, tantalum, molybdenum, palladium, and aluminum, or a conductive layer having a light shield property such as a doped silicon. The formation area of the first light shield layer 13 is represented by an area hatched with downwardly inclined lines in FIG. 8 . The first light shield layer 13 extends vertically and horizontally along the border area of each pixel electrode 9 a in a grid configuration, and is held at a potential common to the pixels.

[0122] The drain electrode 11 is formed below the first light shield layer 13 , and the drain electrode 11 and the first light shield layer 13 are opposed to each other over a wide area with the thin insulator 12 interposed therebetween. In this embodiment, the thin insulator 12 is used as a dielectric layer, and the storage capacitor 70 having the first light shield layer 13 and the drain electrode 11 as the electrodes thereof is thus provided.

[0123] In this embodiment, referring to FIG. 6, a second light shield layer 14 is formed on the TFT array substrate 10 in such a manner that the second light shield layer 14 covers the channel region 1 a ′ of the TFT 30 from below. The underlayer insulator 15 is deposited on the top surface of the second light shield layer 14 . The formation area of the second light shield layer 14 is represented by an area hatched with downwardly inclined lines in FIG. 9 .

[0124] In this embodiment, a side wall formation trench 16 penetrates the thin insulator 12 and the first interlayer insulator 4 , laterally surrounding the channel region 1 a ′ of the TFT 30 . Referring to FIG. 8 , the side wall formation trench 16 is formed along the outline of the first light shield layer 13 within the formation area of the first light shield layer 13 . The formation area of the side wall formation trench 16 is represented by an area hatched with downwardly inclined lines at a pitch smaller than that of the hatch area of the first light shield layer 13 .

[0125] The side wall formation trench 16 in this embodiment communicates with a connection trench 161 penetrating the gate insulator 2 and the underlayer insulator 15 . The connection trench 161 is filled with a conductive layer 162 having a light shield property that is produced at the same time that the scanning line 3 a (the gate electrode) is produced. The side wall formation trench 16 is filled with a light shield side wall 131 that is formed of a conductive layer having a light shield property and produced at the same time when the first light shield layer 13 is produced.

[0126] The channel region 1 a ′ of the TFT 30 is light shielded by the scanning line 3 a , the drain electrode 11 , the first light shield layer 13 , and the data line 6 a from above, by the second light shield layer 14 from below, and by the light shield side wall 131 in the side wall formation trench 16 and the electrically conductive layer 162 in the connection trench 161 from sides.

[0127] Referring back to FIG. 6 , the counter substrate 20 has a counter electrode (common electrode) 21 extending on the entire surface thereof, and an alignment layer (not shown) therebeneath which has been subjected to a predetermined alignment process such as a rubbing process. The counter electrode 21 is fabricated of a transparent conductive film such as an ITO film. The alignment layer of the counter substrate 20 is fabricated of an organic thin film such as a polyimide thin film. There are times that a light shield layer 23 is arranged in a matrix on the counter substrate 20 in an area other than the aperture area in each pixel.

[0128] For this reason, incident light L 1 from the counter substrate 20 cannot enter the channel region 1 a ′, LDD regions 1 b and 1 c of the semiconductor layer 1 a of the TFT 30 . The light shield layer 23 has the function of improving contrast and preventing color mixing of color materials.

[0129] The TFT array substrate 10 and the counter substrate 20 are arranged with the pixel electrodes 9 a facing the counter electrode 21 , and a liquid crystal 50 as an electrooptical material is encapsulated in a space surrounded by a sealing material, to be discussed later, between the TFT array substrate 10 and the counter substrate 20 . The liquid-crystal layer 50 takes a predetermined orientation state by the alignment layers with no electric field applied by the pixel electrode 9 a . The liquid-crystal layer 50 is formed of a mixture of one or several types of nematic electrooptical materials. The sealing material is an adhesive agent made of a thermal setting agent or a photo-setting agent for bonding the TFT array substrate 10 to the counter substrate 20 along the edges thereof, and is mixed with spacers such as glass fiber or glass beads to keep a predetermined distance between the two substrates.

[0130] As discussed above referring to FIG. 1 through FIG. 9 , the scanning line 3 a , the drain electrode 11 , the first light shield layer 13 , and the data line 6 a are arranged over the channel region 1 a ′ and the LDD regions 1 b and 1 c of the TFT 30 . Strong light rays entering from the counter substrate 20 cannot reach the channel region 1 a . The channel region 1 a ′ and the LDD regions 1 b and 1 c of the TFT 30 are light shielded by the second light shield layer 14 from below. Even if light is reflected from the TFT array substrate 10 or light reflected from an external optical member enters the TFT array substrate 10 from the back of the TFT array substrate 10 , the light is prevented from entering the channel region 1 a.

[0131] Moreover, in this embodiment, even if strong light entering from the counter substrate 20 is obliquely or laterally directed to the channel region 1 a , and the LDD regions 1 b and 1 c , no such light is admitted into the channel region 1 a because the lateral portions of the channel region 1 a ′ and the LDD regions 1 b and 1 c are light shielded by the light shield side wall 131 in the side wall formation trench 16 and the conductive layer 162 in the connection trench 161 .

[0132] Accordingly, even if a strong light ray enters from the counter substrate 20 , as in a projection-type display apparatus to be discussed later, the electrooptical device 100 of this embodiment is free from erratic operations of the TFT 30 and a drop in reliability of the TFT 30 , attributed to the admittance of light into the channel region 1 a ′ of the TFT 30 .

[0133] In this embodiment, the drain electrode 11 electrically connected to the pixel electrode 9 a in each pixel and the first light shield layer 13 common to all pixels are opposed to each other with the thin insulator 12 interposed therebetween in a wide area. The first light shield layer 13 and the second light shield layer 14 are electrically connected to each other through the light shield side wall 131 in the side wall formation trench 16 and the conductive layer 162 in the connection trench 161 . If the second light shield layer 14 is fixed to a potential, the first light shield layer 13 is fixed to the same potential. In this embodiment, the storage capacitor 70 is formed by having the drain electrode 11 , the first light shield layer 13 as the capacitive electrodes thereof, and the thin insulator 12 as a conductive layer. Since this arrangement eliminates the need for routing a dedicated capacitive line to each pixel, the pixel aperture ration is increased.

[0134] (Method of Manufacturing the Electrooptical Device)

[0135] The method of manufacturing the electrooptical device 100 of the first embodiment having the above construction is now discussed, referring to FIG. 10 through FIG. 16 .

[0136] The method of manufacturing the TFT array substrate 10 is now discussed.

[0137] Referring to FIG. 10 through FIG. 16 , there shown are cross-sectional views showing processes of manufacturing the TFT array substrate 10 of this embodiment. FIG. 10 through FIG. 16 show cross sections of the TFT array substrate 10 corresponding to those taken along line A-A′, B-B′, and C-C′ in FIG. 2 .

[0138] Referring to FIG. 10 (A), a TFT array substrate 10 fabricated of a glass substrate or a quartz substrate, for instance, is prepared. The TFT array substrate 10 is preferably annealed in an inert gas atmosphere such as N ₂ (nitrogen) gas within a temperature range of 900 to 1300 degrees Centigrade so that the TFT array substrate 10 suffers from less distortion in a subsequent high temperature thermal process. In other words, the TFT array substrate 10 is subjected beforehand to a heat treatment as high as or higher than the maximum temperature expected in the high temperature thermal process in the manufacturing process.

[0139] A tungsten silicide layer 140 as the second light shield layer 14 is formed to be 200 nm thick. The tungsten silicide layer 140 is then patterned as shown in FIG. 10 (B), thereby forming the second light shield layer 14 .

[0140] Formed on the TFT array substrate 10 is the underlayer insulator 15 fabricated of a silicate glass film such as NSG (non-silicate glass), PSG (phosphosilicate glass), BSG (borosilicate glass), or BPSG (borophosphosilicate glass), a silicon nitride film, or a silicon oxide film, using a TEOS (tetraethylorthosilicate) gas, a TEB (triethyl borate) gas, or a TMOP (trimethyl phosphate) gas by an atmospheric CVD method or a reduced pressure CVD method. The thickness of the underlayer insulator 15 is within a range from 500 to 2000 nm.

[0141] Referring to FIG. 10 (C), an amorphous silicon layer 1 a ″ is deposited on the underlayer insulator 15 using a reduced pressure CVD (at a pressure of 20 to 40 Pa) with monosilane gas or disilane gas at a flow rate within a range from 400 cc/minute to 600 cc/minute in a relatively low temperature environment within a range from 450 degrees C. to 550 degrees C., preferably at about 500 degree C. The TFT array substrate 10 is subjected to an annealing process at a temperature within a range from 600 degrees C. to 700 degrees C. for the duration from one hour to ten hours, preferably for the duration from four to six hours in a nitrogen atmosphere, and a polysilicon layer 1 is grown by solid-phase epitaxy to a thickness within a range from 50 nm to 200 nm, preferably to a thickness of approximately 100 nm.

[0142] When the pixel switching TFT 30 is of a P-channel type, the channel formation region may be doped with a small amount of Group V dopant such as Sb (antimony), As (arsenic), or P (phosphorus) through an ion implantation technique. When the pixel switching TFT 30 is of an N-channel type, the channel formation region may be doped with a small amount of Group III dopant such as B (boron), Ga (gallium), or In (indium) through an ion implantation technique. The polysilicon 1 may be directly formed through the reduced pressure CVD rather than by way of the amorphous silicon layer. The polysilicon layer deposited through the reduced pressure CVD is implanted with silicon ions to form an amorphous silicon layer, and the amorphous silicon layer is then recrystallized through an anneal process to form the polysilicon layer 1 .

[0143] Referring to FIG. 10 (D), the semiconductor layer 1 a having the pattern shown in FIG. 2 and FIG. 5 is formed through a photolithographic step and an etching step.

[0144] Referring to FIG. 11 (A), the semiconductor layer 1 a forming the TFT 30 is thermally oxidized at a temperature within a range from 900 degrees Centigrade to 1300 degrees Centigrade, preferably at a temperature of approximately 1000 degrees Centigrade. A relatively thin thermally-oxidized silicon layer 201 as thin as 30 nm is then formed. A high temperature oxide layer 202 (HTO layer) or a silicon nitride layer is deposited to a thickness of about 50 nm using the reduced pressure CVD. A gate insulator 2 having a multi-layer structure thus can be achieved. A gate insulator 2 having a single layer structure may be deposited only through the thermal oxidation. After the formation of the gate insulator 2 , the above-referenced ion implantation may be performed.

[0145] Referring to FIG. 11 (B), the connection trench 161 reaching the second light shield layer 14 is formed in the gate insulator 2 and the underlayer insulator 15 .

[0146] Referring to FIG. 11 (C), a polysilicon layer 3 is deposited through the reduced pressure CVD, and is thermally diffused with phosphorus (P) to make the polysilicon layer 3 conductive. A doped silicon layer may be used which is doped with P ions at the film formation phase of the polysilicon layer 3 .

[0147] Referring to FIG. 11 (D), the scanning line 3 a (the gate electrode) having the pattern shown in FIG. 2 and FIG. 4 is formed through a photolithographic step or an etching step using a resist mask. The thickness of the scanning line 3 a is about 350 nm. The connection trench 161 is filled with a conductive layer 162 which is made from the same material as the scanning line 3 a.

[0148] When the TFT 30 shown in FIG. 6 is of an n-channel TFT having a LDD structure, the semiconductor layer 1 a is lightly doped with a Group V dopant 200 such as P with the scanning line 3 a (the gate electrode) as a diffusion mask (with a dose of P ions falling within a range from 1×10 ¹³ /cm ² to 3×10 ¹³ /cm ² ) in order to form the lightly doped source region 1 b and the lightly doped drain region 1 c in the semiconductor layer 1 a as shown in FIG. 12 (A). The semiconductor 1 a beneath the scanning line 3 a (the gate electrode) becomes the channel region 1 a ′. With this impurity doping, the resistance of the scanning line 3 a is reduced.

[0149] After a resist mask 203 wider than the scanning line 3 a (the gate electrode) is deposited on the scanning line 3 a (the gate electrode), the semiconductor layer 1 a is heavily doped with a Group V dopant 201 such as P (for example, with a dose of P ions falling within a range from 1×10 ¹⁵ /cm ² to 3×10 ¹⁵ /cm ² ) in order to form the heavily doped source region 1 d and the heavily doped drain region 1 e of the TFT 30 as shown in FIG. 12 (B). The n-channel TFT may have an offset structure without implanting a light dose of impurity.

[0150] When the TFT 30 is of a p-channel, the semiconductor layer 1 a is doped with a Group III dopant such as B in order to form the lightly doped source region 1 b , the lightly doped drain region 1 c , the heavily doped source region 1 d , and the heavily doped drain region 1 e in the semiconductor layer 1 a . The TFT may have an offset structure without implanting a light dose of impurity. A self-alignment TFT may be produced using an ion implantation technique for P ions or B ions with the scanning line 3 a (the gate electrode) as a mask. With this low-dose impurity doping, the resistance of the scanning line 3 a is further reduced.

[0151] In parallel with these steps, peripheral circuits such as a data line driving circuit and a scanning line driving circuit, respectively having a complementary structure of a n-channel TFT and a p-channel TFT, are produced on the periphery of the TFT array substrate 10 . Since the pixel switching TFT 30 is a polysilicon TFT in this embodiment, the peripheral circuits such as the data line driving circuit and the scanning line driving circuit are produced at substantially the same steps as those for the pixel switching TFTs. This feature is advantageous from the manufacturing process standpoint.

[0152] Referring to FIG. 12 (C), the interlayer insulator 4 covering the scanning line 3 a (the gate electrode) of the TFT 30 is formed of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, or a silicon oxide film, using a TEOS gas by an atmospheric CVD method or a reduced pressure CVD method. The thickness of the interlayer insulator 4 is preferably within a range from 500 to 1500 nm.

[0153] Referring to FIG. 12 (D), the contact hole 81 for connecting the heavily doped drain region 1 e to the drain electrode 11 is formed using a dry etching process such as a reactive ion etching or a reactive ion beam etching, or a wet etching process.

[0154] Referring to FIG. 13 (A), a polysilicon layer 110 is deposited to produce the drain electrode 11 on the surface of the first interlayer insulator 4 by the reduced CVD method. The polysilicon layer 110 is thermally diffused with phosphorus (P) to be conductive. Alternatively, a doped silicon layer may be used which is doped with P ions at the film formation phase of the polysilicon layer 110 .

[0155] Referring to FIG. 13 (B), the drain electrode 11 having the pattern shown in FIG. 2 and FIG. 7 is produced through a photolithographic step and an etching step using a resist mask.

[0156] Referring to FIG. 13 (C), a thin insulator 12 is deposited on the surface of the drain electrode 11 .

[0157] Referring to FIG. 13 (D), the side wall formation trench 16 for forming the light shield side wall 131 using the first light shield layer 13 is formed in the thin insulator 12 and the first interlayer insulator 4 by using a dry etching process such as a reactive ion etching or a reactive ion beam etching in a way that the side wall formation trench 16 communicates with the connection trench 161 . The side wall formation trench 16 is then integrally formed with the connection trench 161 .

[0158] Referring to FIG. 14 (A), a tungsten silicide layer 130 for forming the first light shield layer 13 on the surface of the insulator 12 is deposited to a thickness of about 200 nm. The tungsten silicide layer 130 is patterned as shown in FIG. 14 (B), thereby forming the first light shield layer 13 . The light shield side wall 131 is formed in the side wall formation trench 16 at the same time that the first light shield layer 13 is produced, and is electrically connected to the layer 162 on the bottom portion of the side wall formation trench 16 .

[0159] Referring to FIG. 14 (C), the second interlayer insulator 7 a is formed, comprising a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, or a silicon oxide film, using a TEOS gas by an atmospheric CVD method or a reduced pressure CVD method. The thickness of the second interlayer insulator 7 a is preferably within a range from 500 to 1500 nm.

[0160] Referring to FIG. 15 (A), the contact hole 5 for the data line 3 a (the source electrode) is formed using a dry etching process such as a reactive ion etching or a reactive ion beam etching, or a wet etching process.

[0161] Referring to FIG. 15 (B), a metal layer 6 of a low-resistance metal such as Al, or a metal silicide, is deposited on the second interlayer insulator 7 a to a thickness falling within a range from 100 nm to 500 nm, preferably, to a thickness of approximately 300 nm using a sputtering technique.

[0162] Referring to FIG. 15 (C), the data line 6 a (the source electrode) is produced using a photolithographic step and an etching step.

[0163] Referring to FIG. 16 (A), the third insulator 7 b covering the data line 6 a (the source electrode) is formed, comprising a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, or a silicon oxide film, using a TEOS gas by an atmospheric CVD method or a reduced pressure CVD method. The thickness of the third insulator 7 b is preferably within a range from 500 to 1500 nm.

[0164] Referring to FIG. 16 (B), the contact hole 82 for electrically connecting the pixel electrode 9 a to the drain electrode 11 is produced by using a dry etching process such as a reactive etching or a reactive ion beam etching.

[0165] Referring to FIG. 16 (C), a conductive transparent layer 9 such as an ITO film is deposited on the third insulator 7 b to a thickness falling within a range from 50 nm to 200 nm by using a sputtering technique.

[0166] The conductive transparent layer 9 is patterned through a photolithographic step, and an etching step, thereby forming the pixel electrode 9 a as shown in FIG. 6 . Polyimide-based alignment liquid is applied on the pixel electrode 9 a to form an alignment layer. A rubbing process is then performed on the alignment layer to impart a predetermined pretilt angle to the alignment layer.

[0167] The production of the TFT array substrate 10 of the electrooptical device 100 is now complete.

[0168] To produce the counter substrate 20 shown in FIG. 6, a glass substrate is first prepared. A light shield layer 23 on the counter substrate and a light shield layer 53 (see FIG. 24 and FIG. 25 ) as a frame for partitioning a display area from a non-display area are produced by sputtering chromium and then through a photolithographic step, and an etching step. The counter substrate light shield layer 23 and the light shield layer 53 as a frame are fabricated of a metal such as Cr, Ni, Al, or dispersed resin black in which carbon or Ti is mixed with photoresist.

[0169] A conductive transparent layer such as an ITO layer is deposited on the entire surface of the counter substrate 20 to a thickness of 50 nm to 200 nm through a sputtering technique. The counter electrode 21 is thus formed. Polyimide-based alignment liquid is applied on the pixel electrode 9 a to form an alignment layer. A rubbing process is then performed on the alignment layer to impart a predetermined pretilt angle to the alignment layer. The formation of the alignment layer is thus completed.

[0170] The production of the counter substrate 20 of the electrooptical device 100 is complete.

[0171] In this way, the TFT array substrate 10 and the counter substrate 20 are bonded together with the alignment layers facing each other using a sealing member (not shown). Through vacuum absorption, an electrooptical material comprising a mixture of a plurality of nematic electrooptical materials is drawn into the space between the two substrates. The liquid crystal layer 50 having a predetermined thickness is thus obtained.

[0172] The production of the electrooptical device 100 of the first embodiment already discussed with reference to FIG. 1 through FIG. 9 is thus completed.

[0173] (Second Embodiment)

[0174] The electrooptical device of a second embodiment of the present invention is now discussed, referring to FIG. 17 . FIG. 17 is a cross-sectional view of an electrooptical device 100 ′ of the second embodiment of the present invention.

[0175] The manufacturing method of the electrooptical device 100 ′ of the second embodiment is different from the that of the electrooptical device 100 of the first embodiment in that the process for forming the connection trench 161 , as in the description of the first embodiment with reference to FIG. 11 (B), is eliminated and in that the side wall formation trench 16 is formed to reach the second light shield layer 14 as shown in FIG. 17 in the second embodiment in the formation step of the side wall formation trench 16 described in the first embodiment with reference to FIG. 13 (D). The rest of the manufacturing process remains unchanged from that of the first embodiment.

[0176] With the electrooptical device 100 ′ manufactured as shown in FIG. 17 , the light shield side wall 131 fabricated of the same material as that of the first light shield layer 13 fills the side wall formation trench 16 when the first light shield layer 13 is formed. The light shield side wall 131 is directly in contact with the second light shield layer 14 on the bottom of the side wall formation trench 16 . The electrooptical device 100 ′ of the second embodiment has a TFT array substrate 10 different from that included in the electrooptical device 100 ′ of the first embodiment shown in FIG. 6 , and the rest of the construction is the same as that of the electrooptical device 100 ′ of the first embodiment as described with reference to FIG. 6 . Therefore, the corresponding elements are designated with the same reference numerals, and the discussion thereof is skipped.

[0177] (Third Embodiment)

[0178] The construction of the pixel of the electrooptical device in a third embodiment of the present invention is now discussed, referring to FIG. 1 and FIG. 18 through FIG. 20 . FIG. 18 is a plan view showing a plurality of pixel groups adjacent to each other in a TFT array substrate having a data line, a scanning line, and a pixel electrode, formed thereon in an electrooptical device of the third embodiment. FIG. 19 is a cross-sectional view of the TFT array substrate taken along line D-D′ in FIG. 18 . FIG. 20 is a cross-sectional view of a part of laminate structure formed on the TFT array substrate taken along line E-E′ in FIG. 18 . Referring to FIG. 19 and FIG. 20 , layers and members are not necessarily drawn to equal scale to show the layers and members in easy-to-recognize sizes. In FIG. 18 through FIG. 20 showing the third embodiment, the components identical to those described with reference to FIG. 1 through FIG. 9 showing the first embodiment are designated with the same reference numerals, and the discussion thereof is skipped as appropriate.

[0179] The basic construction of the circuit arrangement of the electrooptical device of the third embodiment remains substantially similar to that of the electrooptical device of the first embodiment shown in FIG. 1 . In the first embodiment, the second light shield layer 14 has the function of the capacitive line for fixing the fixed-potential capacitive electrode of the storage capacitor 70 to a fixed potential. In the third embodiment, a capacitive line overlaps and runs over the scanning line 3 a.

[0180] Referring to FIG. 18 and FIG. 19, a capacitive line 300 including the fixed-potential capacitive electrode is arranged. Specifically, in a plan view, the capacitive line 300 extends in a stripe configuration along the scanning line 3 a and juts upward and downward in a region overlapping the TFT 30 as shown in FIG. 18 . The formation area of the storage capacitor 70 is increased making use of the area over the scanning line 3 a and the area beneath the data line 6 a.

[0181] Referring to FIG. 18 through FIG. 20 , the storage capacitor 70 in the third embodiment is formed of an intermediary layer 71 , as a pixel-potential capacitive electrode, connected to the heavily doped drain region 1 e of the TFT 30 and to the pixel electrode 9 a , and of a portion of the capacitive line 300 as a fixed-potential capacitive electrode, arranged opposed to each other, with a dielectric layer 75 interposed between the intermediary layer 71 and the portion of the capacitive line 300 .

[0182] The capacitive line 300 , fabricated of a metal layer containing a metal or an alloy, functions as the fixed-potential capacitive electrode. The capacitive line 300 is formed of a single metal layer, an alloy layer, a metal silicide layer, a polysilicide layer, or a multilayer of these layers, each of which layers comprises at least a refractory metal such as Ti, Cr, W, Ta, Mo, and Pb. The capacitive line 300 may have a multi-layer structure formed of a first layer fabricated of a conductive polysilicon layer, and a second layer fabricated of a metal silicide layer containing a refractory metal.

[0183] The intermediary layer 71 , fabricated of a conductive polysilicon layer, functions as a pixel-potential capacitive electrode. Besides the function of the pixel-potential capacitive electrode, the intermediary layer 71 has the function of electrically connecting the pixel electrode 9 a to the heavily doped drain region 1 e of the TFT 30 . The intermediary layer 71 may also have a single layer structure containing a metal or an alloy or a multi-layer structure like the capacitive line 300 .

[0184] Referring to FIG. 18 and FIG. 20, a trench 10 cv is formed in the TFT array substrate 10 in a grid area coarsely hatched with downwardly inclined lines in FIG. 18 . A lower light shield layer 400 is arranged in a grid configuration within the trench 10 cv . Like the capacitive line 300 , the lower light shield layer 400 is formed of a single metal layer, an alloy layer, a metal silicide layer, a polysilicide layer, or a multilayer of these layer, each of which layers comprises at least a refractory metal such as Ti, Cr, W, Ta, Mo, and Pb.

[0185] In the grid area coarsely hatched with downwardly inclined lines shown in FIG. 18 , an upper light shield layer 401 is arranged. Like the lower light shield layer 400 , the upper light shield layer 401 is formed of a single metal layer, an alloy layer, a metal silicide layer, a polysilicide layer, or a multilayer of these layer, each of which layers comprises at least a refractory metal such as Ti, Cr, W, Ta, Mo, and Pb. Further, a narrow groove is formed along the outline of the upper light shield layer 401 , penetrating a fourth interlayer insulator 44 , a third interlayer insulator 43 , a dielectric layer 75 , a second interlayer insulator 42 , a first interlayer insulator 41 , and an underlayer insulator 40 . A side wall light shield layer 402 , filling the narrow groove, extends from the upper light shield layer 401 to the lower light shield layer 400 . The side wall light shield layer 402 is formed of a single metal layer, an alloy layer, a metal silicide layer, a polysilicide layer, or a multilayer of these layer, each of which layers comprises at least a refractory metal such as Ti, Cr, W, Ta, Mo, and Pb. The lower light shield layer 400 , the upper light shield layer 401 and the side wall light shield layer 402 may be formed of the same light shield layer or different light shield layers.

[0186] Referring to FIG. 19 and FIG. 20 , elements and lines formed in the image display area of the TFT array substrate 10 , such as the TFT 30 , the scanning line 3 a , the data line 6 a , the capacitive line 300 , and the storage capacitor 70 , are three-dimensionally light shielded by the lower light shield layer 400 , the upper light shield layer 401 , and the side wall light shield layer 402 in the third embodiment. Referring to FIG. 19, a conductive, light shield layer 403 is arranged in a contact hole 85 connecting the pixel electrode 9 a to the intermediary layer 71 so that no light enters a space defined by the lower light shield layer 400 , the upper light shield layer 401 and the side wall light shield layer 402 through the vicinity of the contact hole 85 .

[0187] Referring to FIG. 19 and FIG. 20 , the dielectric layer 75 , interposed between the intermediary layer 71 as the capacitive electrode and the capacitive line 300 , may be formed of a silicon oxide layer, such as an HTO (High Temperature Oxide) layer or an LTO (Low Temperature Oxide) layer, or a silicon nitride layer, each of which layers has a relatively thin thickness falling within a range from 5 to 200 nm. To increase the capacitance of the storage capacitor 70 , the thinner the dielectric layer 75 is, the better it is as long as layer reliability is assured.

[0188] The capacitive line 300 extends from the image display area, where the pixel electrode 9 a is arranged, to the periphery of the pixel electrode 9 a . The capacitive line 300 is electrically connected to a constant voltage power source to be fixed to a constant potential. The constant voltage power source may be a positive voltage power source or a negative voltage power source for supplying power to a scanning line driving circuit, to be discussed later, which supplies the scanning line 3 a with a scanning signal for driving the TFT 30 , and a data line driving circuit, to be discussed later, for controlling a sampling circuit which supplies the data line 6 a with an image signal. The constant voltage power source may be fixed to a constant voltage supplied to the counter electrode 21 of the counter substrate 20 .

[0189] Like the capacitive line 300 , the lower light shield layer 400 , the upper light shield layer 401 , and the side wall light shield layer 402 may extend from the image display area to its periphery and may be connected to a constant voltage power source to control an adverse effect on the TFT 30 arising from variations in the potential of the lower light shield layer 400 , the upper light shield layer 401 , and the side wall light shield layer 402 .

[0190] The pixel electrode 9 a is electrically connected to the heavily doped drain region 1 e of the semiconductor layer 1 a via the intermediary layer 71 , and the contact holes 83 and 85 . In this embodiment, in addition to the function of the pixel-potential capacitive electrode of the storage capacitor 70 , the intermediary layer 71 has the function of connecting the pixel electrode 9 a to the TFT 30 . Even if an interlayer distance is as long as 2000 nm or so, two relatively small diameter contact holes connected in series connect the pixel electrode 9 a to the TFT 30 in an excellent condition using the intermediary layer 71 , preventing any technical difficulty such as of connecting the pixel electrode 9 a to the TFT 30 using a single contact hole. The aperture ratio of the pixel is thus increased. Etching through is prevented during the opening of the contact hole.

[0191] Similarly, the data line 6 a is connected to the heavily doped source region 1 d of the semiconductor layer 1 a via a intermediary layer 72 , formed of the same conductive layer as that of the intermediary layer 71 , and the contact holes 181 and 182 .

[0192] Referring to FIG. 19 , the TFT array substrate 10 is provided with the pixel electrodes 9 a , and arranged on top of them is an alignment layer 19 which has been subjected to a predetermined rubbing process. The pixel electrode 9 a is fabricated of a transparent conductive film, such as an ITO (Indium Tin Oxide) film. The alignment layer 19 is fabricated of an organic thin film, such as a polyimide film.

[0193] The counter substrate 20 has a counter electrode 21 extending on the entire surface thereof, and an alignment layer 22 therebeneath that has been subjected to a predetermined rubbing process. The counter electrode 21 is fabricated of a transparent conductive film such as an ITO film. The alignment layer 22 is fabricated of an organic film such as a polyimide film.

[0194] An underlayer insulator 40 is arranged beneath the pixel switching TFT 30 . The underlayer insulator 40 is formed on the entire surface of the TFT array substrate 10 . Besides the function of assuring interlayer insulation between the lower light shield layer 400 and the TFT 30 , the underlayer insulator 40 has the function of preventing the characteristics of the pixel switching TFT 30 from being degraded by surface irregularity of the TFT array substrate 10 caused during a polishing process or dirt left after a cleaning operation.

[0195] Arranged on the scanning line 3 a is the first interlayer insulator 41 through which a contact hole 182 leading to the heavily doped source region 1 d and a contact hole 83 leading to the heavily doped drain region 1 e are opened.

[0196] The intermediary layer 71 , the intermediary layer 72 , and the capacitive line 300 are formed on the first interlayer insulator 41 . Arranged on these layers are the second interlayer insulator 42 through which a contact hole 181 and the contact hole 85 , respectively leading to the intermediary layer 72 and the intermediary layer 71 , are opened.

[0197] The data line 6 a is arranged on the second interlayer insulator 42 . Formed on the data line 6 a is the third interlayer insulator 43 through which the contact hole 85 leading to the intermediary layer 71 is opened. The upper light shield layer 401 is formed on the third interlayer insulator 43 . Arranged on the upper light shield layer 401 is the fourth interlayer insulator 44 , through which the contact hole 85 is opened. The pixel electrode 9 a is deposited on the fourth interlayer insulator 44 thus constructed.

[0198] In the third embodiment as described above, the elements and lines formed in the image display area of the TFT array substrate 10 , such as the TFT 30 , the scanning line 3 a , the data line 6 a , the capacitive line 300 , and the storage capacitor 70 , are three-dimensionally light shielded by the lower light shield layer 400 , the upper light shield layer 401 , and the side wall light shield layer 402 . The lower light shield layer 400 , the upper light shield layer 401 , and the side wall light shield layer 402 prevent light rays entering the substrate vertically or obliquely from above, returning light rays entering the substrate vertically or obliquely from below, and internally reflected light or multiple reflected light in response to these light rays, from entering the channel region 1 a ′, the lightly doped source region 1 b , and the lightly doped drain region 1 c of the TFT 30 . Furthermore, as shown in FIG. 18 , the non-aperture area of each pixel is accurately defined in a grid configuration by these light shield layers.

[0199] In accordance with the third embodiment, the electrically conductive, light shield layer 403 formed in the contact hole 85 reliably prevents light from entering into the vicinity of the contact hole 85 which is subject to light ingress. The contact hole 85 is allowed to open at a center position between the TFT 30 and a TFT 30 adjoining the TFT 30 as shown in FIG. 18 . Even if a slight degree of light ingress takes place through the contact hole 85 , the light ingress point is spaced apart from the TFT 30 of interest, and most light is unable to reach the TFT 30 .

[0200] As a result, the third embodiment increases light tightness, and allows the TFT 30 with reduced leakage photocurrent leakage thereof to perform correctly switching control on the pixel electrode 9 a under severe operational conditions in which highintensity light and returning light are present. The present invention thus presents a bright and high-contrast image.

[0201] In accordance with the third embodiment, the lower light shield layer 400 is deposited on the bottom of the trench 10 cv formed in the TFT array substrate 10 , and the upper light shield layer 401 is arranged over the TFT 30 accommodated in the trench 10 cv . The side wall light shield layer 402 fills the groove extending from the upper light shield layer 401 to the lower light shield layer 400 outside the TFT 30 .

[0202] The TFT 30 is reliably three-dimensionally light shielded in a relatively simple construction using a relatively simple manufacturing process such as an etching step and a film formation step as in the manufacturing method in the first embodiment. In the third embodiment, the upper light shield layer 401 and the side wall light shield layer 402 may be integrally formed as in the first and the second embodiment. For example, the upper light shield layer 401 may be laminated to fill the groove after the groove has been formed.

[0203] In the third embodiment, the light shield layer may be arranged on the counter substrate 20 in an area thereof facing the contact hole 85 . In this arrangement, light ingress in the vicinity of the contact hole 85 is further reduced.

[0204] The semiconductor layer 1 a forming the pixel switching TFT 30 in the third embodiment may be a non-monocrystal layer or a monocrystal layer. A known technique such as an alignment method may be applied for the formation of the monocrystal layer. With the semiconductor layer 1 a formed of a monocrystal layer, the performance of the peripheral circuits is increased.

[0205] (Fourth Embodiment)

[0206] The electrooptical device of a fourth embodiment of the present invention is discussed, referring to FIG. 21 . FIG. 21 is a cross-sectional view of the electrooptical device of the fourth embodiment, corresponding to the cross section at line E-E′ in FIG. 18 .

[0207] In the fourth embodiment, as shown in FIG. 21, a trench 10 cv ′ formed in the TFT array substrate 10 is deeper, the lower light shield layer 400 is deposited on the bottom and the tapered side walls of the trench 10 cv ′. An upper light shield layer 401 ′ is arranged covering the large trench 10 cv ′. No side wall light shield layer is not arranged. The rest of the construction of the fourth embodiment remains unchanged from that of the third embodiment.

[0208] In accordance with the fourth embodiment, the TFT 30 and wiring are reliably three-dimensionally light shielded in a relatively simple construction using a relatively simple manufacturing process.

[0209] By adjusting the depth of the trench 10 cv ′, the underlayer of the pixel electrode 9 a in an area where the TFT 30 and the wiring are arranged, i.e., the surface of the fourth interlayer insulator 44 ′ is planarized. In this way, orientation defects of the liquid crystal attributed to steps on the surface thereof are reduced.

[0210] (Fifth Embodiment)

[0211] The electrooptical device of a fifth embodiment of the present invention is now discussed, referring to FIG. 22 . FIG. 22 is a cross-sectional view of the electrooptical device of the fifth embodiment, corresponding to the cross section taken along line E-E′ in FIG. 18 .

[0212] Referring to FIG. 22 , the fifth embodiment is different from the third embodiment in that no trench is formed in the TFT array substrate 10 , and that a side wall light shield layer 402 ″ is deposited in a groove which is accordingly formed deeper. With no trench formed, the lower light shield layer 400 ″ is flat, and the presence of the layers from the underlayer insulator 40 ″ to the data line 6 a to the upper light shield layer 401 ″ causes the surface of the fourth interlayer insulator 44 ″ to be raised in a ridge. The rest of the construction of the fifth embodiment remains unchanged from that of the third embodiment. Although not shown in FIG. 22 , the fourth interlayer insulator 44 ″ is also raised in a ridge along the scanning line 3 a.

[0213] In accordance with the fifth embodiment, the TFT 30 and the wiring are reliably three-dimensionally light shielded in a relatively simple construction using a relatively simple manufacturing process.

[0214] (Sixth Embodiment)

[0215] The electrooptical embodiment of a sixth embodiment is discussed, referring to FIG. 23 . FIG. 23 is a plan view of a plurality of pixel electrodes diagrammatically showing the relationship between the polarity of a driving voltage in each pixel and a generation area of a transverse electric field in an electrooptical device of the sixth embodiment of the present invention during a scanning line alternating driving operation.

[0216] Referring to FIG. 23 ( a ), during the presentation of a n-th (n is a natural number) field video signal or frame video signal, the polarity of the liquid crystal driving voltage represented by + or − in each pixel electrode 9 a is not inverted, and the pixel electrodes 9 a are driven by the same polarity on a row by row basis. Referring to FIG. 23 ( b ), during the presentation of a (n+1)th field video signal or frame video signal, the voltage polarity of the liquid-crystal driving voltage in the pixel electrodes 9 a is inverted, and during the presentation of the (n+1)-th field or frame video signal, the polarity of the liquid-crystal driving voltage represented by + or − in each pixel electrode 9 a is not inverted, and the pixel electrodes 9 a are driven by the same polarity on a row by row basis. The states shown in FIG. 23 ( a ) and FIG. 23 ( b ) are repeated with the period of field and frame, and the device is driven in the scanning line alternating driving method in this embodiment. As a result, in accordance with this embodiment, the device is free from the degradation of the liquid crystal through the application of the direct current while presenting an image with reduced cross talk and reduced flickering. The scanning line alternating driving method outperforms the data line alternating driving method in that almost no vertical cross talk is presented, and the scanning line alternating driving method outperforms the dot alternating driving method in that an area suffering from the transverse electric field is substantially small.

[0217] Referring to FIG. 23 ( a ) and FIG. 23 ( b ), in the scanning line alternating driving method, the generation area C 1 of the transverse electric field is always located in the spacing between pixel electrodes 9 a adjacent in a direction of columns (a Y direction).

[0218] In accordance with the sixth embodiment, as in the fifth embodiment, no trench is formed in the generation area C 1 of the transverse electric field present in the gap area between the pixels along the scanning line 3 a . A ridge is formed on the underlayer beneath the pixel electrode 9 a . In the gap area, between the pixels, along the data line 6 a , where no transverse electric field takes place, a deep trench is formed in the TFT array substrate 10 as in the fourth embodiment to planarize the underlayer beneath the pixel electrode 9 a.

[0219] In accordance with the sixth embodiment, the use of the scanning line alternating driving method prevents the electrooptical material from being degraded by the application of a direct current voltage, while controlling cross-talk and flickering in a presented image. The longitudinal electric field is strengthened by raising the underlayer in a ridge beneath the pixel electrode 9 a in the generation area C 1 of the transverse electric field. The transverse electric field is thus relatively weakened. This arrangement reduces the orientation defects of the liquid crystal due to the transverse electric field.

[0220] The underlayer beneath the pixel electrode 9 a is planarized by forming the deep trench in the gap area where no transverse electric field takes place.

[0221] This arrangement reduces the orientation defect of the liquid crystal due to the step in the underlayer beneath the pixel electrode 9 a.

[0222] As a result, the operational fault attributed to the transverse electric field in the electrooptical material such as a liquid crystal is substantially reduced, while a high-contrast, high-quality and bright image is thus presented.

[0223] When the data line alternating driving method is adopted instead of the scanning line alternating driving method, the longitudinal electric field is strengthened in the gap area, between pixels, extending along the data line 6 a , namely, the generation area of the transverse electric field. To this end, the underlayer extending along the data line 6 a is raised in a ridge while the underlayer beneath the pixel electrode 9 a extending along the scanning line 3 a is planarized. When the dot alternating driving method is adopted, the underlayer beneath the pixel electrode 9 a is raised in a ridge in the areas along the scanning line 3 a and the data line 6 a in order to strengthen the longitudinal electric field in the gap areas between the pixels extending along the scanning line 3 a and the data line 6 a , namely the generation area of the traverse electric field.

[0224] In the scanning line alternating driving method of this invention, the polarity of the driving voltage may be inverted every row, every two adjacent rows, or every plural number of adjacent rows. Similarly, the polarity of the driving voltage may be inverted every column, every two adjacent columns, or every plural number of adjacent columns in the data line alternating driving method of the present invention. In the dot alternating driving method, the polarity of the driving voltage may be inverted every block composed of a plurality of pixel electrodes.

[0225] (General Construction of the Electrooptical Device)

[0226] The general construction of the electrooptical device in each of the above embodiments will now be discussed, referring to FIG. 24 and FIG. 25 . FIG. 24 is a plan view of the electrooptical device 100 with elements formed thereon, viewed from the counter substrate 20 . FIG. 25 is a cross-sectional view of the electrooptical device including the counter substrate 20 taken along line H-H′ in FIG. 24 .

[0227] Referring to FIG. 24 , the TFT array substrate 10 is provided with a sealing material 52 along the edge thereof, and a third light shield layer 53 as a display peripheral outline, fabricated of the same material as that of the light shield layer extends along the internal edge of the sealing material 52 . A data line driving circuit 101 and external-circuit interconnect terminals 102 are arranged on one side of the TFT array substrate 10 , being external to the area of the sealing material 52 , and scanning line driving circuits 104 are arranged on two sides adjacent to the one side of the TFT array substrate 10 . If a delay in the scanning signal supplied to the scanning line 3 a presents no problem, the scanning line driving circuit 104 may be mounted only on one side. Data line driving circuits 101 may be arranged on both sides of the image display area. For instance, odd data lines 6 a may be supplied with the video signal by the data line driving circuit arranged on one side of the image display area, and even data lines 6 a may be supplied with the video signal by the data line driving circuit arranged on the opposite side of the image display area. If the data lines 6 a are driven in such an interdigital fashion, the formation area of the data line driving circuits 101 is expanded, and a complex circuit may be incorporated therewithin. Arranged on the remaining one side of the image display area of the TFT array substrate 10 is a plurality of wire 105 for connecting the scanning line driving circuits 104 mounted on the both sides of the image display area. A conductive material 106 for electrically connecting the TFT array substrate 10 to the counter substrate 20 is mounted at least at one corner of the counter substrate 20 . Referring to FIG. 25 , the counter substrate 20 having almost the same outline as that of the sealing material 52 shown in FIG. 24 is bonded to the TFT array substrate 10 through the sealing material 52 .

[0228] Besides the data line driving circuits 101 and the scanning line driving circuit 104 , the TFT array substrate 10 may be provided with a sampling circuit for applying the video signal to the plurality of the data lines 6 a at a predetermined timing, a precharge circuit for supplying a precharge signal at a predetermined voltage level to the plurality of the data lines 6 a prior to the application of the video signal, and a test circuit for checking the quality and defects of the electrooptical device in the middle of the production or at the shipment thereof. The sampling circuit, the precharge circuit, and the test circuit may be arranged in an area beneath the light shield layer 53 .

[0229] In each of the above-referenced embodiments, the data line driving circuit 101 and the scanning line driving circuit 104 may be electrically and mechanically connected to a driver LSI mounted on a TAB (Tape Automated Bonding board), through an anisotropically electrically conductive film arranged in the vicinity of the TFT array substrate 10 , instead of mounting the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10 . Arranged on the light incident side of the counter substrate 20 and the light exit side of the TFT array substrate 10 are respectively polarizer films, retardation films, and polarizer means in predetermined directions to work with operation modes of the liquid crystal 50 such as a TN (twisted nematic) mode, a VA (Vertically Aligned) mode, or a PDLC (Polymer Dispersed Liquid Crystal) mode, and normally white mode/normally black modes.

[0230] The electrooptical device thus constructed may be used in a projection-type display apparatus (a liquid-crystal projector). Three panels of the electrooptical devices 100 are used as RGB light valves, and each light valve receives each color light separated through RGB color separating dichroic mirrors. In each of the above embodiments, the electrooptical device 100 is equipped with no color filter.

[0231] Optionally, an RGB color filter may be arranged in a predetermined area facing the pixel electrode 9 a , on the counter substrate 20 along with a protective film. In this way, the liquid-crystal display device of each embodiment finds applications in a direct viewing or reflective type color liquid-crystal television, besides the liquid-crystal projector. Microlenses may be arranged on the counter substrate 20 on a one microlens per pixel basis. A color filter layer may be formed of a color resist beneath the pixel electrodes 9 a facing the RGB on the TFT array substrate 10 . In this way, condensation efficiency of the incident light is increased, and a liquid-crystal display device provides a bright image . By laminating interference layers having different refractive indexes on the counter substrate 20 , a dichroic filter for creating the RGB colors is formed taking advantage of interference of light. The counter substrate with such a dichroic filter allows a liquid-crystal display device to provide an even brighter image.

[0232] An example of the pixel switching TFT used in each pixel is a positive stagger type or coplanar type polysilicon TFT as explained earlier. Other types of TFTs including a reverse stagger type TFT or an amorphous silicon TFT may be used for other pixel switching TFT.

[0233] (Projection-type Display Apparatus)

[0234] Discussed next is an embodiment of a projection-type color display apparatus as one example of electronic equipment incorporating the above-referenced electrooptical device as a light valve as shown in FIG. 26 and FIG. 27 .

[0235] Referring to FIG. 26 , the circuit arrangement of the projection-type color display apparatus of this embodiment will now be discussed. FIG. 26 shows the circuit arrangement of one of the three light valves in the projection-type color display apparatus. Since the three light valves basically have the same structure, only one of these valves is discussed. Precisely speaking, however, the three light valves are driven by different input signals (namely, R, G, and B signals). Furthermore, the circuit arrangement of the G light valve changes the order of the video signal to be presented in reverse order within each field or each frame, in comparison with the R and B video signals, or reverses the direction of the horizontal scanning or the vertical scanning.

[0236] As shown in FIG. 26 , the projection-type color display apparatus includes a display information output source 1000 , a display information processing circuit 1002 , a drive circuit 1004 , the above liquid crystal device 100 , a clock generator circuit 1008 , and a power source circuit 1010 . The display information output source 1000 includes a memory, such as a ROM (Read Only Memory), a RAM (Random Access Memory), or an optical disk, and a tuning circuit for outputting a video signal by tuning to the video signal, and outputs, to the display information processing circuit 1002 , display information such as a video signal in a predetermined format in response to a clock signal from the clock generator circuit 1008 . The display information processing circuit 1002 includes a variety of known processing circuits such as an amplifier and polarity reversal circuit, a serial-to-parallel converter circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and successively generates a digital signal from display information input in response to the clock signal, and then outputs, to the drive circuit 1004 , the digital signal along with the clock signal CLK. The drive circuit 1004 also drives the liquid crystal device 100 . The power source circuit 1010 supplies predetermined power to each of the above circuits. The driving circuit 1004 may be mounted on the TFT array substrate of the electrooptical device 100 , and further, the display information processing circuit 1002 may also be mounted on the TFT array substrate.

[0237] Referring to FIG. 27 , the general construction of the projection-type color display apparatus of this embodiment will now be discussed (from the standpoint of optical structure). FIG. 27 is a diagrammatic cross-sectional view of the projection-type color display apparatus.

[0238] Referring to FIG. 27, a liquid-crystal projector 1100 as one example of the projection-type color display apparatus of this embodiment includes three liquid-crystal modules, each including the electrooptical device 100 having the driving circuit 1004 on the TFT array substrate. The liquid-crystal projector 1100 thus includes light valves 100 R, 100 G, and 100 B for RGB colors. When light is emitted from a lamp unit 1102 as a white light source such as a metal halide lamp in the liquid-crystal projector 1100 , the light is separated into three RGB color beams through three mirrors 1106 and two dichroic mirrors 1108 , and the three color light beams are then guided to respective light valves 100 R, 100 G, and 100 B. The blue color beam travels along a path longer than those for the red and green color beams, and to prevent loss, the blue color beam is guided through a relay lens system 1121 , comprising an incident lens 1122 , a relay lens 1123 , and an exit lens 1124 . The red, green, and blue light beams respectively color-modulated by the light valves 100 R, 100 G, and 100 B are incident on a dichroic prism 1112 , thereby synthesizing the three color images, and a synthesized color image is then projected by a projection lens 1114 onto a screen 1120 .

[0239] The present invention is not limited to the above-referenced embodiments, and modifications are possible within the scope of the present invention as in the claims and the specification, and the electrooptical device, the projection-type display apparatus, and the method of manufacturing the electrooptical device, with such modifications accordingly fall within the scope of the present invention. Industrial Applicability

[0240] An electrooptical device of the present invention assures light tightness, and presents a bright, high-quality image. The electrooptical device of the present invention may be used as a display apparatus comprising a display area of a variety of electronic equipment, besides a projection-type display apparatus, such as a liquid crystal display television, a viewfinder type or direct monitoring type video cassette recorder, a car navigation system, an electronic pocketbook, an electronic tabletop calculator, a word processor, a workstation, a mobile telephone, a video phone, a POS terminal, and an apparatus having a touch panel.