DISCLOSURE OF INVENTION

[0013] By forming a bilayer interpoly dielectric having a high dielectric constant, a low defect density and less interface traps, the reliability of the interpoly dielectric layer can be increased in flash memory cells. While not wishing to be bound to any theory, it is believed that by forming a bilayer interpoly dielectric according to the present invention, it is consequently possible to prevent charge leakage from the floating gate to the control gate and facilitate Fowler-Nordheim electron tunneling thereby enhancing the erase operation. It is also possible to increase the coupling ratio by providing an interpoly dielectric layer with a high dielectric constant. The markedly increased coupling ratio leads to reduced applied voltage requirements which, in turn, leads to longer life of flash memory cells made in accordance with the present invention.

[0014] According to the present invention, a bilayer interpoly dielectric instead of an ONO dielectric layer (an oxide/nitride/oxide multilayer dielectric layer) is formed between the floating gate and the erase gate of a flash memory cell. The bilayer interpoly dielectric contains an oxide layer and a tantalum pentoxide layer.

[0015] An oxide layer is initially formed over the first polysilicon layer (floating gate). Any method may be employed so long as the temperature is maintained below about 950° C. In a preferred embodiment, the temperature is maintained below about 925° C. and even more preferably below about 900° C. when forming the oxide layer of the bilayer interpoly dielectric. The relatively low temperature does not degrade or increase the grain size of the first polysilicon layer.

[0016] In one embodiment, the deposition is conducted at a temperature from about 600° C. to about 850° C. and a pressure from about 400 mTorr to about 800 mTorr via low pressure chemical vapor deposition (LPCVD). In another embodiment, the deposition is conducted at a temperature from about 700° C. to about 800° C. and a pressure from about 500 mTorr to about 700 mTorr via LPCVD.

[0017] In one embodiment, the oxide layer is deposited using chemical vapor deposition (CVD) techniques, and particularly using from about 10 sccm to about 30 sccm SiH ₄ , about 0.5 l to about 2 l N ₂ O, and optionally a carrier gas. In another embodiment, the oxide layer may be deposited using from about 15 sccm to about 25 sccm SiH ₄ , about 1 l to about 1.5 l N ₂ O, and optionally a carrier gas.

[0018] In one embodiment, the oxide layer has a thickness from about 30 Å to about 70 Å. In another embodiment, the oxide layer has a thickness from about 40 Å to about 60 Å. The oxide layer has a thickness suitable to minimize or prevent subsequent processing, such as the formation of the tantalum pentoxide layer, from deleteriously effecting the first polysilicon layer. In particular, the oxide layer has a thickness suitable to minimize or prevent oxidation of the first polysilicon layer during formation of the tantalum pentoxide layer.

[0019] A tantalum pentoxide layer is formed by CVD and specifically LPCVD over the oxide layer. The tantalum pentoxide layer is a high K (high dielectric constant) tantalum pentoxide layer. That is, the dielectric constant of the tantalum pentoxide layer made in accordance with the present invention is at least about 15. In another embodiment, the dielectric constant of the tantalum pentoxide layer made in accordance with the present invention is at least about 20. In yet another embodiment, the dielectric constant of the tantalum pentoxide layer made in accordance with the present invention is at least about 25.

[0020] Forming the tantalum pentoxide by CVD is conducted at a temperature below about 700° C., and typically from about 200° C. to about 650° C. and a pressure from about 200 mTorr to about 600 mTorr. In another embodiment, the temperature is from about 300° C. to about 600° C. and the pressure is from about 250 mTorr to about 500 mTorr. In a preferred embodiment, the temperature is from about 400° C. to about 500° C. and the pressure is from about 275 mTorr to about 400 mTorr.

[0021] The gas flow includes an organic tantalum compound such as Ta(OC ₂ H ₅ ) ₅ and oxygen compound such as O ₂ . Although not generally required, the gas flow may optionally include one or more inert gases such as a noble gas or nitrogen. Nobles gases include He, Ne, Ar, Kr, and Xe. In one embodiment, however, the formation of the tantalum pentoxide layer is conducted in the absence of Ar. The gas flow generally contains a sufficient amount of Ta(OC ₂ H ₅ ) ₅ and O ₂ to form a tantalum pentoxide layer (a Ta ₂ O ₅ layer). During CVD, it is believed that the following chemical reaction takes place.

2Ta(OC ₂ H ₅ ) ₅ +30O ₂ →Ta ₂ O ₅ +20CO ₂ +25H ₂ O

[0022] In one embodiment, the gas flow contains from about 5 mg/min to about 20 mg/min of the organic tantalum compound, from about 500 standard cubic centimeters per minute (sccm) to about 2,000 sccm of the oxygen compound and from about 200 sccm to about 600 sccm of the carrier gas, when present. In another embodiment, the gas flow contains from about 6 mg/min to about 15 mg/min of the organic tantalum compound, from about 750 sccm to about 1,500 sccm of the oxygen compound and from about 250 sccm to about 500 sccm of the carrier gas, when present.

[0023] After depositing the tantalum pentoxide layer by CVD, rapid thermal nitridation (RTN) is performed. RTN of the tantalum pentoxide layer is preferably conducted in an N ₂ O atmosphere. An N ₂ O atmosphere includes at least about 95% N ₂ O (an inert gas constituting any remainder), preferably at least about 99% N ₂ O, and more preferably about 100% N ₂ O. In one embodiment, RTN is conducted at a temperature from about 700° C. to about 875° C. In a preferred embodiment, RTN is conducted at a temperature from about 750° C. to about 850° C. It is noted that, analogous to the oxide layer, the temperature associated with forming the tantalum pentoxide layer including RTN is maintained below about 950° C. In a preferred embodiment, the temperature is maintained below about 925° C. and even more preferably below about 900° C. when forming the tantalum pentoxide layer (including RTN) of the bilayer interpoly dielectric.

[0024] In one embodiment, RTN is conducted for a time from about 40 seconds to about 80 seconds. In a preferred embodiment, RTN is conducted for a time from about 50 seconds to about 70 seconds. The RTN serves to decrease the defect density and densify the tantalum pentoxide layer. The RTN also serves to reduce charge trapping in the tantalum pentoxide layer of the completed flash memory cell. It is believed that at elevated temperatures, N ₂ O dissociates into nitrogen gas (N ₂ ) and reactive atomic oxygen. It is also believed that the reactive atomic oxygen diffuses into the CVD tantalum pentoxide layer repairing oxygen vacancies, thereby reducing the defect density and leakage current while simultaneously densifying the layer.

[0025] After CVD and RTN, the thickness of the resultant tantalum pentoxide layer formed in accordance with the present invention is from about 100 Å to about 1,500 Å. In another embodiment, the thickness of the resultant tantalum pentoxide layer formed in accordance with the present invention is from about 150 Å to about 1,000 Å. The resultant tantalum pentoxide layer has a high dielectric constant, a substantially uniform thickness and a low defect density. Since the temperatures associated with making the bilayer interpoly dielectric according to the present invention are relatively low, the resultant flash memory cells have numerous desirable and/or improved properties compared to flash memory cells made with relatively high temperatures. That is, problems associated with relatively high temperatures are minimized and/or eliminated.

[0026] Referring to FIGS. 2A to 2 H, the fabrication of a single flash memory cell is described. A plurality of flash memory cells can be formed on a semiconductor substrate, such as a silicon die, each with an N-type source region and N-type drain region formed within a P portion of the substrate and a P-type channel region interposed between the source and drain regions in accordance with the present invention. Although fabrication of one flash memory cell is described below, it will be understood by those skilled in the art that the methods described herein are applicable to mass production methods wherein two or more cells are formed.

[0027] Specifically referring to FIG. 2A, a P-type substrate 40 is provided. Thereafter, a thin tunnel oxide layer 42 is formed over the substrate 40 having a thickness of, for example, about 50 Å to about 150 Å using a thermal growth process in a dry oxidation furnace. For instance, the tunnel oxide layer 42 can be formed via dry oxidation at a temperature of about 1050° C., under an atmosphere of oxygen at about 1.33 l, HCl at about 70 cc and argon at about 12.6 l. Alternatively, the tunnel oxide can be formed from oxynitride.

[0028] Referring to FIG. 2B, a phosphorus doped polysilicon layer is deposited via CVD to form a doped polysilicon layer 44 at 530° C., 400 mTorr, SiH ₄ at 2000 sccm, and a mixture of 1% by weight PH ₃ in helium at about 22 sccm. Doping lowers the resistivity of the polysilicon rendering it conductive.

[0029] A bilayer interpoly dielectric 46 is then formed over the surface of the substrate 40 , as illustrated in FIG. 2C . This layer 46 is often called the interpoly dielectric since (as will be seen shortly) it is sandwiched between the phosphorus doped polysilicon layer (first polysilicon layer constituting the floating gate for a flash memory cell) and a second polysilicon layer which forms the control gate for the cell. The interpoly dielectric 46 is preferably a two layer region of oxide/tantalum pentoxide and typically has a total thickness from about 130 Å to about 1,570 Å. Generally speaking, the bilayer interpoly dielectric 46 is formed by depositions of oxide and tantalum pentoxide to form a dielectric layer.

[0030] Specifically referring to FIG. 2 C, an oxide layer 46 a is deposited using CVD techniques. For example, an oxide layer 46 a is deposited at a temperature of about 750° C. under SiH ₄ at 20 sccm, N ₂ O at 1.2 l, and a carrier gas and a pressure of about 600 mTorr via CVD on the first polysilicon layer. The oxide layer 46 a may have a suitable thickness, for example, from about 30 Å to about 70 Å, but typically the thickness is about 50 Å. A tantalum pentoxide layer 46 b is next formed over the oxide layer 46 a also by CVD techniques using an organic tantalum compound and an oxygen compound. For example, tantalum pentoxide is formed at a temperature of about 480° C. under O ₂ at 1,000 sccm, Ta(OC ₂ H ₅ ) ₅ at about 7.5 mg/min and He at 300 sccm and a pressure of 300 mTorr to form a tantalum pentoxide layer 46 b . Next, RTN of the CVD tantalum pentoxide layer is conducted in an N ₂ O atmosphere at a temperature of about 800° C. for about 60 seconds. The tantalum pentoxide layer 46 b may have a suitable thickness, for example, from about 100 Å to about 1,500 Å, but in this embodiment, the thickness is about 250 Å.

[0031] Referring to FIG. 2 D, the second polysilicon layer is deposited. Specifically, a phosphorus doped amorphous polysilicon layer is deposited via CVD to form a doped polysilicon layer 48 at about 530° C., 400 mTorr, SiH ₄ at 2,000 sccm, and a mixture of 1% by weight PH ₃ in helium at about 75 sccm. Alternatively, the the second polysilicon layer can be deposited by LPCVD followed by ion implantation of a dopant such as phosphorus. Doping lowers the resistivity of the polysilicon rendering it conductive.

[0032] The remaining steps are generally well known in the art and may be varied. For instance, referring to FIG. 2 E, in one embodiment a tungsten silicide layer 50 is deposited via, for example, LPCVD. The tungsten silicide layer 50 provides a lower resistance contact for improved flash memory cell performance. Poly-cap layer 52 is deposited over the tungsten silicide layer 50 . The poly-cap layer 52 is about 500 Å thick, and is formed via, for example, LPCVD. The poly-cap layer 52 can be used to prevent any potential peeling or cracking of the underlying tungsten silicide 50 . A capping layer 54 , for example, of SiON is deposited over the poly-cap layer 52 . The capping silicon oxynitride layer 54 provides an anti-reflective coating at masking and also acts as a masking layer for subsequent etching.

[0033] Referring to FIG. 2 F, suitable lithography and etching procedures are used to remove various portions of the device. After the second polysilicon layer 48 , the tungsten silicide layer 50 , the poly-cap layer 52 and the capping layer 54 have been formed (a plurality of word lines for the memory cells can be defined in this manner) etching is performed to define one or more pre-stack structures. The etching may be achieved by depositing and defining a photoresist masking layer over the entire surface of the substrate using standard lithography procedures. This is generally termed the gate mask and gate etch. Subsequently, a number of successive etching steps, such as the gate etch and the self aligned etch, are performed to define one or more stack structures 56 . This is generally termed the self aligned mask and self aligned etch.

[0034] The gate mask and gate etch are performed as follows. First, a resist (not shown) is applied, selectively exposed to radiation and developed whereby various portions removed (either the exposed or unexposed portions). Next, in one embodiment, the etching steps take place in a multi-chamber etch tool wherein a silicon oxynitride capping layer is selectively etched with a fluorinated chemistry such as CHF ₃ —O ₂ in an oxide chamber. The exposed poly-cap layer and the tungsten silicide layer are then etched with SF ₆ /HBr (or alternatively, SF ₆ /Cl ₂ or Cl ₂ —O ₂ ) and the exposed second polysilicon layer is etched with HBr—O ₂ in a poly chamber. Etching steps are preferably formed in an integrated process in which the wafers are not exposed to atmosphere when transferring the wafers from one chamber to another.

[0035] Once the second polysilicon layer 48 , the tungsten silicide layer 50 , the poly-cap layer 52 and the capping layer 54 have been removed, a self aligned etch (“SAE”) is performed to remove the bilayer interpoly dielectric 46 and the phosphorus doped polysilicon layer (first polysilicon layer) 44 in the regions that are not covered by the pre-stack structure (constituted by the unremoved second polysilicon layer, tungsten silicide layer, poly-cap layer and capping layer). The SAE etch is a two step etch process in which the bilayer interpoly dielectric 46 is first removed using, for example, an RIE etch. The second phase of the SAE etch is the removal of the exposed first polysilicon layer 44 to thereby further define the floating gate structures for each respective word line. The polysilicon etch includes, for example, an HBr—O ₂ or a HBr—Cl ₂ —O ₂ RIE etch chemistry. The gate etch and SAE serve to define the stack structure 56 .

[0036] The fabrication of the flash memory cells is then completed by forming the source and drain regions by, for example, ion implantation. During the formation of the source and drain regions, the stacked gate structure 56 serves as a self-aligning mechanism. Specifically referring to FIG. 2 G, resist 62 is applied and selectively stripped followed by performing a first ion implantation using phosphorus (1×10 ¹⁴ ions/cm ² at 60 KeV) to form an N-type source region 64 (double diffused implant). Referring to FIG. 2 H, resist 62 is removed followed by performing a second ion implantation using arsenic (5×10 ¹⁴ ions/cm ² at 40 KeV) to form deep N-type source region 66 , shallow N-type source region 68 and N-type drain region 70 (modified drain diffusion). Annealing completes the formation of the source and drain regions. In the above manner, an easy method for forming flash memory cells is provided. Although a flash memory cell with a double-diffused source region is described, the present invention is also applicable to flash memory cells with a single-diffused source region.

[0037] During programming, the source regions 66 and 68 and the substrate 40 of the memory cell may be tied to a ground via a terminal (not shown), respectively, the drain region 70 is coupled to a relatively high voltage (for example, between about +5 V to about +9 V) via a terminal (not shown) and the control gate 48 is connected to a relatively high voltage level (for example, above about +10 V) via a terminal (not shown). Electrons are accelerated from the source regions 66 and 68 to the drain region 70 and so-called “hotelectrons” are generated near the drain region 70 . Some of the hot electrons are injected through the relatively thin tunnel oxide layer 42 and become trapped in the floating gate 44 thereby providing the floating gate 44 with a negative potential.

[0038] During erasure, a high positive voltage (such as above about +12 V) is applied to the source regions 66 and 68 via a source terminal (not shown). A ground potential (V _g equals 0 V) is applied to the control gate 48 via the control terminal (not shown). A similar ground potential (V _sub equals 0 V) is applied to the substrate 40 via a substrate terminal (not shown). The voltage V _D of the drain region 70 is permitted to float. In this mode, electrons previously stored during programming in the floating gate 44 pass through tunnel oxide layer 42 by way of Fowler-Nordheim tunneling and travel into the source regions 66 and 68 as a result of the electric field established between the control gate 48 and the source regions 66 and 68 (V _GS equals about 12 V). Since the bilayer interpoly dielectric 46 is characterized by reduced charge trapping, Fowler-Nordheim tunneling and travel of electrons from the floating gate 44 to the source regions 66 and 68 are facilitated.

[0039] Although the invention has been shown and described with respect to a certain preferred embodiment or embodiments, it is obvious that equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary embodiments of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several embodiments, such feature may be combined with one or more other features of the other embodiments as may be desired and advantageous for any given or particular application.