DETAILED DESCRIPTION OF THE INVENTION

[0031] The present invention will now be described with respect to the accompanying drawings in which like numbered elements represent like parts.

[0032] Referring initially to FIG. 2, a photo-lithographic system 10 for printing a test wafer 20 is depicted. The test wafer 20 is used to produce and test circuits which will ultimately be formed on a final wafer. As best seen in FIG. 3 , in the present embodiment, the test wafer 20 is divided up into a number of test die 25 which are separated by scribe lines 30 . As is conventional, the scribe lines 30 may be either positive mesa type lines or negative lines and allows for separating the individual test die 25 from one another after completing production of the test wafer 20 . In the present embodiment, each test die is produced to have an identical circuit, however, it will be appreciated that test die having various circuit configurations could alternatively be produced.

[0033] Referring back to FIG. 2 , at this stage in the development cycle the test wafer 20 is shown to include a semiconductor substrate 22 having a feature layer 35 formed thereon and a photo-resist 40 (hereinafter “resist 40 ”) formed over the feature layer 35 . The feature layer 25 may, for example, be a film layer or a layer of polysilicon. The resist 40 is the present embodiment is a positive resist, however negative resist could alternatively be used.

[0034] In order to pattern the resist 40 , the system 10 includes an illumination source 50 that provides an appropriate amount of optical energy for transforming the resist 40 . A test reticle 55 is provided between the light source and the wafer 20 to serve as a test mask in transferring a desired pattern through an optical subsystem 60 to the resist 40 as described in more detail below. The test reticle 55 includes a glass or quartz plate 56 with a chrome layer 57 patterned thereon. The pattern formed on the test reticle 55 is provided using conventional techniques known in the art. For example, the test reticle 55 may be patterned by forming a layer of photo-resist over the chrome layer 57 and patterning the photo-resist using electron beam. The chrome layer 57 is then etched and the photo-resist removed thereby leaving behind the desired pattern. It will be appreciated that other known reflective or transmissive type reticles and corresponding pattern transfer systems could be used. Further, it will be appreciated that while the system 10 utilizes projection type printing, other printing techniques such as contact printing or proximity could alternatively be used.

[0035] The inventors of the present invention have observed that the critical dimensions (CD) of active structures produced on a test wafer vary depending on whether the active structure in located in a densely populated area of the wafer or a sparsely populated area of the wafer. Hereinafter “active structures” shall mean structures which form a part of the active or operational circuits produced on a wafer. For example, active structures may be a line that forms part of a an SRAM or transistor circuit on the wafer. It has been found that CD's related to etch bias and the slope profile of a line vary depending on whether the surrounding region is densely or sparsely populated. In particular, it has been found that structures formed in sparsely populated regions have greater slope profiles and greater negative etch bias than structures formed in densely populated regions.

[0036] For instance, referring to FIG. 4 there is shown a conventional test reticle 55 in which the test reticle 55 is divided up into four identical regions 65 for patterning four corresponding test die 25 ( FIG. 3 ) on the test wafer 20 . Dividing lines 70 between each of the four regions 65 correspond to the scribe lines 30 ( FIG. 3 ) formed on the wafer 20 . The density of test patterns at any region along the test reticle 55 is representatively depicted by the frequency of occurrence of the square blocks 75 . Accordingly, as seen in FIG. 4 , conventional test reticles 55 include both densely populated regions 80 such as that near the center of each region 65 , and sparsely populated regions 85 such as that near the edges of the test reticle 55 and near the dividing lines 70 . For example, the densely populated regions 80 may include patterns for forming MRAM or SRAM on the test wafer 20 while the sparsely populated regions 85 may include a small circuit incorporated into a test tile. While the present embodiment depicts the test reticle 55 to include four regions 65 , it will be appreciated that the test reticle 55 may include any number of regions.

[0037] Referring now to FIG. 5 a graph 90 shows the change in line width between a line formed in the densely populated die area and a line formed in a sparsely populated scribe area for various lots of wafers produced over a course of time. For example the various lots of wafers may be produced over the course of one to three days. In particular, the y-axis shown in FIG. 5 corresponds to the change in line widths, in nano-meters, between the structures formed in the densely and sparsely populated regions, and the x-axis corresponds to a given lot number. As can be seen from the graph 90 , during the course of producing various lots, the measured change between the densely and sparsely populated regions can vary significantly from one lot to the next. It was determined that such variations could be minimized by populating each region of the wafer with a uniform density of structures.

[0038] Unlike the individual test die 25 produced during the testing phase, the actual die of a final semiconductor wafer is typically densely populated with active structures across the entire die. In conventional systems, the etch bias and slope profiles determined with respect to structures included in sparsely populated regions of the test wafer 20 was not fully representative of the actual etch bias likely to occur on the densely populated die on a completed wafer. Accordingly, the present invention provides for adding dummy structures in those areas of the test die 25 which would otherwise be sparsely populated. In particular, the present invention provides for adding an adequate number of dummy structures so as to approximate the actual density of structures included at each region of a final die.

[0039] Referring now to FIG. 6 , there is depicted a dummy structure 100 of the type which could be used in conjunction with the present invention. As will be described in more detail below, a patter corresponding to the dummy structure 100 is initially formed in the test reticle 55 and transferred to the wafer 20 using photo-lithography. The dummy structure 100 of the present embodiment includes a cross pattern of horizontal and vertical lines 105 , 110 , respectively. In the present embodiment, each line 105 , 110 is approximately one to two microns in width and 10 to 20 microns in length. Further, each of the dummy structure lines 105 , 110 is situated so they do not contact any active structure and preferably are at least 10 microns away from any active structure on the test wafer 20 . In this manner the dummy structure 110 does not interfere with the active structures used in to form the circuits in the test wafer.

[0040] While the present embodiment provides a dummy structure of a particular pattern and dimension for exemplary purposes, it will be appreciated that any size and any pattern of dummy structures could alternatively be used. For instance, a dummy structure could include one or more lines which is/are oriented horizontally, vertically, bent, or otherwise. In general, the dummy structures will be sized and patterned to adequately populate sparsely populated regions of a test die to more closely emulate the density of a final die of a final wafer.

[0041] Referring now to FIG. 7, a flow chart showing the steps taken to produce and evaluate a test wafer 20 in accordance with the present invention is shown. In step 150 , a determination is made as to a feature of an integrated circuit which is to be tested. For example, the feature may be a series of transistors which are to perform a specific function on a final wafer. Next, in step 153 , a layout of the active structures needed to reproduce and test the selected feature is determined. Based on the layout showing the density of active structures on each test die, a determination is made as to the layout of additional dummy structures to be formed on the test die. As discussed above, the dummy structures are added to the layout in a manner predetermined to emulate the density of structures formed in a region of the selected feature on the final wafer. For example, if the region surrounding the selected feature on the final wafer is densely populated, then the dummy structures are added to form a correspondingly densely populated region around the feature being tested.

[0042] Once the layout of both the active and dummy structures is determined, a test reticle 130 is produced in step 160 . In order to form the test reticle 130 , the active and dummy patterns which respectively correspond to the active structures and dummy structures to be produced on the test wafer are patterned onto the test reticle 130 . For example, referring to FIG. 8 , in the present embodiment the regions of the test reticle 130 having the dummy structures formed thereon is representatively depicted by the dashed square blocks 135 . The regions of the test reticle 130 having active patterns formed thereon are depicted by solid squares 75 . Thus, as can be seen, the overall density of patterns formed in each region 65 of the test reticle 130 is substantially uniform so as to emulate in a predetermine manner the density of patterns formed in a region of a reticle used to produce the selected feature on the integrated circuit. For example, if a reticle used to produce the selected feature included a densely populated pattern around the selected feature, then dummy patterns would be correspondingly added to the test reticle 130 to produce a similar density of patterns.

[0043] Next, in step 165 , the pattern formed on the test reticle is transferred to the test wafer 20 . Formation of both the active structures and dummy structures 100 on the test wafer 20 is accomplished using conventional photo-lithographic pattern transfer techniques. In particular, the pattern formed in the test reticle 130 , which now includes dummy patterns for forming dummy structures 100 and active patters for forming active structures, is transferred to the resist 40 during exposure of the resist 40 to radiation from the illumination source 50 . Once transferred to the resist 40 , the underlying feature layer 35 is etched using conventional etching techniques.

[0044] In step 170 , the etch bias and slope profile of each active structure formed on the test wafer 20 is determined and analyzed using conventional techniques known in the art. Because the dummy structures have been added to provide uniformity in density across regions of densely populated active structures and sparsely populated active structures, etch bias and slope profile differences among structures formed on the test wafer is substantially reduced. Also, since the density of the overall structures formed on the test wafer 20 emulates the density of a final wafer, the critical dimension measurements obtained from the etched layers associated with the test wafer 20 are representative of the actual critical dimension measurements which would result from formation of a corresponding circuit on the final wafer.

[0045] The invention has been described with reference to the preferred embodiments. Obviously, modifications and alterations will occur to others upon reading and understanding the preceding detailed description. For example, while the preferred embodiments described adding a sufficient number of dummy structures to uniformly and densely populate a test wafer, it will be appreciated that such uniformity and density is not required. In particular, if a final production wafer included both densely and sparsely populated regions, then only a sufficient number of dummy structures which correspondingly provided densely and sparsely populated regions of a test wafer may be used. Additionally, while the embodiments disclosed herein refer to developing a test wafer, it will be appreciated that such dummy structures could also be added to production of a final wafer in order to obtain uniform critical dimension control. It is intended that the invention be construed as including all such modifications alterations, and equivalents thereof and is limited only by the scope of the following claims.