DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0050] 1. Overview

[0051] It should be understood that FIGS. 3 , 5 - 6 are not meant to be actual plan or cross-sectional views of any particular portion of an actual integrated circuit device or component. In the actual devices the layers will not be as regular and the thicknesses may have different proportions. The various layers in actual devices often are curved and possess overlapping edges. The figures instead show an idealized representation which is employed to depict more clearly and fully the structure and process of the invention than would otherwise be possible. Also, the figures represent only one of innumerable variations of ferroelectric devices and structures that could be fabricated using the method of the invention.

[0052] The general manufacturing steps for fabricating integrated circuits containing MOSFETs and ferroelectric capacitor elements is described in Yoshimori, U.S. Pat. No. 5,561,307, which is hereby incorporated by reference as if completely contained herein. General fabrication methods have been described in other references also. Therefore, the elements of the circuit of FIG. 3 will be simply identified here.

[0053] In FIG. 3 there is shown a cross-sectional view of an exemplary nonvolatile ferroelectric memory cell that could be fabricated according to the method of the invention. As shown in FIG. 3 , memory cell 300 includes a thin film ferroelectric layer 313 of strontium bismuth tantalum niobate having an empirical formula according to Formula (4) above. A wafer 302 may be any wafer including ruby, sapphire, quartz, or gallium arsenide, but is most preferably a commercially available silicon wafer having a thick oxide layer 303 for isolation. Wafer 302 is doped to provide source/drain regions 308 and 310 . Isolation layer 311 is preferably made of spun-on glass. Bottom electrode 312 is preferably made of sputter-deposited platinum and titanium, but any suitable conductor may be used. The platinum of bottom electrode 312 typically has a thickness in the range of 1500-3500 Å, and preferably about 2000 Å, and a titanium adhesion layer typically has a thickness in the range 200-500 Å. In accordance with the invention, thin-film ferroelectric layer 313 contains layered superlattice material having excess amounts of B-site elements to improve fatigue characteristics. Top electrode 314 typically has a thickness in the range of 1500-3500 Å, and preferably about 2000 Å thick platinum. Interlayer dielectric layer 315 , formed using conventional materials and methods, covers top electrode 314 and insulation layer 311 . Wiring layers 316 and 322 preferably comprise a conventional metallization stack having an aluminum top layer on at least one underlying adhesion and/or barrier layer, such as the combination Al/TiN/Ti or Al/TiW.

[0054] FIG. 4 depicts a schematic process diagram of process 400 for fabricating memory cell 300 of the present invention. In step 402, wafer 302 is made ready by conventional means to receive thin film ferroelectric layer 313 . Accordingly, a wafer 302 may be heated in an oxygen diffusion furnace to grow oxide layer 303 . A contact hole 307 may be formed through oxide layer 303 by ion etching or other techniques to expose wafer 302 , which is then n or p-doped by conventional means to provide source/drain regions 308 and 310 . Gate 306 is formed by conventional means. Isolation layer 311 may be deposited as spin-on glass or other conventional materials. Bottom electrode 312 is sputtered into place and annealed by conventional means. Process 400 differs from conventional processes in the formation of thin film ferroelectric layer 313 .

[0055] Step 404 includes the preparation of a liquid precursor. It is preferred to use a metal alkoxycarboxylate precursor that is prepared according to the reactions:

[0056] (5) alkoxides——M +n +n R—OH——>M(—O—R) n +n/2 H 2 ;

[0057] (6) carboxylates——M +n +n (R—COOH)——>M(—OOC—R) n +n/2 H 2 ;

[0058] (7) alkoxycarboxylates——M(—O—R′) n +b R—COOH+heat——>(R′—O—) n−b M(—OOC—R) b +b HOR;

[0059] (8) (R—COO—) x M(—O—C—R′) a +M′(—O—C—R″) b ——>(R—COO—) x M(—O—M′(—O—C—R″) b−1 ) a +a R′—C—O—C—R″; and

[0060] (9) (R—COO—) x M(—O—C—R′) a +x M′(—O—C—R″) b ——>(R′C—O—) a M(—O—M′(—O—C—R″) b−1 ) x +x R—COO—C—R″,

[0061] where M is a metal cation having a charge of n; b is a number of moles of carboxylic acid ranging from 0 to n; R′ is preferably an alkyl group having from four to 15 carbon atoms; R is an alkyl group having from three to nine carbon atoms; R″ is an alkyl group preferably having from about zero to 16 carbons; and a, b, and x are integers denoting relative quantities of corresponding substituents that satisfy the respective valence states of M and M′. M and M′ are preferably selected from the group consisting of strontium, bismuth, niobium and tantalum. The exemplary discussion of the reaction process given above is generalized and, therefore, non-limiting. The specific reactions that occur depend on the metals, alcohols, and carboxylic acids used, as well as the amount of heat that is applied.

[0062] A reaction mixture including an alcohol, a carboxylic acid, and the metals, is refluxed at a temperature ranging from about 70° C. to 200° C. for one to two days, in order to facilitate the reactions. The reaction mixture is then distilled at a temperature above 100° C. to eliminate water and short chain esters from solution. The alcohol is preferably 2-methoxyethanol or 2-methoxypropanol. The carboxylic acid is preferably 2-ethylhexanoic acid. The reaction is preferably conducted in a xylenes or n-octane solvent. The reaction products are diluted to a molarity that will yield from 0.1 to 0.3 moles of the desired strontium bismuth tantalum niobate material per liter of solution.

[0063] The layered superlattice materials that derive from process 400 work best in their intended environment of use if the liquid precursor solutions of step 404 are mixed to include an excess bismuth amount corresponding to subscript q in Formula (4). Materials for thin film ferroelectric layer 313 have been prepared to include excess bismuth amounts of 100 percent and more. Excess bismuth is preferably added in an amount ranging from five percent to ten percent of the stoichiometrically balanced amount of bismuth that is required to satisfy the Smolenskii type I formula which is shown above.

[0064] Preparation of precursors of layered superlattice compounds, in general, and particularly of strontium bismuth tantalum niobate precursors, has been described in detail in U.S. Pat. No. 5,434,102, issued Jul. 18, 1995, and U.S. Pat. No.5,559,260, issued Sept.24, 1996, which are hereby incorporated by reference as if fully contained herein, as well as in other publications.

[0065] In step 406, the precursor solution from step 404 is applied to the substrate from step 402, which presents the uppermost surface of bottom electrode 312 for receipt of thin film ferroelectric layer 313 . Application of the liquid precursor is preferably conducted by dropping one to two ml of the liquid precursor solution at ambient temperature and pressure onto the uppermost surface of bottom electrode 312 and then spinning wafer 302 at up to about 2000 RPM for about 30 seconds to remove any excess solution and leave a thin-film liquid residue. The most preferred spin velocity is 1500 RPM. Alternatively, the liquid precursor may be applied by a misted deposition technique or chemical vapor deposition.

[0066] In steps 408 and 410, the precursor is thermally treated to form a solid metal oxide having a mixed layered superlattice structure. This treating step is conducted by drying a liquid precursor film that results from step 406. In step 408, the precursor is dried on a hot plate in a dry air atmosphere and at a temperature of from about 200° C. to 500° C. for a sufficient time duration to remove substantially all of the organic materials from the liquid thin film and leave a dried metal oxide residue. This period of time is preferably from about one minute to about 30 minutes. A 400° C. drying temperature for a duration of about two to ten minutes in air is most preferred. This high temperature drying step is essential in obtaining predictable or repeatable electronic properties in the final crystalline compositions of layered superlattice material to be derived from process 400.

[0067] In step 410, if the resultant dried precursor residue from step 408 is not of the desired thickness, then steps 406 and 408 are repeated until the desired thickness is obtained. A thickness of about 1800 Å typically requires two coats of a 0.130M solution under the parameters disclosed herein.

[0068] In step 412, the dried precursor residue is annealed to form the ferroelectric thin film layer 313 of layered superlattice material (see FIG. 3 ). This annealing step is referred to as the first anneal to distinguish it from a later annealing step. The first anneal is preferably performed in oxygen at a temperature of from 500° C. to 1000° C. for a time from 30 minutes to two hours. Step 412 is more preferably performed at from 750° C. to 850° C. for 80 minutes, with the most preferred anneal temperature being about 800° C. The first anneal of step 412 most preferably occurs in an oxygen atmosphere using an 80 minute push/pull process including five minutes for the “push” into the furnace and five minutes for the “pull” out of the furnace. The indicated anneal times include the time that is used to create thermal ramps into and out of the furnace.

[0069] In step 414, the top electrode 314 is deposited by sputtering. The device is then patterned by a conventional photoetching process including the application of a photoresist followed by ion etching, as will be understood by those skilled in the art. This patterning preferably occurs before the second annealing step 416 so that the second anneal will serve to remove patterning stresses from memory cell 300 and correct any defects that are created by the patterning procedure.

[0070] The second annealing step, 416, is preferably conducted in like manner with the first anneal in step 412, taking care not to vary the annealing temperature by an amount greater than a small temperature range of from about 50° C. to 100° C. with respect to the first (e.g., 800° C.) annealing temperature. The time for the second anneal is preferably from about 20 to 90 minutes in duration, and a duration of about 30 minutes is most preferred.

[0071] Finally, in step 418, the device is completed and evaluated. The completion may entail the deposition of additional layers, ion etching of contact holes, and other conventional procedures, as will be understood by those skilled in the art. Wafer 302 may be sawed into separate units to separate a plurality of integrated circuit devices that have been simultaneously produced thereon.

[0072] FIG. 5 is a top view of an exemplary wafer on which thin film capacitors 510 , 520 and 530 fabricated on substrate 500 in accordance with the invention are shown greatly enlarged. FIG. 6 is a portion of a cross-section of FIG. 5 taken through the lines 6-6, illustrating a thin film capacitor device fabricated in accordance with the invention. A silicon dioxide layer 604 is formed on a silicon wafer 602 . A titanium adhesion layer 616 is formed on the silicon dioxide layer 604 . Then bottom electrode 620 made of platinum is sputter-deposited on adhesion layer 616 . Thin film ferroelectric layer 622 comprises layered superlattice material. Top electrode 624 is made of platinum.

[0073] The following non-limiting example sets forth preferred materials and methods for practicing the invention hereof.

EXAMPLE 1

UNIDIRECTIONAL PULSE TESTING OF A STRONTIUM BISMUTH TANTALUM NIOBATE FERROELECTRIC CAPACITOR AT ELEVATED TEMPERATURES

[0074] The polarizability and the percentage imprint after unidirectional voltage cycling at elevated temperatures were calculated using PUND-curve measurements.

[0075] A plurality of ferroelectric capacitors 600 of the type shown in FIG. 6 were formed on a silicon wafer 602 having a silicon dioxide layer 604 , a titanium adhesion layer 616 , a Pt bottom electrode 620 , and a Pt top electrode 624 . Initial precursor solutions respectively comprising strontium 2-ethylhexanoate, bismuth 2-ethylhexanoate, tantalum 2-ethylhexanoate and niobium 2-ethylhexanoate in an octane-based solvent were used to prepare a final precursor solution. The solvent n-octane was the principal solvent used.

[0076] The thin film ferroelectric layer 622 was prepared from the final liquid precursor solution. The final liquid precursor was made by mixing the initial individual metalorganic precursors for each of the metal elements corresponding to the empirical formula:

[0077] (10) Sr a Bi b (Ta c Nb d )O [9+(a−1)+(b−2)(1.5)+(c+d−2)(2.5)] ,

[0078] where b=2.18 and a, c and d were varied as indicated in Tables I and II. Formula (10) expresses the same molar ratios of elements inherent in Formula (4), but in the more familiar form of Formula (3). The molarity of the final precursor solution was approximately 0.2 moles per liter.

[0079] Ferroelectric capacitors containing the layered superlattice compound were formed from the precursor solution in general accordance with the method described in Watanabe, U.S. Pat. No. 5,434,102, which is hereby incorporated by reference as if wholly contained herein.

[0080] A series of p-type 100 Si wafers 602 were oxidized to form silicon dioxide layers 604 . An adhesion layer 616 consisting substantially of titanium was deposited on the substrate, followed by formation of a platinum bottom electrode 620 having a thickness of 300 nm. Next, the wafers were dehydrated for 30 minutes at 180° C. in low vacuum. A first spincoat of 0.2 molar solution of the strontium bismuth tantalum niobate compound was deposited on the bottom electrode 620 at about 2500-2800 rpm for 30 seconds. This was dehydrated for two minutes at 150° C., increasing to 260° C. for four minutes. The first spincoat was “pushed” into a furnace during a period of 22.5 minutes, where it was annealed at 800° C. for 10 minutes with an oxygen flowrate of six liters/minute, and then “pulled” from the furnace for 22.5 minutes. This sequence of the spincoat and anneal steps was repeated for a second spincoat. The sequence was repeated for a third spincoat, except the furnace-anneal step was performed for 60 minutes. These steps formed a thin film ferroelectric layer 622 having a thickness of 230±10 nm, as indicated in Table I. Platinum was sputter-deposited to make top electrode layer 624 with 200 nm thickness. The platinum and strontium bismuth tantalum niobate layers were ion-milled to form the capacitors, and then ashing was performed, followed by a second O 2 anneal for 30 minutes at 800° C. The capacitors had a surface area of 6940 square microns. 1

[0081] 2

[0082] Three sets of measurements were performed on each capacitor: conventional hysteresis measurements at room temperature, and two sets of PUND-switching measurements at elevated temperatures. The hysteresis measurements were used to calculate initial 2Pr values. The PUND measurements were used to calculate both polarizability and the opposite-state percentage imprint values in the capacitors after unidirectional voltage cycling. The PUND measurements show, therefore, the fatigue-effects in the capacitors.

[0083] A Hewlett Packard 8115A dual channel pulse generator and a Hewlett Packard 54502A digitizing oscilloscope were connected to a 10 −8 Farad load or. Probes were positioned to contact the bottom electrode 620 and the top ode 624 for conducting PUND switching measurements. PUND switching curves are generally plotted on graphs in terms of charge displacement, μC/cm 2 , versus time in seconds. As shown in the exemplary graph of FIG. 7 , PUND curves are generated in a well-known manner by first initializing the sample with two pulses in the negative direction, then measuring the charge across a load capacitor for a series of four voltage pulses that give the measurement its name: a positive (P) pulse, a second positive or up (U) pulse, a negative (N) pulse, and then another negative or down (D) pulse. All pulses have the same absolute amplitude. The initial negative pulses make sure the material starts with a negative polarization by switching from a linear dielectric pattern to a nonlinear ferroelectric pattern as domains in the ferroelectric material become oriented to the applied field. The first positive, “Psp” or “P”, pulse therefore switches the material to a positive polarization along side 104 of curve 100 (see FIG. 1 ). Since the sample is already polarized positively with a remnant ferroelectric charge +Pr, the second pulse “Psu” or “U” measures the change from linear dielectric loss between the remnant polarization Pr and the spontaneous polarization Ps in the positive direction. Likewise, the. “Psn” or “N” pulse measures the negative switched charge, and the “Psd” or “D” pulse measures the change from linear dielectric loss between the remnant polarization −Pr and the spontaneous polarization −Ps in the negative direction. One effect of imprinting is to impair memory readout by shifting the Psp and Psu curves towards or away from 0 μC/cm 2 . That is, as the effects of residual polarization increase as a result of fatigue from unidirectional switching, generally less charge is required to polarize the material in the same direction as switching, and more charge is required to polarize the material in the opposite direction. Another related effect is loss of the ability to store data in more than one state because the ferroelectric material can no longer retain two memory polarization states once the hysteresis curve has shifted in such a way that either Pr or −Pr reaches a value of zero.

[0084] For a standard architecture of a memory cell (but not for all architectures), the PUND curves indicate the suitability of the material for a nonvolatile ferroelectric switching memory application. Generally, it is desirable that the “P” and “N” curves are well-separated from the “U” and “D” curves, respectively, which provides a large signal in the standard architecture.

[0085] Residual polarization values are also illustrated on the curves of FIG. 7 . The switching pulse in FIG. 7 is applied during the switching time, T s , commonly named the “pulse width.” When the switching pulse voltage is removed, losses due to linear dielectric behavior cause the polarization charge in the ferroelectric material quickly to “relax” to residual values represented on the respective PUND-curves by Prp, Pru, Prn and Prd.

[0086] Two sets of PUND measurements were conducted to calculate polarization fatigue and percentage imprint resulting from unidirectional voltage cycling. In Test 1, initial PUND-measurements were made using a switching pulse amplitude of 2.7 volts with a rise time of 30 nanoseconds, a fall time of 30 nanoseconds, and a pulse width of one microsecond, with a pulse delay of 75 nanoseconds between pulses. Following the initial “before” PUND-curve measurements, the PUND measurement apparatus was used to deliver 10 10 negative square-wave voltage imprint cycles to the ferroelectric capacitors 600 . These pulses each had an imprint amplitude of six volts, and were delivered at one MHz frequency at a temperature of 75° C. The wait time was one second. Then, the “after” PUND-curve measurements were conducted as described above. The measurements were made in a test lab at ambient atmospheric pressure in Colorado Springs, Colo. In Test 2, the capacitors were subjected to 10 9 negative-polarity imprint cycles at a temperature of 125° C., where the imprint amplitude was three volts and the imprint frequency was one MHz. The PUND-curve measurements were conducted as in Test 1, except the pulse amplitude was three volts.

[0087] The polarizability remaining in each sample capacitor after fatigue-cycling was calculated by adding the absolute values of Prp and Prd from the PUND-curve data, as follows:

[0088] (11) Polarizability=Prp+[Prd]

[0089] The value (Prp+[Prd]) corresponds theoretically to the value 2Pr from an hysteresis curve. Table 1 contains the values of 2Pr from the initial, pre-cycling hysteresis measurements at room temperature and the polarizability-values calculated from PUND-curve data using formula (11). Comparison of the initial hysteresis-curve values shows generally that when the subscript for bismuth equals 2.18, the value of 2Pr improves significantly if the precursor contains relative amounts of the B-site elements, tantalum and niobium, in excess of the stoichiometrically balanced amount. For example, in wafers 1 and 2 , the subscript value, (c+d), of the B-site elements was two, that is, the stoichiometrically balanced value, and the 2Pr value was only about six μC/cm 2 . Yet, when the amount of B-site elements in the precursor solution was increased to correspond to subscript values, (c+d), of 2.05 to 2.3, the 2Pr values increased to between 12 and 18 μC/cm 2 . Comparison of the 2Pr-values with the after-cycling polarizability values shows that polarization fatigue in the capacitors of wafers 3 - 10 results in a decrease of five to 15 percent in polarizability after 10 10 cycles at 75° C., and a decrease of 15 to 30 percent after 10 9 cycles at 125° C. Noteworthy is that the calculated polarizability in the capacitors of wafers 11 and 12 actually increased as a result of the unidirectional voltage cycling. This phenomenon is referred to as the “wake-up” effect of voltage cycling. In contrast, when the ferroelectric material was made from a precursor containing excess strontium, an A-site element, as in wafers 13 - 16 , the capacitors possessed insufficient polarizability.

[0090] The percentage imprint resulting from fatigue in each capacitor was calculated by using the PUND-curve values in the following formula:

[0091] (12) % Imprint=[1−(P sn −P su ) after cycling /(P sn −P su ) before cycling ]×100

[0092] Low percentage imprint values are desired. Percentage imprint generally increases with number of voltage switching cycles and with higher temperature.

[0093] Table II contains values of percentage imprint for the experimental capacitors as calculated using formula (12). Comparison of the values shows generally that the value of percentage imprint improves if the precursor contains relative amounts of bismuth and the B-site elements, tantalum and niobium, in excess of the stoichiometrically balanced amount. The value of percentage imprint in the wafers 11 and 12 was only about six percent in Test 1, and about (−)4 percent in Test 2. Comparison of the values in Tables I and II shows that both low percentage imprint and good polarizability were obtained in wafers 11 and 12 . Thus, an amount of B-site element corresponding to subscript value, (c+d), of 2.3, which was the maximum relative amount tested, resulted in the best overall fatigue behavior in both Test 1 and Test 2.

[0094] The ratio of tantalum to niobium in the precursor was approximately 0.6/0.4 in all of the samples tested. It is believed that the desirable effects of adding excess B-site elements to the precursor are achieved also when the Ta/Nb ratio is different from 0.6/0.4. It is a feature of the invention, therefore, that good fatigue characteristics are achieved in ferroelectric elements of integrated circuits when the overall amount of B-site elements in the precursor is in excess of the stoichiometrically balanced amount, regardless of the identity of the B-site elements. In other words, the beneficial effects of excess B-site elements are achieved whether the B-site metal is tantalum, niobium, another metal, or a combination of two or more B-site metals. Another view of the invention is that the precursor used to make the ferroelectric material contains an amount of A-site element that is less than the stoichiometrically balanced amount. Thus, referring to the example, the precursor can be viewed as strontium-poor rather than Ta/Nb-rich.

[0095] There has been described a method and structure for fabricating ferroelectric integrated circuits that provide ferroelectric devices with good electrical properties even after large numbers of polarization switching cycles at elevated temperatures. It should be understood that the particular embodiments shown in the drawings and 15 described within this specification are for purposes of example and should not be construed to limit the invention which will be described in the claims below. For example, the invention contemplates that the layers 313 , 622 in FIGS. 3 and 6 may be made of any layered superlattice material included in Smolenskii's general class (A), and furthermore, may be made of any layered superlattice compound represented by general formula (1). The invention, therefore, is not limited to only strontium bismuth tantalum niobate. Rather, the invention encompasses any layered superlattice compound made from precursors containing a stoichiometrically excess amount of B-site metal or metals for the purpose of improving fatigue behavior. Thus, the invention comprises those layered superlattice compounds which can be represented by the following stoichiometrically unbalanced chemical formula:

[0096] (13) A a S b B c O [9+(a−1)+(b−2)(1.5)+(c−2)(2.5)] ,

[0097] where A represents at least one A-site element, S represents at least one superlattice generator element, B represents at least one B-site element, a≦1, b≧2, and c≧2.

[0098] Further, it is evident that those skilled in the art may now make numerous uses and modifications of the specific embodiments described, without departing from the inventive concepts. For example, now that a method and structure to provide fatigue-resistant layered superlattice material in an integrated circuit has been identified as an important part of the process for fabricating ferroelectric memory devices, this method can be combined with other processes to provide variations on the method described. It is also evident that the steps recited may in some instances be performed in a different order; or equivalent structures and process may be substituted for the various structures and processes described. Consequently, the invention is to be construed as embracing each and every novel feature and novel combination of features present in and/or possessed by the fabrication processes, electronic devices, and electronic device manufacturing methods described.