DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in which components having like or the same function will be identified by the same reference numeral for the sake of simplicity of description.

EMBODIMENT 1

SRAM Configuration

[0045] FIG. 1 is a circuit diagram illustrating an overall configuration for an SRAM according to a first embodiment of the present invention. As shown in FIG. 1 , the SRAM includes memory array 1 , row decoder 2 , column decoder 3 , column selector 4 , input/output circuit 5 , precharge circuits 6 and 7 , word drivers 8 and 9 , negative voltage generator 10 and NAND gate 11 .

[0046] The memory array 1 includes memory cells MC 1 through MC 4 , word lines WL 0 and WL 1 , two pairs of complementary bit lines BL 0 , /BL 0 and BL 1 , /BL 1 , and access transistors NT 1 a through NT 4 a and NT 1 b through NT 4 b . The memory cells MC 1 through MC 4 are arranged in matrix, or in columns and rows. The word line WL 0 is associated with the memory cells MC 1 and MC 3 , while the word line WL 1 is associated with the memory cells MC 2 and MC 4 . One pair of bit lines BL 0 , /BL 0 is associated with the memory cells MC 1 and MC 2 , while the other pair of bit lines BL 1 , /BL 1 is associated with the memory cells MC 3 and MC 4 . Each of the access transistors NT 1 a through NT 4 a and NT 1 b through NT 4 b has a low threshold voltage. Specifically, in each of these access transistors NT 1 a through NT 4 a and NT 1 b through NT 4 b , when there is a potential difference of 0 V between the gate and source of the transistor, a current of 100 pA/μm or more flows between its drain and source. The access transistor NT 1 a is connected between a data retention node (not shown in FIG. 1 ) of the associated memory cell MC 1 and the bit line BL 0 and receives a voltage on the word line WL 0 at its gate. The access transistor NT 1 b is connected between another data retention node (not shown in FIG. 1 ) of the associated memory cell MC 1 and the bit line /BL 0 and receives the voltage on the word line WL 0 at its gate. The access transistor NT 2 a is connected between a data retention node (not shown in FIG. 1 ) of the associated memory cell MC 2 and the bit line BL 0 and receives a voltage on the word line WL 1 at its gate. The access transistor NT 2 b is connected between another data retention node (not shown in FIG. 1 ) of the associated memory cell MC 2 and the bit line /BL 0 and receives the voltage on the word line WL 1 at its gate. The access transistor NT 3 a is connected between a data retention node (not shown in FIG. 1 ) of the associated memory cell MC 3 and the bit line BL 1 and receives the voltage on the word line WL 0 at its gate. The access transistor NT 3 b is connected between another data retention node (not shown in FIG. 1 ) of the associated memory cell MC 3 and the bit line /BL 1 and receives the voltage on the word line WL 0 at its gate. The access transistor NT 4 a is connected between a data retention node (not shown in FIG. 1 ) of the associated memory cell MC 4 and the bit line BL 1 and receives the voltage on the word line WL 1 at its gate. The access transistor NT 4 b is connected between another data retention node (not shown in FIG. 1 ) of the associated memory cell MC 4 and the bit line /BL 1 and receives the voltage on the word line WL 1 at its gate.

[0047] The NAND gate 11 outputs a negated logical product of a mode signal MD and a precharge control signal PRO as a precharge signal PR 1 .

[0048] The row decoder 2 includes an inverter IV 21 and two NAND gates ND 21 and ND 22 . The inverter IV 21 inverts an address signal A 1 . The NAND gate ND 21 outputs a negated logical product of the precharge signal PR 1 and the address signal A 1 as a word line select signal SW 0 . The NAND gate ND 22 outputs a negated logical product of the precharge signal PR 1 and the output of the inverter IV 21 as a word line select signal SW 1 .

[0049] The negative voltage generator 10 generates a negative voltage Vng.

[0050] The word drivers 8 and 9 together makes word line driving means as defined in the appended claims. Responsive to the word line select signal SW 0 or SW 1 , each of these word drivers 8 and 9 selectively outputs supply voltage VDD, ground voltage Vss or negative voltage Vng to the associated word line WL 0 or WL 1 .

[0051] The column decoder 3 includes an inverter IV 31 and two AND gates AD 31 and AD 32 . The inverter IV 31 inverts an address signal A 0 . The AND gate AD 31 outputs a logical product of the address signal A 0 and an access signal R/W. The AND gate AD 32 outputs a logical product of the output of the inverter IV 31 and the access signal R/W.

[0052] The column selector 4 includes inverters IV 41 and IV 42 and transfer gates TG 41 through TG 44 . The inverters IV 41 and IV 42 invert the outputs of the AND gates AD 31 and AD 32 , respectively. The transfer gates TG 41 and TG 42 are connected between the bit line BL 0 and an input/output line IO and between the bit line /BL 0 and an input/output line /IO, respectively. Responsive to the output of the AND gate AD 31 , the transfer gate TG 41 connects or disconnects the bit line BL 0 to/from the input/output line IO and the transfer gate TG 42 connects or disconnects the bit line /BL 0 to/from the input/output line /IO. In the same way, responsive to the output of the AND gate AD 32 , the transfer gate TG 43 connects or disconnects the bit line BL 1 to/from the input/output line IO and the transfer gate TG 44 connects or disconnects the bit line /BL 1 to/from the input/output line /IO.

[0053] Responsive to the access signal R/W, the input/output circuit 5 transmits data, read out on the input/output line IO or /IO, to an input/output terminal D or another data, externally input to the input/output terminal D, to the input/output line IO or /IO.

[0054] The precharge circuit 6 includes p-channel MOS transistors PT 61 through PT 63 . The p-channel MOS transistors PT 61 and PT 62 are connected between a power supply node receiving the supply voltage VDD and the pair of bit lines BL 0 and /BL 0 , respectively, and turn ON/OFF responsive to the precharge signal PR 1 . The p-channel MOS transistor PT 63 is connected between the pair of bit lines BL 0 and BL 0 and also turns ON/OFF responsive to the precharge signal PR 1 .

[0055] The precharge circuit 7 includes p-channel MOS transistors PT 71 through PT 73 . The p-channel MOS transistors PT 71 and PT 72 are connected between the power supply node receiving the supply voltage VDD and the pair of bit lines BL 1 and /BL 1 , respectively, and turn ON/OFF responsive to the precharge signal PR 1 . The p-channel MOS transistor PT 73 is connected between the pair of bit lines BL 1 and /BL 1 and also turns ON/OFF responsive to the precharge signal PR 1 .

[0056] FIG. 2 illustrates a specific configuration for the memory cells MC 1 through MC 4 shown in FIG. 1 . As shown in FIG. 2 , the memory cell MC 1 includes p-channel MOS transistors MPi a and MP b and n-channel MOS transistors MNia and MNib (where 1≦i≦4).

[0057] The p-channel MOS transistor MPia is connected between the power supply node, receiving the supply voltage VDD, and a data retention node Nia. The n-channel MOS transistor MNia is connected between the data retention node Nia and a ground node receiving the ground voltage Vss. The gates of the p- and n-channel MOS transistors MPia and MNia are connected to another data retention node Nib. The p-channel MOS transistor MPib is connected between the power supply node and the data retention node Nib. The n-channel MOS transistor MNib is connected between the data retention node Nib and the ground node. The gates of the p- and n-channel MOS transistors MPib and MNib are connected to the data retention node Nia.

[0058] In the memory cell MCi with such a configuration, a one-bit complementary data signal is stored at each of the data retention nodes Nia and Nib.

[0059] As shown in FIG. 2 , each access transistor NTia (where 1≦i≦4) is connected between the bit line BL 0 or BL 1 and its associated data retention node Nia, while each access transistor NTib is connected between the bit line /BL 0 or /BL 1 and its associated data retention node Nib.

[0060] FIG. 3 illustrates a specific configuration for the negative voltage generator 10 shown in FIG. 1 . As shown in FIG. 3 , the negative voltage generator 10 includes ring oscillator 101 , inverter 102 , capacitors C 101 through C 104 and p-channel MOS transistors PT 11 through PT 106 .

[0061] The ring oscillator 101 includes multiple inverters (not shown), which are connected together to form an odd number of stages, and outputs a signal with a predetermined oscillation frequency. The inverter 102 inverts the output signal of the ring oscillator 101 . The capacitor C 101 is connected between the output node of the inverter 102 and a node N 102 . The capacitor C 102 is connected between the output node of the inverter 102 and a node N 104 . The capacitor C 103 is connected between the output node of the ring oscillator 101 and a node N 103 . And the capacitor C 104 is connected between the output node of the ring oscillator 101 and a node N 105 .

[0062] The p-channel MOS transistor PT 101 is connected between a node N 101 and the node N 102 . The p-channel MOS transistor PT 102 is connected between the node N 102 and the ground node receiving the ground voltage Vss. The p-channel MOS transistor PT 103 is connected between the nodes N 101 and N 103 . The p-channel MOS transistor PT 104 is connected between the node N 103 and the ground node. The p-channel MOS transistor PT 105 is connected between the node N 104 and the ground node. And the p-channel MOS transistor PT 106 is connected between the node N 105 and the ground node. The gates of the p-channel MOS transistors PT 101 and PT 104 are coupled together and also connected to the node N 104 . The gates of the p-channel MOS transistors PT 102 and PT 103 are coupled together and also connected to the node N 105 . The gate of the p-channel MOS transistor PT 105 is connected to the node N 105 . And the gate of the p-channel MOS transistor PT 106 is connected to the node N 104 .

[0063] The negative voltage generator with such a configuration performs charge pumping and generates the negative voltage Vng at the node N 101 synchronously with the rise or fall of the output signal of the ring oscillator 101 .

[0064] The charge supplied to the node N 101 when the negative voltage Vng is generated is stored on the capacitor 104 shown in FIG. 4 . The capacitor 104 may be a capacitance associated with a gate oxide film, an interconnect capacitance or a coupling capacitance associated with a word line.

[0065] The potential level of the negative voltage Vng is clamped to an intermediate level between a built-in voltage level and the ground voltage level Vss by the pn junction diode 103 shown in FIG. 4 . This intermediate potential level is controllable to a desired level by a known analog technique (e.g., a combination of monitor and reference circuits). It is expected that the level is often set to a range from −0.3 V to −0.5 V in accordance with the characteristic of a GIDL current (to be described later).

[0066] FIG. 5 illustrates a specific configuration for the word drivers 8 and 9 shown in FIG. 1 . Since the word drivers 8 and 9 have the same configuration, only the word driver 8 is illustrated in FIG. 5 . As shown in FIG. 5 , the word driver 8 includes inverters IV 81 through IV 92 , NAND gate ND 81 , level shifters LS 1 and LS 2 , p-channel MOS transistor PT 81 and n-channel MOS transistors NT 81 and NT 82 .

[0067] The inverters IV 81 through IV 85 are connected in series together. The word line select signal SW 0 is supplied to the input terminal of the inverter IV 81 . The output terminal of the inverter IV 85 is connected to one of the two input terminals of the NAND gate ND 81 . The series of inverters IV 81 through IV 85 delays the word line select signal SW 0 for a predetermined amount of time and then provides the delayed signal to one of the two input terminals of the NAND gate ND 81 . The NAND gate ND 81 outputs a negated logical product of the output of the inverter IV 85 and the word line select signal SW 0 . The inverter IV 86 inverts the output of the NAND gate ND 81 . The inverter IV 87 inverts the word line select signal SW 0 . The inverter IV 88 inverts the output of the inverter IV 87 . The inverters IV 89 through IV 92 are also connected in series together. The word line select signal SW 0 is also supplied to the input terminal of the inverter IV 89 . The series of inverters IV 89 through IV 92 delays the word line select signal SW 0 for another predetermined amount of time and then outputs the delayed signal.

[0068] The level shifter LS 1 includes p-channel MOS transistors PT 91 and PT 92 , n-channel MOS transistors NT 91 and NT 92 and inverter IV 93 .

[0069] The p-channel MOS transistor PT 91 is connected between a node N 80 receiving the supply voltage VDD and a node N 82 and receives the output of the inverter IV 86 at its gate. The n-channel MOS transistor NT 91 is connected between the node N 82 and a node N 81 receiving the negative voltage Vng. The gate of the n-channel MOS transistor NT 91 is connected to a node N 83 . The inverter IV 93 inverts the output of the inverter IV 86 . The p-channel MOS transistor PT 92 is connected between the nodes N 80 and N 83 and receives the output of the inverter IV 93 at its gate. The n-channel MOS transistor NT 92 is connected between the nodes N 83 and N 81 . The gate of the n-channel MOS transistor NT 92 is connected to the node N 82 .

[0070] The level shifter LS 2 includes p-channel MOS transistors PT 93 and PT 94 , n-channel MOS transistors NT 93 and NT 94 and inverter IV 94 .

[0071] The p-channel MOS transistor PT 93 is connected between a node N 90 receiving the supply voltage VDD and a node N 92 and receives the output of the inverter IV 92 at its gate. The n-channel MOS transistor NT 93 is connected between the node N 92 and a node N 91 receiving the negative voltage Vng. The gate of the n-channel MOS transistor NT 93 is connected to a node N 93 . The inverter IV 94 inverts the output of the inverter IV 92 . The p-channel MOS transistor PT 94 is connected between the nodes N 90 and N 93 and receives the output of the inverter IV 94 at its gate. The n-channel MOS transistor NT 94 is connected between the nodes N 93 and N 91 . The gate of the n-channel MOS transistor NT 94 is connected to the node N 92 .

[0072] The p- and n-channel MOS transistors PT 81 and NT 81 are connected in series together between a power supply node receiving the supply voltage VDD and a ground node receiving the ground voltage Vss. The p-channel MOS transistor PT 81 receives the output of the inverter IV 88 at its gate. The gate of the n-channel MOS transistor NT 81 receives a voltage Va at the node N 83 . A voltage at an interconnect node between the p- and n-channel MOS transistors PT 81 and NT 81 is supplied onto the word line WL 0 .

[0073] The n-channel MOS transistor NT 82 is connected between the interconnect node N 84 and a node receiving the negative voltage Vng. The gate of the n-channel MOS transistor NT 82 receives a voltage at the node N 93 .

[0074] Hereinafter, it will be described with reference to FIG. 6 how the word driver 8 with such a configuration operates.

[0075] As shown in FIG. 6 , while the word line select signal SW 0 is in logical one state (which will be herein called “at H-level”), the levels of the voltages Va and Vb at the nodes N 83 and N 93 are equal to those of the negative voltage Vng and supply voltage VDD, respectively. Accordingly, the n-channel MOS transistors NT 81 and NT 82 are OFF and ON, respectively, and the p-channel MOS transistor PT 81 is OFF.

[0076] When the word line select signal SW 0 falls from H-level (i.e., logical one) to L-level (i.e., logical zero), the p-channel MOS transistor PT 81 turns ON. Also, the voltage Vb at the node N 93 falls to the Vng level, thereby turning OFF the n-channel MOS transistor NT 82 . As a result, the voltage at the node N 84 , i.e., the voltage on the word line WL 0 , rises from the Vng level to the VDD level.

[0077] Thereafter, when the word line select signal SW 0 rises from L-level to H-level, the p-channel MOS transistor PT 81 turns OFF. Also, synchronously with the rise of the word line select signal SW 0 , a one-shot pulse is applied as the voltage Va to the node N 83 . Responsive to the one-shot pulse, the n-channel MOS transistor NT 81 turns ON and will be kept ON for a certain period of time. As a result, the node N 84 is discharged. That is to say, the voltage on the word line WL 0 drops from the VDD level to the Vss level. After the voltage Va at the node N 83 has risen, the voltage Vb at the node N 93 rises to the VDD level, thereby turning ON the n-channel MOS transistor NT 82 . Consequently, the voltage on the word line WL 0 further drops from the Vss level to the Vng level.

[0078] As described above, the word driver 8 once gets the word line WL 0 rapidly discharged to the Vss level by the n-channel MOS transistor NT 81 . Thereafter, the n-channel MOS transistor NT 82 is turned ON, thereby redistributing the charge that has been stored on the capacitor 104 shown in FIG. 4 in such a manner that the voltage on the word line WL 0 drops from the Vss level to the Vng level. In this manner, the voltage on the word line can be pulled down at a high speed without dissipating charge in vain. That is to say, the power dissipated by the negative voltage generator 10 can be reduced.

SRAM Operation

[0079] Next, it will be described with reference to FIGS. 1 and 7 how the SRAM with such a configuration operates. FIG. 7 is a timing diagram illustrating how the SRAM shown in FIG. 1 operates. In the following description, the operation of the SRAM in (1) its normal mode and (2) its standby mode will be detailed separately.

(1) Normal Mode Operation

[0080] While the mode signal MD is at H-level, the SRAM operates in the normal mode. The “normal mode operation” herein refers to a period in which a memory cell MCi is accessed. The SRAM is controlled so that a memory cell MCi is accessed during the first half of one cycle of the precharge signal PRO and that precharging is carried out during the second half of one cycle of the precharge signal PRO in preparation for the next cycle. The precharge signal PRO is externally supplied to the SRAM synchronously with an external clock signal CLK. The external clock signal CLK is used as a reference signal for operation.

[0081] At a time t 1 , the precharge signal PR 0 falls from H-level to L-level. In response, the precharge signal PR 1 rises to H-level, and the access signal R/W also rises from L-level to H-level. To access the memory cell MC 1 , for example, as shown in FIG. 1 , the address signals A 0 and A 1 both rise to H-level. Since both of the address and precharge signals A 1 and PR 1 are now at H-level, the word line select signal SW 0 falls to L-level. In response, the word driver 8 activates the word line WL 0 and the voltage on the word line WL 0 reaches the VDD level (see FIG. 6 ). Then, the n-channel MOS transistors NT 1 a and NT 1 b turn ON, thereby connecting the data retention nodes N 1 a and N 1 b of the memory cell MCI to the bit lines BL 0 and /BL 0 , respectively (see FIG. 2 ).

[0082] On the other hand, since both of the address and access signals A 0 and R/W are now at H-level, the transfer gates TG 41 and TG 42 turn ON. As a result, the bit lines BL 0 and /BL 0 are connected to the input/output lines IO and /IO, respectively.

[0083] In reading out data from the memory cell MCi, the complementary data, stored at the data retention nodes Nia and Nib, is read out onto the bit lines BL 0 and /BL 0 and input/output lines IO and /IO and then transmitted by the input/output circuit 5 to the input/output terminal D.

[0084] In writing data on the memory cell MCI, the input/output circuit 5 transmits the data, which has been input to the input/output terminal D, through the input/output lines IO and /IO and then bit lines BL 0 and /BL 0 . As a result, the data signal, which has been read out from the memory cell MCi onto the bit line BL 0 and /BL 0 , is rewritten.

[0085] Next, at a time t 2 , the precharge signal PRO rises to H-level. In response, the precharge, access and address signals PR 1 , R/W, A 1 and A 0 all fall to L-level, and the transfer gates TG 41 and TG 42 turn OFF. Also, the word line select signal SW 0 rises to H-level so that the voltage on the word line WL 0 drops to the Vng level (see FIG. 6 ). As a result, the n-channel MOS transistors NT 1 a and NT 1 b turn OFF.

[0086] When the precharge signal PR 1 falls to L-level, the p-channel MOS transistors PT 61 through PT 63 and PT 71 through PT 73 in the precharge circuits 6 and 7 all turn ON. As a result, the two pairs of bit lines BL 0 , /BL 0 and BL 1 , /BL 1 are connected to the power supply nodes receiving the supply voltage VDD so as to be precharged to the VDD level. Furthermore, the p-channel MOS transistor PT 63 equalizes the potential levels on the bit lines BL 0 and /BL 0 with each other, while the p-channel MOS transistor PT 73 equalizes the potential levels on the bit lines BL 1 and /BL 1 with each other. In this manner, the precharge operation is completed and the SRAM is ready to the access that will be performed between times t 3 and t 4 . As for the next one cycle between the times t 3 and t 5 , the access and precharge operations will also be performed in a similar manner.

(2) Standby Mode Operation

[0087] While the mode signal MD is at L-level, the SRAM is in the standby mode. As used herein, the “standby mode” refers to a period in which memory cells are accessed one-tenth or less as frequent as the normal mode.

[0088] At a time t 5 , the mode signal MD falls from H-level to L-level and the SRAM enters the standby mode.

[0089] Once the mode signal MD has fallen to L-level, the precharge signal PR 1 is always at H-level no matter whether the precharge signal PRO is zero or one. Synchronously with the rise of the precharge signal PR 1 , the p-channel MOS transistors PT 61 through PT 63 and PT 71 through PT 73 in the precharge circuits 6 and 7 turn OFF. As a result, the two pairs of bit lines BL 0 , /BL 0 and BL 1 , /BL 1 are electrically disconnected from the power supply nodes receiving the supply voltage VDD. That is to say, the precharge operation is aborted.

[0090] Also, the word line select signals SW 0 and SW 1 are both at H-level, and the voltages on the word lines WL 0 and WL 1 are at the Vng level.

[0091] Furthermore, since the access signal R/W is at L-level, the transfer gates TG 41 through TG 44 are all OFF. As a result, the two pairs of bit lines BL 0 , /BL 0 and BL 1 , /BL 1 are electrically disconnected from the pair of input/output lines IO and /IO.

[0092] The SRAM will be kept in this standby mode until a time t 6 .

[0093] Normally, an SRAM is controlled in such a manner as to perform an access operation during the first half of one cycle and a precharge operation during the second half thereof in preparation for the next cycle. Accordingly, if the precharge operation has been aborted halfway to get the SRAM to enter the standby mode compulsorily, then the SRAM cannot start its next normal mode operation at the beginning of the first half of the next one cycle, i.e., so soon as the standby mode operation is over. However, it usually takes a several milliseconds' delay (i.e., a power stabilizing period to be described later) for a mobile electronic unit including an SRAM to return from the standby state (or standby mode) to the normal operation state (or normal mode). Accordingly, if several dummy cycles are provided for this interval, then there will be no problem because all the bit lines can be precharged completely. For that reason, dummy cycles are also provided for the SRAM of the present invention between the times t 6 and t 7 .

[0094] If no such dummy cycles were allowable, the above problem could be avoidable by changing the method of controlling the memory in such a manner that precharge is performed during the first half of one cycle and that access is performed during the second half thereof. In such a case, however, it would take a longer time after an access request has been issued and before the desired data is actually output. Accordingly, the operation like that is effective only in low-speed applications.

[0095] How current dissipated can be reduced in standby mode Next, it will be described how the current dissipated can be reduced in the standby mode. This effect will be described only on the memory cells MC 1 and MC 2 for the sake of simplicity.

[0096] In a known SRAM, the p-channel MOS transistors PT 61 through PT 63 in the precharge circuit 6 are turned ON during its standby mode operation, thereby precharging the bit lines BL 0 and /BL 0 to the VDD level shown in FIG. 8 . Also, an L-level voltage (i.e., 0 V) is supplied onto the word lines WL 0 and WL 1 . Accordingly, a leakage current II flows from the power supply nodes, receiving the supply voltage VDD, into the ground nodes of the memory cells MC 1 and MC 2 by way of the access transistors NT 1 b and NT 2 a , respectively.

[0097] This leakage current II flows from the power supply nodes into the L-level data retention nodes of all memory cells. Accordingly, a total leakage current I 1 , flowing through the entire SRAM, is obtained by multiplying together the number of memory cells and a leakage current flowing through each access transistor. Only two memory cells MC 1 and MC 2 are illustrated in FIG. 8 . However, supposing a leakage current of 0.1 μA flows through each access transistor, for example, a current of 100 mA in total flows through an SRAM including one million memory cells. If an SRAM dissipates that great amount of current in its standby mode, such an SRAM is far from being qualified for a battery-driven mobile electronic unit of a small size.

[0098] According to a technique of reducing the leakage current I 1 , a negative voltage of −0.3 V, for example, is applied to the gates of the access transistors NT 1 b and NT 2 a . In this method, the source (i.e., the L-level data retention node N 1 b or N 2 a ) and the gate of the access transistor NT 1 b or NT 2 a is reverse biased, thus reducing the leakage current I 1 .

[0099] However, since transistors have been further downsized recently, a different type of problem, or a gate-induced-drain-leakage (GIDL) current, newly arises. As shown in FIG. 9 , if the gate voltage Vgs is negative and if the drain voltage Vds is approximately equal to the supply voltage VDD, then a considerable amount of GIDL current flows. To avoid this problem, it is effective to reduce the drain voltage Vds.

[0100] If a negative voltage of −0.3 v, for example, is applied to the gate of the access transistor NT 1 b or NT 2 a , then a negative potential difference between the gate and drain thereof increases its magnitude. This is because the bit lines BL 0 and /BL 0 have been precharged to the VDD level. For example, where the supply voltage VDD is 1.5 V, the gate-drain voltage Vgd=−0.3−1.5=−1.8 V. Accordingly, a GIDL current I 2 flows unintentionally and the current dissipated in the stand-by mode cannot be reduced.

[0101] To solve this GIDL current problem, the SRAM of the first embodiment turns OFF the p-channel MOS transistors PT 61 through PT 63 and PT 71 through PT 73 of the precharge circuits 6 and 7 in the standby state so that the bit lines BL 0 , /BL 0 and BL 1 , /BL 1 are electrically disconnected from the power supply nodes receiving the supply voltage VDD.

[0102] The potential level on these pairs of bit lines BL 0 , /BL 0 and BL 1 , /BL 1 , which are electrically disconnected from the power supply nodes, is lower than the VDD level, because no power is supplied thereto from the power supply nodes. Usually, the potential level is stabilized at around an intermediate potential level (=½ VDD). Hereinafter, this phenomenon will be described with reference to FIG. 10 . FIG. 10 illustrates the p-channel MOS transistor MP 1 a , access transistors NT 1 a and NT 2 a and n-channel MOS transistor MN 2 a shown in FIG. 8 . When the precharge operation is aborted, the voltage VBN on the bit line BL 0 is stabilized at around the intermediate potential level (e.g., about 0.75 V when VDD=1.5 V). Accordingly, the drain voltage Vds 2 of the access transistor NT 2 a becomes about 0.75 V. As a result, the current I 2 b , flowing through the access transistor NT 2 a , decreases from I 2 to I 3 as shown in FIG. 9 . Also, the drain voltage Vds 1 of the access transistor NT 1 a , which is connected to the H-level data retention node N 1 a , also becomes about 0.75 V. As a result, the current I 2 a , flowing through the access transistor NT 1 a , also decreases from I 2 to I 3 as shown in FIG. 9 .

[0103] In this manner, by electrically disconnecting the bit lines BL 0 , /BL 0 and BL 1 , /BL 1 from the power supply nodes, the access transistors, connected to the L- and H-level data retention nodes, respectively, can have their source-drain voltages decreased to such a level as not causing the GIDL current problem.

[0104] As described above, according to the first embodiment, the negative voltage Vng is supplied onto the word line WL 0 or WL 1 and the bit lines BL 0 , /BL 0 and BL 1 , /BL 1 are electrically disconnected from the power supply nodes in the standby state. Thus, the current dissipated in the standby mode can be reduced while eliminating the GIDL current.

EMBODIMENT 2

[0105] As shown in FIG. 11 , an SRAM according to a second embodiment of the present invention further includes a ½ VDD generator 12 and level holders 13 and 14 in addition to all the components shown in FIG. 1 .

[0106] The ½ VDD generator 12 is a well-known circuit. Specifically, the circuit 12 receives a supply voltage VDD and generates ½ VDD, which is half as high as the supply voltage VDD.

[0107] The level holder 13 includes p-channel MOS transistors PT 131 through PT 133 . The p-channel MOS transistor PT 131 is connected between a node receiving the ½ VDD and a node N 131 and turns ON or OFF responsive to the mode signal MD. The p-channel MOS transistor PT 132 is connected between a node receiving the ½ VDD and a node N 132 and also turns ON or OFF responsive to the mode signal MD. The nodes N 131 and N 132 are connected to the bit lines BL 0 and /BL 0 , respectively. The p-channel MOS transistor PT 133 is connected between these nodes N 131 and N 132 and turns ON or OFF responsive to the mode signal MD.

[0108] The level holder 14 includes p-channel MOS transistors PT 141 through PT 143 . The p-channel MOS transistor PT 141 is connected between a node receiving the ½ VDD and a node N 141 and turns ON or OFF responsive to the mode signal MD. The p-channel MOS transistor PT 142 is connected between a node receiving the ½ VDD and a node N 142 and also turns ON or OFF responsive to the mode signal MD. The nodes N 141 and N 142 are connected to the bit lines BL 1 and /BL 1 , respectively. The p-channel MOS transistor PT 143 is connected between these nodes N 141 and N 142 and turns ON or OFF responsive to the mode signal MD.

[0109] While this SRAM is in the standby mode, the p-channel MOS transistors PT 131 through PT 133 and PT 141 through PT 143 are ON, thereby holding the potential on the pairs of bit lines BL 0 , /BL 0 and BL 1 , /BL 1 at the ½ VDD level. As a result, the current dissipated in the standby mode can also be reduced as in the first embodiment. In addition, the following effects are also attainable.

[0110] According to the first embodiment, the pairs of bit lines BL 0 , /BL 0 and BL 1 , /BL 1 are floating, and therefore the voltage levels thereof are not constant. For that reason, the precharge period needed to make the SRAM return from the standby mode to the normal mode (i.e., the dummy cycle period shown in FIG. 7 ) cannot have a fixed length.

[0111] In contrast, according to the second embodiment, the potential on the pairs of bit lines BL 0 , /BL 0 and BL 1 , /BL 1 is held at a constant level (i.e., ½ VDD level) in the standby mode. As a result, the precharge period needed to make the SRAM return from the standby mode to the normal mode (i.e., the dummy cycle period shown in FIG. 7 ) can have a fixed length.

[0112] In this embodiment, the potential on the bit lines is fixed at the ½ VDD level. Alternatively, any other constant level may be adopted so long as the level is lower than the VDD level. But the level is preferably equal to or lower than the ½ VDD level, i.e., the intermediate voltage level.

EMBODIMENT 3

[0113] FIG. 12 illustrates a configuration for a mobile electronic unit 200 according to a third embodiment of the present invention. As shown in FIG. 12 , the unit 200 includes a microprocessor 210 and a system LSI 220 . Examples of mobile electronic units like this include cell phones.

[0114] The microprocessor 210 is always ON to function as a system controller for the electronic unit 200 . Also, the microprocessor 210 supplies a mode switching signal CTA to the system LSI 220 to instruct the LSI 220 to switch the mode of operation from the normal mode into the standby mode, or vice versa.

[0115] The system LSI 220 includes control circuit 221 , SRAMs 222 and 223 , logic circuit 224 and switch 225 .

[0116] Responsive to the mode switching signal CTA supplied from the microprocessor 210 , the control circuit 221 supplies the mode signal MD to the SRAM 222 and a switching signal CTB to the switch 225 , respectively. The SRAM 222 has the same configuration as the counterpart shown in FIG. 1 and can also reduce the amount of current dissipated in the standby mode. The supply voltage VDD is always supplied to the SRAM 222 even while the SRAM 222 is in the standby mode. On the other hand, to block the leakage current from flowing in the standby mode, the SRAM 223 is supplied with no power while in the standby mode. The switch 225 is connected between a power supply node receiving the supply voltage VDD and a power supply node for the SRAM 223 and logic circuit 224 , and turns ON or OFF responsive to the switching signal CTB. Specifically, while the switch 225 is ON, the supply voltage VDD is supplied to the SRAM 223 and logic circuit 224 . On the other hand, while the switch 225 is OFF, the supply voltage VDD is not supplied thereto.

[0117] That is to say, in this system LSI 220 , power is always supplied to only the control circuit 221 and SRAM 222 that communicate with the microprocessor 210 .

[0118] Hereinafter, it will be described how the mobile electronic unit with such a configuration operates.

[0119] When the system should change its mode of operation from normal mode into standby mode (e.g., when a cell phone enters a standby state), the microprocessor 210 supplies the mode switching signal CTA to the system LSI 220 to instruct the LSI 220 to change into the standby mode. That is to say, as shown in FIG. 13 , the mode switching signal CTA falls from H-level to L-level at a time t 11 .

[0120] Synchronously with this fall of the mode switching signal CTA, the control circuit 221 negates the mode signal MD and switching signal CTB to L-level. Then, responsive to the L-level switching signal CTB, the switch 225 turns OFF. As a result, the power that has been supplied to the SRAM 223 and logic circuit 224 is interrupted. On the other hand, the SRAM 222 aborts the precharge operation in response to the L-level mode signal MD (see FIG. 7 ).

[0121] When the system returns from the standby mode to the normal mode, the mode switching signal CTA rises to H-level at a time t 12 as shown in FIG. 13 . In response, the switching signal CTB rises to H-level to turn the switch 225 ON. The mode signal MD also rises to H-level, thereby allowing the SRAM 222 to start its precharge operation. During the standby mode, the bit lines of the SRAM 222 are electrically disconnected from the power supply nodes, and have their potential levels dropped. Accordingly, it is expected that if all the bit lines were precharged at a time at the beginning of the precharge operation, a large peak current would flow. For that reason, precharging of the bit lines should preferably be started stepwise at some intervals. For example, multiple bit lines may be classified into several groups and the precharge operation on one of those groups may be started some time after the precharge operation on another has been started. It would take several milliseconds (i.e., the interval between times t 12 and t 13 shown in FIG. 13 ) for the voltage Vint to be stabilized at the VDD level after the switch 225 has turned ON. That is to say, it takes some time for the system LSI 220 to start operating stably enough. Accordingly, there is a sufficient amount of time for the SRAM 222 to return to the precharge state (i.e., the dummy cycles shown in FIG. 7 are available), and the precharge operation can be started step by step.

EMBODIMENT 4

[0122] FIG. 14 illustrates an overall configuration for an SRAM according to a fourth embodiment of the present invention. As shown in FIG. 14 , the SRAM includes memory array 1 , row decoder 2 , column decoder 3 , column selector 4 , input/output circuit 5 , precharge circuits 6 and 7 , word drivers 1401 and 1402 and NAND gate 11 . Responsive to an H-level word line select signal SW 0 or SW 1 , each of the word drivers 1401 and 1402 supplies the supply voltage VDD to its associated word line WL 0 or WL 1 . And responsive to an L-level word line select signal SW 0 or SW 1 , each of the word drivers 1401 and 1402 supplies the ground voltage Vss (=0 V) to its associated word line WL 0 or WL 1 .

[0123] Next, it will be described how the SRAM shown in FIG. 14 can reduce the current dissipated in the standby mode. This effect will be described only on the memory cells MC 1 and MC 2 for the sake of simplicity.

[0124] In the standby mode, the ground voltage Vss (=0 V) is supplied onto the word lines WL 0 and WL 1 to turn the access transistors NT 1 a, NT 1 b , NT 2 a and NT 2 b OFF. The transfer gates TG 41 through TG 44 and p-channel MOS transistors PT 61 through PT 63 and PT 71 through PT 73 also turn OFF to allow the bit lines BL 0 , /BL 0 and BL 1 , /BL 1 to be floating. However, as shown in FIG. 15, a leakage current Ix flows along a path running from a power supply node for the memory cell MC 1 to a ground node for the memory cell MC 2 by way of the p-channel MOS transistor MP 1 a , H-level data retention node N 1 a , access transistor NT 1 a, bit line BL 0 , access transistor NT 2 a, L-level data retention node N 2 a and n-channel MOS transistor MN 2 a . The leakage current Ix also flows along a path running from a power supply node for the memory cell MC 2 to a ground node for the memory cell MC 1 by way of the p-channel MOS transistor MP 2 b , H-level data retention node N 2 b , access transistor NT 2 b , bit line /BL 0 , access transistor NT 1 b , L-level data retention node N 1 b and n-channel MOS transistor MN 1 b . This is because the access transistors NT 1 a , NT 1 b , NT 2 a and NT 2 b have a low threshold voltage. The leakage current Ix holds the potential on the bit lines BL 0 and /BL 0 at a positive level, which is higher than the ground voltage Vss (=0 V) and lower than the supply voltage VDD. As a result, a negative potential difference is generated between the gate and source of the access transistors NT 1 a and NT 2 b . Accordingly, although the leakage current Ix flows through the access transistors NT 1 a and NT 2 b , the negative gate-source potential difference reduces the amount of the leakage current Ix flowing.

[0125] As described above, the leakage current Ix holds the potential on the bit lines BL 0 and /BL 0 at a positive level. However, the level is not necessarily constant, but may be close to the ground voltage Vss (=0 V). For example, the level may be 0.1 V. In that situation, each of the access transistors NT 1 a and NT 2 b has a negative gate-source voltage Vgs (i.e., −0.1 V) and a drain-source voltage Vds approximately equal to the supply voltage VDD (which is herein 1.5 V). Accordingly, a GIDL current (≈I 11 ) is unintentionally allowed to flow as shown in FIG. 16 . To avoid this GIDL current problem, the level holders 13 and 14 and ½ VDD generator 12 shown in FIG. 11 may be provided additionally. Then, as shown in FIG. 17 , the potential level VNB on the bit lines BL 0 and /BL 0 during the standby mode gets equal to the ½ VDD level, and the drain-source voltage Vds of the access transistors NT 1 a and NT 2 b gets approximately equal to the ½ VDD level (i.e., 0.75 V). As a result, the GIDL current can be reduced to a negligible level 112 as shown in FIG. 16 . Alternatively, instead of providing the level holders 13 and 14 and ½ VDD generator 12 , the bit lines BL 0 and /BL 0 may be precharged to the ½ VDD level by the precharge circuits 6 and 7 . Furthermore, the potential on the bit lines BL 0 and /BL 0 does not have to held at the ½ VDD level. Rather, the potential on the bit lines BL 0 and /BL 0 may be held at any level higher than the Vss (ground voltage) level (=0 V) and lower than the VDD (supply voltage) level so long as the GIDL current problem is avoidable.