DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] The present invention will now be described in detail with reference to the accompanying drawings.

[0035] FIGS. 2A and 2B are a plan view and a perspective view showing an electrode structure of a capacitor for a semiconductor memory device according to an embodiment of the present invention. As shown in this drawing, each surface of an electrode 52 has the same slope with respect to a substrate. The electrode 52 includes four surfaces having the same slopes except the bottom surface, and the preferred slope each surface of the electrode 52 forms with respect to the substrate (or the bottom surface) is 45 degrees. Described in more detail, FIG. 2C is a cross-sectional view taken along the line a-a in FIG. 2 A, and FIG. 2D is a cross-sectional view taken along the line b-b in FIG. 2A . Each surface of the electrode on an interlayer insulation film 51 is formed to have the same slope with respect to the substrate (not illustrated), and each electrode 52 is isolated therebetween. A dielectric thin film 53 having a predetermined thickness is formed on each isolated electrode 52 and each surface of the dielectric thin film 53 is formed to have the same slope as each surface of the electrode 52 . The dielectric thin film 53 is preferably composed of a dielectric(or ferroelectric) material such as BST or PZT.

[0036] FIGS. 3A and 3B are a plan view and a perspective view showing an electrode structure of a capacitor for a semiconductor memory device according to another embodiment of the present invention. As shown in this drawing, the central portion of an electrode 62 is etched so that each surface of the electrode 62 has the same slope with respect to a substrate, and each electrode includes eight sides having the same slopes except for the bottom surface. The preferred angle each surface of the electrode 62 forms with respect to the substrate (or the bottom surface) is 45 degrees. Described in more detail, FIG. 3C is a cross-sectional view taken along the line a-a in FIG. 3 A, and FIG. 3D is a cross-sectional view taken along the line b-b in FIG. 3A . As shown in these drawings, each surface of the electrode 62 formed on an interlayer insulation film 61 forms the same slope with respect to the substrate (not illustrated).

[0037] The electrode structure of a capacitor shown in FIGS. 2 and 3 according to the present invention has no side of the electrode perpendicular to the substrate as in the conventional electrode structure, and simultaneously, because all the surfaces of the electrode have the same slope with respect to the substrate, the problem of a dielectric film formed on the horizontal surface of the electrode having a thickness that is greater than the minimum requirements in order to obtain a minimum film thickness in the region having a low deposition rate, i.e. the perpendicular surface of the electrode, does not exist.

[0038] In the electrode structure of a capacitor according to the present invention, since each surface of the electrode forms the same slope with respect to the substrate and has no narrow space or large aspect ratio, a dielectric film having a regular thickness can be formed over an entire surface of the electrode, and a thin film having the same structure can be formed on any surface of the electrode. When a line of sight deposition such as a sputtering method is employed, the advantage of the electrode structure of a capacitor according to the present invention can be clearly seen.

[0039] In the conventional electrode structure shown in FIGS. 1A and 1B , since a high dielectric film 3 is disposed between neighboring electrodes 2 , an interference between two electrodes occurs and an electrical charge accumulated owing to the interference is dispersed and cannot produce a normal voltage. However, in the electrode structure of the capacitor according to the present invention, at the parts except the bottom portion, an interval between each electrode is distant and a plate electrode is provided therebetween to minimize an interference between electrodes.

[0040] The fabrication method for a capacitor for a semiconductor memory device according to the present invention will now be described in detail, with reference to the accompanying drawings.

[0041] FIGS. 4A through 4F are cross-sectional views showing the fabrication method for a capacitor for a semiconductor memory device according to a first embodiment of the present invention. As shown in FIG. 4 A, an interlayer insulation film 73 is formed on a substrate 71 having a transistor 72 formed thereon. On the interlayer insulation film 73 , an electrode material 75 is deposited to have a thickness of half as long as the shorter side of the two bottom sides of an electrode to be formed later on the interlayer insulation film 73 , and then a resist 76 is formed on the electrode material 75 for patterning an electrode. Here, a boundary line of the resist 76 is formed to correspond to that of a lower electrode 75 b to be formed later to form an electrode on the lower portion of the resist pattern 76 .

[0042] Then, the electrode material 75 having the resist pattern 76 formed thereon and the resist 76 are etched by a chemical dry etching. Here, as shown in FIG. 4 B, the resist 76 is isotropically etched and simultaneously the electrode material 76 is etched to strip the resist 76 . Then, as shown in FIG. 4 C, the surface portion of the electrode material 75 forms the lower electrode 75 b having surfaces with the same slope with respect to the substrate 71 .

[0043] It is most preferred to etch the resist 76 and the electrode material 75 at the same etching rate, which may be conducted by appropriately controlling the ratio of an etchant gas for etching the electrode material 75 and an etchant gas for stripping the resist 76 .

[0044] For example, when the electrode 75 composed of polycrystalline silicon is patterned by using an organic resist 76 , a chemical dry etching of using a mixture of CHF ₃ which serves as a silicon etchant gas and O ₂ for stripping the organic resist can be employed.

[0045] That is, since an isotropic etching is performed on the organic resist 76 by O ₂ , resulting in gradually narrowing the resist pattern 76 , the etching range of the electrode material 75 composed of the polycrystalline silicon and etched by the F-group generated from CHF ₃ is gradually widened. Therefore, the boundary region starting to be etched from an initial stage is much etched in proportion to a time when it is exposed to the etchant gas, and since the central portion of the resist pattern 76 is exposed to the etchant gas for less time and is less etched, the electrode material 75 is etched to have a regular sloped surface in proportion to the time for which the material 76 is exposed to the etchant gas.

[0046] Finally, when the resist 76 is completely stripped, the electrode material 75 is completely etched to expose a predetermined portion of the surfaces of the interlayer insulation film 73 formed on the lower portion of the electrode material 75 , and, as a result, as shown in FIG. 4 D, each neighboring lower electrode 75 b is electrically isolated.

[0047] Then, after the lower electrode 75 b is formed as shown in FIG. 4D, a dielectric film 80 is formed to have a regular thickness on the lower electrode 75 b as shown in FIG. 4E . The dielectric film 80 may be formed by a chemical vapor deposition (CVD) or physical vapor deposition (PVD) such as a sputtering method, which is selectively used depending on the material for the dielectric film 80 and the lower electrode 75 b.

[0048] Next, as shown in FIG. 4 F, an upper electrode 75 a is formed by a deposition on the dielectric film 80 to have a constant thickness. The upper electrode 75 a may also be formed by the CVD or PVD such as a sputtering method, which is selectively used depending on the material for the dielectric film 80 and the upper electrode 75 a.

[0049] As described above, a similar etching rate of the electrode material 75 and the resist 76 enables the electrode surfaces to have an appropriate slope. Here, by controlling the etching rate of the electrode material 75 and the resist 76 , the degree of the slope of the surfaces of the electrode is determined. That is, the etching rate of the electrode material 75 and the resist 76 can be changed by controlling the mixing rate of each etchant gas.

[0050] In the fabrication method for a capacitor for a semiconductor memory device according to the embodiment of the present invention shown in FIG. 4, a silicon oxide film or a silicon nitride film including the organic resist 76 can be used as the material for the resist 76 to etch the electrode material 75 . Reference numeral 77 represents an etched portion of the resist, and 78 a residual portion of the resist.

[0051] FIGS. 5A through 5G are cross-sectional views showing a fabrication method for a capacitor for a semiconductor memory device according to another embodiment of the present invention.

[0052] First, as shown in FIG. 5 A, an interlayer insulation film 83 is formed on a substrate 81 having a transistor 82 formed thereon, and on the interlayer insulation film 83 , an electrode material 85 is deposited to be two times as thick as a height of a lower electrode 85 c to be formed later, and then, a resist pattern 86 is formed for patterning an electrode on the electrode material 85 . Here, a width of the upper surface of the resist 86 is formed to correspond to that of a lower electrode 85 c to be formed later below the resist pattern 86 .

[0053] Then, as shown in FIG. 5B, a groove 85 a is formed to be half as deep as the thickness of the electrode material 85 in the upper surface of the electrode material 85 , and then the resist 86 is stripped. Here, the groove 85 a is formed by an anisotropic etching.

[0054] Next, as shown in FIG. 5 C, the electrode material 85 having the groove 85 a formed thereon is isotropically etched by a chemical dry etching. Here, when a projection 88 of the electrode material 85 is completely stripped, as shown in FIG. 5 D, the electrode material 85 is formed to have the same slope with respect to the substrate 81 . Then, when the etching process is continued, as shown in FIG. 5 E, the electrode material around the pattern boundary portion is completely etched to expose the interlayer insulation film 83 formed on the lower portion thereof. Therefore, the lower electrode 85 c of each electrode is electrically isolated from each neighboring lower portion 88 .

[0055] Then, as shown in FIG. 5F, a dielectric film 89 is formed to have a regular thickness on the lower electrode 85 c . The dielectric film 89 may be formed by a CVD or a PVD such as a sputtering method, which is selectively used depending on the material for the dielectric film 89 and the lower electrode 85 c.

[0056] Next, as shown in FIG. 5 G, an upper electrode 85 d is formed by a deposition on the dielectric film 89 to have a constant thickness. The upper electrode 85 d may also be formed by a CVD or PVD such as a sputtering method, which is selectively used depending on the material for the dielectric film 89 and the upper electrode 85 d.

[0057] In the fabrication method for a capacitor for a semiconductor memory device according to the embodiment of the present invention shown in FIG. 5 , the material for the upper and lower electrodes 85 d , 85 c is composed of a polycrystalline silicon, a precious metal such as Pt or Au, a transition metal such as Ir or Ru, or a conductive oxide material such as IrO ₂ or RuO ₂ .

[0058] When the upper and lower electrodes 85 d , 85 c are composed of polycrystalline silicon, a conductive layer (not illustrated) can be formed by the CVD of a conductive material such as Pt, Au, Ir, Ru, IrO ₂ or RuO ₂ . Here, the conductive layer is selectively formed only on the upper and lower electrodes 85 d , 85 c composed of polycrystalline silicon, and thereby an electrode layer appropriate to a high dielectric film can be formed without employing an additional photo etching process.

[0059] In FIG. 5 , reference numeral 87 represents an etched portion of the electrode material 85 .

[0060] FIGS. 6A through 6G are cross-sectional views showing the fabrication method for a capacitor for a semiconductor memory device according to a third embodiment of the present invention.

[0061] First, as shown in FIG. 6 A, an interlayer insulation film 92 is formed on a substrate 91 having a transistor (not illustrated) formed thereon, and a resist pattern 94 for processing the interlayer insulation film 92 is formed on the interlayer insulation film 92 .

[0062] Next, as shown in FIG. 6B, a groove 93 is formed in the film 92 to be as high as a lower electrode to be formed later by an anisotropy etching such as a reactive ion etching (RIE), and the resist 94 is stripped to expose an upper surface and a predetermined portion of a side of the interlayer insulation film 92 having the groove 93 therebetween.

[0063] After the process of FIG. 6B is done, the exposed portion of the interlayer insulation film 92 is isotropically etched by a wet etching or a chemical dry etching. Here, each surface of the interlayer insulation film 92 , as shown in FIG. 6 C, is etched to have the same slope with respect to the substrate 91 .

[0064] Then, as shown in FIG. 6D, a lower electrode 95 having a predetermined thickness is formed by a deposition on the etched interlayer insulation film 92 , and as shown in FIG. 6 E, to electrically isolate each lower electrode 95 , the upper end portions of each of the interlayer insulation film 92 and the lower electrode 95 is cut off by using a chemical mechanical polishing (CMP).

[0065] As shown in FIG. 6F, a dielectric film having a constant thickness is formed on the lower electrode 95 , and as shown in FIG. 6 G, an upper electrode 97 having a regular thickness is formed on the dielectric film 96 .

[0066] In the fabrication method for a capacitor for a semiconductor memory device in FIG. 6 , as shown in FIG. 6 E, to electrically isolate each lower electrode 95 , an electrode of each cell can be separated by cutting off the upper end portions of each of the interlayer insulation film 92 and the lower electrode 95 by a chemical mechanical polishing (CMP). Particularly, even if Pt or Au which is a material difficult to etch is used for the lower electrode, an electrode of each cell can be easily isolated.

[0067] As described in detail above, the effects of the electrode structure of a capacitor for a semiconductor memory device and fabrication method thereof according to the invention are as follows.

[0068] Each surface of the electrode has the same slope with respect to the substrate without having a narrow space therebetween and a large aspect ratio. Therefore, a complicated formation process is not required, and no irregular surfaces having different slopes as in the conventional art exist. Thus, when a dielectric material is deposited over the entire surface of an electrode by a CVD or PVD, a dielectric film having the same structure and thickness can be obtained over the entire surface of an electrode, which enables a dielectric film to be formed as thin as reliability permits to a maximum degree, resulting in increasing the capacitance. Further, although another electrode is formed on the dielectric material and as a result, the size and space of a capacitor are decreased, no problem due to an interference between each capacitor occurs.

[0069] In particular, since each surface of the electrode has the same slope, the deposition of a high dielectric or ferroelectric thin film can be achieved although a PVD such as a sputtering is adopted which has an excellent characteristic but little practical conventional use due to its poor step coverage. When a material difficult to form by a CVD is used as in the formation of an upper electrode, the electrode can be easily formed by using a PVD such as a sputtering, and consequently the selection range of electrode materials can be effectively broadened.

[0070] Further, when a method of processing a surface of an interlayer insulation film is employed, the formation of a lower electrode and the isolation of each electrode can be realized so easily that even precious metals on which a dry etching is difficult to perform can be effectively used as a lower electrode.

[0071] Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as recited in the accompanying claims.