DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] A data transfer circuit according to the invention includes a leakage current monitor circuit for monitoring the magnitude of a leakage current in data lines by non-selected data transmission devices connected to data lines, a compensate circuit for compensating the leakage current by supplying a compensation current responsive to the detected magnitude of the leakage current upon data transfer operation through the data lines. This configuration prevents, beforehand, erroneous behaviors caused by the leakage current of non-selected data transfer devices connected to the data lines.

[0039] For example, in a semiconductor storage device, in case an off-leakage current of a non-selected memory cell flows in a data line, the magnitude of the off-leakage current is previously monitored and stored. Then, upon reading data from a selected memory cell, or upon writing data into a selected memory cell, a compensation current that compensates the detected and stored off-leakage current is generated and supplied to the data line. As a result, erroneous operation of the semiconductor storage device caused by the off-leakage current of the non-selected memory cell connected to the data line can be prevented beforehand.

[0040] Explained below are embodiments of the data transfer circuit according to the invention with reference to the drawings.

[0041] FIGS. 3A and 3B are block diagrams that show a configuration of a data transfer circuit according to the first embodiment of the invention.

[0042] The data transfer circuit according to the first embodiment has the most basic configuration for application of the data transfer circuit according to the invention to the semiconductor storage device. A leakage current monitor circuit and a leakage current compensate circuit are shown in a single block as the leakage current monitor and compensate circuit LCMCC. For simplicity of explanation and illustration, here is shown only the part of the No. 0 column.

[0043] The data transfer circuit according to the first embodiment includes word lines WL 0 , WL 1 , . . . , WLn provided in the No. 0 row to the No. n row; RAM cells CL 0 , CL 1 , . . . , CLn that are memory cells provided in the No. 0 row through the No. n row and connected to the word lines of the respective rows; a data line DL 0 provided in the No. 0 column connected to all RAM cells in the No. 0 column; and the leakage current monitor and compensate circuit LCMCC connected to the data line DL 0 to monitor and store the magnitude of a leakage current in the data line DL 0 , generate and supply to the data line DL 0 a compensation current that compensate the detected and stored leakage current upon subsequent input or output of data through the data line DL 0 .

[0044] After storage of data in respective RAM cells, the leakage current detect and compensate circuit LCMCC monitors and stores the magnitude of the leakage current in the data line DL 0 before subsequent input or output through the data line DL 0 . The magnitude of the leakage current in the data line DL 0 depends upon the data stored in respective RAM cells connected to the data line DL 0 .

[0045] For example, in the example of FIG. 3 A, assume that data “1” is stored only in the RAM cell CL 0 in the No. 0 row and the RAM cell CLn in the No. n row, and the other cells store data “0”. In the example of FIG. 3 B, assume that the RAM cell CL 0 in the No. 0 row, RAM cell CLn in the No. n row and some other RAM cells store data “1”, and the remainder RAM cells store data “0”. In this situation, as apparent from comparison between FIG. 3 A and FIG. 3 B, one with a larger number of RAM cells storing data “0” produces a larger total leakage current.

[0046] Due to the dependency of the leakage current upon data, detection and storage of the leakage current has to be carried out between storage of data to respective RAM cells and subsequent data input or output through the data line DL 0 .

[0047] Further, after storage of data in respective RAM cells, magnitude of the leakage current in the data line DL 0 depends upon the potential of the data line. Therefore, it is recommended to detect magnitude of the leakage current in the data line DL 0 as a function of the potential of the data line, so as to make a correction based on the function of the potential of the data line upon subsequent data input or output through the data line DL 0 , and generate and supply to the data line a compensation current that compensates the detected and stored off-leakage current.

[0048] FIG. 4 is a block diagram that shows a configuration of a data transfer circuit according to the second embodiment of the invention. The data transfer circuit according to the second embodiment has a more specific version of the data transfer circuit according to the first embodiment. That is, the configuration of FIG. 4 divides the leakage current monitor and compensate circuit LCMCC shown in FIGS. 3A and 3B into a leakage current monitor circuit LCMC and a leakage current compensate circuit LCCC, and connects them with an N-channel MOS transistor N, which is a transfer gate. Further, the configuration of FIG. 4 includes a capacitor connected between connection node of the N-channel MOS transistor N and the leakage current compensate circuit LCCC, and the ground connection node GND to store the magnitude of the leakage current as a function of the potential of the data line by storage of an electric charge derived from the detected leakage current and to have the leakage current compensate circuit LCCC generate a compensation current for compensating the leakage current on the basis of the potential produced by storage of the electric charge. Similarly to FIGS. 3A and 3B , FIG. 4 . also shows the configuration of the No. 0 column alone for simplicity of explanation and illustration.

[0049] For control of the leakage current monitor circuit LCMC, leakage current compensate circuit LCCC and N channel MOS transistor N, a precharge signal pre for controlling the precharge of the data line DL 0 is used. In this example, the precharge circuit controlled by the precharge signal pre is low-active. That is, the precharge circuit is activated for precharge operation when the input control signal is L (low) level. Although FIG. 4 does not show, the leakage current monitor circuit LCMC can be configured to function as the precharge circuit as well as explained later with reference to another embodiment.

[0050] The precharge circuit is supplied with a reverse precharge signal /pre (the symbol “/” prefixed to a signal label herein means a logical reversal) such that precharge operation takes place when the precharge signal becomes a H (high) level, and therefore, the reverse precharge signal /pre is input also to the leakage current monitor circuit LCMC. On the other hand, the precharge signal pre is input to the leakage current compensate circuit LCCC and the N-channel MOS transistor N.

[0051] In summary, the data transfer circuit according to the second embodiment of the invention includes: the word lines WL 0 , WL 1 , . . . , WLn provided in the No. 0 row to the No. n row; the RAM cells CL 0 , CL 1 , . . . , CLn that are memory cells provided in the No. 0 row through the No. n row and connected to the word lines of the respective rows; the data line DL 0 provided in the No. 0 column and connected to all RAM cells in the No. 0 column; the leakage current monitor circuit LCMC connected to the data line DL 0 and detecting the magnitude of the leakage current in the data line DL 0 in receipt of the reverse precharge signal during data line precharge operation; an N-channel MOS transistor N that is a transfer gate having one end connected to the leakage current monitor circuit LCMC to transfer the detected leakage current in receipt of the precharge signal during data line precharge operation; the capacitor C provided between the connection node of the other end of the N-channel MOS transistor N and the leakage current compensate circuit LCCC, and the ground connection node GND to store the magnitude of the leakage current by storage of an electric charge by the detected leakage current and generate a potential corresponding to the magnitude of the detected leakage current to a high-potential electrode; and the leakage current compensate circuit LCCC connected to the data line DL 0 and, in receipt of the precharge signal, generate a compensation current corresponding to the potential of the high-potential electrode of the capacitor C during data transfer operation through the data line DL 0 and supplies it to the data line DL 0 .

[0052] Next explained are behaviors of the data transfer circuit according to the second embodiment. When the precharge signal pre becomes the H level, i.e., when the reverse precharge signal /pre becomes the L level, simultaneously with the start of the precharge operation, the leakage current monitor circuit LCMC starts its leakage current monitor operation. Eventually, upon completion of the precharge operation, the leakage current monitor operation is also completed.

[0053] During the leakage current monitor operation, the precharge signal pre remains the H level. Therefore, the N-channel MOS transistor N remains ON. Thus the capacitor C is charged with an electric charge by the detected leakage current. Since the precharge signal pre changes from the H level to the L level upon completion of the precharge operation, at that moment, the N-channel MOS transistor N is turned OFF, charging of the capacitor C by the detected leakage current finishes, the amount of the electric charge accumulated in the capacitor C is determined, and the detected leakage current is stored. Since the magnitude of the leakage current is stored by charging the capacitor C with the detected leakage current from the data line DL 0 , magnitude of the leakage current is necessarily corrected in response to the potential of the data line DL 0 .

[0054] Upon switching of the precharge signal pre from the H level to the L level, completion of the precharge operation and storage of the detected leakage current in the capacitor C, simultaneously therewith, data read from the RAM cell or data write in the RAM cell, i.e. data transfer operation through the data line DL 0 , is started, and simultaneously therewith, leakage current compensate operation by the leakage current compensate circuit LCCC is also started. Magnitude of the compensation current is determined by the potential of the high-potential electrode of the capacitor C. The compensation current generated in response to the detected leakage current and the potential of the data line DL 0 has the same polarity as the leakage current and the oppositely equal magnitude, it compensates the leakage current, and prevents, beforehand, erroneous behaviors caused by the off-leakage current of non-selected RAM cells during data transfer operation.

[0055] The transfer gate is not limited to the N-channel MOS transistor N, but any desirable switching element such as P-channel MOS transistor, bipolar transistor, or the like, may be used.

[0056] FIG. 5 is a block diagram that shows a configuration of a data transfer circuit according to the third embodiment of the invention. The data transfer circuit according to the third embodiment has a more specific version of the data transfer circuit according to the second embodiment. Similarly to FIGS. 3A, 3B and FIG. 4 , FIG. 5 also shows the configuration of the No. 0 column alone for simplicity of explanation and illustration.

[0057] The data transfer circuit according to the third embodiment of the invention includes: the word lines WL0, WL1, . . . , WLn provided in the No. 0 row to the No. n row; the RAM cells CL0, CL1, . . . , CLn that are memory cells provided in the No. 0 row through the No. n row and connected to the word lines of the respective rows; the data line DL 0 provided in the No. 0 column and connected to all RAM cells in the No. 0 column; and a first P-channel MOS transistor P 1 with its source connected to a source potential node and its gate supplied with a reverse precharge signal; a second P-channel transistor P 2 connected between the drain of the first P-channel MOS transistor P 1 and the data line DL 0 ; a third P-channel MOS transistor P 3 with its source connected to a source potential node and its gate supplied with a precharge signal; a fourth P-channel MOS transistor P 4 connected between the drain of the third P-channel MOS transistor and the data line DL 0 ; a first N-channel MOS transistor N 1 connected between the gate and the drain of the second P-channel MOS transistor P 2 and the gate of the fourth P-channel MOS transistor P 4 and having the gate supplied with the precharge signal; and a capacitor transistor made up of a second N-channel MOS transistor with its gate connected to the gate of the fourth P-channel MOS transistor P 4 and its source and drain connected to the ground potential node.

[0058] It may be regarded that the first and second P-channel MOS transistors P 1 , P 2 and the first and second N-channel MOS transistor N 1 , N 2 correspond to the leakage current monitor circuit LCMC whereas the third and fourth P-channel MOS transistor P 3 , P 4 correspond to the leakage current compensate circuit LCCC. Alternatively, it may be regarded that the first and second P-channel MOS transistors P 1 , P 2 correspond to the leakage current monitor circuit LCMC, the third and fourth P-channel MOS transistors P 3 , P 4 correspond to the leakage current compensate circuit LCCC, the first N-channel MOS transistor N 1 corresponds to the transfer gate connecting the leakage current monitor circuit LCMC and the leakage current compensate circuit LCCC, and the second N-channel MOS transistor N 2 corresponds to a capacitor for storing an electric charge by the detected leakage current.

[0059] Next explained are behaviors of the data transfer circuit according to the third embodiment. During precharge period of the data line DL 0 , the precharge signal pre becomes the H level, and the reverse precharge signal /pre becomes the L level. Therefore, the first P-channel MOS transistor P 1 is ON, the third P-channel MOS transistor P 3 is OFF, and the first N-channel MOS transistor N 1 is ON. Further, at the start of the precharge operation, since the potential of the data line DL 0 is the L level, the second P-channel MOS transistor P 2 is ON. Since the first and second P-channel MOS transistor P 1 , P 2 are ON, the data line DL 0 is precharged, and its potential gradually increases. When VDD is the source potential and Vthp is the threshold voltage of the P-channel MOS transistor, the potential of the data line DL 0 increases only to VDD-Vthp in maximum. However, if an off-leakage current of RAM cells flows in the data line DL 0 , the potential of the data line DL 0 becomes lower than VDD-Vthp.

[0060] The potential of the data line DL 0 is transmitted to the gate of the second N-channel MOS transistor N 2 through the first N-channel MOS transistor N 1 , and an electric charge corresponding to the potential of the data line DL 0 is accumulated in the capacitor transistor made up of the second N-channel MOS transistor N 2 .

[0061] As the precharge of the data line DL 0 progresses and the potential of the data line DL 0 sufficiently rises, since the potential of the data line DL 0 is input to the gate of the second P-channel MOS transistor P 2 , the second P-channel MOS transistor P 2 turns OFF.

[0062] After that, when data read from a RAM cell in the No. 0column, or data write to the RAM cell in the No. 0 column, i.e. the period of data input/output operation through the data line DL 0 , is started, the precharge signal pre becomes the L level, the reverse precharge signal /pre becomes the H level, and the precharge operation finishes. Therefore, the first P-channel MOS transistor P 1 turns OFF, the third P-channel MOS transistor P 3 turns ON, and the first N-channel MOS transistor N 1 turns OFF.

[0063] At that time, the gate potential of the second N-channel MOS transistor N 2 is input to the gate of the fourth P-channel MOS transistor P 4 . That is, since the potential generated on the basis of the electric charge accumulated in the capacitor transistor made up of the second N-channel MOS transistor N 2 by the leakage current of the data line DL 0 is input to the gate of the fourth P-channel MOS transistor P 4 , the fourth P-channel MOS transistor P 4 turns ON to pass the compensation current of a magnitude corresponding to the leakage current of the data line DL 0 , and the compensation current flows into the data line DL 0 . As a result, the off-leakage current in the data line DL 0 is compensated by the compensation current, and erroneous behaviors of the semiconductor storage device caused by the off-leakage current can be prevented beforehand.

[0064] Strictly, it is desirable that the potential of the data line DL 0 , i.e. the drain potential of the fourth P-channel MOS transistor P 4 , is sufficiently low, and operation of the fourth P-channel MOS transistor P 4 is conducted in the saturation region. In this embodiment, since a voltage drop occurs in the second P-channel MOS transistor P 2 , the potential of the data line DL 0 is sufficiently low.

[0065] The first and third P-channel MOS transistors P 1 , P 3 may be replaced by N-channel MOS transistors. The transfer gate made up of the first N-channel MOS transistor N 1 need not be an N-channel MOS transistor, but any desired switching element such as P-channel MOS transistor, for example, may be used. The capacitor made up of the second N-channel MOS transistor N 2 need not be an N-channel MOS transistor, but any desirable capacitor may be used. Additionally, each MOS transistor may be replaced by a bipolar transistor.

[0066] FIG. 6 is a block diagram that shows a configuration of a data transfer circuit according to the fourth embodiment of the invention. Similarly to FIG. 3 A through FIG. 5 , FIG. 6 also shows the configuration of the No. 0 column alone for simplicity of explanation and illustration.

[0067] The data transfer circuit according to the fourth embodiment of the invention is an example in which each RAM cell forming a semiconductor storage device has a differential type double-end configuration, such as SRAM, for example.

[0068] Therefore, in comparison with the data transfer circuit according to the third embodiment, although they are equal in that the data line DL 0 of the No. 0 column is connected to one-side ends of RAM cells in the No. 0 column, the fourth embodiment is different from the third embodiment in further including a complementary data line DL 0 b of the No. 0 column, which is connected to the other-side ends of the RAM cells in the No. 0 column, and an additional MOS transistor circuit forming the leakage current monitor circuit LCMC and the leakage current compensate circuit LCCC also for the complementary data line DL 0 b in the No. 0 column. More specifically, it includes, also for the complementary data line DL 0 b, a fifth, a sixth, a seventh and an eighth P-channel MOS transistors P 5 , P 6 , P 7 and P 8 and a third and a fourth N-channel MOS transistors N 3 and N 4 corresponding to the first, second, third and fourth P-channel MOS transistors P 1 , P 2 , P 3 and P 4 and the first and second N-channel MOS transistors N 1 and N 2 provided on the part of the data line DL 0 . Connection of MOS transistors and input portions of the precharge signal pre and the reverse precharge signal /pre on the part of the complementary data line DL 0 b are identical to those on the part of the data line DL 0 . Operations of the leakage current monitor circuit LCMC and the leakage current compensate circuit LCCC on the part of the complementary data line DL 0 b are also identical to those on the part of the data line DL 0 .

[0069] The first, third, fifth and seventh P-channel MOS transistors P 1 , P 3 , P 5 and P 7 may be replaced by N-channel MOS transistors. The transfer gate made up of the first and third N-channel MOS transistors N 1 and N 3 need not be N-channel MOS transistors, but any desirable switching element such as P-channel MOS transistors, for example, can be used. The capacitors made up of second and fourth N-channel MOS transistors N 2 , N 4 need not be those made of N-channel MOS transistors, but any desired capacitors may be used. Further, each MOS transistor may be replaced with a bipolar transistor.

[0070] FIG. 7 is a block diagram that shows a configuration of a data transfer circuit according to the fifth embodiment of the invention. Similarly to FIG. 3 A through FIG. 6 , FIG. 7 also shows the configuration of the No. 0 column alone for simplicity of explanation and illustration.

[0071] Similarly to the data transfer circuit according to the fourth embodiment, the data transfer circuit according to the fifth embodiment is an alternative of the configuration in which each RAM cell forming a semiconductor storage device has a differential type double-end structure, such as SRAM, for example.

[0072] In comparison with the data transfer circuit according to the fourth embodiment, the data transfer circuit according to the fifth embodiment is different in including additional components. That is, the data transfer circuit according to the fifth embodiment includes: a ninth P-channel MOS transistor P 9 connected between the data line DL 0 and the complementary data line DL 0 b and supplied at is gate with a reverse equalize signal /eq to equalize the potential of the data line DL 0 and the potential of the complementary data line DL 0 b; a tenth P-channel MOS transistor P 10 forming a pair with the first N-channel MOS transistor N 1 to form a transfer gate and supplied at its gate with a reverse precharge signal /pre; and an eleventh P-channel MOS transistor P 11 forming a pair with the third N-channel MOS transistor N 3 to form a transfer gate and supplied at its gate with a reverse precharge signal /pre. operations of the leakage current monitor circuits LCMC and the leakage current compensate circuits LCCC on the part of the data line DL 0 and on the part of the complementary data line DL 0 b are identical to those of the data transfer circuit according to the fourth embodiment. However, with the additional tenth and eleventh P-channel MOS transistors P 10 and P 11 , even when potentials of the data line DL 0 and the complementary data line DL 0 b are relatively high, these potentials can be readily transmitted to the capacitor transistors N 2 and N 4 without a potential loss.

[0073] Additionally, since the ninth P-channel MOS transistor P 9 is added, in the data transfer circuit according to the fifth embodiment, potential of the data line DL 0 and potential of the complementary data line DL 0 b are equalized.

[0074] However, in the data transfer circuit according to the fifth embodiment shown in FIG. 7 , since the leakage current monitor circuits LCMC of both the data line DL 0 and the complementary data line DL 0 b are configured to be controlled by the precharge signal pre and the reverse precharge signal /pre, detection of the leakage current of the data line DL 0 and the complementary data line DL 0 b is performed during precharge operation.

[0075] The first, third, fifth, seventh and ninth P-channel MOS transistors P 1 , P 3 , P 5 , P 7 and P 9 may be replaced by N-channel MOS transistors. The transfer gate made up of the first N-channel MOS transistor N 1 and the tenth P-channel MOS transistor P 10 , and the transfer gate made up of the third N-channel MOS transistor N 3 and the eleventh P-channel MOS transistor P 11 are not limited to these configurations, but any desired switching elements may be used. The capacitor made up of the second and fourth N-channel MOS transistors N 2 and N 4 need not be made of N-channel MOS transistors, and any capacitor may be used. Further, each MOS transistor may be replaced with a bipolar transistor.

[0076] FIG. 8 is a block diagram that shows a configuration of a data transfer circuit according to the sixth embodiment of the invention. Similarly to FIG. 3 A through FIG. 7 , FIG. 8 also shows the configuration of the No. 0 column alone for simplicity of explanation and illustration.

[0077] Similarly to the data transfer circuit according to the fourth and fifth embodiment, the data transfer circuit according to the sixth embodiment is an alternative of the configuration in which each RAM cell forming a semiconductor storage device has a differential type double-end structure, such as SRAM, for example.

[0078] The circuit arrangement of the data transfer circuit according to the sixth embodiment is identical to the circuit arrangement of the data transfer circuit according to the fifth embodiment. However, the data transfer circuit according to the sixth embodiment is different in part of control signals used for controlling operations, as compared with the data transfer circuit according to the fifth embodiment.

[0079] That is, gates of the third and seventh P-channel MOS transistor P 3 and P 7 are supplied with reverse compensation control signals /comp instead of the precharge signals pre. Further, gates of the first and third N-channel MOS transistors N 1 and N 3 , which are counterparts of transfer gates of the data line DL 0 and the complementary data line DL 0 b, are supplied with detection control signals cal instead of the precharge signals pre. Furthermore, gates of the tenth and eleventh P-channel MOS transistors P 10 and P 11 , which are counterparts of transfer gates of the data line DL 0 and the complementary data line DL 0 b, are supplied with reverse detection control signals /cal instead of the reverse precharge signal /pre.

[0080] FIG. 9 is a timing chart that shows waveforms of control signals in the data transfer circuit according to the sixth embodiment of the invention.

[0081] With reference to FIGS. 8 and 9 , behaviors of the data transfer circuit according to the sixth embodiment of the invention will be explained.

[0082] When the reverse precharge signal /pre and the potential of the word line WL fall to the L level, the first and fifth P-channel MOS transistors P 1 and P 5 turn ON, and the RAM cells are turned OFF. At that time, since the data line DL 0 and the complementary data line DL 0 b are in the L level, the second and sixth P-channel MOS transistors are also ON. Therefore, precharge operations of the data line DL 0 and the complementary data line DL 0 b are started, and they are continued for periods TA, TB and TC as shown in FIG. 9 .

[0083] On the other hand, in the period TA, the reverse equalize signal /eq falls to the L level. Therefore, the ninth P-channel MOS transistor P 9 turns ON, and equalize operation is carried out.

[0084] Further, in the period TA, since the reverse compensation control signal /comp is in the L level, the third and seventh P-channel MOS transistors P 3 and P 7 are ON. Further, since the reverse detection control signal /cal are also in the L level, all of the first and third N-channel MOS transistors N 1 and N 3 and the tenth and eleventh P-channel MOS transistors P 10 and P 11 forming the transfer gates of the data line DL 0 and the complementary data line DL 0 b are turned ON. Therefore, gate potentials of the fourth and eighth P-channel MOS transistors P 4 and P 8 become the L level, and the fourth and eighth P-channel MOS transistors P 4 and P 8 also turn ON.

[0085] As a result, in the period TA, the data line DL 0 is precharged trough the first, second P-channel MOS transistors P 1 , P 2 and the third and fourth MOS transistors P 3 , P 4 . Additionally, the complementary data line DL 0 b is precharged through the fifth and sixth P-channel MOS transistors P 5 , P 6 and the seventh and eighth P-channel MOS transistors P 7 , P 8 .

[0086] Therefore, in the period TA, the data transfer circuit according to the sixth embodiment carries out precharge operation and equalize operation of the data line DL 0 and the complementary data line DL 0 b with the current double that of the data transfer circuit according to the fifth embodiment of the invention. As a result of doubling the current, precharge operation and equalize operation can be improved in speed and reliability.

[0087] Additionally, since the transfer gates of the data line DL 0 and the complementary data line DL 0 b are ON, respectively, leakage current detection operations of the data line DL 0 and complementary data line DL 0 b are also started from the period TA.

[0088] In the next period TB, the reverse equalize signal /eq and the reverse compensation control signal /comp rise to the H level, and the ninth P-channel MOS transistor P 9 and the third and seventh P-channel MOS transistors P 3 and P 7 turn OFF. Therefore, in the period TB, equalize operation does not take place, and the data line DL 0 and the complementary data line DL 0 b are electrically separated. However, since the first and fifth P-channel MOS transistors P 1 and P 5 remain ON, precharge operation is continued. Further, since the transfer gates of the data line DL 0 and the complementary data line DL 0 also remain ON, leakage current monitor operations of the data line DL 0 and the complementary data line DL 0 are also continued.

[0089] As the precharge of the data lien DL 0 and the complementary data line DL 0 b progresses, potentials of the data line DL 0 and the complementary data line DL 0 b gradually increase. The potential of the data line DL 0 is stored in the capacitor made up of the second N-channel MOS transistor N 2 via the transfer gate made up of the first N-channel MOS transistor N 1 and the tenth P-channel MOS transistor P 10 . Similarly, the potential of the complementary data line DL 0 b is stored in the capacitor made up of the N-channel MOS transistor N 4 via the transfer gate made up of the third N-channel MOS transistor N 3 and the eleventh P-channel MOS transistor P 1 . Since the data line DL 0 and the complementary data line DL 0 b are electrically separated in the period TB, the leakage current detecting capacitors of the data line DL 0 and the complementary data line DL 0 b store potentials reflecting respective leakage currents of the data line DL 0 and the complementary data line DL 0 b.

[0090] In the next period TC, the reverse detection control signal /cal rises, transfer gates of the data line DL 0 and the complementary data line DL 0 b turn OFF, respectively, and the leakage current detecting operations of the data line DL 0 and the complementary data line DL 0 b terminate.

[0091] Additionally, the reverse equalize signal /eq and the reverse compensation control signal /comp fall to the L level, the ninth P-channel MOS transistor P 9 and the third and seventh P-channel MOS transistors P 3 and P 7 turn ON, and the leakage current compensation operation is started. At that time, although the second and sixth P-channel MOS transistors P 2 and P 6 become semi-conductive in response to potentials of the data line DL 0 and the complementary data line DL 0 b, they turn OFF when the potentials of the data line DL 0 and the complementary data line DL 0 b rise sufficiently. On the other hand, the fourth and eighth P-channel MOS transistors P 4 and P 8 become semi-conductive in response to the potentials stored in the capacitors made up of the second and fourth N-channel MOS transistors N 2 and N 4 .

[0092] That is, since the gates of the fourth and eighth P-channel MOS transistors P 4 and P 8 are supplied with potentials based on electric charges accumulated in the capacitor transistors N 2 and N 4 by leakage current of the data line DL 0 and the complementary data line DL 0 b, respectively, the fourth and eight P-channel MOS transistors P 4 and P 8 turn ON to pass compensation currents of magnitudes corresponding to the leakage currents of the data line DL 0 and the complementary data line DL 0 b, respectively, and the compensation currents flow into the data line DL 0 and the complementary data line DL 0 b, respectively. As a result, the off-leakage currents of the data line DL 0 and the complementary data line DL 0 b are compensated by the compensation currents, and erroneous behaviors of the semiconductor storage device caused by the off-leakage currents can be prevented beforehand.

[0093] Moreover, since the data transfer circuit according to the sixth embodiment starts the leakage current compensation operation earlier than the data transfer circuit according to the fifth embodiment, erroneous behaviors of the semiconductor storage device caused by the off-leakage current can be prevented reliably.

[0094] In the next period Td, the reverse precharge signal /pre and the reverse equalize signal /eq rise to the H level, and precharge operation and equalize operation terminate. On the other hand, since the reverse compensation control signal /comp still maintains the L level, the leakage current compensation operation is continued. In this status, write or read operation of a desired RAM cell CL is carried out.

[0095] FIG. 10 is a timing chart that shows waveforms of control signals in a data transfer circuit according to the seventh embodiment of the invention.

[0096] Circuit arrangement of the data transfer circuit according to the seventh embodiment is identical to the circuit arrangement of the data transfer circuit according to the sixth embodiment, and input portions of control signals used for controlling operations are also identical. However, as apparent from comparison between the timing chart of FIG. 10 with the timing chart of FIG. 9 , the waveform of the reverse precharge signal /pre and the waveform of the reverse compensation control signal /comp are exchanged in the period TB.

[0097] That is, the data transfer circuit according to the seventh embodiment uses the fourth and eighth P-channel MOS transistors P 4 and P 8 instead of the second and sixth P-channel MOS transistors P 2 and P 6 for leakage current detecting operation, and uses the fourth and eighth P-channel MOS transistors P 4 and P 8 also for the leakage current compensating operation.

[0098] Since all P-channel MOS transistors used here have the same characteristics, even when using the second and sixth P-channel MOS transistors P 2 and P 6 for leakage current detecting operation and using the fourth and eighth P-channel MOS transistors P 4 and P 8 for leakage current compensating operation, as the data transfer circuit according to the sixth embodiment, no particular problems occur normally.

[0099] Strictly, however, P-channel MOS transistors are different in characteristics to a certain level. Therefore, if different transistors are used for leakage current detecting operation and leakage current compensation operation, there may occurs a difference between the magnitude of the detected leakage current and the magnitude of the compensated leakage current.

[0100] Taking it into consideration, the data transfer circuit according to the seventh embodiment uses common transistors for both leakage current detecting operation and leakage current compensating operation, thereby to prevent the problem of characteristic fluctuation.

[0101] FIG. 11 is a block diagram that shows a configuration of a data transfer circuit according to the eighth embodiment of the invention.

[0102] The data transfer circuit according to the eighth embodiment of the invention is a version in which the construction of the data transfer circuit according to the fourth embodiment or the fifth embodiment is applied to a semiconductor storage device having a RAM cell array of 256 rows and 64 columns. Specific configuration of each column is as already explained with the data transfer circuit according to the fourth embodiment or fifth embodiment.

[0103] Since the data transfer circuit according to the eighth embodiment includes 64 sets of data lines DL 0 through DL 64 and complementary data lines DL 0 b through DL 64 b, 64 sets of leakage current monitor and compensate circuits LCMCC are preferably provided in association with respective data line pairs. However, by sequential connection to individual data line pairs by time-divisional switching, a single leakage current monitor and compensate circuit LCMCC may be shared among 64 sets of data lines.

[0104] FIG. 11 is shown as connecting a write/read circuit WRC, in addition to the leakage current monitor and compensate circuit LCMCC, to the data lines and the complementary data lines, so is it also in FIG. 3 through FIG. 7 .

[0105] FIG. 12 is a block diagram that shows a configuration of a data transfer circuit according to the ninth embodiment of the invention.

[0106] The data transfer circuit according to the ninth embodiment is a version applying configurations of the data transfer circuits according to the first to three embodiments to a semiconductor storage device having a plurality of hierarchical banks of RAM cell arrays. The RAM cell arrays shown here have 16 banks from the first bank B 1 to the sixteenth bank B 16 .

[0107] The banks are connected longitudinally by global bit lines GBL0, GBL1, . . . , GBLm provided in individual columns of the RAM cell arrays. Then, for the first bank B1, for example, the respective global bit lines GBL0, GBL1, . . . , GBLm are connected to the local bit lines BL0, BL1, . . . , BLm of the first bank B 1 via N-channel MOS transistors N0, N1, . . . , Nm that are bank-selecting switching devices. Selection of a bank is carried out by a bank selection signal BSS input to the bank-selecting switching device of each bank. Precharge of each global bit line and data input or output through each local bit line are executed by a precharge and write/read circuit PWRC connected to the global bit lines.

[0108] In the memory blocks having hierarchical bit lines (data line) as explained above, for certain memory blocks, it will be more efficient, depending upon the purpose of use, to access to the first bank B 1 through the sixteenth bank B 16 at random and continuously read out data, upon reading data, for example.

[0109] For such a memory block, upon continuous data read of the banks, read operation can be speeded up by precharging quickly only the global bit line as a higher hierarchical data line and sequentially reading out data of each bank. In this case, assume here that the circuit is configured to precharge/equalize a local bit line as a lower hierarchical data line directly connected to the RAM cells immediately after writing data in RAM cells of each bank and thereafter leave the local bit line not precharged or not equalized until continuous read of each bank as explained above is carried out. Then, if there is a leakage current in the local bit line of a particular bank, potential of the precharged local bit line may decrease significantly during a relatively long wait time after the precharge/equalize of the local bit line until the data read of the banks is carried out. That is, in case of a configuration of 16 banks, since the data read time of one bank is {fraction (1/16)} of the data read time of all banks, all the data read time of the other banks is the wait time, and the potential of a precharged local bit line may decrease significantly during that wait time.

[0110] Taking it into consideration, the data transfer circuit according to the ninth embodiment additionally connects a precharge, leakage current monitor and compensate circuit PLCMCC to each local bit line of each bank. Therefore, even when a local bit line is not precharged or equalized after it is once precharged or equalized until continuous read of banks takes place, because a leakage current is detected, and a compensation current for compensating the leakage current is generated and supplied to the local bit line after completion of precharge operation until data write or read operation is carried out and upon data read operation, erroneous behaviors of the semiconductor storage device caused by the leakage current in the local bit line can be prevented beforehand.

[0111] The data transfer circuit according to the ninth embodiment has been shown as an example in which configurations of the data transfer circuits according to the first to third embodiments are applied to RAM cell arrays of respective banks. Instead, however, configurations of the data transfer circuits according to the fourth to eighth embodiments may be applied to RAM cell arrays of respective banks.

[0112] Further, in the data transfer circuit according to the ninth embodiment, the precharge, leakage current monitor and compensate circuit PLCMCC added to the local bit lines BL 0 , BL 1 , . . . , BLm is provided in each bank. However, instead of adding the precharge, leakage current monitor and compensate circuit PLMCC to respective local bit lines BL 0 , BL 1 , . . . , BLm, by adding it to respective global bit lines GBL 0 , GBL 1 , . . . , GBLm and sequentially connecting it to the local bit lines of each bank by time divisional switching using N-channel MOS transistors N 0 , N 1 , . . . , Nm that are bank-selecting switching devices, a single precharge, leakage current monitor and compensate circuit PLMCC can be commonly shared by the local bit lines of each bank connected to a common global bit line GBL.

[0113] FIG. 13 is a block diagram that shows a configuration of a data transfer circuit according to the tenth embodiment of the invention.

[0114] The data transfer circuit according to the tenth embodiment is a configuration of a basic concept, which wholly contains the above-explained embodiments, and this is a more general form of the configuration of the data transfer circuit according to the second embodiment shown in FIG. 4 . That is, this embodiment shows that configuration of the data transfer circuit according to the invention is applicable not only to data lines (bit lines) of a semiconductor storage device but also to a data bus BUS to which one or more interface input/output blocks I/F•I/O are connected.

[0115] Regarding structures, connections and operations of the leakage current monitor circuit LCMC, N-channel MOS transistors N as transfer gates, capacitors C, and leakage current compensate circuit LCCC are identical or equivalent to those of the data transfer circuit according to the second embodiment.

[0116] Data width of the data but BUS may be determined as desired, and the number of interface input/output blocks I/F•I/O connected to the data bus BUS, as well, may be determined as desired. Circuit configuration of each interface input/output block I/F•I/O may be that of a wired OR circuit, tri-state buffer, multiplexer, or any other desired circuit.

[0117] As the transfer gates, P-channel MOS transistors, bipolar transistors or any other desired switching elements may be used in lieu of N-channel MOS transistors N.