<?xml version="1.0" encoding="UTF-8"?>

<rss version="2.0">
    <channel>
        <image>
            <title>freepatentsonline.com</title>
            <width>141</width>
            <height>131</height>
            <link>http://www.freepatentsonline.com/</link>
            <url>http://www.freepatentsonline.com/images/logo.gif</url>
        </image>
        
        <title>Free Patents Online: Error detection/correction and fault detection/recovery</title>
        <link>http://www.freepatentsonline.com./rssfeed/rsspat714.xml</link>
        <description>USPTO Class 714 Error detection/correction and fault detection/recovery</description>
        <language>en-us</language>
        <lastBuildDate>Tue, 22 Dec 2009 08:00:00 EST</lastBuildDate>
        <item>
            <title><![CDATA[Unwanted file modification and transactions]]></title>
            <link>http://www.freepatentsonline.com./7636946.html</link>
            <description><![CDATA[Aspects of the subject matter described herein relate to antivirus protection and transactions. In aspects, a filter detects that a file is participating in a transaction and then may cause the file to be scanned together with any changes that have made to the file during the transaction. After a file is scanned, a cache entry may be updated to indicate that the file is clean. The cache entry may be used subsequently for like-type states. For example, if the file was scanned inside a transaction, the cache entry may be used later in the transaction. If the file was scanned outside a transaction, the cache entry may be used later for requests pertaining to files not in a transaction. Cache entries may be discarded when they are invalid or no longer useful.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and system for tracking memory usage by software agents]]></title>
            <link>http://www.freepatentsonline.com./7636918.html</link>
            <description><![CDATA[A method and system for tracking memory usage by software agents operating in a computer system is disclosed. A memory resource tracking application is executed in the system. When an operating software agent is detected, a determination is made about the memory consumed by the running agent. Measurements are made at periodic intervals to determine if the agent has ended. When the agent has ended, all memory allocations associated with the agent are added together to arrive at a peak memory usage for the agent.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Error correction scheme for memory]]></title>
            <link>http://www.freepatentsonline.com./7636880.html</link>
            <description><![CDATA[An embedded DRAM ECC architecture for purging data errors. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, and the parity block stores column parity bits. A row parity circuit coupled in parallel to an existing local databus of each memory checks the parity of the local databus bits against a row parity bit during a refresh or read operation to identify parity failure. Identification of the incorrect bit of the word is achieved by iteratively transferring the data of the local databus of each memory block onto an existing global databus, and checking the parity across the global databus with a column parity circuit. When global databus parity failure is detected, all bits of the global databus are inverted to purge the incorrect bit from the memory block via the local databus.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Error correction decoder]]></title>
            <link>http://www.freepatentsonline.com./7636879.html</link>
            <description><![CDATA[An error correction decoder possessing a decoding method with high error correction performance and capable of operating at a low operating frequency and on a reduced circuit scale. A decoding method based on the SOVA method for improving error correction performance and boosting reliability of the soft decision output by allowing branching of paths other than the survival path at trace-back is achieved by preparing a trace-back circuit for each state, and selecting an output from that output and survival state (survival state+difference of likelihood).]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method of configuring transmission in mobile communication system]]></title>
            <link>http://www.freepatentsonline.com./7636878.html</link>
            <description><![CDATA[Method for configuring a transmission chain in a 3GPP2 system for supporting a flexible or variable data rate of an information bitstream in a process for mapping an information bitstream of a data rate on a physical layer, including the steps of (1) channel coding the information bitstreams with bit rates different from each other into turbo codes or convolution codes having a value inverse of 1/coding rate, and (2) repeating coded bitstream when the channel coded bitstream is smaller than a desired interleaving size, and puncturing the coded bitstream when the channel coded bitstream is greater than the desired interleaving size, for matching the channel coded bitstream to the interleaving size.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Test apparatus having a pattern memory and test method for testing a device under test]]></title>
            <link>http://www.freepatentsonline.com./7636877.html</link>
            <description><![CDATA[The test apparatus includes: a pattern memory that stores therein data to be outputted to the device under test; a device judgment section that judges whether the device under test passes or fails based on an output signal; the number of data information storage section that stores therein the number of data information based on the number of logic H data included in an input data; a counter that receives output data outputted from the pattern memory to the device under test and counts the number of logic H data included in the output data; a pattern memory judgment section that judges that the data stored in the pattern memory is correct when the number of data information on the input data is corresponding to the number of logic H data counted by the counter and outputs a signal according to this judgment result.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Cost-based performance driven legalization technique for placement in logic designs]]></title>
            <link>http://www.freepatentsonline.com./7636876.html</link>
            <description><![CDATA[A method of placing a circuit design can include selecting one or more candidate mobile nodes from a plurality of overlapped nodes of the circuit design and determining a gain region for each candidate mobile node. The method also can include assigning the candidate mobile node to a site within a gain region according to a cost function. The gain region is associated with the candidate mobile node. The method further can include iteratively selecting and assigning candidate mobile nodes according to a measure of overlap for the circuit design.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Low noise coding for digital data interface]]></title>
            <link>http://www.freepatentsonline.com./7636875.html</link>
            <description><![CDATA[A digital data interface system comprises a data transmitter configured to transmit a data word across a plurality of data lines. The data word can comprise a plurality of digital data bits having a bit number order from a lowest bit number to a highest bit number with the lowest ordered bit numbers having higher noise content and the highest ordered bit numbers having higher harmonic content. The system also comprises an encoder configured to arrange the plurality of digital data bits as serialized data sets to be transmitted over each of the plurality of data lines by the data transmitter with consecutive data bits of at least one serialized data set being matched such that bits with the higher harmonic content are matched with bits of the higher noise content to substantially mitigate of at least one of the noise content and the harmonic content of the data word.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and apparatus for computer-implemented processing of payment entries]]></title>
            <link>http://www.freepatentsonline.com./7636874.html</link>
            <description><![CDATA[Method and apparatus for the computer-implemented processing of payment entries which are intended to move money in an account, wherein a payment entry is automatically checked for errors as it is received and if at least one error occurs an error sequence is decided upon from a list of error routines by means of an error routine, all the errors occurring in a given payment entry being supplied collectively to the error routine, and within the scope of the error routine the errors which have occurred are weighted and appropriate error follow-up measures are initiated depending on the results of the error weighting.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Enhancement of assured event delivery mechanism to eliminate external XA store requirement]]></title>
            <link>http://www.freepatentsonline.com./7636873.html</link>
            <description><![CDATA[Aspects of the present invention provide a method, system, computer usable program code, and computer implemented method for assured event delivery in an enterprise information system. The method comprises mapping the capabilities of the enterprise information system onto an interface, wherein the mapping allows the enterprise information system to be used in global transactions.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Threat event-driven backup]]></title>
            <link>http://www.freepatentsonline.com./7636872.html</link>
            <description><![CDATA[A method and apparatus for backing up data in response to detection of an imminent threat to the integrity of the data stored on the storage component a computing device is disclosed. The storage component may be a hard drive and the imminent threat may be a hard drive failure or a malware threat. In response to the receipt of an imminent threat, data stored on the storage component is copied to a computer-readable media either automatically or in response to user input. The backup procedure is configured by selecting data to backup and a media of storage on which to store the backup. Various sources of threat events are described.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method for comparing customer and test load data with comparative functional coverage hole analysis]]></title>
            <link>http://www.freepatentsonline.com./7636871.html</link>
            <description><![CDATA[One aspect of the present invention includes performance of a comparative functional coverage technique for comparing analysis of actual operational load data, such as customer data, with test operational load data. In one embodiment, coverage and holes analysis operations are performed on each of actual trace data produced by the operation of actual activities, and test trace data produced by the operation of a simulation within a test execution. The functional coverage and hole analysis results produced for each of the actual data source and the test data source are then compared to discover the most important functional holes relevant to testing, namely holes which appear only in the test but not within the actual operation. The results of the holes comparison detailing which holes exist within the test are then presented and ultimately utilized to improve the test.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Semiconductor integrated circuit device, and debugging system and method for the semiconductor integrated circuit device]]></title>
            <link>http://www.freepatentsonline.com./7636870.html</link>
            <description><![CDATA[To provide a debugging system, debugging method, and a semiconductor integrated circuit device capable of collecting debug-target information with accuracy and improving debug efficiency. A semiconductor integrated circuit device according to an embodiment of the present invention includes: subsystems; a break detecting unit detecting that a program execution of a CPU core in one subsystem satisfies a predetermined break condition; and a break selecting unit stopping operations of one selected from the subsystems in accordance with the detection result of the break detecting unit.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Program dynamically burnt system and method]]></title>
            <link>http://www.freepatentsonline.com./7636869.html</link>
            <description><![CDATA[A program dynamically burnt method is provided. The method includes the following steps: dividing a system program into a first part system program and a second part system program; linking a diagnostic program, the second system program and the first system program orderly to form an integration program; burning the integration program to a storage of an electronic apparatus; deleting the diagnostic program from the data storage; and moving the first part system program to occupy address space of the diagnostic program in the data storage.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Data replication in a distributed system]]></title>
            <link>http://www.freepatentsonline.com./7636868.html</link>
            <description><![CDATA[A global state management service manages replication in a distributed system. A distributed system can have several replica groups. The global state management service manages state associated with each replica group. Data replication is implemented without implementing an instance of a state machine on each device in a replica group. A replica group comprises a primary device and at least one secondary device. Each device in a replica group contains a replica of data of interest. The global state management service manages the allocation of primary and secondary devices. In the absence of a failure in either a primary device or a secondary device, read and write operations are performed without consulting the global state management service. When a failure is detected, the global state management service manages failover.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Memory system with hot swapping function and method for replacing defective memory module]]></title>
            <link>http://www.freepatentsonline.com./7636867.html</link>
            <description><![CDATA[A serial-transmission type memory system with a hot swapping function is provided which is capable of replacing a defective memory module without stopping the system. One end of a row of memory modules is connected to one input-output section of a memory controller and the memory controller exerts control so that, when a failure occurs in any of the memory modules, by disconnecting the defective memory module from the memory module in its preceding stage and by sequentially connecting the memory module in the row of the memory modules in a next and onward stage and a spare memory module connected to another end of the row of the memory modules to the other input-output section of the memory controller in series through second read and write signal lines to gain access to each of the memory modules.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Situational aware output configuration and execution]]></title>
            <link>http://www.freepatentsonline.com./7636866.html</link>
            <description><![CDATA[A method and apparatus are provided which allow a user to define an output device behavior in a variety of status and/or event circumstances via creating a binding or logical connection between a logic function and one or more status/event indicators. The method provides for user-defined output behavior through linking a logical function with system and module status/event indicators, whereby the output value may be determined according to the status/event indicators and user-defined function blocks. Also disclosed is an output device with an output providing an output signal according to an output value, a communication interface adapted to receive messages from a network, an indicator adapted to receive message information from a network and providing indicator data, and a logic unit which receives message information from the network, indicator data from the indicator, and which performs a logic function. The logic unit selectively provides the output value to the output according to one of the message information and the logic function.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Data storage and protection apparatus and methods of data storage and protection]]></title>
            <link>http://www.freepatentsonline.com./7636804.html</link>
            <description><![CDATA[An exemplary storage system for storing data from a host system and emulating a storage tape device is presented. In one example, the storage system includes a compression device configured to associate with a controller of a plurality of storage devices. The compression device is adapted to receive a sequence of data to be stored, divide the sequence of data into two or more blocks, and compress at least two of the two or more blocks in parallel. The system may further create an index associated with the blocks of data to output the data as a continuous stream of data. The compression device may further include dual or multiple ports.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Data storage system and method by shredding and deshredding]]></title>
            <link>http://www.freepatentsonline.com./7636724.html</link>
            <description><![CDATA[A system and method for data storage by shredding and deshredding of the data allows for various combinations of processing of the data to provide various resultant storage of the data. Data storage and retrieval functions include various combinations of data redundancy generation, data compression and decompression, data encryption and decryption, and data integrity by signature generation and verification. Data shredding is performed by shredders and data deshredding is performed by deshredders that have some implementations that allocate processing internally in the shredder and deshredder either in parallel to multiple processors or sequentially to a single processor. Other implementations use multiple processing through multi-level shredders and deshredders. Redundancy generation includes implementations using non-systematic encoding, systematic encoding, or a hybrid combination. Shredder based tag generators and deshredder based tag readers are used in some implementations to allow the deshredders to adapt to various versions of the shredders.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Extracting synchronous secondary signals by functional analysis]]></title>
            <link>http://www.freepatentsonline.com./7636655.html</link>
            <description><![CDATA[Programmable devices include configurable logic hardware for implementing logic gates, registers for storing data, and secondary hardware for additional functions, such as loading and clearing. The secondary hardware can implement portions of the user design, thereby decreasing the number of gates to be implemented elsewhere. A set of possible alternative implementations of portions of the user design is identified by enumerating the inputs connected with a register. Logic diagrams are created for the set of inputs, and alternative implementations are identified from the logic diagrams by recognizing patterns similar to the secondary hardware functions. To determine an implementation that balances gate savings against routing costs, alternative implementations are grouped according to compatible inputs and ranked by the number of registers in each group. The implementation with the highest rank is selected, and selected registers are removed from other alternative implementations. The remaining alternative implementations are re-ranked for further selections.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method for dynamic sensor configuration and runtime execution]]></title>
            <link>http://www.freepatentsonline.com./7636608.html</link>
            <description><![CDATA[Graphical User Interfaces (GUIs) are presented for configuring and setting-up dynamic sensors for monitoring tool and process performance in a semiconductor processing system. The semiconductor processing system includes a number of processing tools, a number of processing modules (chambers), and a number of sensors. The graphical display is organized so that all significant parameters are clearly and logically displayed so that the user is able to perform the desired configuration and setup tasks with as little input as possible. The GUI is web-based and is viewable by a user using a web browser.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and a system for controlling a process device]]></title>
            <link>http://www.freepatentsonline.com./7636606.html</link>
            <description><![CDATA[The present invention relates to a method for process control, wherein at least one process device to be controlled is controlled by at least one process module and at least one safety module in that process signals of the process module not relevant to safety and safety signals of the safety module relating to process safety are logically linked to one another and at least one local safety signal of a local safety sensor is supplied directly to at least one control output of a local control unit associated with the process device while bypassing this logical linking operation in order to effect a fast change in state at the process device to be controlled which is connected to the control output, wherein the fast switching path includes a fast switching function with which the result of the logical linking operation and the local safety signal are evaluated together and wherein a fast change in state at the process device to be controlled effected via the fast changing path is changed again, and is in particular reversed again, when the common evaluation produces a predetermined result. The invention moreover relates to a system for process control, in particular for the carrying out of the method in accordance with the invention.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Decoding system and method for digital communications]]></title>
            <link>http://www.freepatentsonline.com./7636400.html</link>
            <description><![CDATA[A Viterbi decoding system interprets bits in received QAM constellations as many-valued parameters rather than binary valued parameters. It performs the Viterbi algorithm using these many-valued parameters to provide results superior to hard decision decoding. Rather than applying a hard 0-1 function to the QAM data, the system uses a non-stepped linear or curved transfer function to assign values to the bits. In another aspect, a system differentiates between data bits based on their estimated reliability, giving more emphasis to decoding reliable bits than unreliable bits using any of a variety of techniques. By differentiating between god and bad bits and de-emphasizing or ignoring unreliable bits, the system can provide a significant reduction in uncorrectable errors and packet loss.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and apparatus for transmitting and receiving convolutionally coded data for use with combined binary phase shift keying (BPSK) modulation and pulse position modulation (PPM)]]></title>
            <link>http://www.freepatentsonline.com./7636397.html</link>
            <description><![CDATA[A method and apparatus for transmitting and receiving convolutionally coded data in a communication system employing a combination of Pulse Position Modulation (PPM) and Binary Phase Shift Keying (BPSK), wherein the code is selected to have error rate performance that is as good as the best convolutional code used with systems employing only BPSK.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Encoding Viterbi error states into single chip sequences]]></title>
            <link>http://www.freepatentsonline.com./7636382.html</link>
            <description><![CDATA[A technique for receiving an error state in a single chip sequence in a wireless communications network is disclosed. The error state may comprise a Viterbi error state. The error state may be identified as a target code encoded in the single chip sequence, the target code comprising either a code or the complement of the code. The code may comprise a PN-Code. The error state may be identified using a previous mapping of error states from a set of error states to a group of codes, the group of codes comprising a plurality of codes and their complements. The error states in the set of error states in the previous mapping may be uniquely mapped to plurality of codes and their complements in the group of codes.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Distributed transmitting apparatus and method with retransmission function]]></title>
            <link>http://www.freepatentsonline.com./7636301.html</link>
            <description><![CDATA[A distributed transmitting apparatus and a method are provided in a communications system in which retransmission of data frames can be requested by a receiver. According to the method, a transmitting unit in the distributed transmitting apparatus transmits data frames to a receiver and stores the transmitted data frames. The apparatus further includes a control unit which transmits the data frames to the transmitting unit for transmission to the receiver, and further the control unit transmits control data to the transmitting unit for controlling retransmission of the data frames, wherein the control unit controls the transmitting unit to retransmit data frames stored in the transmitting unit to the receiver.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Apparatus and method for packet error correction]]></title>
            <link>http://www.freepatentsonline.com./7636298.html</link>
            <description><![CDATA[A packet error correcting apparatus includes a retransmission request controlling unit controlling a timing of transmission of a retransmission request to a packet transmitting apparatus from a retransmission request transmitting unit according to whether an error correcting unit can restore the lost packet within a predetermined time period when loss of the packet is detected. In a packet receiving apparatus supporting both Forward Error Correction (FEC) and Automatic Repeat reQuest (ARQ), it is possible to control a timing of transmission of a retransmission request when packet loss occurs, thereby to regenerate video and/or voice with the most suitable delay time while suppressing transmission of unnecessary retransmission requests.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
    </channel>
</rss>