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<title>freepatentsonline.com: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)</title>
<link>http://www.freepatentsonline.com/result.html?query_txt=ccl/712%20and%20isd/04/29/2008&amp;uspat=on</link>
<description>USPTO Class 712 Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)</description>
<language>en-us</language>
<lastBuildDate>Wed Apr 30 16:35:39 EDT 2008</lastBuildDate>

<item>
<title><![CDATA[Speculative instruction issue in a simultaneously multithreaded processor]]></title>
<link>http://www.freepatentsonline.com/7366877.html</link>
<description><![CDATA[A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Efficient emulation instruction dispatch based on instruction width]]></title>
<link>http://www.freepatentsonline.com/7366876.html</link>
<description><![CDATA[In one embodiment, a state machine receives a plurality of instructions from an instruction register to be processed by a digital signal processor. After receiving a single RTI, the state machine loads each of the plurality of instructions one at time and determines the validity of each instruction. If the instruction is valid, the state machine transfers the instruction to the decoder. If the instruction is invalid or if a no-operation instruction is present, the state machine discards the instruction and immediately loads the next instruction.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Apparatus and method for dispatching very long instruction word having variable length]]></title>
<link>http://www.freepatentsonline.com/7366874.html</link>
<description><![CDATA[Apparatus and method for dispatching a very long instruction word (VLIW) instruction having a variable length are provided. The apparatus for dispatching a VLIW instruction includes a packet buffer for storing at least one or more VLIW instructions, and a decoding unit configured to constitute a VLIW instruction to be currently executed among the VLIW instructions stored in the packet buffer and decode predetermined bits of each sub-instruction contained in the VLIW instruction. The apparatus dispatches a corresponding sub-instruction to an FU which corresponds to each sub-instruction, based on the results of decoding performed in the decoding unit, position information on the sub-instructions that are placed on the packet buffer, and position information on the sub-instructions that are placed in the current VLIW instruction. Sub-instructions can be effectively dispatched to corresponding FUs using simple decoding logic even in a case where the length of the VLIW instruction is not fixed.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Context switching system for a multi-thread execution pipeline loop and method of operation thereof]]></title>
<link>http://www.freepatentsonline.com/7366884.html</link>
<description><![CDATA[A context switching system for a multi-thread execution pipeline loop having a pipeline latency and a method of operation thereof. In one embodiment, the context switching system includes a context switch requesting subsystem configured to: (1) detect a device request from a thread executing within the multi-thread execution pipeline loop for access to a device having a fulfillment latency exceeding the pipeline latency, and (2) generate a context switch request for the thread. The context switching system further includes a context controller subsystem configured to receive the context switch request and prevent the thread from executing until the device request is fulfilled.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Alteration of functional unit partitioning scheme in multithreaded processor based upon thread statuses]]></title>
<link>http://www.freepatentsonline.com/7366879.html</link>
<description><![CDATA[A method and apparatus are provided for entering and exiting multiple threads within a multithreaded processor. A state machine is maintained to indicate a respective status of an associated thread of multiple threads being executed within a multithreaded processor. A change of status for a first thread within the multithreaded processor is detected and, responsive to the change of status for the first thread within the multithreaded processor, a partitioning scheme for the functional unit is altered to service a second thread, but not the first thread, within the multithreaded processor when the change of the status of the first thread comprises a transition from an active state to an inactive state.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Facilitating value prediction to support speculative program execution]]></title>
<link>http://www.freepatentsonline.com/7366880.html</link>
<description><![CDATA[One embodiment of the present invention provides a system that predicts a result produced by a section of code in order to support speculative program execution. The system begins by executing the section of code using a head thread in order to produce a result. Before the head thread produces the result, the system generates a predicted result to be used in place of the result. Next, the system allows a speculative thread to use the predicted result in speculatively executing subsequent code that follows the section of code. After the head thread finishes executing the section of code, the system determines if a difference between the predicted result and the result generated by the head thread has affected execution of the speculative thread. If so, the system executes the subsequent code again using the result generated by the head thread. If not, the system performs a join operation to merge state associated with the speculative thread with state associated with the head thread. In one embodiment of the present invention, executing the subsequent code again involves performing a rollback operation for the speculative thread to undo actions performed by the speculative thread.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Scheduling instructions from multi-thread instruction buffer based on phase boundary qualifying rule for phases of math and data access operations with better caching]]></title>
<link>http://www.freepatentsonline.com/7366878.html</link>
<description><![CDATA[A processor buffers asynchronous threads. Current instructions requiring operations provided by a plurality of execution units are divided into phases, each phase having at least one math operation and at least one texture cache access operation. Instructions within each phase are qualified and prioritized, with texture cache access operations in a subsequent phase not qualified until all of the texture cache access operations in a current phase have completed. The instructions may be qualified based on the status of the execution unit needed to execute one or more of the instructions. The instructions may also be qualified based on an age of each instruction, a divergence potential, locality, thread diversity, and resource requirements. Qualified instructions may be prioritized based on execution units needed to execute current instructions and the execution units in use. One or more of the prioritized instructions is issued per cycle to the plurality of execution units.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Methods and apparatus to provide dual-mode drivers in processor systems]]></title>
<link>http://www.freepatentsonline.com/7366891.html</link>
<description><![CDATA[Methods and apparatus to provide dual-mode drivers in a processor system are disclosed. An example method disclosed herein comprises including operating system (OS) agnostic mode services that are available during an OS agnostic mode to allow a single set of drivers to be used during boot mode and the OS agnostic mode. The example method further comprises including a dual-mode library that is capable of determining the current operating mode of the processor system and binding the drivers to available services accordingly.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method for optimizing loop control of microcoded instructions]]></title>
<link>http://www.freepatentsonline.com/7366885.html</link>
<description><![CDATA[A method for optimizing loop control of microcoded instructions includes identifying an instruction as a repetitive microcode instruction such as a move string instruction, for example, having a repeat prefix. The repetitive microcode instruction may include a loop of microcode instructions forming a microcode sequence. The microcode sequence is stored within a storage of a microcode unit. The method also includes storing a loop count value associated with the repetitive microcode instruction to a sequence control unit of the microcode unit. The method further includes determining a number of iterations to issue the microcode sequence for execution by an instruction pipeline based upon the loop count value. In response to receiving the repetitive microcode instruction, the method includes continuously issuing the microcode sequence for the number of iterations.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Address calculation unit for an object oriented processor having differentiation circuitry for selectively operating micro-instructions]]></title>
<link>http://www.freepatentsonline.com/7366882.html</link>
<description><![CDATA[A processor is provided with a address calculation unit so as to generate addresses for elements of object oriented data structures in one processor clock cycle.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Processor based system and method for virus detection]]></title>
<link>http://www.freepatentsonline.com/7367057.html</link>
<description><![CDATA[A processor based system and method for virus detection is described. In one embodiment, a processor comprises a plurality of functional units. The plurality of functional units includes a first functional unit and a second functional unit, the first functional unit to receive instructions, to determine whether ones of the instructions are associated with a virus, and to transmit the ones of the instructions not associated with the virus to the second functional unit.  In one embodiment, the method includes receiving an instruction in a first functional unit of a processor pipeline. The method further includes determining whether the instruction is associated with a virus. The method further includes transmitting the instruction to a second functional unit of the processor pipeline for further processing.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Indirectly addressed vector load-operate-store method and apparatus]]></title>
<link>http://www.freepatentsonline.com/7366873.html</link>
<description><![CDATA[A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, one vector register is loaded with the “add-in” values, and another vector register is loaded with address values of “add to” elements to be gathered from memory into a third vector register. If the vector of address values has a plurality of elements that point to the same memory address, the algorithm should add all the “add in” values from elements corresponding to the elements having the duplicated addresses. An indirectly addressed load performs the “gather” operation to load the “add to” values. A vector add operation then adds corresponding elements from the “add in” vector to the “add to” vector. An indirectly addressed store then performs the “scatter” operation to store the results.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for performing fast closest match in pattern recognition]]></title>
<link>http://www.freepatentsonline.com/7366352.html</link>
<description><![CDATA[A method and apparatus for determining a closest match of N input patterns relative to R reference patterns using K processing units. Each of a set of input patterns are loaded into the K processing units. One of the Reference patterns is sequentially loaded into each of the processing units and a distance defining the similarity between the reference pattern and each of the input patterns is calculated. A present calculated distance replaces its corresponding stored present minimum distance if it is has a smaller value. After the R reference patterns have been processed the minimum distance and its corresponding identification for all N input patterns is determined without merging outputs. The minimum distances and the identifications may be read either in parallel or serially. The apparatus is easily scalable by adding processors. The number of reference patterns may be easily increased without altering system configuration.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization]]></title>
<link>http://www.freepatentsonline.com/7367026.html</link>
<description><![CDATA[A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous stream of memory is disclosed. A preferred embodiment identifies groups of isomorphic statements within a loop body where the isomorphic statements operate over a contiguous stream of memory over the iteration of the loop. Those identified statements are then converted into virtual-length vector operations. Next, the hardware's available vector length is used to determine a number of virtual-length vectors to aggregate into a single vector operation for each iteration of the loop. Finally, the aggregated, vectorized loop code is converted into SIMD operations.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method for the manipulation, storage, modeling, visualization and quantification of datasets]]></title>
<link>http://www.freepatentsonline.com/7366719.html</link>
<description><![CDATA[There is described a method for manipulation, storage, modeling, visualization, and quantification of datasets, which correspond to target strings. An iterative algorithm is used to generate comparison strings corresponding to some set of points that can serve as the domain of an iterative function. The comparison string is scored by evaluating a function having the comparison string and one of the plurality of target strings as inputs. The score measures a relationship between a comparison string and a target string. The evaluation may be repeated for a number of the other target strings. The score or some other property corresponding to the comparison string is used to determine the target string's placement on a map. The target string may also be marked by a point on a visual display.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

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