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        <title>Free Patents Online: Electrical computers and digital data processing systems: input/output</title>
        <link>http://www.freepatentsonline.com./rssfeed/rsspat710.xml</link>
        <description>USPTO Class 710 Electrical computers and digital data processing systems: input/output</description>
        <language>en-us</language>
        <lastBuildDate>Tue, 29 Dec 2009 08:00:00 EST</lastBuildDate>
        <item>
            <title><![CDATA[Data processing system and method]]></title>
            <link>http://www.freepatentsonline.com./7640588.html</link>
            <description><![CDATA[A data processing system ( 102 ) determines whether or not the access destination according to an access request from an access request source is an infectable storage device that is a storage device ( 111 ) that may already store data that has not been virus scanned, and the system changes the virus scan mode executed with respect to the object data of the access request according to the results of the determination as to whether or not the access destination is an infectable storage device.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Print system, apparatus, and method for performing printing based on document information stored in document server]]></title>
            <link>http://www.freepatentsonline.com./7640576.html</link>
            <description><![CDATA[The present invention provides a print system having an enhanced operability for printing document information transmitted/received through a network. In this system, documents stored in a database are searched for so as to obtain a search result, and a user specifies a document to be printed from among documents indicated by the search result in a browser screen. Accordingly, a printer extracts information about a storage location of the document and downloads the information of the document stored in a document server thereto.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method for installing a printer driver and computer-readable medium storing installation program]]></title>
            <link>http://www.freepatentsonline.com./7640554.html</link>
            <description><![CDATA[One of the printer drivers is selected from multiple printer drivers stored in a recording medium by referring to regional information set in the computer in advance and in accordance with the referred regional information. The selected printer driver is to be installed in the computer. It is also possible to select setup information that includes a screen display language, a default printing paper size, and a measurement unit system, instead of selecting a printer driver itself, and have the setup information to be installed in the computer.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and system for exporting menu objects to a peripheral using a direct data entry structure]]></title>
            <link>http://www.freepatentsonline.com./7640504.html</link>
            <description><![CDATA[A method and system for exporting menu objects to a peripheral, which includes the steps of collecting configuration data of the current setting, creating a Direct Data Entry menu of pages and elements, storing the configuration data into the Direct Data Entry menu, and sending a Direct Data Entry string for a requested element in the Direct Data Entry menu.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Integrated circuit having multiple modes of operation]]></title>
            <link>http://www.freepatentsonline.com./7640481.html</link>
            <description><![CDATA[A method according to one embodiment may include operating an integrated circuit in a selected mode of operation. The integrated circuit may include first circuitry and second circuitry. The first circuitry may be capable of performing at least one operation including, at least in part, generating check data based at least in part upon other data, regenerating the other data based at least in part upon the check data, and/or determining locations of the check data and the other data in storage. The second circuitry may be capable of controlling, at least in part, at least one interface to transmit from and/or receive at the integrated circuit the check data and/or the other data. Depending at least in part upon the selected mode of operation, the first circuitry may be either enabled to perform or disabled from performing the at least one operation.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Information processor and data communication control method capable of preventing problems in data communication caused by breakdowns]]></title>
            <link>http://www.freepatentsonline.com./7640456.html</link>
            <description><![CDATA[A DGP, upon detecting the occurrence of a fault in an IOP that controls a CH, causes another IOP that can control the CH to control the CH and reports to an EPU the occurrence of the fault in the CH and the recovery from the fault. The DGP stores information in a CH configuration table indicating that the other IOP is controlling the CH. Upon receiving the reports of the occurrence of the fault in the CH and the recovery, the EPU refers to the CH configuration table, verifies that the other IOP is controlling the CH, and provides data transfer instructions to the other IOP.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and apparatus for handling nested faults]]></title>
            <link>http://www.freepatentsonline.com./7640450.html</link>
            <description><![CDATA[Apparatus and a method for handling nested faults including the steps of determining whether a fault is a first level fault, responding to a determination of a first level fault by saving a first amount of state sufficient to handle a first level fault, and responding to a determination of a nested fault by saving an additional amount of state before handling the fault.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[System-on-chip power reduction through dynamic clock frequency]]></title>
            <link>http://www.freepatentsonline.com./7640446.html</link>
            <description><![CDATA[A dynamic clock frequency module for a system-on-chip (SOC) including modules that communicate over a system bus includes a request evaluation module that receives requests to utilize the system bus from the modules. A frequency assignment module calculates a clock frequency value for the system bus based on the requests received by the request evaluation module. The request evaluation module includes a summing module that generates a sum of requests between the modules. A pulse stretch module increases a period of time that at least one of the requests is asserted. A low pass filter prevents changes to the clock frequency value when the sum at least one of increases and decreases for less than a predetermined period. A slew rate control module adjusts at least one of a rate of increase and a rate of decrease in the clock frequency value.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Multi-function apparatus and control method thereof]]></title>
            <link>http://www.freepatentsonline.com./7640442.html</link>
            <description><![CDATA[A multi-function apparatus having a wider variety of uses and easily employed when carrying a USB cable only without having a power source cord. The apparatus includes means for detecting a connection between the USB interface and the PC, means for detecting a connection to the power line, and control means for selecting a function depending on a detected state of the connection between the USB interface and PC and a detected state of the connection to the AC power line. All the functions in the multi-function apparatus are operable in a connected state of the AC power line to the AC power source, while even in an unconnected state of the AC power line to the AC power source, if the USB interface is connected to the PC, a possible operation is enabled using electric power of 5 V at 500 mA supplied from the PC.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Initialization of flash storage via an embedded controller]]></title>
            <link>http://www.freepatentsonline.com./7640424.html</link>
            <description><![CDATA[A digital system including flash memory, coupled to a system-on-a-chip within which a flash memory subsystem controller is embedded, is disclosed. The system-on-a-chip includes support for a standard external interface, such as a Universal Serial Bus (USB) or IEEE 1394 interface, to which a host system such as flash memory test equipment can connect. Initialization of the flash memory is effected by opening a communications channel between the host system and the embedded flash memory subsystem controller. The host system can then effect initialization of the flash memory subsystem, including formatting of the flash memory arrays, loading application programs, and the like, over the communications channel.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and apparatus for implementing heterogeneous interconnects]]></title>
            <link>http://www.freepatentsonline.com./7640387.html</link>
            <description><![CDATA[Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transfer path is independent from a transfer of data on another transfer path. In some cases, data is concurrently transferred among more than two of the devices on at least one of the address interconnect and the data interconnect. Other embodiments are described and claimed.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Systems and methods for providing memory modules with multiple hub devices]]></title>
            <link>http://www.freepatentsonline.com./7640386.html</link>
            <description><![CDATA[Systems and methods for providing memory modules with multiple hub devices. Exemplary systems include a cascade-interconnect memory system with a memory bus, a memory controller and a memory module. The memory controller is in communication with the memory bus for generating, receiving and responding to memory access requests. The memory module includes a first hub device with three or more ports and a second hub device with three or more ports. A first port on the first hub device is in communication with the memory controller via the memory bus, a second port on the first hub device is in communication with a first set of memory devices, and a third port on the first hub device is cascade connected to a first port on the second hub device. A second port on the second hub device is in communication with a second set of memory devices and a third port on the second hub device supports a cascaded connection to a subsequent hub device in the memory system.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Dual-mode bus station and system for communications]]></title>
            <link>http://www.freepatentsonline.com./7640385.html</link>
            <description><![CDATA[A bus station in the form of a hardware dongle, operates in conjunction with a USB Device running suitable software. When the bus station determines that a bus host is connected to a first bus communication port thereof, it acts as a transceiver to allow conventional bus communications between said bus host and a bus device connected to a second bus communication port thereof. When the bus station determines that a bus device running suitable software is connected to the first bus communication port thereof, it acts as an alternate host to allow bus communications between said bus device connected to the first bus communication port and a bus device connected to a second bus communication port.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Queued locks using monitor-memory wait]]></title>
            <link>http://www.freepatentsonline.com./7640384.html</link>
            <description><![CDATA[A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. In one embodiment, a memory to store instructions to perform functions of a monitoring mechanism is provided. The monitoring mechanism having a first logic to cause a processor to exit a sleep state in response to an event, wherein exiting the sleep state comprises resuming control of processing resources that were relinquished by the processor during the sleep state. The monitoring mechanism having a second logic to disable monitoring of a node associated with a contended lock after the processor exits the sleep state.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and related apparatus for configuring lanes to access ports]]></title>
            <link>http://www.freepatentsonline.com./7640383.html</link>
            <description><![CDATA[A method and related apparatus for different lane and access port configurations of a bus. Such different configurations can apply to different applications requirements. In a preferred embodiment of the invention, a chipset can configure 18 lanes to 4 access ports of a peripheral communication interconnect express bus for selectively 4 different configurations. A first configuration provides single access port with 16 lanes, and two access ports for each has one lane. A second configuration provides two access ports for each has eight lanes, and two access ports for each has single lane. A third configuration provides one access port with eight lanes, two access ports for each has four lanes and another one access port with single lane. And a fourth configuration provides four access ports for each has four lanes.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Virtual media systems, methods and devices]]></title>
            <link>http://www.freepatentsonline.com./7640382.html</link>
            <description><![CDATA[In a KVM system, a system provides for USB devices to be accessed by target computers. A KVM switch connects a client with a target server via a network, the client computer having at least one device attached thereto. A second mechanism connects to a USB port of the target and communicates with the target using a USB protocol. A client mechanism communicates with the second mechanism via the network. A virtual media mechanism enables the target server to access the USB device attached to the client.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Input/output decoupling system method having a cache for exchanging data between non-volatile storage and plurality of clients having asynchronous transfers]]></title>
            <link>http://www.freepatentsonline.com./7640381.html</link>
            <description><![CDATA[An I/O decoupling system comprising an I/O accelerator coupled between a host interface and a channel interface, wherein the I/O accelerator comprises a host manager, a buffer manager a function manager, and a disk buffer. The host manager is coupled to the host interface to receive a request from a connected host computer. The function manager in response to receiving the request allocates the disk buffer and determines a threshold offset for the buffer while coordinating the movement of data to the disk buffer through the channel interface coupled to the disk buffer.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Disk-array device having storage-device recognition and identification of a storage area network link environment]]></title>
            <link>http://www.freepatentsonline.com./7640380.html</link>
            <description><![CDATA[A disk-array device includes an information managing database for acquiring link information among a server device, a switch device, and a storage device via the switch device so as to manage the link information in a combined manner, and a collection/analysis unit for retrieving and collecting desired combined information of the link information from the information managing database so as to analyze the desired combined information.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[System method for I/O pads in mobile multimedia processor (MMP) that has bypass mode wherein data is passed through without being processed by MMP]]></title>
            <link>http://www.freepatentsonline.com./7640379.html</link>
            <description><![CDATA[In a multimedia system, a method and system for input/output pads in a mobile multimedia processor are provided. Input, output, and/or bidirectional pads in a host bus interface and/or a slave bus interface may be configured to provide bypass capabilities when a mobile multimedia processor is powered down or hibernating. The pads may be adapted to provide pull-up and pull-down capabilities. The pull-up and pull-down capabilities may be dynamically programmed.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and apparatus for improving the performance of USB mass storage devices in the presence of long transmission delays]]></title>
            <link>http://www.freepatentsonline.com./7640378.html</link>
            <description><![CDATA[A method and apparatus for improving the performance of Universal Serial Bus mass storage devices is provided wherein a local extender located adjacent to a host computer is used in combination with a remote extender located adjacent to a peripheral device. The local extender and remote extender units jointly implement a protocol that enables bulk data to be transferred efficiently between the units even when the transmission delay between the units exceeds 1 microsecond. No alterations to the host computer or the USB mass storage device are required to achieve the improved performance. An improved method for connecting USB mass storage devices to a host controller is provided.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[DMA circuit with pattern generation unit for DMA verification]]></title>
            <link>http://www.freepatentsonline.com./7640377.html</link>
            <description><![CDATA[In a send engine of a protocol/DMA control circuit, a descriptor control circuit obtains a descriptor, and notifies the information of the descriptor to each circuit. A dummy/padding generation circuit generates a data pattern according to the instruction of the descriptor. A write control circuit performs data transfer using the generated data pattern as a dummy transfer data according to the instruction of the descriptor. The write control circuit also inserts the generated data pattern into the transfer data as a padding data according to the instruction of the descriptor, and performs data transfer.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method apparatus and computer programming product for direct memory access(DMA) technique on sequentially stored data]]></title>
            <link>http://www.freepatentsonline.com./7640376.html</link>
            <description><![CDATA[A memory includes a set of sequentially stored data. Each of the data includes a variable-length data and length information indicative of a data length of the variable-length data. An MPU creates a read instruction for reading the set of data. A DMS chip, upon receiving the read instruction, reads length information from the memory, calculates a storage location of subsequent data in the memory, and reads the subsequent data from the first memory. Thus, the DMS chip reads the subsequent data from the memory instead of the MPU thereby reducing load on the MPU.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[DMA controller, method, information processing system, and program for transferring information blocks comprising data and descriptors]]></title>
            <link>http://www.freepatentsonline.com./7640375.html</link>
            <description><![CDATA[In a DMA control method in which a DMA controller transfers data in memory to an input/output device in accordance with the control information which is provided by a processing device to a DMA controller, a processing device implements a step in which the processing device sets an information block comprising the control information and the data in the memory; a step in which address information of the information block is provided by the processing device to the DMA controller; a step in which the DMA controller reads the information block from the memory based on the address information and extracts the control information; and a step in which the DMA controller transfers the data in the information block to the I/O device based on the control information.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Data transfer apparatus by direct memory access controller]]></title>
            <link>http://www.freepatentsonline.com./7640374.html</link>
            <description><![CDATA[A DMA apparatus which reads data corresponding to a descriptor from memory, and a dividing unit in a descriptor management device divides one descriptor into a plurality of sub-descriptors. A plurality of DMA controllers produce a plurality of reading requests for reading data corresponding to the plurality of sub-descriptors from the memory. A memory controller reads the corresponding data from the memory according to the plurality of reading requests.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and apparatus for channel quality feedback within a communication system]]></title>
            <link>http://www.freepatentsonline.com./7640373.html</link>
            <description><![CDATA[A base station ( 101 ) will request the transmission of quality information from a particular remote stations ( 102, 103 ) only when data is queued to be transmitted to the remote stations. Once a remote station begins the transmission of channel quality information, the transmission of such information continues until the data transmission is successfully delivered to the remote station. The base station receives the channel quality information and adjusts the modulation and coding of the remote stations accordingly. Where data is transmitted simultaneously to a plurality of remote stations, a set of queues ( 303 ) for the multiple remote stations is maintained, and based on queue status, a channel quality request messages is sent to a sub-set of remote stations with data queued.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Information processing apparatus, control method thereof, program, and storage medium]]></title>
            <link>http://www.freepatentsonline.com./7640372.html</link>
            <description><![CDATA[An information processing apparatus connectable to a server via a network and performing information processing. The information processing apparatus includes a managing unit configured to manage count information pertaining to the information processing, a notifying unit configured to notify the server of the count information managed by the managing unit, a receiving unit configured to receive, from a user, an instruction of deleting the count information managed by the managing unit, and a control unit configured to control the notifying unit to notify the server of the count information managed by the managing unit when the receiving unit receives the instruction.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Integrated circuit and information processing apparatus]]></title>
            <link>http://www.freepatentsonline.com./7640371.html</link>
            <description><![CDATA[When a program from a master device  1  is received during a burst mode, a slave device  2  judges that an address field is also treated as a data field and extracts data in the address field as the program. The slave device  2  uses a transmission FIFO  222  as an extension FIFO of a reception FIFO  224  during the burst mode.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and apparatus for controlling data transfer between EEPROM and a physical layer device]]></title>
            <link>http://www.freepatentsonline.com./7640370.html</link>
            <description><![CDATA[An IEEE 802.3 compliant physical layer device provides efficient loading of configuration information of the physical layer device. The configuration information is written into a volatile memory in the physical layer device, and then uploaded to at least one EEPROM. The configuration information is downloaded to the volatile memory during startup of the physical layer device. The system controller can also directly access the EEPROMs, bypassing the volatile memory. By providing a bridge between the system controller and the EEPROMs and providing additional bits in the volatile memory of the physical layer device, the system controller can read and write the EEPROMs one byte at a time. During reset time, the content of the EERPOMs is written to registers in the physical layer device to configure the physical layer device.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Peripheral device capable of blocking and unblocking connection detection]]></title>
            <link>http://www.freepatentsonline.com./7640369.html</link>
            <description><![CDATA[A peripheral device has a communication section for communicating with operational equipment, the operational equipment including a detecting unit configured to detect a peripheral device, and an installing unit configured to install a driver to control the peripheral device detected by the detecting unit, a first setting section configured to set a blocking state that blocks detection by the detecting unit prior to activation of the installing unit, a determining section configured to determine whether the installing unit has been activated or not, and a second setting section configured to cancel the blocking state set by the first setting section after the determining section determines that the installing unit has been activated and configured to set a permitting state in which detection by the detecting unit is permitted.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Automatic driver installation method and system]]></title>
            <link>http://www.freepatentsonline.com./7640368.html</link>
            <description><![CDATA[A method and system for automatically installing drivers in a host device for driving an apparatus that is connected to the host device and having at least one emulation. The method includes the steps of executing a driver installation module included in the host device, the driver installation module requesting the apparatus to transmit model information of the apparatus and emulation information indicating which emulations are included with the apparatus, and receiving the emulation information and the model information from the apparatus. The driver installation module then automatically selecting and installing drivers based on the received emulation information and the received model information.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method for executing a software updating process and computer for implementing the method]]></title>
            <link>http://www.freepatentsonline.com./7640367.html</link>
            <description><![CDATA[A method to update firmware in a plurality of peripheral devices and a computer using the method to reduce data transmission collisions and to reduce the time required to complete the update process. The process involves sending firmware update data from a computer that is connected to a communication network to printers or other peripheral devices that are also connected to the communication network. The computer  11  groups a plurality of peripheral devices (such as printers  13 a 1 ) connected to the communication network into separate transmission unit groups each containing up to a maximum number of peripheral devices with the maximum number determined by measuring the transmission speed of the network and thereafter deriving the maximum number by experimentation at the measured transmission speed. The update data for updating the firmware is transmitted to the peripheral devices of any one transmission unit group. Thereafter update data is sequentially transmitted to the peripheral devices in another transmission unit group but not until the completion of transmitting the update data to all of the peripheral devices in the first transmission unit group is confirmed.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Storage controller to control access to storage device via serial communication unit by executing control step units]]></title>
            <link>http://www.freepatentsonline.com./7640366.html</link>
            <description><![CDATA[A storage controller includes a CPU for controlling each component in the storage controller; a ROM for storing programs executed by the CPU and data required for this execution; a RAM employed as a work area when the CPU executes the programs; a first ASIC (USB system) for controlling data transfers based on the USB standard; slots in which can be inserted various external memory units; a second ASIC (external memory system) for controlling data accesses to the external memory units to read data therefrom or write data thereto; and an address bus and a data bus connecting these components to one another.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Highly reliable disk controller]]></title>
            <link>http://www.freepatentsonline.com./7640365.html</link>
            <description><![CDATA[Provided is a unit for protecting data with respect to data transfer between memories of a disk controller. The disk controller for controlling data transfer between a host computer and a disk drive includes: a channel unit having a channel memory; a cache unit having a cache memory, and a control unit for controlling the data transfer. The data transferred to/from the host computer is transferred in a packet between the channel memory and the cache memory, and The control unit for verifying consistency of information included in a header of the packet to be transferred to decide whether transfer can be permitted when the packet is transferred.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Methods and apparatus for issuing updates to multiple management entities]]></title>
            <link>http://www.freepatentsonline.com./7640325.html</link>
            <description><![CDATA[A system for updating management entities or devices in a computer system network with configuration change information from the devices being managed. The management entities are configured to discover, monitor and configure managed devices, such as storage systems, connected to the network. Preferably, the managed devices include a comparator which can track changes made to the managed device configuration or properties and report that change back to the various management entities. In this way, the management entities can keep track of the configurations of the various devices that they manage, even though they might not be responsible for issuing the configuration change. This can be accomplished even when managed devices developed by different manufacturers according to different standards or protocols are involved.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Implementing locks in a distributed processing system]]></title>
            <link>http://www.freepatentsonline.com./7640315.html</link>
            <description><![CDATA[A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using an interconnect structure of dual-unidirectional links. Each unidirectional link forms a point-to-point interconnect to transfer packetized information between two processing nodes. A lock acquisition request from a lock requesting node is placed into service by an arbitrating node when no previous lock requests are pending for service. The arbitrating node transmits a broadcast message to all nodes in the system, which, in turn, respond with a corresponding probe response message to inform the arbitrating node of cessation of issuance of new requests by the node sending the probe response message. The arbitrating node informs the lock requesting node of the requesting node's lock ownership by transmitting a target done message thereto. After completion of lock operations, the lock requesting node sends a lock release request to the arbitrating node, which, in turn, informs all processing nodes of lock release by transmitting another broadcast message within the system. The messaging protocol is completed when each node sends another probe response to the arbitrating node, which, in turn, sends a final target done message to the lock requesting node. Lock operations are performed without contention for system resources and without deadlocks among various processing nodes.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Unified control and memory for a combined DVD/HDD system]]></title>
            <link>http://www.freepatentsonline.com./7639927.html</link>
            <description><![CDATA[A combined digital versatile disc (DVD)/hard disk drive (HDD) system controls a HDD assembly and a DVD assembly comprises a DVD/HDD control module controls operation of the HDD assembly and the DVD assembly. Volatile memory communicates with the DVD/HDD control module and stores volatile data relating to the operation of the DVD assembly and the HDD assembly. Nonvolatile memory communicates with the DVD/HDD control module and stores nonvolatile data relating to the operation of the DVD assembly and the HDD assembly.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Unified control and memory for a combined DVD/HDD system]]></title>
            <link>http://www.freepatentsonline.com./7639926.html</link>
            <description><![CDATA[A combined digital versatile disc (DVD)/hard disk drive (HDD) system controls a HDD assembly and a DVD assembly comprises a DVD/HDD control module controls operation of the HDD assembly and the DVD assembly. Volatile memory communicates with the DVD/HDD control module and stores volatile data relating to the operation of the DVD assembly and the HDD assembly. Nonvolatile memory communicates with the DVD/HDD control module and stores nonvolatile data relating to the operation of the DVD assembly and the HDD assembly.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Variable size FIFO memory]]></title>
            <link>http://www.freepatentsonline.com./7639707.html</link>
            <description><![CDATA[A variable size first in first out (FIFO) memory is disclosed. The variable size FIFO memory may include head and tail FIFO memories operating at a very high data rate and an off chip buffer memory. The off chip buffer memory may be, for example, of a dynamic RAM type. The off chip buffer memory may temporarily store data packets when both head and tail FIFO memories are full. Data blocks of each of the memories may be the same size for efficient transfer of data. After a sudden data burst which causes memory overflow ceases, the head and tail FIFO memories return to their initial functions with the head FIFO memory directly receiving high speed data and transmitting it to various switching element and the tail FIFO memory storing temporary overflows of data from the head FIFO memory.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Magnetic disk controller and method]]></title>
            <link>http://www.freepatentsonline.com./7639443.html</link>
            <description><![CDATA[Among other disclosed subject matter, a magnetic disk controller includes an interface that receives and transmits data to be written into a magnetic disk. The magnetic disk controller includes a first buffer and a second buffer each of which temporarily stores data that is to be written into at least one sector of the magnetic disk. The magnetic disk controller includes an encoding unit that encodes the data stored in any of the first buffer and the second buffer into data representing a signal to be applied to the magnetic disk. A data width M between the encoding unit and the first and second buffers is at least equal to twice a data width N between the interface and the first and second buffers.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[System and method of validating asset tracking codes]]></title>
            <link>http://www.freepatentsonline.com./7639144.html</link>
            <description><![CDATA[A system and method for validating adherence of an UII identifier code to one of several prescribed DOD codes by means of a programmed series of tests. First the code is tested for a prescribed header and a last character message. If one or the other is not found, the process stops and an error message is displayed. Field separator characters are identified that divide the message into fields. If the header, end of message character, and field separator are found and tested successfully, the program proceeds, and searches for an identifier of one of the DOD prescribed semantic formats. The semantic format identifier is extracted and tested. If valid, the process proceeds. If not, an error message is displayed. In proceeding, each field is stored, and the data from each field is extracted in accordance with the format identifier that had been extracted.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[In-vehicle electronic system, in-vehicle electronic apparatus and method of controlling power supply of portable electronic device]]></title>
            <link>http://www.freepatentsonline.com./7638896.html</link>
            <description><![CDATA[An in-vehicle electronic system includes: an in-vehicle electronic apparatus mounted in a vehicle; and a portable electronic apparatus detachably provided to the in-vehicle electronic apparatus, and the in-vehicle electronic apparatus causes the portable electronic apparatus to be operable, when the in-vehicle electronic apparatus being operable detects attachment of the portable electronic apparatus.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[System and method for combining low-power signals and high-power signals on a single circuit board in a gaming machine]]></title>
            <link>http://www.freepatentsonline.com./7637816.html</link>
            <description><![CDATA[A gaming control board having low-power circuitry and high-power circuitry for controlling the operation of a gaming machine. The low-power circuitry includes logic components including a CPU that executes instructions for randomly selecting a plurality of game outcomes in response to wagers inputted by a player. The high-power circuitry includes high-power components such as lamp drivers for interfacing high-power signals between the gaming control board and a game interface board. Two connectors are provided on the gaming control board, one to interface low-power signals and another to interface high-power signals. The high-power circuitry is located near the connector interfacing the high-power signals for optimal EMI suppression.]]></description>
            <pubDate>Tue, 29 Dec 2009 08:00:00 EST</pubDate>
        </item>
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