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Buffer-layer treatment of MOCVD-grown nitride structures

April 29, 2008

Methods are disclosed for fabricating a compound nitride semiconductor structure. An amorphous buffer layer that includes nitrogen and a group-III element is formed over a substrate disposed within a substrate processing chamber at a first temperature. The temperature within the chamber is increased to a second temperature at which the amorphous buffer layer coalesces into crystallites over the substrate. The substrate is exposed to a corrosive agent to destroy at least some of the crystallites. A crystalline nitride layer is formed over the substrate at a third temperature using the crystallites remaining after exposure to the corrosive agent as seed crystals. The third temperature is greater than the first temperature. The crystalline nitride layer also includes nitrogen and a group-III element.

Semiconductor package and substrate having multi-level vias fabrication method

April 29, 2008

A semiconductor package and substrate having multi-level plated vias provide a high density blind via solution at low incremental cost. Via are half-plated atop a circuit pattern and then a second via half is added to complete the via after isolation of elements of the circuit pattern. Successive resist pattern applications and etching are used to form a via tier atop a circuit pattern that is connected by a thin plane of metal. After the tier is deposited, the thin metal plane is etched to isolate the circuit pattern elements. Dielectric is then deposited and the top half of the via is deposited over the tier. The tier may have a larger or smaller diameter with respect to the other half of the via, so that the via halves may be properly registered. Tin plating may also be used to control the etching process to provide etching control.

Carbon nanotube interconnects in porous diamond interlayer dielectrics

April 29, 2008

A method and structure for using porous diamond interlayer dielectrics (ILDs) in conjunction with carbon nanotube interconnects is herein described. A diamond ILD is deposited on an underlaying layer. The diamond layer is optionally and selectively removed of non-sp3 bond to create a porous diamond film. Trenches and vias are etched in the porous diamond ILD. Carbon nanotubes are deposited on the diamond ILD filling the trenches using a liquid crystal host-carbon nanotube solution. Using methods of nematic liquid crystal alignment, the carbon nanotubes are aligned under the influence of the liquid crystals. At least some of the liquid crystal solution is removed leaving an aligned carbon nanotubes.

Method for interconnecting semiconductor components with substrates and contact means

April 29, 2008

A semiconductor component includes a substrate having a plurality of compliant contact bumps formed over a surface thereof. A semiconductor chip has a plurality of contact regions formed over a surface thereof. The compliant contact bumps of the substrate are electrically connected with the contact regions of the semiconductor chip and wherein the semiconductor chip is mechanically attached to the substrate. As an example, this connection and attachment can be achieved by soldering the contact bumps to the contact regions.

Capacitance detection type sensor and manufacturing method thereof

April 29, 2008

Capacitance sensor electrodes are arranged in a form of matrix on a semiconductor substrate and coated with a cover film. These capacitance sensor electrodes are connected to a drive circuit. ESD electrodes are arranged in the vicinities of corner portions of the capacitance sensor electrodes. Each ESD electrode is composed of a film containing, for example, aluminum excellent in conductivity and a TiN film formed thereon. The ESD electrodes are grounded through the semiconductor substrate. On each ESD electrode, a plurality of fine ESD holes reaching the ESD electrode from a surface of the cover film are formed.

Shallow trench isolation process utilizing differential liners

April 29, 2008

A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.

System for the preferential removal of silicon oxide

April 29, 2008

A system, composition, and a method for planarizing or polishing a composite substrate are provided. The planarizing or polishing system comprises (i) a polishing composition comprising (a) about 0.5 wt. % or more of fluoride ions, (b) about 1 wt. % or more of an amine, (c) about 0.1 wt. % or more of a base, and (d) water, and (ii) an abrasive. The present invention also provides a method of planarizing or polishing a composite substrate comprising contacting the substrate with a system comprising (i) a polishing composition comprising (a) about 0.5 wt. % or more of fluoride ions, (b) about 1 wt. % or more of an amine, (c) about 0.1 wt. % or more of a base, and (d) water, and (ii) an abrasive.

Atmospheric process and system for controlled and rapid removal of polymers from high aspect ratio holes

April 29, 2008

A system that generates an intense hot gas stream is described to etch a polymer on a substrate used in the manufacture of semiconductor and MEMS devices with no surface damage. The etching process is particularly useful to remove a polymer from relatively high aspect Height-to-Width and Width-to-Height ratio holes that can include trenches, having relatively large aspect ratios for removal of polymers used in connection with the manufacturing of microstructures.

Method of fabricating an interconnection layer above a ferroelectric capacitor

April 29, 2008

A highly reliable semiconductor device having a ferroelectric capacitor structure by sufficiently preventing the H 2 attack without damaging the function of an interlayer insulating film covering interconnections and the like to obtain a high capacitor performance. The position of a semiconductor substrate mounted on and secured to a substrate support plate in an HDP-CVD system is adjusted in the vertical direction, whereby a second HDP-CVD oxide film is deposited so that voids are formed between aluminum interconnections at lower positions than the height of the aluminum interconnections.

Double gate FET and fabrication process

April 29, 2008

A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material, an upper gate insulating layer of crystalline rare earth insulating material, and an upper gate layer of crystalline rare earth conductive material. The upper gate layer and the upper gate electrically insulating layer are etched and a contact is deposited on the upper gate layer to define an upper gate structure. An impurity is implanted into the lower gate layer to define a lower gate area aligned with the upper gate structure. A source and drain are formed in the active layer and contacts are deposited on the source and drain, respectively.

Method for fabricating semiconductor device

April 29, 2008

A method for fabricating a semiconductor device is provided. The method includes: implanting impurities onto a substrate by performing an ion implantation process; recessing portions of the substrate to form a plurality of trenches; performing a first thermal process to form junction regions between the trenches in the substrate by diffusing the impurities and simultaneously to form a gate oxide layer on the substrate and on the junction regions; forming a polysilicon layer on the gate oxide layer; sequentially etching the polysilicon layer and the gate oxide layer to form a gate structure, and to form first spacers on lateral walls of the junction regions; forming second spacers on lateral walls of the first spacers and the gate structure; and forming a metal silicide layer on top portions of the junction regions and the gate structure.

Method of manufacturing NOR-type mask ROM device and semiconductor device including the same

April 29, 2008

A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.

Methods of fabricating patterned layers on a substrate

April 29, 2008

A method of fabricating a pattern on a substrate, comprises the steps of: depositing; such as by ink-jet printing, multiple drops of a first liquid material as a first deposit ( 15 ) on the substrate: depositing, such as by ink-jet printing, multiple drops of a second liquid material ( 17 ) as a second deposit on the substrate, and in contact with the first material ( 15 ) while the first material is liquid, the first and second liquid materials being mutually immiscible; and producing on the substrate a solid deposit from at least one of said liquid materials. In a preferred embodiment, the method comprises ink-jet printing multiple drops of liquid material immiscible with said second liquid material as a third deposit ( 16 ) on the substrate, the third deposit ( 16 ) being spaced from the first ( 15 ) by a predetermined gap and the second deposit ( 17 ) applied in said gap overlapping the first and third deposits ( 15, 16 ). At least one of the deposits may contain a suspension or solute, and said solid deposit may be formed by solidification of at least one of said liquids. Applicable to the production of thin-film transistor arrays or other integrated circuits.

Microelectronic imaging units and methods of manufacturing microelectronic imaging units

April 29, 2008

Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method for manufacturing a plurality of microelectronic imaging units includes placing a plurality of singulated imaging dies on a support member. The individual imaging dies include a first height, an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member and forming a base on the support member between adjacent imaging dies. The base has a second height less than or approximately equal to the first height of the dies. The method further includes attaching a plurality of covers to the base so that the covers are positioned over corresponding image sensors.

Porous underlayer coating and underlayer coating forming composition for forming porous underlayer coating

April 29, 2008

There is provided an underlayer coating causing no intermixing with photoresist layer and having a high dry etching rate compared with photoresist, which is used in lithography process of manufacture of semiconductor device. Concretely, it is an underlayer coating forming composition for forming a porous underlayer coating for use in manufacture of semiconductor device, comprising a blowing agent, an organic material and a solvent, or a polymer having a blowing group and a solvent. The underlayer coating formed from the composition has porous structure which has pores therein, and makes possible to attain a high dry etching rate.

Electronic device and method of manufacturing the same

April 29, 2008

In the present invention, an etching hole 21 is formed in a polysilicon film 14 as a cavity-wall member. Through the etching hole 21 , hydrofluoric acid is injected, so as to dissolve a silicon oxide film 13 , thereby forming a cavity 22 . In the cavity 22 , a detecting unit 12 of a sensor is in an exposed condition. Next, by sputtering, an Al film 16 is deposited in the etching hole 21 and on an upper face of a substrate. Thereafter, a portion of the Al film 16 positioned on the polysilicon film 14 is removed by etching back, thereby leaving only a metal closure 16 a of Al which closes the etching hole. The sputtering step is performed under a pressure of 5 Pa or less, so that the pressure in the cavity can be held to be low.

SRAM cell design for soft error rate immunity

April 29, 2008

A new method to form a SRAM memory cell in an integrated circuit device is achieved. The method comprises providing a bi-stable flip-flop cell having a data storage node and a data bar storage node. A first capacitor is formed coupled to the data bar storage node, and a second capacitor is formed coupled to the data storage node. The first and second capacitors comprise a first conductor layer overlying a second conductor layer with a dielectric layer therebetween. One of the first and second conductor layers is coupled to ground. A new SRAM device is disclosed.

Method for manufacturing gallium nitride light emitting diode devices

April 29, 2008

A method for manufacturing GaN LED devices is disclosed herein. First, a LED epitaxial layer is formed on a provisional substrate. Part of the LED epitaxial layer is removed to form a plurality of LED epitaxial areas. Then, a first transparent conductive layer, a metal reflective layer, and a first metal bonding layer are sequentially formed on the plurality of LED epitaxial areas and then part of the first transparent conductive layer, the metal reflective layer, and the first metal bonding layer are removed. Next, a permanent substrate is provided. At least a metal layer and a second metal bonding layer are formed on the permanent substrate. Then, part of at least the metal layer and the second metal bonding layer are removed. Next, the provisional substrate is bonded to the permanent substrate by aligned wafer bonding method. Then, the provisional substrate is removed to expose a surface of the LED epitaxial layer and then an n-type electrode is formed on the surface. Next, the permanent substrate is cut to form a plurality of LED devices.

Method of fabricating semiconductor device

April 29, 2008

There is provided a method of fabricating semiconductor devices that allows ion implantation to be performed at high temperature with ions accelerated with high energy to help to introduce dopant in a semiconductor substrate, in particular a SiC semiconductor substrate, at a selected region to sufficient depth. To achieve this the method includes the steps of: providing the semiconductor substrate at a surface thereof with a mask layer including a polyimide resin film, or a SiO 2 film and a thin metal film; and introducing dopant ions.

CMOS image sensor and method for fabricating the same

April 29, 2008

A CMOS image sensor and a method for fabricating the same improve photosensitivity by imparting a color filter layer with the function of a microlens layer. The CMOS image sensor includes a semiconductor substrate; a plurality of photo-sensing elements formed in the semiconductor substrate; and a color filter layer comprised of a plurality of color filters for filtering light according to wavelength, wherein the plurality of color filters correspond to the plurality of photo-sensing elements and each color filter has a predetermined curvature for focusing light and for transmitting the focused light according to a corresponding wavelength.

Method for manufacturing semiconductor device

April 29, 2008

The invention is aimed to prevent that fall of characteristic of a solar battery and producing yield caused by particles of powder condition generating from working part at laser beam process in the method producing the solar battery by laser beam process. The constitution of the invention is characterized by comprising: a first step forming the lower electrode and the semiconductor layer on the insulating substrate by laminating; a second step forming a protective film on surface of the semiconductor; a third step forming an opening portion at the semiconductor layer, or the semiconductor layer and the lower electrode by laser beam process after the second step; and a fourth step removing the protective film.

Semiconductor device package

April 29, 2008

A semiconductor package that includes two circuit boards and at least one semiconductor device which is disposed between the two circuit boards and connected to external connectors disposed on at least one of the circuit boards.

Method for etching upper metal of capacitator

April 29, 2008

A method for etching an upper metal film of a capacitor, enables a safe etching of the upper metal film of a capacitor by exploiting an over-etch step. The method for etching the upper metal film of the capacitor includes the steps of forming a lower metal film, a lower nitride film, an upper metal film, and an upper nitride film on a substrate having a predetermined device formed thereon, and then forming a pattern thereover; etching the upper nitride film with CHF 3 , Ar and Cl 2 using the pattern; over etching the upper metal film more than 50% with CHF 3 , Ar and N 2 using the pattern; etching the upper metal film with CHF 3 , Ar and N 2 using the pattern; and etching the lower nitride film with CHF 3 and Ar using the pattern.

Reticle fabrication using a removable hard mask

April 29, 2008

We have reduced the critical dimension bias for reticle fabrication. Pattern transfer to the radiation-blocking layer of the reticle substrate essentially depends upon use of a hard mask to which the pattern is transferred from a photoresist. The photoresist pull back which occurs during pattern transfer to the hard mask is minimalized. In addition, a hard mask material having anti-reflective properties which are matched to the reflective characteristics of the radiation-blocking layer enables a reduction in critical dimension size and an improvement in the pattern feature integrity in the hard mask itself. An anti-reflective hard mask layer left on the radiation-blocking layer provides functionality when the reticle is used in a semiconductor device manufacturing process.

Semiconductor device

April 29, 2008

A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.

Method for producing a memory cell

April 29, 2008

A method for producing a memory cell includes masking a desired polysilicon structure with an oxidation-inhibiting layer, preferably a nitride layer. The polysilicon above source/drain regions and field regions is then converted into silicon dioxide. At the same time, filling with silicon dioxide is effected between adjacent polysilicon paths. The field oxide thickness is increased by the conversion of polysilicon in the field regions as well. A second polysilicon layer is applied over a field region, with inclusion of the oxidation-inhibiting layer present there. One electrode of a capacitor is produced therefrom through the use of marking and etching, with the first polysilicon situated under the oxidation-inhibiting layer forming another electrode and the oxidation-inhibiting layer forming a dielectric. The structure provides a less complex masking and etching technique as well as improved reliability of the components.

Damascene replacement metal gate process with controlled gate profile and length using Si_1-xGe_xas sacrificial material

April 29, 2008

A method of forming a metal gate in a wafer. PolySi 1-x Ge x and polysilicon are used to form a tapered groove. Gate oxide, PolySi 1-x Ge x , and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi 1-x Ge x , and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolyS 1-x Ge x , and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi 1-x Ge x , and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.

Selective etch for patterning a semiconductor film deposited non-selectively

April 29, 2008

A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A four-component wet etch mixture is tuned to selectively etch the amorphous region while retaining the epitaxial region, wherein the four-component wet etch mixture comprises an oxidizing agent, an etchant, a buffer and a diluent.

Method for fabricating semiconductor package

April 29, 2008

A semiconductor package and a fabrication method thereof are proposed. A lead frame is provided between a chip and a substrate in a window ball grid array semiconductor package, wherein an active surface of the chip is electrically connected to the lead frame via bonding wires formed in an opening of the substrate and is electrically connected to the substrate via the lead frame. The provision of lead frame can improve the heat dissipating efficiency and electrical performances. The bonding wires located in the opening of the substrate eliminate the prior-art drawback of requiring different molds in response to different opening structures of a substrate.

Method for manufacturing a superjunction device with wide mesas

April 29, 2008

A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.

Silicon phosphor electroluminescence device with nanotip electrode

April 29, 2008

An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.

Method for manufacturing semiconductor device

April 29, 2008

In a method of forming a semiconductor device, a copper diffusion-prevention layer is formed underneath a substrate. Impurity regions are formed on the surface of the substrate. A copper wiring is electrically connected to the impurity regions. The copper diffusion-prevention layer is formed before forming the lightly doped source/drain regions to prevent copper atoms from diffusing into the substrate.

Method for manufacturing a MOS transistor

April 29, 2008

A method for manufacturing a MOS transistor integrated into a chip of semi-conductive material comprising a first and a second active region which extend from the inside of the chip to a surface of the chip. The method comprises the steps of: a) forming a layer of insulating material on the surface of the chip and depositing a layer of conductive material on said insulating layer, b) defining an insulated gate electrode of the transistor, from said superimposed insulating and conductive layers, c) defining, from said superimposed insulating and conductive layers, an additional structure arranged on a first surface portion of the first active region, and d) placing between the insulated gate electrode and the additional structure a dielectric spacer placed on a second surface portion of the first active region.

Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry

April 29, 2008

The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.

Chemical solution coating method and chemical solution coating apparatus

April 29, 2008

A chemical solution coating method includes: a first step of disposing a semiconductor substrate on a substrate supporting unit with a first face to be coated with a chemical solution facing upward; a second step of moving a chemical solution spraying member for spraying the chemical solution to an initial position which is positioned in the vicinity of the first face of the semiconductor substrate and where the chemical solution is to be applied; and a third step of moving the chemical solution spraying member from the initial position in accordance with a predetermined travel pattern and, simultaneously, spraying the chemical solution from the chemical solution spraying member toward the first face of the semiconductor substrate.

Method for fabricating thermally enhanced semiconductor package

April 29, 2008

A thermally enhanced semiconductor package and a fabrication method thereof are provided. A plurality of conductive bumps are formed on bond pads on an active surface of a chip. A heat sink is attached to an inactive surface of the chip and has a surface area larger than that of the chip. An encapsulation body encapsulates the heat sink, chip and conductive bumps, while exposing a bottom or surfaces, not for attaching the chip, of the heat sink and ends of the conductive bumps outside. A plurality of conductive traces are formed on the encapsulation body and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with a plurality of openings for exposing predetermined portions of the conductive traces. A solder ball is implanted on each exposed portion of the conductive traces.

Fabrication of semiconductor device for flash memory with increased select gate width

April 29, 2008

A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3 F or 5 F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F, and select gates of width 3 F spaced apart by 3 F or 5 F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.

Semiconductor device and method of fabrication

April 29, 2008

A semiconductor device having a DRAM has a capacitor in which a dielectric film and an upper electrode are laminated on a lower electrode comprising a polysilicone, in which a natural oxide film oxidized by oxygen in the atmosphere grows to at least 1.5 nm on the surface of a lower electrode of the capacitor. Further, in forming the dielectric film, the dioxide film further grows in the case of using an oxidative raw material. This brings forth a reduction in capacitance, and an increase of a leakage current is caused. Therefore, after a dielectric film having a reduction property has been formed, the reduction property is promoted by a heat treatment to thereby reduce a dioxide film and realize making the dioxide film on the lower electrode surface thinner.

Anhydrous HF release of process for MEMS devices

April 29, 2008

A method of etching a sacrificial oxide layer covering an etch-stop silicon nitride underlayer, involves exposing the sacrificial oxide to anhydrous HF at a temperature of less than about 100° C. and/or at vacuum level lower than 40 Torr; and subsequently performing an in-situ vacuum evaporation of etch by-products at a temperature of more than about 100° C. and at vacuum level lower than the 40 Torr without exposure to ambient air.

Interconnects with direct metalization and conductive polymer

April 29, 2008

Embodiments include an interconnect or trace of electrically conductive material with a contact surface, and a dielectric layer overlying the contact surface with a via formed on the dielectric layer and to the contact surface. The via sidewalls and perimeter are layered with a manganese oxide (MnO 2 ) layer which is layered over with a conductive polymer material. An interconnect material is formed in the via and in a trench above the perimeter of the via such that the interconnect material is on the conductive polymer material and contacts the contact surface. An additional dielectric layer may be formed over the interconnect material and an additional via may be formed therethrough so that an additional structure having a MnO 2 layer, conductive polymer material, and interconnect material can be formed in the additional via and to the interconnect material.

Methods of fabricating a semiconductor device using an organic compound and fluoride-based buffered solution

April 29, 2008

Methods are provided for fabricating a semiconductor device that include the steps of: sequentially forming a metal interconnection and a protecting layer on a semiconductor substrate; forming a contact hole on the protecting layer; isolating the contact hole by forming a molding layer and an etching stop layer stacked thereon; forming a sacrificial layer on the etching stop layer so as to fill the contact hole; forming a photoresist layer with an opening so as to expose the sacrificial layer and such that the opening of the photoresist layer aligns with the contact hole; forming a trench in the molding layer to penetrate the sacrificial layer and the etching stop layer; and performing a wet etching on the semiconductor substrate having the trench to remove the photoresist layer and the sacrificial layer, wherein the wet etching step is performed using an organic compound and fluoride ion-based buffered solution.

Method for manufacturing semiconductor device having super junction construction

April 29, 2008

A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the first part. The trench gate electrode penetrates the body region and reaches the drift region so that the trench gate electrode faces the body region and the drift region through an insulation layer. The trench gate electrode extends in a direction crossing with the extending direction of the first and second parts. The first part includes a portion near the trench gate electrode, which has an impurity concentration equal to or lower than that of the body region.

Method for manufacturing SOI substrate

April 29, 2008

The object of the invention is to provide a method for manufacturing an SOI layer which is devoid of damages, has a reduced variation in thickness, and is uniform in thickness. The object is met by providing a method for manufacturing an SOI substrate comprising the steps of forming an oxide film at least on one surface of a first silicon substrate, implanting hydrogen ions from the surface of the first silicon substrate thereby forming an ion-implantation zone in the interior of the first silicon substrate, bonding the first silicon substrate over a second silicon substrate with the oxide film interposed thereby forming a laminated assembly, subjecting the laminated assembly to a first heating treatment consisting of heating at a specified temperature, so that the first silicon substrate is split at the ion-implantation zone thereby manufacturing a bonded substrate, flattening the exposed surface of the SOI layer by subjecting the bonded substrate to wet etching, subjecting the bonded substrate to a second heating treatment consisting of heating at 750 to 900° C. in an oxidative atmosphere thereby reducing damages inflicted to the SOI layer, and subjecting the resulting bonded substrate to a third heating treatment consisting of heating at 900 to 1200° C. thereby enhancing the bonding strength of the bonded substrate.

Capacitor in semiconductor device and manufacturing method

April 29, 2008

The capacitor in a semiconductor device includes a substrate, a lower electrode formed over the substrate, a diffusion barrier formed over the lower electrode, a plurality of agglomerates formed over the diffusion barrier, a dielectric layer formed over the surface of the agglomerates to form an uneven surface, and an upper electrode formed over the dielectric layer.

Semiconductor fabrication process for integrating formation of embedded nonvolatile storage device with formation of multiple transistor device types

April 29, 2008

A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step is performed without oxidizing the nanocrystals. A gate electrode film is then deposited over the second dielectric and patterned to form first and second gate electrodes. The second dielectric may be an annealed, CVD oxide. The additional thermal oxidation may include forming by dry oxidation a third dielectric overlying a third region of the semiconductor substrate. The dry oxidation produces a interfacial silicon oxide underlying the second dielectric in the second region. An upper surface of a fourth region of the substrate may then be exposed and a fourth dielectric formed on the upper surface in the fourth region.

Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same

April 29, 2008

A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the one or more openings in the dielectric layer, and is then planarized to form one or more individual contact plugs. Next, the buried bit line layer is etched to recess the buried bit line layer, and a capacitor plate is formed to contact the contact plug.

Method for manufacturing semiconductor device

April 29, 2008

The present invention provides a manufacturing method of a semiconductor device at low cost and with high reliability. According to one feature of a method for manufacturing a semiconductor device includes the steps of forming a metal film over a substrate; forming a metal oxide film over the surface of the metal film by performing plasma treatment to the metal film in an atmosphere containing oxygen; forming a base film over the metal oxide film; forming an element layer having a thin film transistor over the base film; forming a protective layer over the element layer; forming an opening after selectively removing the metal film, the metal oxide film, the base film, the element layer, and the protective layer; separating the base film, the element layer, and the protective layer from the substrate; and sealing the base film, the element layer, and the protective layer by using flexible first and second films, in which an electron density of plasma around the substrate is 1×10 11 cm −3 or more and 1×10 13 cm −3 or less and an electron temperature of the plasma treatment is 0.5 eV or more and 1.5 eV or less.

Common word line edge contact phase-change memory

April 29, 2008

A method of fabricating a phase-change memory cell is described. The cross-sectional area of a contact with a phase-change memory element within the cell is controlled by a first dimension of a bottom electrode and a second dimension controlled by an etch process. The contact area is a product of the first dimension and the second dimension. The method allows the formation of very small phase-change memory cells.

Method and apparatus for semiconductor device with improved source/drain junctions

April 29, 2008

A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.

Method of manufacturing gallium nitride based high-electron mobility devices

April 29, 2008

A method of manufacturing a heterojunction device includes forming a first layer of p-type aluminum gallium nitride; forming a second layer of undoped gallium nitride on the first layer; and forming a third layer of aluminum gallium nitride on the second layer, to provide an electron gas between the second and third layers. A heterojunction between the first and second layers injects positive charge into the second layer to compensate and/or neutralize negative charge within the electron gas.

Method of manufacturing a semiconductor device

April 29, 2008

A method of manufacturing a semiconductor device. The device includes a plurality of layers on a semiconductor substrate. The method includes the steps of dividing a pattern of at least one layer into a plurality of sub-patterns, and joining the divided sub-patterns to perform patterning. A layer that includes wiring substantially affects operation of the semiconductor device depending on a positional relationship to any other wiring. The patterning is performed by one-shot exposure using a single mask.

Method for silicon nitride chemical vapor deposition

April 29, 2008

Embodiments of the invention generally provide a method for depositing a film containing silicon (Si) and nitrogen (N). In one embodiment, the method includes heating a substrate disposed in a processing chamber to a temperature less than about 650 degrees Celsius, flowing a nitrogen-containing gas into the processing chamber, flowing a silicon-containing gas into the processing chamber, and depositing a SiN-containing layer on a substrate. The silicon-containing gas is at least one of a gas identified as NR 2 —Si(R′ 2 )—Si(R′ 2 )—NR 2 (amino(di)silanes), R 3 —Si—N═N═N (silyl azides), R′ 3 —Si—NR—NR 2 (silyl hydrazines) or 1,3,4,5,7,8-hexamethytetrasiliazane, wherein R and R′ comprise at least one functional group selected from the group of a halogen, an organic group having one or more double bonds, an organic group having one or more triple bonds, an aliphatic alkyl group, a cyclical alkyl group, an aromatic group, an organosilicon group, an alkyamino group, or a cyclic group containing N or Si.

CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding

April 29, 2008

A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive interface is provided. Also provided are the hybrid substrate produced by the method as well as using the direct bonding method to provide an integrated semiconductor structure in which various CMOS devices are built upon a surface orientation that enhances device performance.

Semiconductor device and method of manufacturing the same

April 29, 2008

A semiconductor device is provided including a semiconductor element having a plurality of electrodes, a plurality of bonding portions of a lead frame, a plate-like current path material which electrically connects at least one of the plurality of electrodes and one of the plurality of bonding portions, a housing which packages the semiconductor element having the plurality of electrodes, the plurality of bonding portions of the lead frame, and the current path material, wherein the plate-like current path material is arranged to be directly bonded to one of the plurality of electrodes and one of the plurality of bonding portions, and the middle portion of the current path material is formed apart from the surface of the semiconductor element. A method of manufacturing the same is also provided.

Element substrate, test method for element substrate, and manufacturing method for semiconductor device

April 29, 2008

A test circuit and a test method using a plurality of oscillation circuits for evaluation are provided in order to reduce the measuring time and simplify the test. One measuring terminal is shared by a plurality of oscillation circuits for evaluation that are formed over the same substrate as a semiconductor device such as a display device, and the plurality of oscillation circuits for evaluation can be tested by the measuring output terminal. Then, the measurement results are Fourier transformed to obtain the oscillation frequency of the plurality of oscillation circuits for evaluation at the same time. Thus, variations in semiconductor elements can be evaluated.

Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost

April 29, 2008

A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

Heterojunction bipolar transistor and method of fabricating the same

April 29, 2008

Disclosed are a heterojunction bipolar transistor and a method of fabricating the same. A first dielectric layer easily etched is deposited on the overall surface of a substrate before an isolation region is defined. The first dielectric layer and a sub-collector layer are selectively etched, and then a second dielectric layer etched at a low etch rate is deposited on the overall surface of the substrate. Via holes are formed in the first and second dielectric layers, and then the first dielectric layer is removed using a difference between etch characteristics of the first and second dielectric layers. Accordingly, a reduction in power gain, generated at the interface of a compound semiconductor and a dielectric insulating layer (the second dielectric layer), can be eliminated.

Method for creating electrical pathways for semiconductor device structures using laser machining processes

April 29, 2008

A method for creating electrical pathways for semiconductor device structures using laser machining processes is provided. The method of the present invention includes providing a semiconductor substrate and forming one or more depressions in the semiconductor substrate using laser machining processes. Optionally, a film may be deposited over the semiconductor substrate and the depressions may be formed therein. Subsequently, the semiconductor substrate and/or film are etched to smooth out the depressions and the depressions are then filled with an electrically conductive material. The electrically conductive material is then planarized down to the surface of the semiconductor substrate or film thereby isolating the electrically conductive material in the depressions.

Semiconductor device fabrication methods

April 29, 2008

Methods of fabricating semiconductor devices are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece including a plurality of active area regions defined therein, and forming at least one trench in the workpiece between at least two of the plurality of active area regions. A first insulating material is deposited over the plurality of active area regions and the at least one trench, partially filling the at least one trench with the first insulating material and forming peaks of the first insulating material over the plurality of active area regions. A masking material is formed over the first insulating material in the at least one trench, leaving the peaks of the first insulating material over the plurality of active area regions completely exposed. At least the peaks of the first insulating material are removed from over the plurality of active area regions.

Manufacturing method to construct semiconductor-on-insulator with conductor layer sandwiched between buried dielectric layer and semiconductor layers

April 29, 2008

A method for treating exposed metal in a semiconductor wafer ( 301 ) in wafer processing is disclosed herein. In accordance with the method, a wafer is provided which is equipped with a metal layer ( 307 ) and a substrate ( 303 ), wherein a portion of the metal layer is exposed at the edge of the wafer. The exposed portion of the metal layer is then covered with a dielectric material ( 317 ).

Method for manufacturing semiconductor devices

April 29, 2008

A method for manufacturing semiconductor devices includes a step of etching a sample including an interlayer insulating layer containing Al 2 O 3 and a polysilicon or SiO 2 layer in contact with the interlayer insulating layer using a plasma etching system. The interlayer insulating layer is etched with a gas mixture containing BCl 3 , Ar, and CH 4 or He. The gas mixture further contains Cl 2 . The interlayer insulating layer is etched in such a manner that a time-modulated high-frequency bias voltage is applied to the sample. The interlayer insulating layer is etched in such a manner that the sample is maintained at a temperature of 100° C. to 200° C. The interlayer insulating layer and the polysilicon or SiO 2 layer are separately etched in different chambers.

C_xH_ysacrificial layer for cu/low-k interconnects

April 29, 2008

A semiconductor method of manufacturing involving low-k dielectrics is provided. The method includes depositing a hydrocarbon of the general composition C x H y on the surface of a low-k dielectric. The hydrocarbon layer is deposited by reacting a precursor material, preferably C 2 H 4 or (CH 3 ) 2 CHC 6 H 6 CH 3 , using a PECVD process. In accordance with embodiments of this invention, carbon diffuses into the low-k dielectric, thereby reducing low-k dielectric damage caused by plasma processing or etching. Other embodiments comprise a semiconductor device having a low-k dielectric, wherein the low-k dielectric has carbon-adjusted dielectric region adjacent a trench sidewall and a bulk dielectric region. In preferred embodiments, the carbon-adjusted dielectric region has a carbon concentration not more than about 5% less than in the bulk dielectric region.

Semiconductor packages and methods for making and using same

April 29, 2008

A semiconductor package is provided which includes a substrate having a plurality of semiconductor dice mounted thereon. The substrate is divided into segments by grooves formed in the bottom surface of the substrate. Each semiconductor die is electrically connected to the substrate by electrical connections which extend from bond pads on the semiconductor die to corresponding bond pads on the substrate. An encapsulant is formed over each segment and contains grooves which correspond to the grooves of the substrate. Break points are thus formed at the grooves to permit the segments to be easily detached from the substrate to form individual integrated circuits.

Display device, manufacturing method thereof, and television receiver

April 29, 2008

The present invention discloses a method for manufacturing a display device comprising the steps of forming a first film pattern using a photosensitive material over a substrate, forming a second film pattern in such a way that the first film pattern is exposed by being irradiated with a laser beam, modifying a surface of the second film pattern into a droplet-shedding surface, forming a source electrode and a drain electrode by discharging a conductive material to an outer edge of the droplet-shedding surface by a droplet-discharging method, and forming a semiconductor region, a gate-insulating film, and a gate electrode over the source electrode and the drain electrode.

Catalytic nucleation monolayer for metal seed layers

April 29, 2008

A method of forming a copper interconnect on a substrate comprises providing a substrate that includes a dielectric layer and a trench etched into the dielectric layer, depositing a barrier layer within the trench, using a palladium immobilization process to form a metal catalyst layer on the barrier layer, activating the metal catalyst layer, and using a vapor deposition process to deposit a copper seed layer onto the metal catalyst layer. The vapor deposition process may include PVD, CVD, or ALD. An electroplating process or an electroless plating process may then be used to deposit a bulk copper layer onto the copper seed layer to fill the trench. A planarization process may follow to form the final interconnect structure.

Wafer polishing control

April 29, 2008

Methods of controlling polishing of wafers are disclosed. In one aspect, a method may include measuring one or more pre-polish thicknesses of one or more layers of a wafer. The one or more layers may then be polished. Then a post-polish thickness of a layer of the wafer may be measured. Polishing may be controlled by using feed-forward control with the one or more pre-polish thicknesses and by using feed-back control with the post-polish thickness. Machine-accessible software to perform such methods are also disclosed as are systems in which such methods may be implemented.

Wafer demounting method, wafer demounting device, and wafer demounting and transferring machine

April 29, 2008

It is an object of the present invention to provide a wafer release method capable of releasing a wafer safely, simply and certainly and improving a wafer releasing rate, a wafer release apparatus and a wafer release transfer machine using the wafer release apparatus. A wafer release method of the present invention comprises the steps of: pressing the uppermost wafer along an axis direction (L-L′) shifted by an angle in the range of from 15 to 75 degrees from a crystal habit line axis (A-A′) or (B-B′) of the uppermost wafer clockwise or counterclockwise; bending upwardly the peripheral portion of the uppermost wafer so as to cause a bending stress in the uppermost wafer in the axis direction (L-L′) shifted by the angle; blowing a fluid into a clearance between the lower surface of the uppermost wafer and the upper surface of the lower wafer adjacent thereto; and raising the uppermost wafer for releasing.

Methods of forming metal oxide and semimetal oxide

April 29, 2008

The invention includes methods of forming metal oxide and/or semimetal oxide. The invention can include formation of at least one metal-and-halogen-containing material and/or at least one semimetal-and-halogen-containing material over a semiconductor substrate surface. The material can be subjected to aminolysis followed by oxidation to convert the material to metal oxide and/or semimetal oxide. The aminolysis and oxidation can be separate ALD steps relative to one another, or can be conducted in a reaction chamber in a common processing step.

Method and apparatus for creating RFID devices

April 29, 2008

A process is disclosed for creating semiconductor devices such as RFID assemblies wherein an array of dies mounted to a substrate is spaced apart at a first pitch, and the substrate is removed after the positions of the dies in the array is fixed by a solidifiable substance. The solidifiable substance is then removed without changing the relative positions of the dies in the array. All or a selected portion of the array of dies is then electrically attached to a plurality of straps or interposers arranged in a corresponding array. The spacing, or pitch, between the dies in the die array may be changed before or after the substrate is removed to match the pitch of the straps or interposers in the corresponding array. An RFID device created using the process inventive is also disclosed.

Method for finishing metal line for semiconductor device

April 29, 2008

A method for finishing a metal line for a semiconductor device is disclosed, in which polymer generated when forming the metal line including aluminum and its alloy is effectively removed and the metal line is prevented from being eroded. A chlorine radical and a chlorine compound remaining on a surface of the metal line are removed using H 2 O plasma and the polymer is removed using H 2 O gas and HF gas not plasma. Therefore, it is possible to improve reliability and yield of the semiconductor device.

Nonvolatile semiconductor memory device and method for manufacturing the same

April 29, 2008

A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.

Image sensor and method for forming the same

April 29, 2008

A method for forming an image sensor is provided. The method includes providing a semiconductor substrate having a pixel region and a peripheral circuit region, forming a photoelectric transformation section at the semiconductor substrate of the pixel region, forming a plurality of interlayer dielectrics over the semiconductor substrate with interconnections interposed therebetween, forming a passivation layer, partially patterning the passivation layer at the peripheral circuit region to form a via hole exposing the interconnection and removing the passivation layer and the underlying interlayer dielectric at the pixel region. The method further includes forming a conductive layer to fill the via hole and etching the conductive layer to remove the conductive layer at the pixel region and form a via plug and a conductive pad at the peripheral circuit region. The via plug fills the via hole and the conductive pad protrudes outwardly from the via hole.

Systems and methods for processing thin films

April 29, 2008

The present disclosure is directed to methods and systems for processing a thin film samples. In an exemplary method, semiconductor thin films are loaded onto two different loading fixtures, laser beam pulses generated by a laser source system are split into first laser beam pulses and second laser beam pulses, the thin film loaded on one loading fixture is irradiated with the first laser beam pulses to induce crystallization while the thin film loaded on the other loading fixture is irradiated with the second laser beam pulses. In a preferred embodiment, at least a portion of the thin film that is loaded on the first loading fixture is irradiated while at least a portion of the thin film that is loaded on the second loading fixture is also being irradiated. In an exemplary embodiment, the laser source system includes first and second laser sources and an integrator that combines the laser beam pulses generated by the first and second laser sources to form combined laser beam pulses. In certain exemplary embodiments, the methods and system further utilize additional loading fixtures for processing additional thin film samples. In such methods and systems, the irradiation of thin film samples loaded on some of the loading fixtures can be performed while thin film samples are being loaded onto the remaining loading fixtures. In certain exemplary methods and systems, the crystallization processing of the semiconductor thin film samples can consist of a sequential lateral solidification (SLS) process.

Electro-optical device and method of manufacturing the same, element driving device and method of manufacturing the same, element substrate, and electronic apparatus

April 29, 2008

In a circuit to drive driven elements such, as electro-optical elements, an electro-optical device has an element layer, a wire-forming layer, and an electronic component layer in order to suppress variation in characteristics of active elements. The element layer has a plurality of organic EL elements, each of which is arranged in a different position in a plane. The electronic component layer has pixel-driving IC chips. The respective pixel-driving IC chips include a plurality of pixel circuits, each of which drives each organic EL element corresponding to the pixel circuit. The wire-forming layer is positioned between the element layer and the electronic component layer. The wire-forming layer has wires to connect the respective pixel circuits included in the pixel-driving IC chips with the organic EL elements corresponding to the pixel circuits.

Circuit device manufacturing method

April 29, 2008

A circuit device manufacturing method is provided, wherein the adhesion of an overcoat resin, formed on a conductive wiring layer, to a sealing resin layer is improved by irradiating plasma onto the overcoat resin. A first conductive film 23 A and a second conductive film 23 B, which are laminated with an interlayer insulating layer 22 interposed in between, are formed. By selectively removing the first conductive film, a first conductive wiring layer 12 A is formed and the first conductive wiring layer is covered with an overcoat resin 18 . Overcoat resin 18 is irradiated with plasma to roughen its top surface. A sealing resin layer 17 is formed so as to cover the top surface of the roughened overcoat resin 18 and circuit elements 13.

Manufacturing method of semiconductor substrate

April 29, 2008

Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a silicon substrate 13 , a step of forming a trench 14 in this epitaxial layer, and a step of filling the inside of the trench 14 with the epitaxial film 12 , wherein mixed gas made by mixing halogenoid gas into silicon source gas is circulated as material gas in filling the inside of the trench with the epitaxial film, and when the standard flow rate of the halogenoid gas is defined as Xslm and the film formation speed of the epitaxial film formed by the circulation of the silicon source gas is defined as Yμm/min, in the case when the aspect ratio of the trench is less than 10, an expression Y<0.2X+0.10 is satisfied, and in the case that the aspect ratio of the trench is between 10 and less than 20, an expression Y<0.2X+0.05 is satisfied, and in the case that the aspect ratio of the trench is 20 or more, an expression Y<0.2X is satisfied.

Method of forming reduced short channel field effect transistor

April 29, 2008

A method for manufacturing a semiconductor device capable of reducing a short channel effect, whereby the semiconductor device includes a pair of impurity regions for a source and a drain formed on a semiconductor substrate, a gate having a gate electrode used to control a drain current, side walls formed on both sides of the gate electrode, and a pair of electrode members formed on both sides of the semiconductor substrate and in contact with the side walls. First impurity regions are formed by thermal diffusion of impurities from each of the electrode members, and second impurity regions each having thickness smaller than the first impurity region and extending below the gate electrode are formed by thermal diffusion of impurities from the side walls.

Additive printed mask process and structures produced thereby

April 29, 2008

A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.

Dressed qubits

April 29, 2008

A quantum computing method comprising constructing a dressing transformation V between a physical Hamiltonian H and an ideal Hamiltonian H ID . The physical Hamiltonian H describes a physical quantum computer that comprises a plurality of qubits, including interactions between the plurality of qubits and a continuum. The ideal Hamiltonian H ID describes the universal quantum computer that corresponds to the physical quantum computer. Each qubit in the plurality of qubits is initialized and quantum calculations are performed using the plurality of qubits. Measurement of the plurality of qubits is performed in the dressed state.

ALD of amorphous lanthanide doped TiO_xfilms

April 29, 2008

The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiO x ) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety of electronic devices. The dielectric structure is formed by depositing titanium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing a layer of a lanthanide dopant, and repeating to form a sequentially deposited interleaved structure. Such a dielectric layer may be used as the gate insulator of a MOSFET, as a capacitor dielectric, or as a tunnel gate insulator in flash memories, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because the reduced leakage current of the dielectric layer when the percentage of the lanthanide element doping is optimized.

Method for filling of a recessed structure of a semiconductor device

April 29, 2008

This invention relates to process sequence by high-speed atomic layer chemical vapor processing that includes deposition for diffusion barriers in the etched features on substrate followed by gap fill and subsequent in-situ removal of the blanket films on the top by plasma enhanced vapor phase processes. The apparatus and process sequences employed in these processing scheme allows the practitioner to complete all vapor phase process sequences of diffusion barrier deposition, gap fill and planarization of copper and diffusion barrier planarization. In case of copper metallization scheme, vapor phase gap fill can be employed to replace electrochemical deposition of copper and removal of copper and the diffusion barrier by vapor phase reactions can replace chemical-mechanical-polishing. Furthermore, such a processing scheme can be employed to deposit gate level dielectric layer, shallow trench isolation and also to form first metal contact plugs with a suitable barrier at the front end of line processing.

Method of enhancing the photoconductive properties of a semiconductor

April 29, 2008

A semiconductor material with photoconductive properties and a method of the semiconductor, wherein a base material is grown and then annealed post-growth at a temperature of 475° C. or less. It has been found that be annealing at temperatures of 475° C., or less the carrier lifetime of the material and the resistivity can be optimized so as to obtain semiconductor with useful photoconductive properties.

Method of making a multi-bit non-volatile memory (NVM) cell and structure

April 29, 2008

A multi-bit non volatile memory cell includes a first floating gate sidewall spacer structure and a second floating gate sidewall spacer structure physically separated from the first floating gate sidewall spacer structure. Each floating gate sidewall spacer structure stores charge for logically storing a bit. The floating gate sidewall spacer structures are formed adjacent to a patterned structure by sidewall spacer formation processes from a layer of floating gate material (e.g. polysilicon). A control gate is formed over the floating gate sidewall spacer structures by forming a layer of control gate material and then patterning the layer of control gate material.

Methods of manufacturing semiconductor devices having single crystalline silicon layers

April 29, 2008

Methods of manufacturing semiconductor devices having at least one single crystal silicon layer are provided. Pursuant to these methods, a first seed layer that includes silicon is formed. A first non-single crystalline silicon layer is then formed on the first seed layer. The first non-single crystalline silicon layer is irradiated with a laser to transform the first non-single crystalline silicon layer into a first single crystalline silicon layer. Corresponding semiconductor devices are also disclosed.

Method for fabricating semiconductor device

April 29, 2008

Disclosed is a method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process due to a density difference created by reliance on a thickness of a SOG layer subjected to a curing process and of overcoming defects caused by an improper contact opening in a certain region and a punch taken place by micro voids of an APL layer. Particularly, the method includes the steps of: forming a plurality of conductive structure on a substrate; forming a spin-on-glass layer; curing the spin-on-glass layer; forming an advanced-planarization-layer on the spin-on-glass layer; and forming a plurality of contact holes by selectively etching the advanced-planarization-layer and the spin-on-glass layer, thereby exposing portions of the substrate.

Method of forming polycrystalline silicon thin film and method of manufacturing thin film transistor using the method

April 29, 2008

A method of forming a polycrystalline silicon thin film with improved electrical characteristics and a method of manufacturing a thin film transistor using the method of forming the polycrystalline silicon thin film. The method includes forming an amorphous silicon thin film on a substrate, partially melting a portion of the amorphous silicon thin film by irradiating the portion of the amorphous silicon thin film with a laser beam having a low energy density, forming polycrystalline silicon grains with a predetermined crystalline arrangement by crystallizing the partially molten portion of the amorphous silicon thin film, completely melting a portion of the polycrystalline silicon grains and a portion of the amorphous silicon thin film by irradiation of a laser beam having a high energy density while repeatedly moving the substrate by a predetermined distance, and growing the polycrystalline silicon grains by crystallizing the completely molten silicon homogeneously with the predetermined crystalline arrangement.

Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same

April 29, 2008

Methods of fabricating semiconductor devices having a carbon-containing metal silicide layer and semiconductor devices fabricated by the methods are provided. A representative method includes the steps of preparing a semiconductor substrate and forming a gate electrode and source/drain regions on the semiconductor substrate, such that the gate electrode has a first metal silicide layer on an upper part thereof which contains carbon and the source/drain regions have second metal silicide layers on their substantially carbon-free upper parts.

Pattern forming method, device, method of manufacture thereof, electro-optical apparatus, and electronic apparatus

April 29, 2008

A method of forming a predetermined pattern by disposing a functional liquid on a substrate, the method includes the steps of forming banks on the substrate, and disposing the functional liquid on a region divided by the banks, wherein a width of the region is partially formed so as to be large.

Flexible circuits and method of making same

April 29, 2008

Disclosed is a method for making flexible circuits in which portions of a tie layer are removed by etching the underlying polymer. Also disclosed are flexible circuits made by this method.

Method for producing micromechanical and micro-optic components consisting of glass-type materials

April 29, 2008

What is proposed here is a method of structuring surfaces of glass-type materials and variants of this method, comprising the following steps of operation: providing a semiconductor substrate, structuring, with the formation of recesses, of at least one surface of the semiconductor substrate, providing a substrate of glass-type material, joining the semiconductor substrate to the glass-type substrate, with a structured surface of the semiconductor substrate being joined to a surface of the glass-type surface in an at least partly overlapping relationship, and heating the substrates so bonded by annealing in a way so as to induce an inflow of the glass-type material into the recesses of the structured surface of the semiconductor substrate. The variants of the method are particularly well suitable for the manufacture of micro-optical lenses and micro-mechanical components such as micro-relays or micro-valves.

Method for cutting lead terminal of package type electronic component

April 29, 2008

In an electronic component comprising a semiconductor chip packaged in a molded part from which the lead terminals of the semiconductor chip project, a main cutting notch is formed on the obverse surface of each lead terminal before molding the molded part while leaving unnotched portions adjoining both ends of the main notch. Then, each lead terminal is cut at the main notch after molding the molded part, thereby making fewer and smaller cutting burrs occurring at the cut faces.

Active matrix display device

April 29, 2008

In order to provide an active matrix display device in which a thick insulating film is preferably formed around an organic semiconductive film of a thin film luminescent device without damaging the thin film luminescent device, the active matrix display device is provided with a bank layer (bank) along a data line (sig) and a scanning line (gate) to suppress formation of parasitic capacitance in the data line (sig), in which the bank layer (bank) surrounds a region that forms the organic semiconductive film of the thin film luminescent device by an ink-jet process. The bank layer (bank) includes a lower insulating layer formed of a thick organic material and an upper insulating layer of an organic material which is deposited on the lower insulating layer and has a smaller thickness so as to avoid contact of the organic semiconductive film with the upper insulating layer.

Gate-coupled EPROM cell for printhead

April 29, 2008

An EPROM cell in a printhead control circuit for an inkjet printer, having exactly one polysilicon layer and a conductive layer disposed above the polysilicon layer, includes a control transistor and an EPROM transistor. The control and EPROM transistors each have floating gates comprising a portion of the polysilicon layer, and an electrical interconnection, comprising a portion of the conductive layer, interconnects the floating gate of the control transistor and the floating gate of the EPROM transistor.

Laser beam processing method and laser beam machine

April 29, 2008

A laser beam processing method comprising the step of processing-feeding a wafer having devices which are formed in a large number of areas sectioned by streets arranged in a lattice pattern on the front surface while a laser beam capable of passing through the wafer is applied to the wafer to form deteriorated layers along the streets in the inside of the wafer, wherein the laser beam is applied at a predetermined angle toward a direction intersecting at right angles to the processing-feed direction relative to a direction perpendicular to the laser beam applied surface of the wafer.

Method for forming high reliability bump structure

April 29, 2008

Methods for forming a bump on a semiconductor substrate, the substrate having a contact pad thereon, is provided. In one embodiment, the method comprises depositing a passivation layer over the substrate and the contact pad. The passivation layer is patterned and etched to form a plurality of openings in the passivation layer exposing portions of the contact pad. An under bump metallurgy (UBM) layer is deposited over the etched passivation layer and in the plurality of openings thereof to contact the contact pad. A photoresist layer is formed on the UBM layer and then patterned and etched to form at least one opening substantially overlying the contact pad. An electrically conductive material is deposited into the opening formed in the photoresist layer and overlying the UBM layer and aligned with the contact pad. A portion of the remaining photoresist layer is removed. The UBM layer is etched using the electrically conductive material as a mask. Thereafter, the electrically conductive material is reflowed to provide a bump on the semiconductor substrate.

Semiconductor device fabricating apparatus and semiconductor device fabricating method

April 29, 2008

A semiconductor device fabricating method comprises a substrate forming step of forming a plurality of separate conductive pads 20 on an adhesive layer included in an adhesive sheet 50 , and a semiconductor chip mounting step of bonding semiconductor chips to the adhesive sheet 50 with surfaces thereof not provided with any electrodes in contact with the adhesive sheet 50 , and electrically connecting electrodes 11 formed on the semiconductor chips 10 and upper parts of the conductive pads 20 with wires 30 . The semiconductor chips 10 , the wires 30 and the conductive pads 20 are sealed in a sealing resin molding 40 , and then the adhesive sheet 50 is separated from the sealing resin molding 40 . Each of the conductive pads 20 has a reduced part 20 b , and a jutting part 20 a jutting out from the reduced part 20 b . The conductive pads 20 having such construction can be firmly bonded to the sealing resin molding 40.

Method of bonding a microelectronic die to a substrate and arrangement to carry out method

April 29, 2008

A method and an arrangement to bond a die to a substrate of a die-substrate combination to form a microelectronic package. The method comprises: providing the die-substrate combination including a die, a substrate, pre-connection bumps and an underfill material, the pre-connection bumps and underfill material being disposed between the die and the substrate; forming joints from the pre-connection bumps at a joint formation site to obtain an intermediate package; curing the underfill material of the intermediate package at an underfill curing site to obtain the microelectronic package; using a conveying device to transfer the intermediate package from the joint formation site to the underfill curing site; and applying heat energy to the intermediate package during at least part of a transfer thereof from the joint formation site to the underfill curing site to control a temperature of the intermediate package.

System for infrared spectroscopic imaging of libraries

April 29, 2008

Methods and apparatus for screening diverse arrays of materials using infrared imaging techniques are provided. Typically, each of the individual materials on the array will be screened or interrogated for the same material characteristic. Once screened, the individual materials may be ranked or otherwise compared relative to each other with respect to the material characteristic under investigation. According to one aspect, infrared imaging techniques are used to identify the active sites within an array of compounds by monitoring the temperature change resulting from a reaction. This same technique can also be used to quantify the stability of each new material within an array of compounds. According to another aspect, identification and characterization of condensed phase products is achieved, wherein library elements are activated by a heat source serially, or in parallel. According to another aspect, a Fourier transform infrared spectrometer is used to rapidly characterize a large number of chemical reactions contained within a combinatorial library.

Organic thin film transistor including fluorine-based polymer thin film and method of fabricating the same

April 29, 2008

An organic thin film transistor including a fluorine-based polymer thin film and method of fabricating the same. The organic thin film transistor may include a gate electrode, a gate insulating layer, an organic semiconductor layer, source electrode, and a drain electrode formed on a substrate wherein a fluorine-based polymer thin film may be formed (or deposited) at the interface between the gate insulating layer and the organic semiconductor layer. The organic thin film transistor may have higher charge carrier mobility and/or higher on/off current ratio (I on /I off ). In addition, a polymer organic semiconductor may be used to form the insulating layer and the organic semiconductor layer by wet processes, so the organic thin film transistor may be fabricated by simplified procedure(s) at reduced costs.

Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics

April 29, 2008

Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole.

Automated semiconductor wafer salvage during processing

April 29, 2008

The present invention provides a recovery processing method to restore the substrate processing apparatus to an operating state after correcting an abnormality having occurred in the substrate processing apparatus in operation and having resulted in a stop in the operation, comprising a substrate retrieval step in which substrate salvage processing is first executed for a wafer W left in a chamber in the substrate processing apparatus in correspondence to the extent to which the wafer has been processed at the time of the operation stop and the substrate having undergone the substrate salvage processing is then retrieved into the cassette storage container and an apparatus internal state restoration step in which the states inside the individual chambers of the substrate processing apparatus are restored.

Apparatus for judging target to be temperature-regulated

April 29, 2008

Between a characteristic a of a process chamber 21 a having a large pressure loss and a characteristic b of a process chamber 21 b having a small pressure loss, threshold value A (flow rate value Q 3 , pressure value P 3 ) is set on the characteristic a. The threshold value A is set on a controller 9 . When a rotation speed of a pump 3 is increased by an electric motor 8 , the flow rate of a fluid flowing through pipelines 1, 2 and a flow path of a process chamber 21 increases. At the time, the flow rate of the fluid is measured by a flowmeter 4 and a pressure of the fluid is measured by a pressure switch 5 . If the pressure reaches the pressure value P 3 when the flow rate of the fluid reaches the flow rate value Q 3 , the pressure switch 5 operates. At the time, the controller 9 judges that the process chamber 21 a having a large pressure loss is connected to the pipelines 1, 2 . Meanwhile, if the pressure does not reach the pressure value P 3 when the flow rate of the fluid reaches the flow rate value Q 3 , the pressure switch 5 does not operate. At the time, the controller 9 judges that the process chamber 21 b having a small pressure loss is connected to the pipelines 1, 2.

Methods for fabricating solid state image sensor devices having non-planar transistors

April 29, 2008

Methods for fabricating CMOS image sensor devices are provided, wherein active pixel sensors are constructed with non-planar transistors having vertical gate electrodes and channels, which minimize the effects of image lag and dark current.

Semiconductor memory having charge trapping memory cells and fabrication method thereof

April 29, 2008

A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Trench buried bit line memory devices and methods thereof

April 29, 2008

A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.

Developer-soluble materials and methods of using the same in via-first dual damascene applications

April 29, 2008

Wet-recess (develop) gap-fill and bottom anti-reflective coatings based on a polyamic acid or polyester platform are provided. The polyamic acid platform allows imidization to form a polyimide when supplied with thermal energy. The gap-fill and bottom anti-reflective coatings are soluble in standard aqueous developers, and are useful for patterning via holes and trenches on semiconductor substrates in a dual damascene patterning scheme. In one embodiment, compositions composed of polyamic acids can be used as gap-filling (via-filling) materials having no anti-reflective function in a copper dual damascene process to improve iso-dense fill bias across different via arrays. In another embodiment, the same composition can be used for anti-reflective purposes, wherein the photoresist can be directly coated over the recessed surface, while it also acts as a fill material to planarize via holes on the substrate. The compositions described here are particularly suitable for use at exposure wavelengths of less than about 370 nm.

Low-voltage flexible optic polymer modulators

April 29, 2008

An electro-optic modulator is formed from all flexible materials, to form a flexible electro-optic modulator. The formation process uses a photoresist which selectively adheres to one material more than it adheres to another material. This allows selective liftoff, where only parts of the substrate are lifted off. For example, this allows silicon ends on the modulator, thereby facilitating pig tailing and also facilitates handling. Another aspect describes testing the bending radius.

Semiconductor device having multilayer structure and method for manufacturing thereof

April 29, 2008

A semiconductor device having a first wiring layer including first wirings on a substrate, a contact layer on the first wiring layer and including contacts connected to the first wirings, and a second wiring layer on the contact layer and including second wirings connected to the contacts. Contact pitch is larger than the minimum wiring pitch of the first wirings or the minimum wiring pitch of the second wirings.

CMOS APS with stacked avalanche multiplication layer and low voltage readout electronics

April 29, 2008

An image sensor includes a pixel having a protection circuit connected to a charge multiplying photoconversion layer. The protection circuit prevents the pixel circuit from breaking down when the voltage in the pixel circuit reaches the operating voltage applied to the charge multiplying photoconversion layer in response to the image sensor being exposed to a strong light. The protection circuit causes additional voltage entering the pixel circuit from the charge multiplying photoconversion layer over a predetermined threshold voltage level to be dissipated from the storage node and any downstream components.

Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package

April 29, 2008

A method is provided for making a semiconductor multi-package module, by providing a lower molded ball grid array package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Microelectronic component assemblies with recessed wire bonds and methods of making same

April 29, 2008

The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, a substrate, and at least one bond wire. The substrate has a reduced-thickness base adjacent terminals of the microelectronic component and a body having a contact surface spaced farther from the microelectronic component than a bond pad surface of the base. The bond wire couples the microelectronic component to a bond pad carried by the bond pad surface and has a maximum height outwardly from the microelectronic component that is no greater than the height of the contact surface from the microelectronic component.

Methods of forming storage capacitors for semiconductor devices

April 29, 2008

Methods of forming a storage capacitor include forming an interlayer insulation layer having an opening therethrough on a semiconductor substrate, forming a contact plug in the opening, forming a molding oxide layer on the interlayer insulation layer and the contact plug, selectively removing portions of the molding oxide layer to form a recess above the contact plug, forming a titanium layer on a bottom surface and side surfaces of the recess, forming a titanium nitride layer on the titanium layer, and forming a titanium oxide nitride layer on the titanium nitride layer. A storage capacitor includes a semiconductor substrate, an interlayer insulation layer having a contact plug therein on the substrate, and a storage electrode on the contact plug including a titanium silicide layer, a titanium nitride layer on the titanium silicide layer, and a titanium oxide nitride layer on the titanium nitride layer.

Epitaxial crystal growth process in the manufacturing of a semiconductor device

April 29, 2008

First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection structure of a material having an amorphous state is formed on a portion of the insulation layer located between the first and second preliminary epitaxial layers. The material having an amorphous state is then changed into material having a single-crystalline state. Thus, portions of the first and second epitaxial layers are connected to each other through the connection structure so that the epitaxial layers and the connection structure constitute a single-crystalline structure layer that is free of voids for use as a channel layer or the like of a semiconductor device.

Thin semiconductor package having stackable lead frame and method of manufacturing the same

April 29, 2008

Provided is a thin semiconductor package comprising a semiconductor chip and a lead frame, the lead frame including a paddle portion configured for mounting the semiconductor chip in a manner that exposes bonding pads within an aperture formed in a center portion of the lead frame and a peripheral terminal pad portion for establishing external contacts. A plurality of bonding wires are used to establish electrical connection between a lower surface of the paddle part and corresponding bonding pads with intermediate leads providing connection to the terminal pad portions. The semiconductor chip, lead frame and bonding wires may then be encapsulated to form a thin semiconductor package having a thickness substantially equal to that of the terminal pad portions. The thin semiconductor packages may, in turn, be used to form multi-chip stack packages using known good semiconductor chips to form a high-density compound semiconductor packages.

Light emitting diode package with direct leadframe heat dissipation

April 29, 2008

A packaged circuit and method for packaging an integrated circuit are disclosed. The packaged circuit has a lead frame, an integrated circuit chip, and an encapsulating layer. The lead frame has first and second sections, the first section including a lateral portion, a chip mounting area and a first extension. The integrated circuit chip is mounted in the chip mounting area and is in thermal contact with the chip mounting area. The encapsulating layer has top, bottom, and first and second side surfaces. The first extension is bent to provide a first heat path from the chip mounting area to the bottom surface. The heat path connects the heat chip mounting area to the bottom surface without passing through the first and second side surfaces and provides a heat path that has less thermal resistance than the heat path through either the lateral portion or the second section.

Methods of forming integrated circuitry and methods of forming local interconnects

April 29, 2008

In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the etching, a circuit component is formed in the first circuitry area and a circuit component is formed in the second circuitry area. Dielectric material is formed over the first and second circuitry areas. The dielectric material comprises a conductive contact extending outwardly from the circuit component in the first circuitry area. The dielectric material has a first outermost surface. A portion of the dielectric material and a portion of the conductive contact are removed to form a second outermost surface of the dielectric material which has greater degree of planarity than did the first outermost surface. Other aspects are contemplated.

Semiconductor device and method of manufacturing the same

April 29, 2008

Disclosed herein is a semiconductor device and method of manufacturing the same. A step between a memory cell formed in a cell region and a transistor formed in a peripheral circuit region is minimized, and the height of a gate in the memory cell is minimized. Accordingly, subsequent processes are facilitated and the electrical property of the device is thus improved.

Method of testing using compliant contact structures, contactor cards and test system

April 29, 2008

A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein. The compliant contact structure includes a portion fixed within the substrate and at least another portion integral with the fixed portion, laterally unsupported within a thickness of the substrate and extending beyond a side thereof. Dual-sided compliant contact structures, methods of forming compliant contact structures, a method of testing a semiconductor device and a testing system are also disclosed.

Semiconductor topography including a thin oxide-nitride stack and method for making the same

April 29, 2008

A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dielectric thickness of less than approximately 20 angstroms.

Etching method, a method of forming a trench isolation structure, a semiconductor substrate and a semiconductor apparatus

April 29, 2008

An etching method of subjecting a base material to an etching process using an etching agent containing hydrogen fluoride and ozone is disclosed. The base material has a first region constituted from silicon as a main material and a second region constituted from SiO 2 as a main material. The etching method includes the steps of: preparing the base material; and supplying the etching agent onto the base material to form a step between the first and second regions using a feature that an etching rate of silicon by the etching agent is higher than an etching rate of SiO 2 by the etching agent, so that the height of the surface of the first region is lower than the height of the surface of the second region.

Crystal film, crystal substrate, and semiconductor device

April 29, 2008

A crystal foundation having dislocations is used to obtain a crystal film of low dislocation density, a crystal substrate, and a semiconductor device. One side of a growth substrate ( 11 ) is provided with a crystal layer ( 13 ) with a buffer layer ( 12 ) in between. The crystal layer ( 13 ) has spaces ( 13 a ), ( 13 b ) in an end of each threading dislocation D 1 elongating from below. The threading dislocation D 1 is separated from the upper layer by the spaces ( 13 a ), ( 13 b ), so that each threading dislocation D 1 is blocked from propagating to the upper layer. When the displacement of the threading dislocation D 1 expressed by Burgers vector is preserved to develop another dislocation, the spaces ( 13 a ), ( 13 b ) vary the direction of its displacement. As a result, the upper layer above the spaces ( 13 a ), ( 13 b ) turns crystalline with a low dislocation density.

Structure of metal interconnect and fabrication method thereof

April 29, 2008

A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.

Semiconductor device and manufacturing method for the same

April 29, 2008

To provide a semiconductor device with high performance and reliability, in which peeling off an interconnection layer caused due to peeling off of a resin film at a land part is suppressed and thus electrical break down is prevented, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate (e.g., a silicon wafer 10 ); an insulating film 12 formed on the semiconductor substrate 10; a conductive layer 20 formed on the insulating film 12, the conductive layer 20 formed of an interconnection part 22 and a land part 24 which connects the interconnection part 22 to an external terminal 40; and a resin film 30 covering the conductive layer 20, wherein the resin film 30 is in contact with the insulating film 12 at least at a part of the land part 24 by passing through the conductive layer 20.

Encapsulation of thin-film electronic devices

April 29, 2008

One embodiment of this invention pertains to multiple encapsulated thin-film electronic devices. These encapsulated devices include a substrate and multiple thin-film electronic devices are on this substrate. Each of the multiple thin-film electronic devices has an active area. The encapsulated devices also include an encapsulation layer that is on the substrate and this encapsulation layer has multiple holes and these multiple holes are over the active areas of the multiple thin-film electronic devices. The encapsulated devices also include multiple substantially flat encapsulation pieces that are on the encapsulation layer and these multiple substantially flat encapsulation pieces cover the multiple holes of the encapsulation layer. An absorbent material is not attached to any of the substantially flat encapsulation pieces.

Dual damascene process

April 29, 2008

A method of photoresist processing includes forming a first photoresist layer over composite layers of dielectric insulation and a top insulating layer and patterning a via hole pattern in the first photoresist layer by exposing to radiation of a first sensitivity. A second photoresist layer is formed over via patterned and the first photoresist layer. A trench line pattern is formed in the second photoresist layer by exposing to radiation of a second sensitivity. The layers are then etched and the trench line and via hole openings are filled with metal.

Method of mounting an integrated circuit package in an encapsulant cavity

April 29, 2008

An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.

Flash memory device and method for fabricating the same, and programming and erasing method thereof

April 29, 2008

A flash memory device of SONOS structure and a method for fabricating the same, and programming and erasing operation methods, to improve reliability such as endurance and retention, are disclosed, which includes a first conductive type semiconductor substrate; an ONO layer on the semiconductor substrate; a first control gate on the ONO layer; second and third control gates on the ONO layer at both sides of the first control gate; and source and drain regions in the surface of the semiconductor substrate at both sides of the second and third control gates.

Nitride semiconductor based light-emitting device and manufacturing method thereof

April 29, 2008

An object of the present invention is to provide a nitride semiconductor based light-emitting device, which is low in operating voltage reduction and is high in performance, and a manufacturing method thereof. A first metal film is formed on a P-type conductive nitride semiconductor formed on a substrate, and then, a film (WO x ) made of tungsten oxide is formed in superimposition, followed by annealing.

Substrate having a penetrating via and wiring connected to the penetrating via and a method for manufacturing the same

April 29, 2008

A disclosed substrate includes a base member having a through-hole, and a conductive metal filling in the through-hole so as to form a penetrating via. The penetrating via contains a conductive core member that is substantially at the central axis of the through-hole.

SOI SRAM products with reduced floating body effect

April 29, 2008

A memory device is formed on a semiconductor-on-insulator (SOI) structure, the SOI structure including a substrate, an insulating layer on the substrate, and a semiconductor film on the insulating layer. The memory device includes a memory array in a memory region of the SOI structure, a plurality of first substrate contacts in the peripheral region of the memory device, and a plurality of second substrate contacts in the memory region of the SOI structure, wherein the first substrate contacts and the second substrate contacts are formed in and over the semiconductor film and in the insulating layer and are electrically connected to the substrate of the SOI structure.

Fabrication methods for micro compounds optics

April 29, 2008

Methods for fabricating refractive element(s) and aligning the elements in a compound optic, typically to a zone plate element. The techniques are used for fabricating micro refractive, such as Fresnel, optics and compound optics including two or more optical elements for short wavelength radiation. One application is the fabrication of the Achromatic Fresnel Optic (AFO). Techniques for fabricating the refractive element generally include: 1) ultra-high precision mechanical machining, e.g,. diamond turning; 2) lithographic techniques including gray-scale lithography and multi-step lithographic processes; 3) high-energy beam machining, such as electron-beam, focused ion beam, laser, and plasma-beam machining; and 4) photo-induced chemical etching techniques. Also addressed are methods of aligning the two optical elements during fabrication and methods of maintaining the alignment during subsequent operation.

Redistributed solder pads using etched lead frame

April 29, 2008

A semiconductor package has a thinned semiconductor die fixed in a shallow opening in a conductive body. The die electrodes at the bottom of the die are plated with a redistributed contact which overlaps the die bottom contact and an insulation body which fills the annular gap between the die and opening. A process is described for the manufacture of the package in which plural spaced openings in a lead frame body and are simultaneously processed and singulated at the end of the process.

Semiconductor device and method for manufacturing the same

April 29, 2008

A semiconductor device, comprising: a semiconductor substrate in which an integrated circuit is formed, the semiconductor substrate having an electrode electrically connected to the integrated circuit; a resin layer formed on a face in which the electrode of the semiconductor substrate is formed, as to avoid the electrode; a wiring formed as to have a protruding portion projecting upwards on the resin layer, the wiring being electrically connected to the electrode; and a solder formed on the protruding portion of the wiring, wherein the upper face portion of the protruding portion is melt-eroded by the solder and the material of the protruding portion.

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Buffer-layer treatment of MOCVD-grown nitride structures

Semiconductor package and substrate having multi-level vias fabrication method

Carbon nanotube interconnects in porous diamond interlayer dielectrics

Method for interconnecting semiconductor components with substrates and contact means

Capacitance detection type sensor and manufacturing method thereof

Shallow trench isolation process utilizing differential liners

System for the preferential removal of silicon oxide

Atmospheric process and system for controlled and rapid removal of polymers from high aspect ratio holes

Method of fabricating an interconnection layer above a ferroelectric capacitor

Double gate FET and fabrication process

Method for fabricating semiconductor device

Method of manufacturing NOR-type mask ROM device and semiconductor device including the same

Methods of fabricating patterned layers on a substrate

Microelectronic imaging units and methods of manufacturing microelectronic imaging units

Porous underlayer coating and underlayer coating forming composition for forming porous underlayer coating

Electronic device and method of manufacturing the same

SRAM cell design for soft error rate immunity

Method for manufacturing gallium nitride light emitting diode devices

Method of fabricating semiconductor device

CMOS image sensor and method for fabricating the same

Method for manufacturing semiconductor device

Semiconductor device package

Method for etching upper metal of capacitator

Reticle fabrication using a removable hard mask

Semiconductor device

Method for producing a memory cell

Damascene replacement metal gate process with controlled gate profile and length using Si1-xGex as sacrificial material

Selective etch for patterning a semiconductor film deposited non-selectively

Method for fabricating semiconductor package

Method for manufacturing a superjunction device with wide mesas

Silicon phosphor electroluminescence device with nanotip electrode

Method for manufacturing semiconductor device

Method for manufacturing a MOS transistor

Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry

Chemical solution coating method and chemical solution coating apparatus

Method for fabricating thermally enhanced semiconductor package

Fabrication of semiconductor device for flash memory with increased select gate width

Semiconductor device and method of fabrication

Anhydrous HF release of process for MEMS devices

Interconnects with direct metalization and conductive polymer

Methods of fabricating a semiconductor device using an organic compound and fluoride-based buffered solution

Method for manufacturing semiconductor device having super junction construction

Method for manufacturing SOI substrate

Capacitor in semiconductor device and manufacturing method

Semiconductor fabrication process for integrating formation of embedded nonvolatile storage device with formation of multiple transistor device types

Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same

Method for manufacturing semiconductor device

Common word line edge contact phase-change memory

Method and apparatus for semiconductor device with improved source/drain junctions

Method of manufacturing gallium nitride based high-electron mobility devices

Method of manufacturing a semiconductor device

Method for silicon nitride chemical vapor deposition

CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding

Semiconductor device and method of manufacturing the same

Element substrate, test method for element substrate, and manufacturing method for semiconductor device

Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost

Heterojunction bipolar transistor and method of fabricating the same

Method for creating electrical pathways for semiconductor device structures using laser machining processes

Semiconductor device fabrication methods

Manufacturing method to construct semiconductor-on-insulator with conductor layer sandwiched between buried dielectric layer and semiconductor layers

Method for manufacturing semiconductor devices

CxHy sacrificial layer for cu/low-k interconnects

Semiconductor packages and methods for making and using same

Display device, manufacturing method thereof, and television receiver

Catalytic nucleation monolayer for metal seed layers

Wafer polishing control

Wafer demounting method, wafer demounting device, and wafer demounting and transferring machine

Methods of forming metal oxide and semimetal oxide

Method and apparatus for creating RFID devices

Method for finishing metal line for semiconductor device

Nonvolatile semiconductor memory device and method for manufacturing the same

Image sensor and method for forming the same

Systems and methods for processing thin films

Electro-optical device and method of manufacturing the same, element driving device and method of manufacturing the same, element substrate, and electronic apparatus

Circuit device manufacturing method

Manufacturing method of semiconductor substrate

Method of forming reduced short channel field effect transistor

Additive printed mask process and structures produced thereby

Dressed qubits

Damascene replacement metal gate process with controlled gate profile and length using Si_1-xGe_xas sacrificial material

C_xH_ysacrificial layer for cu/low-k interconnects

ALD of amorphous lanthanide doped TiO_xfilms