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<title>freepatentsonline.com</title>
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<title>freepatentsonline.com: Static information storage and retrieval</title>
<link>http://www.freepatentsonline.com/result.html?query_txt=ccl/365%20and%20isd/04/29/2008&amp;uspat=on</link>
<description>USPTO Class 365 Static information storage and retrieval</description>
<language>en-us</language>
<lastBuildDate>Wed Apr 30 16:35:24 EDT 2008</lastBuildDate>

<item>
<title><![CDATA[Memory]]></title>
<link>http://www.freepatentsonline.com/7366004.html</link>
<description><![CDATA[A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Ferroelectric memory device and display-driving IC]]></title>
<link>http://www.freepatentsonline.com/7366005.html</link>
<description><![CDATA[A ferroelectric memory device including: a first bit line which extends, from one end toward another end thereof, in a first direction; a plurality of first memory cells, which are connected to the first bit line and store predetermined data; a second bit line which extends, from one end toward another end thereof, in a second direction, which is a direction substantially opposite to the first direction; a plurality of second memory cells, which are connected to the second bit line and store predetermined data; a sense amplifier, which is connected to the one end of the first bit line and the one end of the second bit line, and which amplifies data which have been stored at the first memory cells and the second memory cells; a latch circuit, which is connected to the other end of the first bit line, and which latches data that the sense amplifier has amplified; a data bus, which transfers data which are to be stored at the first memory cells and the second memory cells; and a first switch, which is connected to the other end of the second bit line and which switches between connecting and not connecting the second bit line with the data bus.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Current reduction circuit of semiconductor device]]></title>
<link>http://www.freepatentsonline.com/7366043.html</link>
<description><![CDATA[A current reduction circuit of a semiconductor device is disclosed which includes an enabling signal generator which outputs a predetermined enabling signal in association with a cell block in which a bridge has been formed between a word line and a bit line, and an isolation controller which is enabled in response to the enabling signal, and outputs a control signal to periodically isolate the bridge-formed cell block from a sense amplifier array for a predetermined period in a standby mode in response to a periodic signal enabled at intervals of a predetermined time.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory]]></title>
<link>http://www.freepatentsonline.com/7366045.html</link>
<description><![CDATA[A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are generated by corresponding power circuits. In accordance with a second exemplary embodiment, the power circuits are coupled to the bit lines and replace the reference circuit in a manner to improve sensing margin.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for reducing standby current in a dynamic random access memory during self refresh]]></title>
<link>http://www.freepatentsonline.com/7366047.html</link>
<description><![CDATA[A dynamic random access memory including a first dynamic random access memory cell, a second dynamic random access memory cell to be refreshed, a sense amplifier, and a control circuit. The control circuit is configured to isolate the sense amplifier from at least one of the first dynamic random access memory cell and the second dynamic random access memory cell in an idle state and to couple the sense amplifier to only the second dynamic random access memory cell to be refreshed in a refresh state.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method of operating a complementary bit resistance memory sensor and method of operation]]></title>
<link>http://www.freepatentsonline.com/7366003.html</link>
<description><![CDATA[A method and apparatus are disclosed for sensing the resistance state of a resistance-based memory element using complementary resistance-based elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the high and low resistance elements to determine the resistance state of an element being read.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Simultaneous read circuit for multiple memory cells]]></title>
<link>http://www.freepatentsonline.com/7366030.html</link>
<description><![CDATA[A memory device including a simultaneous read circuit design for multiple memory cells on a single interconnect using a fast fourier transform analysis circuit. The simultaneous read circuit can be used with any memory type storing information as an energy-absorbing state.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Power consumption minimization in magnetic random access memory by using the effect of hole-mediated ferromagnetism]]></title>
<link>http://www.freepatentsonline.com/7366011.html</link>
<description><![CDATA[A low-power memory device that uses hole-mediated ferromagnetism creates substantial advantages over conventional systems. Some of these advantages include reducing power consumption by several orders of magnitude and facilitating wireless monitoring of memory cells. In one implementation, an electronic device is described that includes a plurality of memory cells. Each of the memory cells has a material with first and second magnetic states. The material is in the first magnetic state when a contact associated with the material is at a first voltage, and the material is in the second magnetic state when the contact is at a second voltage. A conductor is positioned proximate to and extending around the plurality of memory cells. An inductive voltage across the conductor varies when at least one of the memory cells changes magnetic state. A detection device determines the magnetic state of the memory cells based on an inductive voltage measurement.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method of reducing settling time in flash memories and improved flash memory]]></title>
<link>http://www.freepatentsonline.com/7366040.html</link>
<description><![CDATA[A method of biasing word lines in a flash memory array wherein a selected word line is selected for a reading operation during data access includes the steps of biasing deselected word lines with a deselected word line voltage, delaying for a delay period and after the delay period, biasing the selected word line with a selected word line voltage for performing the reading operation.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Defective column(s) in a memory device/card is/are skipped while serial data programming is performed]]></title>
<link>http://www.freepatentsonline.com/7366042.html</link>
<description><![CDATA[A semiconductor device includes an interface which executes an interfacing process with a semiconductor memory, and a circuit which performs control to write serial data to the semiconductor memory while skipping a position of a defective column on the semiconductor memory.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method and storage device for the permanent storage of data]]></title>
<link>http://www.freepatentsonline.com/7366002.html</link>
<description><![CDATA[It is proposed that bitline inversion coding data be integrally stored in the structure of a column multiplexer of a storage device. For this purpose, connections to a predefined potential are selectively provided at connection points, which are respectively assigned to one of the bitlines connected to the column multiplexer, in dependence on whether or not the assignment of a first state and of a second state of memory cells, connected to the bitline, to a binary value “0” and to a binary value “1” is inverted for the respective bitline. The connection points are connected to a common nodal point via switching means. The switching means are activated through control signals of the column multiplexer. Selection signals for activating inverter means, in order to effect a selective inversion of values read out from the memory cells, are generated in dependence on the signal level at the common nodal point. A precharging of the common nodal point is preferably effected between to read-out operations in each case, for which purpose precharging switching means are provided.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Separate write and read access architecture for a magnetic tunnel junction]]></title>
<link>http://www.freepatentsonline.com/7366009.html</link>
<description><![CDATA[A magnetoresistive device is provided with separate read and write architecture. In one embodiment, a magnetic tunnel junction (MTJ) has a nonmagnetic nonconductive barrier layer sandwiched between two ferromagnetic conducting layers. A first read line is coupled to a first ferromagnetic layer and a second read line is coupled to a second ferromagnetic layer such that a voltage difference between the two read lines will produce a current flowing perpendicularly through each layer of the MTJ. A first write line is separated from the first read line by a first insulator and a second write line is separated from the second read line by a second insulator.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Synchronous memory device with reduced power consumption]]></title>
<link>http://www.freepatentsonline.com/7366012.html</link>
<description><![CDATA[A synchronous non-volatile memory device that includes a circuit for performing operations on the memory device, a circuit for receiving a request of operation and operative information required for performing the operation in temporal succession, an activation circuit for activating the circuit in response to the request of operation, a circuit for enabling the execution of the operation in response to the operative information, and a deactivation circuit for deactivating the operations performing circuit in response to the completion of the operation.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[RFID device having nonvolatile ferroelectric memory device]]></title>
<link>http://www.freepatentsonline.com/7366039.html</link>
<description><![CDATA[A RFID device having a nonvolatile ferroelectric memory regulates bit line capacitance to optimize a bit line sensing margin and minimize power consumption. The RFID device having an analog block adapted and configured to transmit and receive a radio frequency signal to/from an external communication apparatus, a digital block adapted and configured to receive a power voltage and the radio frequency signal from the analog block, transmit a response signal to the analog block and output a memory control signal, and a memory adapted and configured to store data and regulate bit line capacitance.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Nonvolatile memory]]></title>
<link>http://www.freepatentsonline.com/7366034.html</link>
<description><![CDATA[For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor memory device]]></title>
<link>http://www.freepatentsonline.com/7366007.html</link>
<description><![CDATA[A semiconductor memory device capable of performing a high-speed write operation at lower voltage without increasing the word line activation period at normal voltage. The memory device has a write circuit including two NMOS transistors respectively having sources connected to ground potential. One of the transistors has a drain connected to one of a pair of bit lines, and the other transistor has a drain connected to the other bit line. The memory device also has a column selecting and data input circuit which generates a logical product of inverted data of data to be written and a write column selecting signal, inputs the logical product to the gate of the one transistor, generates a logical product of the data to be written and the write column selecting signal, and inputs the logical product to the gate of the other transistor.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Ferroelectric memory and method of driving the same]]></title>
<link>http://www.freepatentsonline.com/7366035.html</link>
<description><![CDATA[A ferroelectric memory includes: a memory cell array in which a plurality of memory cells are disposed, a plurality of wordlines, a plurality of platelines, and a plurality of wordline driver circuits, each of the memory cells including a ferroelectric capacitor. A wordline driver circuit circuits includes: a driver DRV which drives a wordline WL; a transfer transistor TRA provided between the driver DRV and the wordline WL; and a gate control circuit. The gate control circuit performs gate control which causes the transfer transistor TRA to be turned on, and performs gate control which causes the transfer transistor TRA to be turned off, before a voltage of the wordline WL is boosted (before a plateline PL is driven) after the transfer transistor TRA has been turned on.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[DRAM density enhancements]]></title>
<link>http://www.freepatentsonline.com/7366046.html</link>
<description><![CDATA[In one embodiment, a sense amplifier includes: a differential amplifier adapted to amplify a voltage difference between a pair of bit lines; and a self-bias generation circuit adapted to reduce an offset bias in the differential amplifier with regard to the amplification of the voltage difference between the pair of bit lines.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Bulk bias voltage level detector in semiconductor memory device]]></title>
<link>http://www.freepatentsonline.com/7366048.html</link>
<description><![CDATA[There is provided a bulk bias voltage VBB level detector in a semiconductor memory device capable of improving tWR fail generated at a low temperature by compensating a temperature variance. The VBB level detector includes A bulk bias voltage level detector in a semiconductor memory device, comprising: a voltage divider for generating detection voltage based on an inputted bulk voltage; and a CMOS circuit for generating a output signal having predetermined logic value determined by the detection voltage wherein the voltage divider includes a first transistor having a gate coupled to a ground voltage and a second transistor having a gate coupled to an internal power voltage and a bulk coupled to the inputted bulk voltage.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor integrated circuit device, production and operation method thereof]]></title>
<link>http://www.freepatentsonline.com/7366015.html</link>
<description><![CDATA[A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells function to generate hot electrons and are alternately arranged with other auxiliary gates functioning to prevent write errors in the non-selected memory cells.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Word line driver circuitry and methods for using the same]]></title>
<link>http://www.freepatentsonline.com/7366051.html</link>
<description><![CDATA[Word line driver circuitry for selectively charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology, where a first transistor is driven by a signal, DOUT, and a second transistor is driven by a time-delayed complement of the DOUT, DOUT_BAR. The time delay prevents DOUT_BAR from changing its state immediately after DOUT changes state. As result, both the first and second transistors are turned ON at the same time for a predetermined of time. It is during this time that the voltage on the word line is rapidly driven to a LOW voltage. When the second transistor turns OFF, high impedance circuitry limits the flow of leakage current. This minimizes leakage current when the word line is OFF and when short circuit conditions are present between two or more word lines or between a word line and a bit line.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Memory arrangement and method for addressing a memory]]></title>
<link>http://www.freepatentsonline.com/7366031.html</link>
<description><![CDATA[A memory arrangement includes a plurality of switching elements arranged in the form of a binary tree. The memory elements are supplied with data to be stored by the switching elements coupled to the leaves of the binary tree.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for erasing memory]]></title>
<link>http://www.freepatentsonline.com/7366027.html</link>
<description><![CDATA[The present invention provides a method and apparatus for erasing memory blocks. The apparatus includes a first plurality of memory cells formed in a substrate and a second plurality of memory cells formed in the substrate. The apparatus further includes a bias circuit adapted to provide an erasing voltage differential to the first plurality of memory cells and a compensating voltage differential to the second plurality of memory cells, wherein the erasing voltage differential is larger than the compensating voltage differential.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Magnetic memory]]></title>
<link>http://www.freepatentsonline.com/7366010.html</link>
<description><![CDATA[A TMR element has a free first magnetic layer, a second magnetic layer with a magnetization direction B fixed, a nonmagnetic insulating layer provided between the first magnetic layer and the second magnetic layer, a third magnetic layer provided above a surface of the first magnetic layer and having a fixed magnetization direction, and a first nonmagnetic conductive layer provided between the first magnetic layer and the third magnetic layer, and an area of a cross section of the first magnetic layer perpendicular to a stack direction is not less than 0.001 μm 2 , and less than 0.02 μm 2 .]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Nonvolatile memory]]></title>
<link>http://www.freepatentsonline.com/7366019.html</link>
<description><![CDATA[There is provided a non-volatile memory capable of being supplied with two varieties of externally supplied voltages, stabilizing the operation thereof, at a voltage in the vicinity of a threshold voltage for switching over between the externally supplied voltages, and stabilizing the operation thereof, at the times of writing and erasing, respectively. The non-volatile memory comprises a power supply circuit incorporating a hysteresis comparator having two voltage levels for the threshold voltage, wherein by detection of 2.3V at a time when an externally supplied voltage rises, a detection signal goes to an “H” level, whereupon an internal step-down circuit, made up of a constant voltage circuit, and so forth, comes into action, generating an internal operation voltage at 2.2V to be subsequently supplied, and thereafter, by detection of 2.1V, the detection signal goes to an “L” level, whereupon the externally supplied voltage, as it is, is supplied as the internal operation voltage. Accordingly, since the detection signal remains in the “H” condition even when the externally supplied voltage is unstable in the vicinity of 2.3V, the internal operation voltage does not undergo variation.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Radiation tolerant SRAM bit]]></title>
<link>http://www.freepatentsonline.com/7366008.html</link>
<description><![CDATA[In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Apparatus and method for updating data in a dual port memory]]></title>
<link>http://www.freepatentsonline.com/7366049.html</link>
<description><![CDATA[A dual port memory is updated at substantially the same data sampling rate as a clock frequency of the dual port memory. The dual port memory stores data relating to each different parameter value in a stream of data samples, and provides the stored data from an address in the memory corresponding to the received parameter value. An updating element updates stored data and provides the updated data to an input of the dual port memory for writing back into the address corresponding to the received parameter value. A first port of the dual port memory is utilised as the output of the dual port memory coupled to the input of the updating element on a first clock cycle of the dual port memory, and a second port of the dual port memory is normally utilised as the input of the dual port memory coupled to the output of the updating element on a second clock cycle, the next address being accessed via the first port on the second clock cycle. A comparator receives the parameter value on the first clock cycle of the dual port memory and a next received parameter value on a second clock cycle, and provides a match signal if the received parameter value and the next received parameter value are the same. The match signal is utilised to enable the first port of the dual port memory to be used as the input for the second clock cycle so that the data updated by the updating element on the first clock cycle is provided at the first port rather than the second port and is therefore correctly provided to the input of the updating element on the second clock cycle.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Double page programming system and method]]></title>
<link>http://www.freepatentsonline.com/7366014.html</link>
<description><![CDATA[A method for programming an electrically programmable memory including a plurality of memory cells arranged in individually-selectable memory cell sets each including at least one memory cell. The programming method includes causing the memory cells of a selected memory cells set to be brought into a predetermined, starting programming state. Receiving a target value for the first data bits groups of the memory cells of the selected memory cells set. Receiving a target value for the second data bits groups of the memory cells of the selected memory cells set. After having received the target values of both the first and the second data bits groups, applying to the memory cells of the selected memory cells set a programming sequence adapted to cause the memory cells of the selected memory cells sets to be brought into a target programming state jointly determined by the target values of the first and second data bits groups.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor memory]]></title>
<link>http://www.freepatentsonline.com/7366037.html</link>
<description><![CDATA[A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each connected to the first or second bit line, a selected one of the memory cells maintaining or discharging one of the precharged first and second bit lines according to a signal held by the selected memory cell; word lines for selecting the memory cells; first and second reference cells connected to the first and second bit lines, respectively, a selected one of the first and second reference cells discharging the first or second bit line connected to the selected reference cell; and first and second reference cell word lines for selecting the first and second reference cells, respectively.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Input buffer for low voltage operation]]></title>
<link>http://www.freepatentsonline.com/7366041.html</link>
<description><![CDATA[An input buffer having differential amplifiers for receiving input signals to generate an output signal. The input buffer operates with a relatively low supply voltage and a relatively wide range of input signal levels while improving the symmetry between rising and falling signal transitions of the output signal.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Flash memory device capable of preventing an overerase of flash memory cells and erase method thereof]]></title>
<link>http://www.freepatentsonline.com/7366020.html</link>
<description><![CDATA[We describe a NAND flash memory device including a memory cell array formed on a substrate including a plurality of cell strings each including a string selecting transistor, a ground selecting transistor, and plural memory cells serially coupled between the string selecting transistor and the ground selecting transistor. A high voltage generator is configured to supply a bulk voltage to the substrate and an erase control circuit is configured to stepwise increase the bulk voltage during a first period of an erase operation and to maintain the bulk voltage substantially constant during a second period of the erase operation.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for sensing flash memory using delta sigma modulation]]></title>
<link>http://www.freepatentsonline.com/7366021.html</link>
<description><![CDATA[A simple method and device for accurately measuring flash memory cell current. The sensing scheme comprises an integrator, an analog to digital converter, and a digital to analog converter. The method comprises the acts of applying an input current and a feedback output current to a summer, integrating the resulting summer output over time, passing the integrated output to a clocked comparator, outputting a comparator output which controls a feedback circuit that keeps the integrator's voltage at the same level as a reference voltage, and outputting a digital average current to a counter. Delta sigma modulation (averaging) is employed to cancel out noise that would otherwise affect the cell current measurement.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method of high-performance flash memory data transfer]]></title>
<link>http://www.freepatentsonline.com/7366028.html</link>
<description><![CDATA[A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe, and presents data synchronously with both the falling and rising edges of that read data strobe. In the advanced mode, the input data is presented by the controller synchronously with both edges of the write data strobe. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Nonvolatile semiconductor memory]]></title>
<link>http://www.freepatentsonline.com/7366016.html</link>
<description><![CDATA[Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method for modifying data more than once in a multi-level cell memory location within a memory array]]></title>
<link>http://www.freepatentsonline.com/7366017.html</link>
<description><![CDATA[A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a multi-level cell device. The method includes the steps of initializing the bit in the lower page and the bit in the upper page by storing a value of one in each of the bits. One or more bits in the lower page are then programmed such that a one is stored in the one or more bits of the lower page. One or more bits in the upper page are then programmed such that a one is stored in the one or more bits of the upper page. The one or more bits in the upper page are then reprogrammed such that the value in the one or more bits of the upper page transitions from a one to a zero. The transition from a one to a zero in the one or more bits of the upper page is used to mark for performance of a block management function the block.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[High-performance flash memory data transfer]]></title>
<link>http://www.freepatentsonline.com/7366029.html</link>
<description><![CDATA[A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe at a higher frequency, for example at twice the frequency, of that available in the normal mode. In the advanced mode, the input data is presented by the controller synchronously with a higher frequency write data strobe than is available in the normal mode. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Single level cell programming in a multiple level cell non-volatile memory device]]></title>
<link>http://www.freepatentsonline.com/7366013.html</link>
<description><![CDATA[A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire data into either the least significant or most significant bit of the cell. A second programming operation the programs reinforcing data that adjusts the threshold level of the cell to the appropriate level for the desired data.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Flash memory device]]></title>
<link>http://www.freepatentsonline.com/7366023.html</link>
<description><![CDATA[A flash memory device includes first to n th  banks sharing an I/O line, a page buffer unit commonly connected to a bit line of the first to n th  banks, for buffering data to be transmitted to the first to n th  banks, a first X-decoder connected to a word line of the first banks, for applying a driving voltage to the word line of the first banks, a n th  X-decoder connected to a word line of the n th  banks, for applying a driving voltage to the word line of the n th  banks, a program/erase pump for generating a program voltage/erase voltage applied to the first to n th  banks, a first switch unit that switches the program voltage/erase voltage and transmits the voltage to the first banks and the first X-decoder, and a n th  switch unit that switches the program voltage/erase voltage and transmits the voltage to the n th  banks and the n th  X-decoder.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Circuit and method of driving a word line of a memory device]]></title>
<link>http://www.freepatentsonline.com/7366038.html</link>
<description><![CDATA[A word line driving circuit may include a first word line driver, a second word line driver and a pass transistor. In response to a word line selecting signal, the first word line driver may drive a word line using a first word line driving voltage signal in a first operation mode or the second word line driver may drive the word line using a second word line driving voltage signal. The pass transistor coupled between the first word line driver and the word line may transmit the first word line driving voltage signal to the word line in response to a control voltage signal, which is self-boosted at an initial stage of the first operation mode and is maintained at a stable voltage level after a time period.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Reduced power programming of non-volatile cells]]></title>
<link>http://www.freepatentsonline.com/7366025.html</link>
<description><![CDATA[Methods for minimizing current consumption in a memory array during programming of non-volatile memory cells, such as NROM cells, in the array include: programming a cell without having a direct current flowing from a positive supply to ground through the array, programming a plurality of cells with programming pulses without discharging a global bit line carrying a programming voltage between programming pulses, and programming a cell with transient currents.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor integrated circuit]]></title>
<link>http://www.freepatentsonline.com/7366965.html</link>
<description><![CDATA[Test functions are expanded by adopting a self test part, and circuit scale is reduced by adding the self test part. A semiconductor integrated circuit includes a memory that includes plural memory banks and is accessed by specifying a bank address, an X address, and a Y address, and a self-test part that tests the memory in response to commands. The self-test part has an address counter covering plural addressing modes that are different in the updating of X addresses, Y addresses, and bank addresses. A variety of addressing modes provided expand BIST-based test functions.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[3-level non-volatile semiconductor memory device and method of driving the same]]></title>
<link>http://www.freepatentsonline.com/7366033.html</link>
<description><![CDATA[A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Apparatus for programming of multi-state non-volatile memory using smart verify]]></title>
<link>http://www.freepatentsonline.com/7366022.html</link>
<description><![CDATA[In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (V TH ) that falls within a first V TH  distribution or a higher, intermediate V TH  distribution. Subsequently, the non-volatile storage elements with the first V TH  distribution either remain there, or are programmed to a second V TH  distribution, based on an upper page of data. The non-volatile storage elements with the intermediate V TH  distribution are programmed to third and fourth V TH  distributions. The non-volatile storage elements being programmed to the third V TH  distribution are specially identified and tracked. Verification of the non-volatile storage elements being programmed to the fourth V TH  distribution is initiated after one of the identified non-volatile storage elements transitions to the third V TH  distribution from the intermediate V TH  distribution.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Multi-ported register cell with randomly accessible history]]></title>
<link>http://www.freepatentsonline.com/7366032.html</link>
<description><![CDATA[A multi-ported register cell. The register cell includes a base cell and a plurality of history cells, each of which is coupled to the base cell. Each of the plurality history cells is coupled to write to the base cell through a first port, and each of the plurality of history cells is coupled to receive data from the base cell through a second port.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Row expansion reduction by inversion for range representation in ternary content addressable memories]]></title>
<link>http://www.freepatentsonline.com/7366830.html</link>
<description><![CDATA[A method and circuit to implement a match against range rule functionality. A first rule entry and a second rule entry are stored. The first rule entry includes at least two consecutive identical bits. The first rule entry represents a numerical range. A first field of a binary key is compared with the first rule entry to determine whether any of the bits of the first field are not identical. A logical result of the comparison between the first field and the first rule entry is inverted to generate a first comparison result. A second field of the binary key is compared with a second rule entry to generate a second comparison result. The first comparison result is then logically ANDed with the second comparison result to determine whether the binary key falls within the numerical range represented by the first rule entry and matches the second rule entry.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Content addressable memory including main-match lines and sub-match lines]]></title>
<link>http://www.freepatentsonline.com/7366001.html</link>
<description><![CDATA[The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Apparatus and method for data outputting]]></title>
<link>http://www.freepatentsonline.com/7366050.html</link>
<description><![CDATA[An data output circuit for outputting a data stored in a core of a semiconductor memory device includes a clock generator for generating a rising clock and a falling clock by using an external clock, a clock repeater for outputting the rising clock and the falling clock as one of a high voltage clock and a low voltage clock in response to an external voltage level check signal, a level shifter for outputting a high voltage data generated by shifting the data synchronized with the high voltage clock, a data carrier for outputting a low voltage data synchronized with the low voltage clock, and a data repeater for outputting one of the high voltage data and the low voltage data in response to the external voltage level check signal.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for operating a string of charge trapping memory cells]]></title>
<link>http://www.freepatentsonline.com/7366024.html</link>
<description><![CDATA[A string of memory cells with a charge trapping structure is read, by selecting part of a memory cell selected by a word line. Part of the memory cell is selected by turning on one of the pass transistors on either side of the string of memory cells. The charge storage state of the selected part is determined by measuring current in a bit line tied to both pass transistors.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[High-speed memory system]]></title>
<link>http://www.freepatentsonline.com/7366821.html</link>
<description><![CDATA[A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein the plurality of memories are controlled by the switch. By suppressing reflection and loads on the bus, a higher data transmission speed can be obtained.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Storage device configured to sequentially input a command]]></title>
<link>http://www.freepatentsonline.com/7366860.html</link>
<description><![CDATA[A storage device is capable of sequentially inputting a command, which includes address information and attached information, from an information processor through an input/output unit. The storage device includes a storage unit for storing data; an extractor for extracting the address information and the attached information from an input command inputted through the input/output unit; a generator for, in response to input of the input command, generating transition information that transitions according to rules using an initial value; a comparator for determining whether the attached information and the transition information agree with each other; and an output controller for, only when the attached information and the transition information agree with each other, outputting storage data out of the data, which corresponds to the address information extracted by the extractor, through the input/output unit.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for selectively transmitting command signal and address signal]]></title>
<link>http://www.freepatentsonline.com/7366827.html</link>
<description><![CDATA[A method for transmitting a command signal and an address signal to a rank which is to be accessed includes receiving and buffering the command signal and the address signal, and transmitting the buffered command signal and address signal to the rank, in response to a clock signal and a select signal for accessing rank. Transmitting the buffered command signal and address signal to the rank includes latching the buffered command signal and address signal, in response to the select signal, and transmitting the latched command signal and address signal to the rank, in response to the clock signal. The method and an associated apparatus can selectively transmit a command signal and an address signal to a rank or plurality of memory devices in a memory module, thereby reducing the amount of current consumed by memory modules that are not to be accessed.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Compact SRAMs and other multiple transistor structures]]></title>
<link>http://www.freepatentsonline.com/7365398.html</link>
<description><![CDATA[A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one to form p-channel and n-channel devices very compactly by taking advantage of placement of gates on both sides, making common contacts and dense interconnections in 3D.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Edge transition detection circuitry for use with test mode operation of an integrated circuit memory device]]></title>
<link>http://www.freepatentsonline.com/RE40282.html</link>
<description><![CDATA[An integrated circuit structure and method provides for an integrated circuit device to respond to an edge transition detection (ETD) pulse in one of two ways. First, in response to the ETD pulse, the integrated circuit device exits a test mode at least temporarily every cycle of the integrated circuit device. Second, a node of the integrated circuit device is re-initialized every cycle if it is not forced by a super voltage indicative of test mode entry. Both of these responses prevent accidental entry of the integrated circuit device into the test mode. If the integrated circuit device is supposed to be in the test mode, it stays in the test mode. If, however, the integrated circuit device is not intended to be in the test mode, the ETD pulse forces the integrated circuit device out of the test mode. Subsequent entry into the test mode of the device is permitted if conditions for entry into the test mode have otherwise been met.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Flash memory device and method for fabricating the same, and programming and erasing method thereof]]></title>
<link>http://www.freepatentsonline.com/7366026.html</link>
<description><![CDATA[A flash memory device of SONOS structure and a method for fabricating the same, and programming and erasing operation methods, to improve reliability such as endurance and retention, are disclosed, which includes a first conductive type semiconductor substrate; an ONO layer on the semiconductor substrate; a first control gate on the ONO layer; second and third control gates on the ONO layer at both sides of the first control gate; and source and drain regions in the surface of the semiconductor substrate at both sides of the second and third control gates.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor memory device capable of reading and writing data at the same time]]></title>
<link>http://www.freepatentsonline.com/7366822.html</link>
<description><![CDATA[A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for self-adjusting input delay in DDR-based memory systems]]></title>
<link>http://www.freepatentsonline.com/7366862.html</link>
<description><![CDATA[A method and apparatus are provided for interfacing with a synchronous dynamic memory in which memory commands are provided to the memory. The memory is accessed in response to the memory commands. Read data is captured in a data capture circuit having a delay setting. The delay setting is updated in response to detection of a period of read inactivity of the memory.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Data identification method and apparatus]]></title>
<link>http://www.freepatentsonline.com/7365656.html</link>
<description><![CDATA[Disclosed herein is a data identification method for identifying, from within a readout signal from a recording medium on or in which user data of k bits are recorded using a recording modulation code wherein m bits from among n bits which compose one codeword have a value of “1” while the remaining n-m bits have another value of “0”, the data, n and m being integers including, a first step of delimiting the readout signal in a unit of a codeword and adding, with regard to one of the n-bit codewords obtained by the delimiting, an amplitude of the readout signal of the bits of “1” to 2^k different codewords which may possibly be recorded and setting results of the addition as evaluation values, and a second step of finding a maximum value among the 2^k evaluation values and outputting the maximum value as an evaluation result.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[SOI SRAM products with reduced floating body effect]]></title>
<link>http://www.freepatentsonline.com/7365396.html</link>
<description><![CDATA[A memory device is formed on a semiconductor-on-insulator (SOI) structure, the SOI structure including a substrate, an insulating layer on the substrate, and a semiconductor film on the insulating layer. The memory device includes a memory array in a memory region of the SOI structure, a plurality of first substrate contacts in the peripheral region of the memory device, and a plurality of second substrate contacts in the memory region of the SOI structure, wherein the first substrate contacts and the second substrate contacts are formed in and over the semiconductor film and in the insulating layer and are electrically connected to the substrate of the SOI structure.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[High speed bus with alignment, re-timing and buffer underflow/overflow detection enhancements]]></title>
<link>http://www.freepatentsonline.com/7366935.html</link>
<description><![CDATA[In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of data alignment, data re-timing, and circular buffer underflow/overflow detection, are described.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

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