<?xml version="1.0" encoding="UTF-8"?>

<rss version="2.0">

<channel>
<image>
<title>freepatentsonline.com</title>
<width>141</width>
<height>131</height>
<link>http://www.freepatentsonline.com/index.html</link>
<url>http://www.freepatentsonline.com/images/logo.gif</url>
</image>

<title>freepatentsonline.com: Coded data generation or conversion</title>
<link>http://www.freepatentsonline.com/result.html?query_txt=ccl/341%20and%20isd/04/29/2008&amp;uspat=on</link>
<description>USPTO Class 341 Coded data generation or conversion</description>
<language>en-us</language>
<lastBuildDate>Wed Apr 30 16:35:22 EDT 2008</lastBuildDate>

<item>
<title><![CDATA[Digital-to-analog converter]]></title>
<link>http://www.freepatentsonline.com/7365670.html</link>
<description><![CDATA[An analog-to-digital converter has a resistor string that generates a series of voltages that are equally spaced in the middle range of the series and unequally spaced at the upper and lower ends. An upper selector selects voltages at the upper end. A lower selector selects voltages at the lower end. A pair of midrange selectors select a pair of adjacent voltages in the middle range. A midrange voltage generator generates further voltages equally spaced between the two selected midrange voltages. An output selector selects one of the further voltages. The selectors are controlled by various bits of a digital input signal. The voltage selected by the upper selector, lower selector, or output selector becomes an analog output signal. This analog-to-digital converter has comparatively few resistors and transistors and can generate accurate voltages for driving a gray-scale display.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Absolute angle detection apparatus]]></title>
<link>http://www.freepatentsonline.com/7365654.html</link>
<description><![CDATA[In an absolute angle detection apparatus, sectors are obtained by dividing 360° by an even number, each sector having combinations of first and second code lines. The first code lines are Gray codes including third code lines that do not appear the same even when a digit from which they are read is changed and fourth code lines that appear the same when a digit from which they are read is changed. The first code lines at adjacent steps and the first code lines at the first and last steps differ from each other at one bit. Each first code line is shifted by one digit at every predetermined number of steps, and the first code line without shift is obtained when the first code line corresponding to the maximum shift is further shifted by one digit. The second code lines identify the fourth code lines.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Delta-sigma analog-to-digital converter (ADC) having an intermittent power-down state between conversion cycles]]></title>
<link>http://www.freepatentsonline.com/7365667.html</link>
<description><![CDATA[A delta-sigma analog to digital converter (ADC) having an intermittent power down state between conversion cycles provides for power consumption savings when the converter is in a lower sample rate operating mode. Clocks provided to the digital portions of the converter are disabled, except for a periodic interval in which a conversion is performed at the higher selectable sample rate of the converter. The analog portions of the converter can also be disabled, but are re-enabled for a predetermined time period and reset before the digital clocks are enabled, so that the loop filter and feedback value supplied from the quantizer to the loop filter are stable prior to each conversion.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Flux-quantizing superconducting analog to digital converter (ADC)]]></title>
<link>http://www.freepatentsonline.com/7365663.html</link>
<description><![CDATA[A superconducting analog-to-digital converter includes a superconducting input loop to which is applied an analog voltage to be converted to a digital format. The superconducting loop includes two Josephson junctions for converting said analog input voltage into a single flux quantum (SFQ) pulse stream having a frequency f1 which is directly proportional to the amplitude of the analog input voltage. The loop includes two outputs for distributing the pulse stream in a cyclical and staggered fashion onto the two loop outputs such that the frequency of the pulses along each one of the loop outputs is f½. Additional frequency divider circuits may be coupled to the loop outputs to produce pulse streams on N output lines having a frequency of f1/N.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Voltage conversion device having non-linear gain and changeable gain polarity]]></title>
<link>http://www.freepatentsonline.com/7365666.html</link>
<description><![CDATA[A voltage conversion device having non-linear gain and changeable gain polarity includes a switch module, a gain decision module, a first voltage selection module, a second voltage selection module, a first switch unit, a second switch unit and a voltage output module. The switch module is used for outputting analog voltage provided by the analog voltage source or voltage corresponding to the system ground end. The gain decision module is used for determining a gain. The first voltage selection module is used for outputting a first DC voltage. The second voltage selection module is used for outputting a second DC voltage. The first switch unit is used for outputting the first DC voltage. The second switch unit is used for outputting the second DC voltage. The voltage output module is used for outputting an amplified result of a DC voltage according to the gain.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[DC-offset correction circuit for a communication system and method of correcting a DC-offset in a communication system]]></title>
<link>http://www.freepatentsonline.com/7365662.html</link>
<description><![CDATA[A DC-offset correction circuit includes an analog circuit to generate a plurality of analog offset-correction signal values, each of which are assigned to a hop band. The analog circuit is coupled to a tap of an analog receiver chain and includes a first analog selector to select an analog offset-correction signal value, the selected analog offset correcting signal value being assigned to a current hop band. Further, the DC-offset correction circuit includes a combiner to combine a received signal with the selected analog offset-correction signal value and feed the analog receiver chain.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for lossless run-length data encoding]]></title>
<link>http://www.freepatentsonline.com/7365658.html</link>
<description><![CDATA[An apparatus and method for lossless run-length data encoding is disclosed. In the first stage of the method, an input data sequence is transformed without increasing its volume in order to obtain long sequences of identical digits. In the second stage, every such sequence is replaced with a unique shorter sequence. The compressed data is decoded performing corresponding inverse operations. The method is very efficient for compression of some classes of digital images with long sequences of the same number, such as graphics, texts, signatures, and fingerprints.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Data identification method and apparatus]]></title>
<link>http://www.freepatentsonline.com/7365657.html</link>
<description><![CDATA[A data identification method including: a first step; a second step; a third step; and a fourth step, and the third and fourth steps being repeated until an identification result included in the table of recording modulation codes is obtained at the third step.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Data identification method and apparatus]]></title>
<link>http://www.freepatentsonline.com/7365656.html</link>
<description><![CDATA[Disclosed herein is a data identification method for identifying, from within a readout signal from a recording medium on or in which user data of k bits are recorded using a recording modulation code wherein m bits from among n bits which compose one codeword have a value of “1” while the remaining n-m bits have another value of “0”, the data, n and m being integers including, a first step of delimiting the readout signal in a unit of a codeword and adding, with regard to one of the n-bit codewords obtained by the delimiting, an amplitude of the readout signal of the bits of “1” to 2^k different codewords which may possibly be recorded and setting results of the addition as evaluation values, and a second step of finding a maximum value among the 2^k evaluation values and outputting the maximum value as an evaluation result.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method and device for decoding syntax element in CABAC decoder]]></title>
<link>http://www.freepatentsonline.com/7365660.html</link>
<description><![CDATA[A method and a device for decoding a syntax element in a context-based adaptive binary arithmetic coding (CABAC) decoder perform a binary arithmetic coding (BAD) process and a binarization matching (BM) process in parallel. The method includes determining an expected bin value to make a bin string including the bin value valid while generating a one-bit bin value by performing a BAD process for a syntax element to be decoded; determining whether the generated bin value is the same as the expected bin value; generating the decoded value of the syntax element by de-binarization of a bin string including the generated bin value if the bin value generated in the BAD process is the same as the expected bin value; and performing the BAD process to generate the next bin value if the bin value generated in the BAD process is different from the expected bin value.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Transcoding media content from a personal video recorder for a portable device]]></title>
<link>http://www.freepatentsonline.com/7365655.html</link>
<description><![CDATA[A media signal is controlled using a portable media content device. The media signal is received and encoded into an encoded media signal for a portable media content device. The encoded media signal is stored for playback on the portable media content device.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Low-delay signal processing based on highly oversampled digital processing]]></title>
<link>http://www.freepatentsonline.com/7365669.html</link>
<description><![CDATA[A low-delay signal processing system and method are provided which includes a delta-sigma analog-to-digital converter, an oversampling processor, and a delta-sigma digital-to-analog converter. The delta-sigma analog-to-digital converter receives an input or audio signal and generates a digital sample signal at a high oversampling rate. The oversampling processor is connected to the analog-to-digital converter for processing the digital sample signal at the high oversampling rate with low-delay. The delta-sigma digital-to-analog converter is connected to the oversampling processor for receiving the digital sample signal at the high oversampling rate with low-delay for generating an analog signal. The oversampling processor includes a low-delay filter and a programmable delay element. In this manner, the analog signal is produced with a low delay and high accuracy.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Power converter circuitry and method]]></title>
<link>http://www.freepatentsonline.com/7365661.html</link>
<description><![CDATA[A control system and method for simultaneously regulating the operation of a plurality of different types of switching power converters. The system utilizes in regulating the power converters sampled data and nonlinear feedback control loops.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[ADC with dynamic range extension]]></title>
<link>http://www.freepatentsonline.com/7365664.html</link>
<description><![CDATA[ADC circuitry has a first programmable gain amplifier to amplify an analog input, a first analog to digital converter coupled to an output of the first amplifier, a second programmable gain amplifier, to amplify the analog input, a second analog to digital converter coupled to an output of the second amplifier, and a digital circuit for deriving a digital output from the outputs of the first and second converters and a controller for controlling the gains of the first and second amplifiers, according to the outputs of the first and second converters. Such programmable gain pre amplifiers help enable effective dynamic range to be extended without unduly increasing the number of quantisation bits, or the number of components or the power dissipation. It can be used in applications sensitive to size and power, such as DSP based acoustic devices including hearing aids.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Continuous-time delta-sigma analog digital converter having operational amplifiers]]></title>
<link>http://www.freepatentsonline.com/7365668.html</link>
<description><![CDATA[The invention concerns a continuous-time delta-sigma analog-digital converter for the conversion of an analog input signal into a digital output signal, comprising an analog filter which filters the analog input signal and at least one externally circuited operational amplifier (OPAMP) for the formation of an integrator stage, a clock-driven quantizer, which quantizes the filtered analog signal outputted through the analog filter to generate the digital output signal, and a feedback arrangement with at least one digital-analog converter, which supplies to the analog filter at least one feedback signal on the basis of the digital output signal. For the reduction of the necessary amplification-bandwidth product for the operational amplifier (OPAMP) it is stipulated according to the invention that the operational amplifier (OPAMP) has a first amplifier path (gm 3 ) and parallel to this a second amplifier path (gm 2 , gm 5 ), wherein the transit frequency of the second amplifier path (gm 2 , gm 5 ) is lower than the transit frequency of the first amplifier path (gm 3 ).]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Communication channel with undersampled interpolative timing recovery]]></title>
<link>http://www.freepatentsonline.com/7365671.html</link>
<description><![CDATA[Method and apparatus for processing transmitted data. A sampling circuit preferably performs lossy sampling of a continuous signal to provide a corresponding sequence of discrete samples at a sampling rate less than a Nyquist rate of the continuous signal. A processing circuit reconstructs an informational content of the continuous signal from the discrete samples, and operates to periodically insert additional samples into the sequence, which preferably increases an effective rate of said sampling to match or exceed the Nyquist rate. Preferably, the lossy discrete samples are temporarily stored in a memory space prior to reconstruction by the processing circuit. The sampling circuit preferably comprises an analog-to-digital converter (ADC) of an analog front end (AFE). The processing circuit preferably comprises a digital back end (DBE) employing partial-response, maximum-likelihood (PRML) detection. The additional samples are preferably provided by an iterative timing recovery (ITR) block of the DBE.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Phonetic searching using multiple readings]]></title>
<link>http://www.freepatentsonline.com/7366984.html</link>
<description><![CDATA[The names of contacts are stored as characters. Each character may include one or more phonic codes that are encoded into the character. A smart filter decodes the character into its constituent sounds. An input string is received that includes phonic codes. An application matches the decoded constituent sounds with the specified phonetic codes from the input string in accordance with rules of the spoken language and character boundaries to determine a contact to display.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Embedding a multi-resolution compressed thumbnail image in a compressed image file]]></title>
<link>http://www.freepatentsonline.com/7366319.html</link>
<description><![CDATA[A method ( 300 ) of encoding an image into an image code-stream. The method ( 300 ) generates a reduced resolution representation of the image and encodes the reduced resolution representation in accordance with a multi-resolution format to form an encoded reduced resolution representation of the image. The encoded reduced resolution representation is embedded into a first portion of the image code-stream and a compressed representation of the image is encoded into a further portion of the image code-stream.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

</channel>
</rss>
