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        <title>Free Patents Online: Miscellaneous active electrical nonlinear devices, circuits, and systems</title>
        <link>http://www.freepatentsonline.com./rssfeed/rsspat327.xml</link>
        <description>USPTO Class 327 Miscellaneous active electrical nonlinear devices, circuits, and systems</description>
        <language>en-us</language>
        <lastBuildDate>Tue, 22 Dec 2009 08:00:00 EST</lastBuildDate>
        <item>
            <title><![CDATA[Multiplex bus system with duty cycle correction]]></title>
            <link>http://www.freepatentsonline.com./7636410.html</link>
            <description><![CDATA[The present invention is related to a method for treating a digital signal within a protocol handler which is part of a module coupled to a multiplex bus. The method consists in detecting the duty cycle of the digital signal, and in modifying said digital signal so that the modified signal contains the same data, but has a duty cycle of approximately 50%.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Signal detector used in wireless communication system]]></title>
            <link>http://www.freepatentsonline.com./7636407.html</link>
            <description><![CDATA[A signal detector arranged in a receiver of a wireless communication device includes a variable passband bandpass filter configured to bandlimit a received signal using a variable passband; a signal parameter detection unit configured to detect a signal parameter of each of a plurality of signals contained in the received signal; a detection order determination unit configured to determine a detection order for detecting the signals from the received signal based on the signal parameter; a parameter control unit configured to control the passband of the variable passband bandpass filter based on the detection order and the signal parameter; and an equalization and decision unit configured to equalize and decide the bandlimited signal output from the variable passband bandpass filter. The signals contained in the received signal are successively detected from the received signal according to the detection order by means of the variable passband bandpass filter and the equalization and decision unit.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Single-ended sense amplifier for very low voltage applications]]></title>
            <link>http://www.freepatentsonline.com./7636264.html</link>
            <description><![CDATA[A sense amplifier has a transimpedance amplifier capable of producing an output voltage level proportionate to a current variation sensed going into a bitline. A transconductance device is configured to produce varying bitline current in response to the transimpedance amplifier output voltage. The transconductance device is capable of utilizing the transimpedance amplifier output voltage as feedback to produce a bitline clamp voltage level. The transimpedance amplifier configured to produce an output voltage proportionate to a cell current of a selected memory cell and provide an output signal corresponding to a memory cell state. An output amplifier is coupled to the transimpedance amplifier and capable of producing an output signal level proportionate to the transimpedance amplifier output voltage. A bias circuit is coupled to the transimpedance amplifier and the output amplifier, the bias circuit is capable of producing reference mirror currents through the transimpedance amplifier and the output amplifier.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Current sample and hold circuit and method and demultiplexer and display device using the same]]></title>
            <link>http://www.freepatentsonline.com./7636075.html</link>
            <description><![CDATA[A data current sample and hold circuit having an input terminal of a current source type and an output terminal of a current sink type. The sample and hold circuit includes a first transistor, a capacitor, and a plurality of switches, for sampling and holding the data current sunk to an output terminal of a data driver. When the sampled and held data current is applied to the data line, the data current is sunk to an output terminal of the sample and hold circuit. The sample and hold circuit is used together with a data driver having an output terminal of the current sink type.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Fast, efficient reference networks for providing low-impedance reference signals to signal converter systems]]></title>
            <link>http://www.freepatentsonline.com./7636057.html</link>
            <description><![CDATA[Reference network embodiments are provided for use in pipelined signal converter systems. The network embodiments are fast and power efficient and they generate low-impedance reference signals through the use of a complimentary common-drain output stage, an output current valve inserted between transistors of the output stage, and a controller. The controller is configured to provide gate voltages to the output current valve to thereby establish a substantially-constant output current. The controller is further configured to provide gate voltages to the output stage to establish top and bottom reference voltages about the output current valve that are spaced from a common-mode voltage. This reference structure maintains a constant output current as the span between the top and bottom reference voltages is selectively altered. In different embodiments, transistors of the output current valve are arranged in a drain-to-source-coupled configuration and in a source-coupled configuration.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Phase locked loop with phase shifted input]]></title>
            <link>http://www.freepatentsonline.com./7636018.html</link>
            <description><![CDATA[In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to the phase difference signals, charge pumps (CPs) control output voltages thereof. Based on the output voltages of the CPs, a voltage controlled oscillator (VCO) outputs an output signal. A frequency divider divides the frequency of the output signal from the VCO to generate the frequency division output signal. A circulator outputs the frequency division output signal to one of the PFDs at a proper timing. A modulator reduces quantization errors of the frequency divider.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Charge domain filter device]]></title>
            <link>http://www.freepatentsonline.com./7636012.html</link>
            <description><![CDATA[A charge domain filter device includes a SINC filter with a frequency characteristic expressed by a SINC function, and a bandpass filter connected to an output end of the SINC filter and having a frequency characteristic with a particular center frequency.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Controller for ORing field effect transistor]]></title>
            <link>http://www.freepatentsonline.com./7636011.html</link>
            <description><![CDATA[An ORing element for use in a power supply and/or power system. The ORing element may include a field effect transistor (FET), a first bi-polar transistor and a second bi-polar transistor. The FET may be electrically connected between an input and an output. The first bipolar transistor may have an emitter electrically connected to the source of the FET and a collector electrically connected to a gate of the FET. The second bi-polar transistor may be diode connected, with its emitter electrically connected to its base. The emitter of the second bi-polar transistor may also be electrically connected to the base of the first bi-polar transistor. The collector of the second bi-polar transistor may be electrically connected to the drain of the FET.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Process independent curvature compensation scheme for bandgap reference]]></title>
            <link>http://www.freepatentsonline.com./7636010.html</link>
            <description><![CDATA[In a voltage reference circuit, a bandgap reference circuit, for generating a bandgap reference voltage and a reference current, includes an operation amplifier, and a first transistor for providing the reference current. Another transistor mirrors the reference current to provide a first current. A compensation controller converts a node voltage from the bandgap reference circuit into a second current and performs current subtraction on the first current and the second current to provide a compensation feedback current to another node of the bandgap reference circuit. So that, second order temperature compensation is performed on the bandgap reference voltage.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Bias current generating apparatus with adjustable temperature coefficient]]></title>
            <link>http://www.freepatentsonline.com./7636009.html</link>
            <description><![CDATA[There is provided a bias current generating apparatus capable of providing a bias current where a characteristic change is compensated, to one of an analog circuit and RF circuit where various characteristic changes occur according to a temperature, by generating bias currents having a plurality of temperature coefficients. The apparatus includes: a positive temperature coefficient current generator generating a positive temperature coefficient current in direct proportion to an absolute temperature; a zero temperature coefficient current generator generating a zero temperature coefficient current constant regardless of the absolute temperature; and an adjustable temperature coefficient current generator generating and outputting an adjustable temperature coefficient current by amplifying the positive temperature coefficient current by A times, amplifying the zero temperature coefficient current by B times, adding the two amplified temperature coefficient currents, wherein a temperature coefficient of the adjustable temperature coefficient current is varied by adjusting sizes of the A and B.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Pass gate circuit stably transferring signal and control method]]></title>
            <link>http://www.freepatentsonline.com./7636008.html</link>
            <description><![CDATA[Provided are a pass gate circuit and a method of controlling the same for improving meta-stability when transferring signals. The gate circuit includes a signal transfer unit transferring an input signal in response to a transfer control signal, and a control signal generating unit generating a safety window having a predetermined width in response to detection of a transition of the input signal, generating an internal control signal for maintaining the signal transfer state of the signal transfer unit, and outputting the internal control signal to the signal transfer unit as the transfer control signal.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Low jitter high phase resolution PLL-based timing recovery system]]></title>
            <link>http://www.freepatentsonline.com./7636007.html</link>
            <description><![CDATA[A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Voltage supply interface circuit]]></title>
            <link>http://www.freepatentsonline.com./7636006.html</link>
            <description><![CDATA[A monolithic interface circuit for providing a voltage, from a control circuit supplied by a supply voltage referenced to a reference voltage, to a terminal likely to be at a high voltage with respect to the reference voltage, comprising a high-voltage N-channel MOS transistor having its gate intended to receive a control signal referenced to the reference voltage and having its source intended to be connected to the reference voltage, and a high-voltage PNP transistor having its base connected to the drain of the MOS transistor, having its emitter intended to receive the supply voltage and having its collector intended to provide a voltage to the terminal likely to be at a high voltage.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Active clamp for semiconductor device]]></title>
            <link>http://www.freepatentsonline.com./7636005.html</link>
            <description><![CDATA[An active clamp circuit for avalanching and clamping voltage at a gate terminal of a first transistor connected to a power source. The active clamp circuit includes a second transistor for turning ON the first transistor; a third transistor having EPI breakdown voltage less than that of the first transistor; a resistor coupled between a node and source and gate terminals of the third transistor; and an amplifier for comparing voltage on the resistor to a reference voltage and providing an output signal to control the second transistor, wherein, when the third transistor avalanches and the voltage across the resistor exceeds the reference voltage, the output signal turns ON the second transistor thereby clamping the gate terminal of the first transistor, wherein the active clamp circuit tracks the channel characteristic of the first transistor.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[High-frequency switching device and semiconductor]]></title>
            <link>http://www.freepatentsonline.com./7636004.html</link>
            <description><![CDATA[The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Limiting amplifiers]]></title>
            <link>http://www.freepatentsonline.com./7636003.html</link>
            <description><![CDATA[A limiting amplifier with an input stage with dc offset cancellation, identical gain stages, an output buffer and a feedback filter. The input stage receives a differential input signal and outputs a first intermediate differential signal. The gain stages are cascaded to amplify the first intermediate differential signal and generate a second intermediate differential signal, amplified by the output buffer to produce an output signal. The feedback filter provides a dc offset voltage of the output signal to the input stage for the dc offset cancellation. The input stage comprises a resistor network coupled between a pair of input nodes and a power line and comprising a common resistor, a pair of load resistors and a shunt resistor. The load resistors share a common terminal connected to the common resistor that is connected to the power line. The shunt resistor has two terminals respectively connected to the load resistors.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Clock multiplier and method of multiplying a clock]]></title>
            <link>http://www.freepatentsonline.com./7636002.html</link>
            <description><![CDATA[A clock multiplier for multiplying an input clock by N includes a phase/frequency detector, a clock selector, and a voltage-controlled delay line. The phase/frequency detector generates a first control signal and a second control signal according to a frequency/phase difference between the input clock and a count signal indicating a signal that is generated by delaying the input clock N times. The clock selector selects one of the input clock and a feedback clock based on the input clock and the count signal. The voltage-controlled delay line adjusts a delay time of the selected signal according to a control voltage that is generated based on the first control signal and the second control signal, and outputs the feedback clock based on the adjusted signal. The clock multiplier operates without accumulating a frequency/phase difference between the input clock and the output clock when the multiplying ratio is increased.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Digital DLL circuit]]></title>
            <link>http://www.freepatentsonline.com./7636001.html</link>
            <description><![CDATA[A digital DLL circuit includes: a first register configured to hold a first delay specifying value to specify a delay of a rising edge side of a signal; a second register configured to hold a second delay specifying value to specify a delay of a falling edge side of a signal; and a digitally-controlled variable delay circuit configured to be allowed to individually control delays of a rise side and a fall side of a signal. The digital DLL circuit further includes a control circuit configured to implement control so that a rise-side delay and a fall-side delay by the variable delay circuit are kept at the first delay specifying value of the first register and the second delay specifying value of the second register, respectively.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Phase locked loop without a charge pump and integrated circuit having the same]]></title>
            <link>http://www.freepatentsonline.com./7636000.html</link>
            <description><![CDATA[A phase locked loop includes a phase-frequency detector and a loop filter. The phase-frequency detector compares phases of an input signal and a feedback signal to generate first and second control signals. The loop filter includes a pull-up resistor, a pull-down resistor and a capacitance unit. The loop filter receives a first reference voltage to charge the capacitance unit through a path formed by the pull-up resistor to the capacitance unit, receives a second reference voltage to discharge the capacitance unit through a path formed by the pull-down resistor to the capacitance unit and outputs a control voltage generated based on a charge amount of the charged capacitance unit. Therefore, the phase locked loop can operate at a relatively low voltage and can operate based on a control voltage with a wide input range.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Clock frequency division methods and circuits]]></title>
            <link>http://www.freepatentsonline.com./7635999.html</link>
            <description><![CDATA[Frequency division methods and circuits are provided for producing an output clock signal with a frequency related to the frequency of an input clock signal by a predetermined factor. The method and circuit rely on the input clock signal and on feedback from the output signal to produce an intermediate signal. The frequency of the intermediate signal is divided to produce the output clock signal. The method and circuit may be implemented using few circuit components. In an exemplary embodiment, the method and circuit may be used to produce an output clock signal with a frequency that is two-and-a-half times lower than the frequency of the input clock signal.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Pre-driver for bridge circuit]]></title>
            <link>http://www.freepatentsonline.com./7635998.html</link>
            <description><![CDATA[A pre-driver for driving a high-side transistor of a bridge driver is connected to a bridge driver including first and second drive transistors connected in series between a high voltage power supply and ground. A reference circuit generates a reference voltage that varies depending on the output voltage of the bridge driver. In response to the reference voltage, the regulator circuit generates an internal power supply voltage that is substantially higher than the output voltage by a constant value. A buffer circuit generates a drive voltage for driving the first drive transistor based on the internal power supply voltage and the output voltage.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Circuit for and method of changing a frequency in a circuit]]></title>
            <link>http://www.freepatentsonline.com./7635997.html</link>
            <description><![CDATA[The circuits and methods of the various embodiments of the present invention enable changing the frequency of a frequency synthesizer. According to one embodiment, a method of changing a frequency of a clock signal generated by a frequency synthesizer comprises the steps of receiving a reference clock signal; receiving a command comprising a new frequency synthesizer value; locking to a new frequency based upon the new frequency synthesizer value; and dynamically outputting a generated clock signal based upon the new frequency synthesizer value. According to another embodiment, a method of changing a frequency of a clock signal comprises adaptively adjusting the digital loop bandwidth of the frequency synthesizer. A circuit for changing a frequency of a clock signal generated in an integrated circuit is also disclosed.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Differential blocking sampler, in particular for an analog digital converter]]></title>
            <link>http://www.freepatentsonline.com./7635996.html</link>
            <description><![CDATA[The invention relates to a blocking sampler intended in particular to be used upstream of a fast analog digital converter.  The blocking sampler comprises two main semi-samplers each having a respective differential input (E, E′) and a respective differential output (S, S′). With each main semi-sampler is associated a respective auxiliary blocking semi-sampler comprising an auxiliary tracking transistor (T 1 a , T 1 a ′) powered by a voltage tapped off from the terminals of the storage capacitor (C′, C) of the other main blocking sampler, an auxiliary storage capacitor (Ca, Ca′) linked to the output of this auxiliary tracking transistor and an auxiliary current switch (T 2 a , T 3 a , SC 1 a ; T 2′ a , T 3′ a , SC 1 a ′) controlled in synchronism with the current switch of the main blocking sampler so as to authorize or block the passage of current in the auxiliary tracking transistor. The auxiliary samplers serve to improve the sampling dynamics in the cases where the signal to be sampled varies rapidly.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Voltage comparator]]></title>
            <link>http://www.freepatentsonline.com./7635995.html</link>
            <description><![CDATA[A voltage comparator where the difference of currents from transistors is converted into voltage, which is amplified and conducted to a gate terminal of a switching transistor. A source of a limiting transistor is connected to the gate terminal. The voltage at the gate terminal when the switching transistor is quiescent is equal to a value between eight and nine tenths of the switching voltage at the gate of the transistor, at which voltage the transistor triggers a switching in the output stage. A response to an input voltage change at one direction of the sign reversal of the difference of the input voltages is fast. The voltage comparator is robust and reliable with regard to temperature variations.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Fast rail-to-rail voltage comparator and method for rail-to-rail voltage comparison]]></title>
            <link>http://www.freepatentsonline.com./7635994.html</link>
            <description><![CDATA[Method and apparatus are provided for fast rail-to-rail voltage comparison. A rail-to-rail voltage comparator for indicating one of two states with an output signal in response to an input signal is provided comprising an input stage having an input configured to receive the input signal and having an output, and an amplification circuit having an input coupled to the output of the input stage. The input stage comprises a first differential amplifier having a first input-voltage range and configured to produce a first current based on the input signal, a second differential amplifier having a second input-voltage range and configured to produce a second current based on the input signal, and a summing circuit having a first input coupled to the first differential amplifier and having a second input coupled to the second differential amplifier. The first input-voltage range overlaps the second input-voltage range. The summing circuit is configured to produce a first voltage at the output of the input stage based on a sum of the first current and the second current. The amplification circuit is configured to incrementally amplify the first voltage to a second voltage and further configured to produce the output signal having the second voltage. The second voltage indicates one of the two states.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Configurable tapered delay chain with multiple sizes of delay elements]]></title>
            <link>http://www.freepatentsonline.com./7635992.html</link>
            <description><![CDATA[A tapered chain of delay elements. The chain of delay elements includes a plurality of delay elements comprising a plurality of smaller sized stacked inverter delay elements each configured to implement a first delay, and a plurality of larger sized stacked inverter delay elements each configured to implement a second delay larger than the first delay. A switch circuit is coupled to the plurality of delay elements and is configured to select at least one of the plurality of delay elements to create a delay signal path having an amount of delay in accordance with a number of delay elements comprising the delay signal path. An input is coupled to a first delay element of the delay signal path to receive an input signal. An output is coupled to the switch circuit, wherein the output is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.]]></description>
            <pubDate>Tue, 22 Dec 2009 08:00:00 EST</pubDate>
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