<?xml version="1.0" encoding="UTF-8"?>

<rss version="2.0">

<channel>
<image>
<title>freepatentsonline.com</title>
<width>141</width>
<height>131</height>
<link>http://www.freepatentsonline.com/index.html</link>
<url>http://www.freepatentsonline.com/images/logo.gif</url>
</image>

<title>freepatentsonline.com: Miscellaneous active electrical nonlinear devices, circuits, and systems</title>
<link>http://www.freepatentsonline.com/result.html?query_txt=ccl/327%20and%20isd/04/29/2008&amp;uspat=on</link>
<description>USPTO Class 327 Miscellaneous active electrical nonlinear devices, circuits, and systems</description>
<language>en-us</language>
<lastBuildDate>Wed Apr 30 16:35:22 EDT 2008</lastBuildDate>

<item>
<title><![CDATA[Internal voltage generator]]></title>
<link>http://www.freepatentsonline.com/7365595.html</link>
<description><![CDATA[An internal voltage generator is highly tolerant of electrical parameter changes of transistors occurring due to process deviation. The generator can produce an internal voltage within a short setup time when there is a significant difference between a voltage level of an internal voltage when power is initially supplied to the internal voltage generator and a voltage level of an internal voltage to be produced. In one embodiment, the internal voltage generator of the present invention includes a comparator block and an output driving block to produce an internal voltage. The internal voltage generator further includes a reference voltage generation block, which generates at least two reference voltages to be supplied to the comparator block, and an offset section control block, which supplies a control signal for optimizing an offset section, that is, a voltage difference between the reference voltages, to the reference voltage generation block. The internal voltage generator can further optionally include an auxiliary output driving block in addition to a main output driving block to reduce the setup time for which the internal voltage is produced when voltage is initially supplied and to reduce power consumption. The internal voltage generator further includes a first control signal generation block and a control block to control operations of the main and auxiliary output driving blocks.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Output equalized charge pump]]></title>
<link>http://www.freepatentsonline.com/7365593.html</link>
<description><![CDATA[A charge pump circuit has a charge pump section and a replica charge pump section. The replica charge pump section produces a replica voltage at which the UP current will match the DOWN current. A comparator compares the replica voltage to the output voltage, and adjusts the bias to the charge pump section and replica charge pump section so that the voltage level produced by the replica charge pump section matches the output voltage.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Bootstrapped charge pump driver in a phase-lock loop]]></title>
<link>http://www.freepatentsonline.com/7365582.html</link>
<description><![CDATA[A charge pump includes first and second pairs of differential transistors. Each transistor includes control, first, and second terminals. First and second charge pump drivers communicate with the control terminal of one of the first pair of differential transistors and one of the second pair of differential transistors, respectively. Third and fourth charge pump drivers communicate with the control terminal of the other of the first pair of differential transistors and the other of the second pair of differential transistors, respectively. The first through fourth charge pump drivers include respective pairs of differential transistors that receive control signals from respective control circuits.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[System and method for jitter control]]></title>
<link>http://www.freepatentsonline.com/7365580.html</link>
<description><![CDATA[A fractional-N frequency synthesizer is described that includes a voltage controlled oscillator (VCO), a programmable integer divider, and a glitch-free phase rotator. The phase select inputs of the phase rotator are controlled by a delta-sigma modulator to provide fine frequency resolution in addition to randomization and noise shaping of fractional quantization noise. The delta-sigma modulator is clocked at rates higher than the synthesizer reference clock resulting in an improvement in clock jitter at the output of the frequency synthesizer. A glitch-free phase multiplexer design is used to implement the phase rotator fractional divider to enables operation at rates higher than the reference clock. The over-sampling ratio of the delta-sigma modulator over the reference clock frequency of the PLL translates directly into an improvement in the quality of the output clock with respect to fractional quantization noise, phase mismatch, and digital noise injection.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Hysteresis-type input circuit]]></title>
<link>http://www.freepatentsonline.com/7365586.html</link>
<description><![CDATA[Hysteresis circuit  10  is composed of three inverters  40, 42, 44.  Node N B  in hysteresis circuit  10  is connected to the input terminal of transition-detecting part  14  of transmission control part  12.  Transition-detecting part  14  detects the timing of the start of the output inversion operation and the timing of the completion of the transition in hysteresis circuit  10  corresponding to potential V B  of node N B , and it controls activation/deactivation of inverter  50  on the signal transmission path.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Delay locked loop for high speed semiconductor memory device]]></title>
<link>http://www.freepatentsonline.com/7365583.html</link>
<description><![CDATA[A delayed locked loop supports increased operation frequency in a semiconductor memory device. An output driver for use in a delay locked loop includes a first driving block for receiving an output from the delay locked loop to generate a first DLL clock for outputting read data corresponding to a read command, and a second driving block for receiving an output from the delay locked loop to generate a second DLL clock for reducing current consumption during a write operation, wherein the first driving block has larger delay amount than the second driving block.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Automatic time constant adjustment circuit]]></title>
<link>http://www.freepatentsonline.com/7365588.html</link>
<description><![CDATA[An automatic time constant adjustment circuit has an error detection circuit and a variable time constant circuit. The error detection circuit detects, based on the resistance of an error reference resistor and the capacitance of an error reference capacitor provided therein, a resistance/capacitance error resulting from a variation attributable to an IC process, and then outputs a control signal corresponding to the resistance/capacitance error. The variable time constant circuit includes a resistance portion, a capacitance portion, and a switch portion. The resistance portion is build with one or more resistors. The capacitance portion is build with one or more capacitors. The switch portion sets the time constant of the variable time constant circuit according to the resistance/capacitance error by connecting together one of the resistors of the resistor portion and one of the capacitors of the capacitor portion according to the control signal.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Slew-rate control apparatus and methods for a power transistor to reduce voltage transients during inductive flyback]]></title>
<link>http://www.freepatentsonline.com/7365584.html</link>
<description><![CDATA[Apparatus and methods that reduce the amount of conducted/radiated emissions from a power switch ( 200 ) when a transistor ( 210 ) is switched OFF are disclosed. In addition, apparatus and methods that reduce the slew rate in a power switch when the power switch is switched off are disclosed. The apparatus comprises a transistor ( 210 ) including an inductive load ( 230 ) coupled to the transistor, a plurality of current sources ( 222, 224 ) coupled to the gate of the transistor, and a clamp ( 250 ) coupled to either the gate and the drain of the transistor, or to the gate and to ground depending on the location of the inductive load, wherein the clamp comprises a resistive element ( 260 ) to increase the voltage of the clamp when current flows through the clamp, and wherein the increased voltage causes the apparatus to include a different slew rate.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Noise waveform generator with spectrum control]]></title>
<link>http://www.freepatentsonline.com/7365577.html</link>
<description><![CDATA[A waveform generator for generating a desired waveform is provided, including a noise kernel configured to store a plurality of samples from a predetermined waveform, the plurality of samples being assigned to a plurality of memory blocks; and an address arrangement configured to randomly select a selected one of the plurality of memory blocks; wherein the noise kernel is configured to communicate the plurality of samples assigned to the selected memory block.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Contention-free keeper circuit and a method for contention elimination]]></title>
<link>http://www.freepatentsonline.com/7365587.html</link>
<description><![CDATA[A contention-free keeper circuit including a keeper circuit having a first node and a second node, is provided. The contention-free keeper circuit may further include a delay element for providing time delay. The contention-free keeper circuit may further include a high-to-low contention element coupled between the first node and a first supply, and coupled to the delay element output. The contention-free keeper circuit may further include a low-to-high contention elimination element coupled between the first node and a second supply, and coupled to the delay element output, (i) wherein responsive to a low-to-high transition at the first node and the time delay, the low-to-high contention elimination element eliminates a low-to-high contention within the keeper circuit, and (ii) wherein responsive to a high-to-low signal transition at the first node and the time delay, the high-to-low contention elimination element eliminates a high-to-low contention within the keeper circuit.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[State retention within a data processing system]]></title>
<link>http://www.freepatentsonline.com/7365596.html</link>
<description><![CDATA[Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor device with pump circuit]]></title>
<link>http://www.freepatentsonline.com/7365578.html</link>
<description><![CDATA[In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Gate driving circuit]]></title>
<link>http://www.freepatentsonline.com/7365579.html</link>
<description><![CDATA[A gate driving circuit has a variable current carrying path that switches a current carrying path among a driving target device, a DC power source and a reactor to operate in plural operation modes including at least a hold mode, a preparation mode, and an execution mode. The variable current carrying path includes a backflow path for causing a reactor current flowing through the reactor to flow back to the DC power source when a gate voltage of the driving target device deviates from a preset allowable voltage range. A drive control part sets the operation mode of the variable current carrying path to the hold mode and holds the ON state or the OFF state of the driving target device, and further switches the operation mode in sequence of the preparation mode and the execution mode, and realizes turn-on or turn-off of the driving target device.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Voltage generating circuit]]></title>
<link>http://www.freepatentsonline.com/7365591.html</link>
<description><![CDATA[A first transistor is arranged between a reference voltage node and a first node, and is connected at its gate to a second node. A second transistor is arranged between the second node and the reference voltage node, and is connected at its gate to the first node. Charges are supplied to the first and second nodes via capacitance elements receiving first and second control signals, respectively. Further, a third transistor is arranged between the second node and an output node, and is connected at its gate node to a third control signal φCT via a third capacitance element. A fourth transistor is connected between the output node and a gate node of the third transistor, and is connected at its gate to the second node. An internal voltage at an intended level can be generated with low power consumption while efficiently using charges without causing an ineffective current flow.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Current driver, data driver, display device and current driving method]]></title>
<link>http://www.freepatentsonline.com/7365594.html</link>
<description><![CDATA[A current driver includes a gate line having a first and second nodes, K driving transistors, a terminal and a voltage generation section. The terminal receives a first current. The voltage generation section generates a bias voltage according to a current value of the first current. The gate line receives, at one of the first and second nodes, the bias voltage generated by the voltage generation section. Gates of the K transistors are connected between the first and second nodes of the gate line. In the voltage generation section, the relationship between the first current and the bias voltage is adjusted in the first mode, according to a current value of an output current flowing in a first driving transistor of the K driving transistors, and in the second mode, according to a current value of an output current flowing in a second driving transistor of the K driving transistors.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Bandgap reference circuit]]></title>
<link>http://www.freepatentsonline.com/7365589.html</link>
<description><![CDATA[A bandgap reference circuit, taking two or more power supplies as the input power supply for outputting a reference voltage, includes a first reference circuit, a second reference circuit, a power selection circuit and a switch circuit. The first and second reference circuits receive two respective power supplies for producing first and second voltages, respectively. As the power selection circuit takes the first power voltage level as the input voltage, the power selection circuit outputs a first control signal; while the power selection circuit takes the second power voltage level as the input voltage, the power selection circuit outputs a second control signal. The switch circuit is coupled to the power selection circuit, the first reference circuit and the second reference circuit. As the switch circuit receives the first control signal, it outputs the first voltage; while the switch circuit receives the second control signal, it outputs the second voltage.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Regulated adaptive-bandwidth PLL/DLL using self-biasing current from a VCO/VCDL]]></title>
<link>http://www.freepatentsonline.com/7365581.html</link>
<description><![CDATA[A PLL/DLL circuit is current self-biased responsive to a current I ld  provided from a voltage regulator to a VCO or VCDL. Bias current I bias , which is proportional to I ld , is provided to components of the PLL/DLL, such as a charge pump or loop resistor, from an interconnect coupled to the voltage regulator. In an embodiment of the present invention, a component of the PLL/DLL includes a bias-generating device, such as a MOSFET p-type transistor having a drain coupled to the interconnect. In an embodiment of the present invention, a voltage regulator includes an AMP having a bias-generating device, such as a p-type transistor, acting as a current source, having a source coupled to V dd  and a drain coupled to the interconnect. The gate of the bias-generating device is coupled to the gate of four other p-type devices. Each of the four p-type devices has a source coupled to V dd . The drains of the first and second p-type transistors are coupled to an output providing I ld . A negative input of the AMP (“INM”) is coupled to the gate of a first n-type transistor and a positive input of the AMP (“INP”) is coupled to the gate of a second n-type transistor. The drains of the first and second n-type transistors are coupled to the drains of the second and third p-type transistors. The sources of the first and second n-type transistors are coupled to the drain of a third n-type transistor. The source of the third n-type transistor is coupled to ground and the gate is coupled to a fourth n-type transistor. The drain of the fourth n-type transistor is coupled to the drain of the fourth p-type transistor and the source of the fourth n-type transistor is coupled to ground.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Wideband attenuator circuits and methods]]></title>
<link>http://www.freepatentsonline.com/7365617.html</link>
<description><![CDATA[Embodiments of the present invention include wideband attenuator circuits and methods. In one embodiment the present invention includes a first divider circuit coupled in series with two or more second divider circuits. The divider circuits include resistance and capacitance values that may be set according to particular relationships. In one embodiment, a wideband attenuator may include capacitors that are selectively coupled to each output node.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Continuous-time delta-sigma analog digital converter having operational amplifiers]]></title>
<link>http://www.freepatentsonline.com/7365668.html</link>
<description><![CDATA[The invention concerns a continuous-time delta-sigma analog-digital converter for the conversion of an analog input signal into a digital output signal, comprising an analog filter which filters the analog input signal and at least one externally circuited operational amplifier (OPAMP) for the formation of an integrator stage, a clock-driven quantizer, which quantizes the filtered analog signal outputted through the analog filter to generate the digital output signal, and a feedback arrangement with at least one digital-analog converter, which supplies to the analog filter at least one feedback signal on the basis of the digital output signal. For the reduction of the necessary amplification-bandwidth product for the operational amplifier (OPAMP) it is stipulated according to the invention that the operational amplifier (OPAMP) has a first amplifier path (gm 3 ) and parallel to this a second amplifier path (gm 2 , gm 5 ), wherein the transit frequency of the second amplifier path (gm 2 , gm 5 ) is lower than the transit frequency of the first amplifier path (gm 3 ).]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Apparatus and method for charge pump slew rate control]]></title>
<link>http://www.freepatentsonline.com/7365585.html</link>
<description><![CDATA[An apparatus and method for improving memory cell reliability is disclosed. The slew rate is reduced in an applied voltage signal used to program a memory cell when Fowler-Nordheim (FN) tunneling injection is detected. The applied programming signal is provided by a charge pump that is preferably a regulated charge pump. The charge pump is selectively controlled by a slew rate control circuit when FN tunneling injection is detected by a voltage level detection circuit at a predetermined threshold voltage level.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Power supply circuit]]></title>
<link>http://www.freepatentsonline.com/7365592.html</link>
<description><![CDATA[A power supply circuit includes at least one capacitor, a plurality of switching members, a power supply which outputs a plurality of voltages and a selecting section for controlling said plurality of switching sections to periodically select one of said plurality of voltages and apply the selected voltage to one terminal and the other terminal of the capacitor. The selecting section includes a member for applying the selected voltage to one terminal and the other terminal of the capacitor across a resistor, during a current limiting period immediately after the application of the selected one of said plurality of voltages to one terminal and another terminal of the capacitor is started.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Gated clock logic circuit]]></title>
<link>http://www.freepatentsonline.com/7365575.html</link>
<description><![CDATA[A gated clock logic circuit includes a pulse generator and a precharged latch. The pulse generator generates a pulse signal in response to a clock signal, and the precharged latch generates a gated clock signal in response to the clock signal, the pulse signal, and a control signal.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Fast synchronization of a number of digital clocks]]></title>
<link>http://www.freepatentsonline.com/7366937.html</link>
<description><![CDATA[The present invention relates to a method for synchronizing a number of digital clocks to a synchronizing signal, said method comprising generating centrally a reference clock, synthesizing said digital clocks from said reference clock using a clock multiplier, respectively, resetting said clock multiplier in response to said synchronizing signal, and masking an output signal of said clock multiplier during settling time of said clock multiplier.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Gate-coupled EPROM cell for printhead]]></title>
<link>http://www.freepatentsonline.com/7365387.html</link>
<description><![CDATA[An EPROM cell in a printhead control circuit for an inkjet printer, having exactly one polysilicon layer and a conductive layer disposed above the polysilicon layer, includes a control transistor and an EPROM transistor. The control and EPROM transistors each have floating gates comprising a portion of the polysilicon layer, and an electrical interconnection, comprising a portion of the conductive layer, interconnects the floating gate of the control transistor and the floating gate of the EPROM transistor.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[PLL/DLL dual loop data synchronization utilizing a granular FIFO fill level indicator]]></title>
<link>http://www.freepatentsonline.com/7366270.html</link>
<description><![CDATA[A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. In particular, a system and method for dual loop data synchronization using a granular FIFO fill level indicator is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL, which represents a fill level of a FIFO. A granular FIFO fill level indicator of the DLL provides input to the phase shifter to adjust the frequency of the PLL accordingly. Thus, the frequency of the data input rate can be controlled and a constant fill level of the FIFO can be maintained. A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Input buffer for low voltage operation]]></title>
<link>http://www.freepatentsonline.com/7366041.html</link>
<description><![CDATA[An input buffer having differential amplifiers for receiving input signals to generate an output signal. The input buffer operates with a relatively low supply voltage and a relatively wide range of input signal levels while improving the symmetry between rising and falling signal transitions of the output signal.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Multipath input buffer circuits]]></title>
<link>http://www.freepatentsonline.com/7365572.html</link>
<description><![CDATA[Provided is a multi-path input buffer circuit, which passes a signal input to a semiconductor device through different paths in consideration of the voltage level of the input signal. The multi-path input buffer circuit includes an input buffer stage, which can be driven using one of at least two power supply voltages, outputs path signals by passing an input signal through at least two paths, selects and enables one of the path signals in response to a plurality of path selection signals, and maintains the rest of the path signals in a high impedance state. The buffer circuit also includes a level shifter, which shifts the voltage level of a signal output from the input buffer stage via the first path, and a first logic operation circuit, which operates in response to the output signal of the input buffer stage and a signal output from the level shifter.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[System and method for the detection of presence of a signal and its synchronization, for a frequency hopping system working in a disturbed environment]]></title>
<link>http://www.freepatentsonline.com/7366224.html</link>
<description><![CDATA[A method and device are disclosed for the detection and synchronization of a signal in a frequency-hopping system. The method has a step, for each frequency F( 1 ) . . . F(M), of selecting the K samples corresponding to the greatest values of the signal, and their positions. For a given position, the M greatest values are combined which are selected from among K samples on each frequency having the given position. The greatest combined value is kept and the corresponding position. The greatest combined value is compared with a threshold value, and if the greatest combined value is greater than this threshold value, then the detection of the signal is declared.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

<item>
<title><![CDATA[Reset in a system-on-chip circuit]]></title>
<link>http://www.freepatentsonline.com/7366938.html</link>
<description><![CDATA[An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated circuit further including: a soft reset hold circuit clocked in the first clock environment connected to receive the soft reset signal and to generate an output reset signal in an asserted state; and a synchronizer clocked in the second clock environment connected to receive the output reset signal and to generate a retimed reset signal in an asserted state after a predetermined period, wherein the retimed reset signal is fed back to the soft reset hold circuit to cause the output reset signal to adopt a deasserted state at the end of said predetermined period.]]></description>
<pubDate>April 29, 2008</pubDate>
</item>

</channel>
</rss>
