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        <title>Free Patents Online: Error detection/correction and fault detection/recovery</title>
        <link>http://www.freepatentsonline.com./rssfeed/rssapp714.xml</link>
        <description>USPTO Class 714 Error detection/correction and fault detection/recovery</description>
        <language>en-us</language>
        <lastBuildDate>Thu, 17 Dec 2009 08:00:00 EST</lastBuildDate>
        <item>
            <title><![CDATA[Method for Updating Control Program of Physical Storage Device in Storage Virtualization System and Storage Virtualization Controller and System Thereof]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313617.html</link>
            <description><![CDATA[Method for updating control program of physical storage devices including the steps of: selecting PSD(s) to be updated with the control program; making the PSD(s) in an off-line state; and updating the control program of the PSD(s), wherein if it needs to issue a write request to the selected PSD(s) before completion of updating the control program, unmodified data segment(s) corresponding to the write request is marked as modified data segment(s). the selected PSD(s) performs partial rebuilding after completion of updating the control program, and if it needs to read out from or write to an unmodified data segment of the selected PSD(s) before completion of the partial rebuilding, a R/W request can be issued to the PSD directly without waiting for completion of the partial rebuilding of the PSD. Multiple parity data chunks can also be provided in the same data stripe in another embodiment.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[EFFICIENT IN-BAND RELIABILITY WITH SEPARATE CYCLIC REDUNDANCY CODE FRAMES]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313533.html</link>
            <description><![CDATA[Embodiments of the invention are generally directed to systems, methods, and apparatuses for efficient in-band reliability with separate cyclic redundancy code (CRC) frames. In some embodiments, a memory system uses data frames to transfer data between a host and a memory device. The system also uses a separate frame (e.g., a CRC frame) to transfer a CRC checksum that covers the data frames.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD AND SYSTEM FOR DATA REPLICATION]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313532.html</link>
            <description><![CDATA[A method for writing data to a storage pool includes receiving a write operation to write a logical block of data to the storage pool, determining a number (n−1) of physical blocks required to store the logical block of data, generating a parity block using the logical block of data, allocating n physical blocks in the storage pool, writing the parity block in the first of n allocated physical block, and writing the logical block of data across the remaining n−1 allocated physical blocks, where n is less than a number of disks in the storage pool, and where each of the n allocated physical blocks is located on a different disk in the storage pool.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Methods and Apparatus for Processing a Received Signal Using a Multiple-Step Trellis and Selection Signals for Multiple Trellis Paths]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313531.html</link>
            <description><![CDATA[Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle).]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Error correcting viterbi decoder]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313530.html</link>
            <description><![CDATA[Methods and corresponding systems in a Viterbi decoder include computing a maximum likelihood (ML) path in a Viterbi trellis in response to executing a first Viterbi algorithm. Thereafter, one or more merge points are selected on the ML path in a second Viterbi algorithm, wherein the merge points each have a path metric difference, which is a difference between an ML path metric at the merge point and a non-surviving path metric at the merge point. Merge points are selected based upon relative path metric differences associated with nodes on the ML path. Next, alternate paths in the Viterbi trellis are computed based on the ML path with alternate paths substituted at corresponding merge points. A passing decoded bit sequence is output in response to passing an error check, wherein the passing decoded bit sequence is associated with one of the one or more alternate paths.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD AND APPARATUS FOR ERROR MANAGEMENT]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313529.html</link>
            <description><![CDATA[To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and System for Cooperative Communications with Minimal Coordination]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313528.html</link>
            <description><![CDATA[A method and system are provided in a wireless communications system comprising a plurality of nodes (users) working cooperatively. The system provides cooperative diversity by allowing nodes to actively share their antennas and other resources to obtain spatial diversity. The nodes receive the same message (information data) from a common source. Each node enhances the reliability of the message with a modern forward error correction (FEC) code, converts the FEC encoded message into an ensemble of symbols, divides the ensemble of symbols into packets, modulates, dithers and transmits the packets to a receiving node. The dithering process is performed by varying the signal amplitude, phase, frequency and/or symbol timing of the modulated packets. A unique dither pattern is assigned to each node. The receiving node captures a composite signal comprising the transmitted packets of all or most of the transmitting nodes in the cooperative communications system. Because the transmitted packets are dithered independently in phase and/or amplitude, spatial diversity is transformed into temporal diversity.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[METHODS AND SYSTEMS FOR CAPTURING ERROR INFORMATION IN A SATA COMMUNICATION SYSTEM]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313527.html</link>
            <description><![CDATA[Methods and systems for capturing error information regarding a Serial Advanced Technology Attachment (SATA). An initiator device is enhanced in accordance with features and aspects hereof to detect an error condition in operation of the system and to transmit error information to the SATA target device during a soft reset condition applied to the SATA target device. The SATA target device discards all such frames received during the soft reset condition until the initiator device clears the soft reset condition. The error information may be captured for further analysis and debug of the error condition by suitable error analyzer equipment such as a SATA bus analyzer. The initiator device may be a SATA initiator or a Serial Attached SCSI (SAS) initiator using the SATA Tunneling Protocol (STP). Features and aspects hereof may also include a SAS/SATA bridge device coupling a SAS initiator to the SATA target device.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Apparatus and method for merging data blocks with error correction code protection]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313526.html</link>
            <description><![CDATA[An apparatus and method for selectively deriving Error Correction Codes (ECCs) or other data integrity information for integration into merged data blocks. First data is merged into second data that is error-protected using an ECC generated by a coding algorithm. Bytes or other data units are identified in the first data to be merged into the second data. It is determined whether each of the check bits of the ECC will differ from its original state in response to merging the first and second data. The check bits of the ECC that have been determined to differ from their respective original states are modified to create a “merged ECC.” The resulting data block includes the merged data and the merged ECC.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD OF DECODING BY MESSAGE PASSING WITH SCHEDULING DEPENDING ON NEIGHBOURHOOD RELIABILITY]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313525.html</link>
            <description><![CDATA[The invention relates to an iterative method by message passing for decoding of an error correction code that can be displayed in a bipartite graph comprising a plurality of variable nodes and a plurality of check nodes. For each iteration in a plurality of decoding iterations of said method:
 
     variable nodes or check nodes are classified ( 720 ) as a function of the corresponding degrees of reliability of decoding information available in the neighbourhoods (V n (d) ,V m (d) ) of these nodes, a node with a high degree of reliability being classified before a node with a low degree of reliability; each node thus classified ( 725 ) passes at least one message (α mn ,β mn ) to an adjacent node, in the order defined by said classification. 
     
  The invention also relates to a computer program designed to implement said decoding method.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[LOW DENSITY PARITY CODE ENCODING DEVICE AND DECODING DEVICE AND ENCODING AND DECODING METHODS THEREOF]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313524.html</link>
            <description><![CDATA[A low density parity code (LDPC) encoding and decoding devices and encoding and decoding methods thereof are provided. An LDPC encoding device includes an information obtaining unit which obtains status information of at least two frequency bands, a matrix generation unit which generates a parity check matrix based on the status information, the parity check matrix including sub matrices which correspond to the at least two frequency bands, and an encoder which generates data bits and parity bits using an LDPC with the generated parity check matrix.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[ENCODERS AND METHODS FOR ENCODING DIGITAL DATA WITH LOW-DENSITY PARITY CHECK MATRIX]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313523.html</link>
            <description><![CDATA[A method for encoding digital data with a low-density parity check (LDPC) matrix includes: indirectly storing a non-regular portion of the LDPC matrix by storing a plurality of indices corresponding to a plurality of non-zero sub-matrices of the non-regular portion, and by storing a plurality of distance/location parameters respectively corresponding to numbers of zero sub-matrices between adjacent non-zero sub-matrices of the non-regular portion or respectively corresponding to distances between adjacent non-zero sub-matrices of the non-regular portion; generating at least one address according to at least one distance/location parameter; accessing information bits corresponding to the address; and recovering at least one element of the LDPC matrix according to at least one index and the information bits to encode the digital data according to the LDPC matrix.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD AND APPARATUS FOR LOW LATENCY TURBO CODE ENCODING]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313522.html</link>
            <description><![CDATA[A method and apparatus for performing low latency Turbo Code encoding of a frame of data is described. The disclosure includes a method for performing Turbo Code encoding on frame of data using by encoding via subsections using multiple constituent encoders in parallel. The information gains during a first encoding pass of the subsections is used to determine the start state for a second pass during which parity bits are generated. Both the interleaved and natural order encoding may be performed in parallel.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[DATA BUS INVERSION USABLE IN A MEMORY SYSTEM]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313521.html</link>
            <description><![CDATA[Implementations of Data Bus Inversion (DBI) techniques within a memory system are disclosed. In one embodiment, a set of random access memory (RAM) integrated circuits (ICs) is separated from a logic system by a bus. The logic system can contain many of the logic functions traditionally performed on conventional RAM ICs, and accordingly the RAM ICs can be modified to not include such logic functions. The logic system, which can be a logic integrated circuit intervening between the modified RAM ICs and a traditional memory controller, additionally contains DBI encoding and decoding circuitry. In such a system, data is DBI encoded and at least one DBI bit issued when writing to the modified RAM ICs. The RAM ICs in turn store the DBI bit(s) with the encoded data. When the encoded data is read from the modified RAM ICs, it is transmitted across the bus in its encoded state along with the DBI bit(s). The logic integrated circuit then decodes the data using the DBI bit(s) to return it to its original state.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD OF ENCODING/DECODING USING LOW DENSITY CHECK CODE MATRIX]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313520.html</link>
            <description><![CDATA[A method of encoding data using a parity check matrix, a method of decoding encoded data, and a data retransmission method using the same are disclosed. A data retransmission method in a communication system includes transmitting a codeword encoded by a first parity check matrix corresponding to a first coding rate, among at least two parity check matrixes corresponding to different coding rates, receiving NACK from the receiver in response to the codeword, and transmitting parity bits encoded by some of the second parity check matrix corresponding to a second coding rate, among the at least two parity check matrixes, to the receiver.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[REDUCING HARQ RETRANSMISSIONS USING PEAK POWER MANAGEMENT TECHNIQUES]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313519.html</link>
            <description><![CDATA[Systems, methods and apparatuses for reducing HARQ retransmissions using peak power management techniques are presented. In one example, a receiver may perform multi-level error correction for reducing HARQ retransmissions. The receiver may include a Peak to Average Power Ratio Management Module (PAPR MM) decoder configured to perform a first level of error correction utilizing retransmissions originating at a front end of a distal transmitter. The receiver may further include a symbol demapping module connected to the PAPR MM decoder, a deinterleaver connected to the symbol demapping module, and a decoder connected to the deinterleaver and the PAPR MM decoder, where the decoder may be configured to perform a second level of error correction utilizing retransmissions originating at a back end of a distal transmitter. A transmitter for reducing HARQ retransmissions using PAPR techniques is also presented.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD AND APPARATUS FOR HYBRID AUTOMATIC REPEAT REQUEST]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313518.html</link>
            <description><![CDATA[The present invention provides two primary Hybrid Automatic Repeat reQuest (HARQ) mechanisms for a multi-hop network, i.e. an active Mobile Multi-hop Relaying (MMR) HARQ and a passive Mobile Multi-hop Relaying (MMR) HARQ. According to the solution of the present invention, there are provided a method and a device for HARQ retransmission in relay stations of a wireless communication network, wherein in HARQ retransmission, the HARQ procedure is implemented based on resource allocated by a base station; and a method and device for HARQ in a base station, characterized in that a HARQ procedure is implemented in-between one or more relay stations and a mobile station. With the methods of the present invention, the HARQ problems existing in a multi-hop network are overcome, the correction rate of data transmission is improved, while time delay for data transmission is reduced.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[RETRANSMISSION SCHEME FOR COMMUNICATION SYSTEMS]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313517.html</link>
            <description><![CDATA[One embodiment relates to a method of transmitting data from a transmitter to a receiver. In the method, a payload data stream is provided which comprises a plurality of payload data units. A container stream is formed which comprises a plurality of containers having respective container identifiers, where a container includes an integer number of the payload data units and where the container identifiers collectively establish a predetermined order for consecutive containers. A codeword stream is formed which comprises a plurality of codewords having respective redundancy information, where a codeword includes at least a portion of the container and where redundancy information of the codeword facilitates detection of erroneous data in the codeword. The codeword is transmitted from the transmitter to the receiver. Other methods and systems are also disclosed.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[ENHANCED HYBRID AUTOMATIC REPEAT REQUEST FOR LONG TERM EVOLUTION]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313516.html</link>
            <description><![CDATA[A method and an apparatus are provided for receiving a transport block that is segmented into a plurality of code blocks (CBs), each CB having an attached cyclic redundancy check (CRC), decoding each of the plurality of CBs with attached CRC, determining whether each CRC fails, and in response to a determination that a CRC has failed, transmitting a CB index number of the CB attached to the CRC that has failed. Also provided are a method and an apparatus for a transmitter receiving an index number of a CB for retransmission (CBSIRT) attached with a CRC that has failed, determining the CB that correspond to the CRC that has failed based on the CBSIRT, and retransmitting the failed CB in a subsequent transmission time interval (TTI).]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[MINIMIZING SLOT WASTAGE USING OVERLAPPING HARQ REGIONS IN OFDMA WiMAX SYSTEM]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313515.html</link>
            <description><![CDATA[A method and system for minimizing slot wastage by overlapping HARQ regions in a communication system. A control region allocation (CRA) utility defines a group of HARQ regions for transmission of control data. A HARQ region definition includes a starting symbol and a starting sub-channel number for the HARQ region, a number of symbols and a number of sub-channels to define the dimensions of the region and the slot duration for each sub-burst in a sequence of allocated sub-bursts. The CRA utility overlaps one HARQ region with the other to minimize slot wastage. The slots that carry data in one HARQ region overlap un-used slots in another HARQ region or are overlapped with a dummy allocation in the other HARQ region. Since mobile stations do not carry data for the slots with a dummy allocation, the overlap of HARQ regions avoids conflict with the HARQ operation.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Dynamically Reconfigurable Shared Scan-In Test Architecture]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313514.html</link>
            <description><![CDATA[A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR MEMORY DEVICE]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313513.html</link>
            <description><![CDATA[A semiconductor memory device for performing a reliability test includes a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an external circuit into the local I/O line pair during a data access operation in a normal mode, a local I/O line pair coupled to the write driving block for receiving the predetermined test voltage in the test mode, and a cell array having a plurality of unit cells and a plurality of bit line pairs respectively having first and second bit lines and coupled to at least one unit cell for receiving the predetermined test voltage from each local I/O line pair to thereby check a result of the reliability test in the test mode.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[APPARATUS AND METHOD FOR MEMORY CARD TESTING]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313512.html</link>
            <description><![CDATA[The invention provides a memory card testing apparatus for performing automated operations on memory cards. The memory card testing apparatus comprises a host device, a database, a processing unit and an interface. The host device is provided for accessing a memory card. The database maintains a plurality of test script files to be processed. The processing unit is coupled to the database for selecting a test item from one of the plurality of test script files according to a device identification number corresponding to a target device to be tested and a communication protocol associated with the memory card. The interface is connected to the processing unit and the host device for enabling the host device to execute at least one card command on the memory card according to the test item.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE TESTING]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313511.html</link>
            <description><![CDATA[A semiconductor device test circuit includes a data producing unit to produce first test data to be fed into a semiconductor device, and expected value data; a first data retaining unit to retain the first test data, and feed the first test data into the semiconductor device; a second data retaining unit to retain the expected value data; a comparison unit to compare output data outputted through the first data retaining unit and the expected value data outputted from the second data retaining unit to supply data indicating comparison result between the output data and the expected value data; and a switching unit to switch the data fed into the second data retaining unit between the expected value data and the output data, wherein the first data retaining unit and the second data retaining unit form parts of a scan chain into which second test data may externally be fed.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[PORT SELECTOR, DEVICE TESTING SYSTEM AND METHOD USING THE SAME]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313510.html</link>
            <description><![CDATA[A port selector, a device testing system and a method using the same. The port selector includes: a plurality of terminal ports to which a device is respectively coupled; an integration port which is connected to the plurality of terminal ports through a signal transmitting line; a plurality of terminal switches which are disposed to correspond to each terminal port, and open and close the signal transmitting line; and a control unit which independently controls each terminal switch. Thus, the present general inventive concept provides a port selector, a device testing system and a method using the same including a plurality of terminal ports to which devices are respectively coupled, and independently controlling each terminal port, thereby selecting a port.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[CONTROL METHOD FOR INFORMATION STORAGE APPARATUS, INFORMATION STORAGE APPARATUS, PROGRAM AND COMPUTER READABLE INFORMATION RECORDING MEDIUM]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313509.html</link>
            <description><![CDATA[A control method for an information storage apparatus has the steps of: providing redundancy of information stored in the information storage apparatus; a redundancy failure recording part recording a record of a redundancy failure in a state recording part, when the failure has occurred in keeping of the redundant state of the information; a redundancy monitoring part reading the record of the redundancy failure from the state recording part the record; and a reporting part reporting the redundancy failure when the record of the redundancy failure is read by the redundancy monitoring part.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[MONITORING DATA CATEGORIZATION AND MODULE-BASED HEALTH CORRELATIONS]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313508.html</link>
            <description><![CDATA[Architecture for aggregating health alerts from a number of related components into a single aggregated health state that can be analyzed to isolate the component responsible for the fault condition. In a hierarchy of related components within various component groups in a computer system, a number of health indicators can indicate alerts occurring in one or more of the related components whereas the fault condition occurs in only one component upon which the other components depend. The health indicators of related components are aggregated into an aggregated health state for each component group. These aggregated health states are analyzed to identify the related component associated with a root cause of the alert condition for an affected component group.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Generation of trace data in a multi-processor system]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313507.html</link>
            <description><![CDATA[A data processing apparatus is provided having a plurality of processing circuits each having access to a memory. Tracing circuitry is provided for generating a stream of trace data for generating a stream of trace data corresponding to at least one of the plurality of processing circuits. Selection circuitry is provided to enable selective switching of the tracing circuitry from generating a first trace data stream corresponding to a first one of the plurality of processing circuits generating a second different trace data stream corresponding to a different one of the plurality of processing circuits. The selective switching is performed in dependence upon processing state information associating with one or more of the plurality of processing circuits. A corresponding method and computer program product are also provided.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Test Result Aggregation and Analysis Using Text Expressions]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313506.html</link>
            <description><![CDATA[A test and analysis system may use Xpath or other text based analysis descriptors to analyze test results that may be presented in XML. The text based analysis descriptors may be installed and used on an analysis system without exposing the analysis system to security vulnerabilities, and such descriptors may be frequently updated and distributed. A server device may have a test manager that may coordinate tests performed on other devices connected through a local area network, and may gather and store the test results for analysis. In some cases, the test results may be converted to XML for analysis.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[SYSTEM AND METHOD FOR DETECTING COMBINATIONS OF PERFOMANCE INDICATORS ASSOCIATED WITH A ROOT CAUSE]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313505.html</link>
            <description><![CDATA[Methods and system are provided for detecting combinations of performance indicators that are associated with a root cause. The method comprises storing a plurality of error codes, each representative of at least one performance indicator, storing descriptive data associated with each of the plurality of error codes, storing a plurality of root causes, each associated with descriptive data that corresponds to the descriptive data of the plurality of error codes, identifying the error codes from the plurality of error codes that correspond to at least one of the plurality of root causes, and analyzing the error codes that correspond to at least one root cause to determine combinations of performance indicators that are associated with the root cause.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[BIOS TEST SYSTEM AND TEST METHOD THEREOF]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313504.html</link>
            <description><![CDATA[A basic input output system (BIOS) test system includes a protocol conversion module and a computer. The protocol conversion module is connected to a tested device. The computer is connected to the protocol conversion module. The computer controls the protocol conversion module to simulate a keyboard to send keyboard commands to the device. The computer storing correct setting lists and comments of the setting lists of the BIOS. The tested device selects setting lists and comments thereof according to the keyboard selection commands sent by the protocol conversion module. The tested device is connected to the computer to deliver selected setting lists and comments thereof to the computer. The computer compares the selected setting lists and comments thereof with the correct setting lists.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[SYSTEMS AND METHODS OF EVENT DRIVEN RECOVERY MANAGEMENT]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313503.html</link>
            <description><![CDATA[Systems and methods of event driven recovery management are disclosed. In one embodiment, a method of providing event driven recovery management includes continually copying one or more data blocks that are generated from a computing device, associating at least one event marker with the copies of the one or more data blocks, and allowing access to the copies of the one or more data blocks according to the at least one event marker in order to provide event driven recovery. For purposes of this disclosure, an event marker, a book mark, an application consistency point, and/or a business event are interchangeably used, depending on the context.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[DATA TRANSFERRING METHOD AND CONTENT TRANSFERRING METHOD]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313502.html</link>
            <description><![CDATA[A method of transferring data and a method of transferring contents are provided. In the method of transferring data in a data interoperable environment, a secure authenticated channel is established with a receiving entity corresponding to receiver information included in a received control message, when the control message is received from a control entity, a plurality of data designated by the control entity are transmitted to the receiving entity through the established secure authenticated channel, and an event message for representing a transmission status of the transmitted data is transmitted to the control entity,. Accordingly, it is possible to transmit the plurality of data through a single transmission session and provide a transmission status of each data through an event.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD AND ARRANGEMENT FOR PROCESSING TRANSACTIONS IN A FLASH TYPE MEMORY DEVICE]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313501.html</link>
            <description><![CDATA[The invention relates to a method and arrangement for processing transactions in a flash type memory device, wherein the transaction is a data update and/or changing operation consisting of one or more suboperations, all of which must be successfully executed in order to regard the discussed transaction as having been successfully completed in its entirety. In the solution according to the invention, memory-block specific status information ( 131 ) of a memory block present in a flash type memory device is utilized not only for managing payload data ( 141 ) present in the memory block but also for the management of an entire transaction. Consequently, there is no need for a separate status bookkeeping of transactions, thus reducing the number of reading and writing operations required in transactions.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[CONTAINMENT AND RECOVERY OF SOFTWARE EXCEPTIONS IN INTERACTING, REPLICATED-STATE-MACHINE-BASED FAULT-TOLERANT COMPONENTS]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313500.html</link>
            <description><![CDATA[A method, system and article of manufacture are disclosed for error recovery in a replicated state machine. A batch of inputs is input to the machine, and the machine uses a multitude of components for processing those inputs. Also, during this processing, one of said components generates an exception. The method comprises the steps of after the exception, rolling the state machine back to a defined point in the operation of the machine; preemptively failing said one of the components; re-executing the input batch in the state machine; and handling any failure, during the re-executing step, of the one of the components using a defined error handling procedure. The rolling, preemptively failing, re-executing and handling steps are repeated until the input batch runs to completion without generating any exception in any of the components that are not preemptively failed.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[SYSTEM AND METHOD FOR RECONSTRUCTING LOST DATA IN A STORAGE SYSTEM]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313499.html</link>
            <description><![CDATA[A system (and method) for determining reconstruction formulas for partial strip reconstruction in a storage system in which a plurality of lost strips have been detected, includes using a combination of a direct reconstruction method and a sequential reconstruction method.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[CONTROL METHOD AND STORAGE DEVICE]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313498.html</link>
            <description><![CDATA[A control method includes the steps of storing data in a cache; generating parity data corresponding to the data stored in the cache and storing the parity data in a buffer; writing the data stored in the cache and the parity data stored in the buffer into a plurality of the storage units; reading the data and the parity data from the plurality of storage units; checking error over the read out data by using the read out parity data; storing, if an error is detected in the read out data and the read out parity data, data for reading a plurality of data constituting a stripe in each of the plurality of storage units in the buffer, regenerating parity data by using the plurality of data readout from the storage units; and overwriting the plurality of data and the parity data into the plurality of the storage units.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Failover Enabled Telemetry Systems]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313497.html</link>
            <description><![CDATA[The present invention discloses several techniques for providing failover in telemetry systems. The invention allows the continuous and uninterrupted connection between gathering units and a central data collection server, thereby ensuring the proper operation of telemetry systems.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Computer implemented systems and methods for pre-emptive service and improved use of service resources]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313496.html</link>
            <description><![CDATA[Systems and methods are provided for collecting, aggregating, and analyzing data associated with the installation and deployment of systems. Energy systems, ( 500 ) specifically renewable energy generation systems, are used as examples. The aggregated data serve as the basis for a variety of services that improve the system performance, improve the installation, lower the cost, and provide. monitoring and service to maintain optimum performance, Finally, services are provided that facilitate the optimization of responses to poor system performance based on criticality of the failure, servicing of the system by a Certified VAR, or other prioritization method.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[DATA CONFLICT RESOLUTION FOR SOLID-STATE MEMORY DEVICES]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313453.html</link>
            <description><![CDATA[In a particular embodiment, a controller is disclosed that is adapted to control read/write access to a storage media. The controller includes data corruption detection logic to reconstruct a logical block address (LBA) lookup table from metadata stored at the storage media upon restart and re-initialization after a power loss event. The controller further includes duplicate conflict resolution logic to identify a valid data block from multiple data blocks that refer to a single LBA. The duplicate conflict resolution logic counts a first number of valid physical pages and a second number of different sectors in each of the multiple data blocks. The duplicate conflict resolution logic selects the valid data block from the multiple data blocks based on at least one of the first and second numbers.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[METHODS AND SYSTEM FOR SIMPLIFIED SAS ERROR RECOVERY]]></title>
            <link>http://www.freepatentsonline.com./y2009/0313443.html</link>
            <description><![CDATA[Methods and systems for simplified error recovery in a SAS device. A SAS device (e.g., a SAS/SSP target device such as a storage device) enhanced in accordance with features and aspects hereof NAKs a received frame that has an error and then NAKS all subsequently received frames, regardless of whether received with or without error, until the connection is closed. The second SAS device (e.g., a SAS/SSP initiator) then performs required error recovery by re-establishing a connection and re-transmitting all previously NAKed frames. The enhanced SAS thereby simplifies logic for error recovery.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[SYSTEM AND METHOD FOR MONITORING AND CONTROLLING THE OPERATIONAL CONDITION OF A POWER TRANSFORMER]]></title>
            <link>http://www.freepatentsonline.com./y2009/0312880.html</link>
            <description><![CDATA[The present invention refers to a system and method for monitoring and controlling the operational condition of a power transformer. The system for monitoring and controlling the operational condition of a power transformer comprised in a single substation comprising a control a control and data processing station linked to the transformers containing detection devices of the indicative signals of the measurements of operational parameters of the transformer; the signals being continuously detected by said devices; a user interface linked to said control station, the interface allowing a user to follow the measurements of the operational parameters of the transformer and determine ranges of desirable values of said operational parameters, said control station comprises a database that stores the data referring to the indicative signals of the measurements of the operational parameters of the transformer only when the measurements of the operational parameters differ from a range of operational parameter values previously defined as desirable. The method of the present invention comprises the steps of (a) continuously measuring operational parameters of a power transformer; and (b) storing the data referring to the measurements performed in step (a) only when said measurements are not within a range of previously determined as desirable for the measurements of said operational parameters.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[CAPSULE ENDOSCOPE SYSTEM]]></title>
            <link>http://www.freepatentsonline.com./y2009/0312601.html</link>
            <description><![CDATA[A capsule endoscope system includes: a receiving device that receives in-vivo images captured by a capsule endoscope inserted into an organ of a subject; and an image display device that acquires ID information of one or more capsule endoscopes, acquires through the receiving device the in-vivo images captured by the capsule endoscopes identified by the ID information, and displays thereon the in-vivo images thus acquired. The image display device is connected via a communication network to a central server that uniformly manages information about the capsule endoscopes, notifies the central server the ID information of the one or more capsule endoscopes, acquires information about the one or more capsule endoscopes from the central server, and performs a warning process about the one or more capsule endoscopes according to the information thus acquired.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and apparatus for link adaptation in wirless communication network]]></title>
            <link>http://www.freepatentsonline.com./y2009/0310550.html</link>
            <description><![CDATA[A method and apparatus for link adaptation in a wireless communication network is provided. The method includes computing a first channel quality parameter based on one or more channel quality parameters. The one or more channel quality parameters are associated with a communication link between a Mobile Station (MS) and a Base Station (BS). The method further includes determining a qualifying transmission unit to compute a correction parameter. The correction parameter is computed based on the first channel quality parameter and one or more transmission parameters. The one or more transmission parameter is associated with the communication link. Thereafter, the method schedules a transmission mode of the communication link based on a second channel quality parameter. The second channel quality parameter is estimated based the first channel quality parameter and the correction parameter.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[APPARATUS AND METHOD FOR CHANNEL ERROR CONTROL OF NON-EXCLUSIVE MULTIPLEXING FOR CONTROL CHANNELS]]></title>
            <link>http://www.freepatentsonline.com./y2009/0310536.html</link>
            <description><![CDATA[An apparatus and method for non-exclusive multiplexing of at least one active control channel comprising preparing the at least one active control channel for transmission in a next frame using a transmitter data processor; assessing channel robustness of the at least one active control channel based on a channel robustness threshold; and if the channel robustness threshold is not met, performing constellation control or power control on the at least one active control channel which is active prior to transmitting the at least one active control channel; or if the channel robustness threshold is met, transmitting the at least one active control channel using a transmitter.]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[COMMUNICATION UNIT, COMMUNICATION SYSTEM, COMMUNICATION METHOD AND COMMUNICATION PROGRAM]]></title>
            <link>http://www.freepatentsonline.com./y2009/0310493.html</link>
            <description><![CDATA[A transmission-time measurement section ( 201 ) and a jitter measurement section ( 202 ) measure transmission time length and jitter, respectively, by using the packets transmitted/received. A forward-error-correction (FEC)-scheme maximum-jitter measurement section ( 203 ) calculates a maximum jitter in the case of adopting an FEC scheme, and an automatic-retransmission-request (ARQ)-scheme maximum-jitter measurement section ( 204 ) calculates a maximum jitter in the case of adopting an ARQ scheme from the measured information. A packet control section ( 205 ) selects a communication scheme having a smaller maximum jitter from both schemes based on the calculation result of the FEC-maximum-jitter measurement section ( 203 ) and ARQ-maximum-jitter measurement section ( 204 ).]]></description>
            <pubDate>Thu, 17 Dec 2009 08:00:00 EST</pubDate>
        </item>
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