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        <title>Free Patents Online: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)</title>
        <link>http://www.freepatentsonline.com./rssfeed/rssapp712.xml</link>
        <description>USPTO Class 712 Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)</description>
        <language>en-us</language>
        <lastBuildDate>Thu, 31 Dec 2009 08:00:00 EST</lastBuildDate>
        <item>
            <title><![CDATA[Systems, Methods, and Program Products For Secure Code Execution]]></title>
            <link>http://www.freepatentsonline.com./y2009/0328232.html</link>
            <description><![CDATA[Methods, program product, and systems for providing tamper-resistant executable software code are provided to enable software code transport, storage, and execution security by formatting all instructions to use operand indirect addressing, resulting in an indirect table for each operand position, or field, in the instruction set. That is, rather than each instruction including an operand, each instruction includes an index to the location of the value of the operand in an indirect table. The methods, program product, and systems can also implement a non-typical instruction fetch associated with a program counter and a sequentially stored vector table, or jump table, to retrieve the next sequential instruction (“NSI”). Following rearranging or scrambling or encoding of the executable code, the code can be loaded and executed directly in scrambled form using the jump table, but cannot be meaningfully disassembled, nor executed properly, without the jump table to resolve the NSI.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Systems And Methods For Regulating Execution Of Computer Software]]></title>
            <link>http://www.freepatentsonline.com./y2009/0328003.html</link>
            <description><![CDATA[A method for regulating execution of an application program includes a process for preparing the application and a process for executing the application. The preparation process divides the application program into related segments and encrypts instructions of at least one segment. The preparation process positions encrypted instructions in at least two discontiguous regions within an executable file and associates header information with at least one discontiguous region. The header identifies a decryption key and the location of the other discontiguous region. The resulting execution file thus has portions that would not execute and would cause an operating system to call a responsive process. The execution process initiates execution of the protected application when at least a portion of the application instructions are available to the computer only in encrypted form. The user is authenticated, after which the encrypted portions can be decrypted and execution resumed. The processes may also include capability to detect and respond to tampering, or the ability to block execution snooping via a debugger. Also provided are systems and methods to allow debugging of code extensions to protected applications without sacrificing protection of the application. A Secure Debugger allows extension developers to examine memory and set breakpoints in their own extensions, without permitting them to view information in the rest of the protected application.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Methods and apparatus for analyzing SIMD code]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327937.html</link>
            <description><![CDATA[A method for analyzing and presenting in a graphical manner single instruction, multiple data (SIMD) instructions involves disassembling a stream of machine instructions into a stream of assembly language instructions. Instruction objects “M” and “N” are created to represent SIMD instructions “M” and “N” from the stream of instructions. Instruction objects “M” and “N” include multiple data objects corresponding to the multiple data items of the respective SIMD instruction. Different colors are assigned to at least two of the multiple data objects of instruction object “M.” If a data item of SIMD instruction “N” is based on a data item of SIMD instruction “M,” the color from the source object is automatically assigned to the target object. Dependencies between data items of instruction “M” and “N” are annotated by arrows between corresponding data objects. Other embodiments are described and claimed.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[NETWORK TASK OFFLOAD APPARATUS AND METHOD THEREOF]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327693.html</link>
            <description><![CDATA[A network task offload apparatus includes an offload circuit and a buffer scheduler. The offload circuit performs corresponding network task processing on a plurality of packets in parallel according to an offload command. The buffer scheduler includes a buffer control unit and a plurality of buffer units. The plurality of buffer units are controlled by the buffer control unit and are scheduled to store the processed packets.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Loop Control System and Method]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327674.html</link>
            <description><![CDATA[Loop control systems and methods are disclosed. In a particular embodiment, a hardware loop control logic circuit includes a detection unit to detect an end of loop indicator of a program loop. The hardware loop control logic circuit also includes a decrement unit to decrement a loop count and to decrement a predicate trigger counter. The hardware loop control logic circuit further includes a comparison unit to compare the predicate trigger counter to a reference to determine when to set a predicate value.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[ESTIMATOR, TABLE MANAGING DEVICE, SELECTING DEVICE, TABLE MANAGING METHOD, PROGRAM FOR ALLOWING COMPUTER TO EXECUTE THE TABLE MANAGING METHOD, AND RECORDING MEDIUM WHERE THE PROGRAM IS RECORDED]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327673.html</link>
            <description><![CDATA[An estimator suitable for hot-path detection conducted while managing the history of the executed instructions is provided. A hot-path estimator ( 1 ) comprises a table in which branch instruction specifying information for specifying a branch instruction, the branch destination address of each executed branch instruction, the number of branches, and execution frequency information are treated as one entry and each piece of branch instruction specifying information corresponds to a predetermined number of entries, a history managing section ( 11 ) for selecting one of the processings of adding a new entry to the table, replacing one of the entries of the table, and not storing the information on the executed branch instructions in the table if the information on the executed branch instructions is not stored in the table, and a hot-path qualifying section ( 7 ) for outputting the instruction path searched for by a hot-path searching section ( 13 ) according to the table to the outside if the instruction path has been not detected.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[SECURED PROCESSING UNIT]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327672.html</link>
            <description><![CDATA[A method for executing by a processing unit a program stored in a memory, includes: detecting a piece of information during the execution of the program by the processing unit, and if the information is detected, triggering the execution of a hidden subprogram by the processing unit. The method may be applied to the securization of an integrated circuit.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Processor resource management]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327671.html</link>
            <description><![CDATA[Processor resource management devices and methods are disclosed. In some implementations, a device includes a processor, a hardware resource, and a resource manager operable to compare a first execution of one or more instructions pursuant to an optimistic resource management policy and a second execution of one or more instructions pursuant to a pessimistic resource management policy, the optimistic resource management policy assuming that less than an optimistic level of at least one error will occur during the first execution, and the pessimistic resource management policy assuming that greater than a pessimistic level of the at least one error will occur during the second execution. Based at least partially on the comparison, the resource manager selects a resource management policy from between the optimistic and pessimistic resource management policies, and associates the selected resource management policy with the one or more instructions.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[VARIABLE LENGTH STAGES IN A PIPELINE]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327670.html</link>
            <description><![CDATA[A circuit having a pipeline and a configuration circuit. The pipeline generally has multiple stages linked in series by registers. The registers may be governed by a clock signal having a first frequency in a first mode and a second frequency in a second mode. The second frequency may be slower than the first frequency. Each stage may have a respective one of multiple first latencies each shorter than a first period of the first frequency. The configuration circuit may be disposed in the pipeline. The configuration circuit generally bypassing selectively a particular register while in the second mode to form a combined stage. The combined stage may (i) comprise a first of the stages adjoining the particular register and a second of the stages adjoining the particular register and (ii) have a second latency shorter than a second period of the second frequency.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[INFORMATION PROCESSING APPARATUS, PROGRAM EXECUTION METHOD, AND STORAGE MEDIUM]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327669.html</link>
            <description><![CDATA[According to one embodiment, an information processing apparatus comprises a storage storing program modules and parallel execution control description describing relationships of the program modules, a conversion module extracting a part relating to the program module from the parallel execution control description, and creating graph data structure creation information including preceding and succeeding information of the program module, an adding module extracting graph data structure creation information to which the input data is given, creating a node, and adding the created node to a formerly created graph data structure, and an execution module subjecting the graph data structure to at least one of depth-first search and breadth-first search with a restricted breadth, selecting one node from nodes stored in the node memory, and executing a program module corresponding to the selected node.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Multi-Threaded Processes For Opening And Saving Documents]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327668.html</link>
            <description><![CDATA[Tools and techniques are described for multi-threaded processing for opening and saving documents. These tools may provide load processes for reading documents from storage devices, and for loading the documents into applications. These tools may spawn a load process thread for executing a given load process on a first processing unit, and an application thread may execute a given application on a second processing unit. A first pipeline may be created for executing the load process thread, with the first pipeline performing tasks associated with loading the document into the application. A second pipeline may be created for executing the application process thread, with the second pipeline performing tasks associated with operating on the documents. The tasks in the first pipeline are configured to pass tokens as input to the tasks in the second pipeline.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[System and Method to Perform Fast Rotation Operations]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327667.html</link>
            <description><![CDATA[Systems and methods to perform fast rotation operations are disclosed. In a particular embodiment, a method includes executing a single instruction. The method includes receiving first data indicating a first coordinate and a second coordinate, receiving a first control value that indicates a first rotation value selected from a set of ninety degree multiples, and writing output data corresponding to the first data rotated by the first rotation value.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD AND SYSTEM FOR HARDWARE-BASED SECURITY OF OBJECT REFERENCES]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327666.html</link>
            <description><![CDATA[A method for managing data, including obtaining a first instruction for moving a first data item from a first source to a first destination, determining a data type of the first data item, determining a data type supported by the first destination, comparing the data type of the first data item with the data type supported by the first destination to test a validity of the first instruction, and moving the first data item from the first source to the first destination based on the validity of the first instruction.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Efficient parallel floating point exception handling in a processor]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327665.html</link>
            <description><![CDATA[Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Arithmetic processing apparatus]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327664.html</link>
            <description><![CDATA[An arithmetic processing apparatus includes an operation circuit group that performs encryption and a redundant operation circuit group configured the same as the operation circuit group. The arithmetic processing apparatus, while performing encryption, performs normal encryption in the operation circuit group, and performs an encryption mask processing program by using data and the like randomly generated by a random data generating unit and the like in the redundant operation circuit group. The arithmetic processing apparatus, when not performing encryption, performs normal arithmetic processing in the redundant operation circuit group.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Power Aware Retirement]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327663.html</link>
            <description><![CDATA[In one embodiment, the present invention includes a retirement unit to receive and retire executed instructions. The retirement unit may include a first array to receive information at allocation and a second array to receive information after execution. The retirement unit may further include logic to calculate an event associated with an executed instruction if information associated with the executed instruction is stored in an on-demand portion of at least one of arrays. Other embodiments are described and claimed.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Managing active thread dependencies in graphics processing]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327662.html</link>
            <description><![CDATA[A scoreboard for a video processor may keep track of only dispatched threads which have not yet completed execution. A first thread may itself snoop for execution of a second thread that must be executed before the first thread's execution. Thread execution may be freely reordered, subject only to the rule that a second thread, whose execution is dependent on execution of a first thread, can only be executed after the first thread.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[MECHANISMS TO HANDLE FREE PHYSICAL REGISTER IDENTIFIERS FOR SMT OUT-OF-ORDER PROCESSORS]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327661.html</link>
            <description><![CDATA[Methods and apparatus relating to mechanisms to handle free physical register identifiers for SMT (Simultaneous Multi-Threading) out-of-order processors are described. In some embodiments, a physical register file stores both speculative data and architectural data corresponding to a plurality of registers. A free list logic may maintain free physical register identifiers corresponding to the plurality of registers. An instruction may read the architectural data from the physical register file at dispatch. Other embodiments are also described and claimed.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[MEMORY THROUGHPUT INCREASE VIA FINE GRANULARITY OF PRECHARGE MANAGEMENT]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327660.html</link>
            <description><![CDATA[Methods and apparatus to improve throughput in memory devices are described. In one embodiment, memory throughput is increased via fine granularity of precharge management. In an embodiment, three separate precharge timings may be used, e.g., optimized per memory bank, per memory bank group, and/or per a memory device. Other embodiments are also disclosed and claimed.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[TRAP-BASED MECHANISM FOR TRACKING MEMORY ACCESSES]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327659.html</link>
            <description><![CDATA[In general, the invention relates to a method. The method includes receiving notification, which includes context information, of a trap. The method further includes accessing, based at least partially upon the context information, a particular instruction that caused the trap, determining, based at least partially upon the context information, a particular address that is to be accessed by the particular instruction, updating a set of log information to indicate accessing of the particular address, causing subsequent accesses of the particular address to not give rise to a trap, after causing subsequent accesses of the particular address to not give rise to a trap, accessing the particular address, after accessing the particular address, causing subsequent accesses of the particular address to give rise to a trap, and causing the particular instruction to not be executed.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[COMPARE, SWAP AND STORE FACILITY WITH NO EXTERNAL SERIALIZATION]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327658.html</link>
            <description><![CDATA[A compare, swap and store facility is provided that does not require external serialization. A compare and swap operation is performed using an interlocked update operation. If the comparison indicates equality, a store operation is performed. The compare, swap and store operations are performed as a single unit of operation.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[GENERATING AND PERFORMING DEPENDENCY CONTROLLED FLOW COMPRISING MULTIPLE MICRO-OPERATIONS (uops)]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327657.html</link>
            <description><![CDATA[A processor to perform an out-of-order (OOO) processing in which a reservation station (RS) may generate and process a dependency controlled flow comprising multiple micro-operations (uops) with specific clock based dispatch scheme. The RS may either combine two or more uops into a single RS entry or make a direct connection between two or more RS entries. The RS may allow more than two source values to be associated with a single RS by combining sources from the two or more uops. One or more execution units may be provisioned to perform the function defined by the uops. The execution units may receive more than two sources at a given time point and produce two or more results on different ports.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[EFFICIENCY-BASED DETERMINATION OF OPERATIONAL CHARACTERISTICS]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327656.html</link>
            <description><![CDATA[Techniques are disclosed involving techniques that may dynamically adjust processor (e.g., CPU) performance. For instance, an apparatus includes a counter, an efficiency determination module, and a management module. The counter determines a number of event occurrences, wherein each of the event occurrences involves a processor component (e.g., a processor core) awaiting a response from a device. The efficiency determination module determines an efficiency metric based on the number of event occurrences. The management module establishes one or more operational characteristics for the processor component that correspond to the efficiency metric. Other embodiments are described and claimed.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE AND DATA PROCESSING METHOD PERFORMED BY SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327655.html</link>
            <description><![CDATA[The semiconductor device includes a controller and a plurality of dynamically reconfigurable circuits connected to one another in series below the controller to perform operations in the manner of a pipeline. The controller inputs data and reconfiguration information to the first one of the dynamically reconfigurable circuits. Each of the dynamically reconfigurable circuits includes a processing unit that performs a data computation, an updating unit that updates the reconfiguration information, and a repetition controlling unit that determines whether to repeat the computation and controls the data and the reconfiguration information.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method of Handling Duplicate or Invalid Node Controller IDs in a Distributed Service Processor Environment]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327654.html</link>
            <description><![CDATA[A method for enabling a Node Controller (NC), which claims a duplicate or invalid service processor Node Controller Identification (NCID) in a distributed service processor system, to be integrated into the system includes reading an NCID by the NC after the NC is booted, saving the NCID into a non-volatile storage and broadcasting an NC Present Message (NPM) to a Service Processor (SC) repeatedly until the SC initiates communication, updating the NCID for the NC in the non-volatile storage when the NC receives an NCID change message from the SC and rating any future NPM as a new NCID, and checking a record of an new NC in the non-volatile storage when the SC receives the NPM from the NC. If the SC has a record of a recorded NC with the same NCID as the new NC, then the SC checks its role as a primary SC. If the SC does not have the record of the recorded NC with the same NCID as the new NC, then the SC checks validity of the NCID.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[RECONFIGURABLE COMPUTING CIRCUIT]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327653.html</link>
            <description><![CDATA[A reconfigurable computing circuit for reducing amount of dummy data to be stored in data registers, which is required when the wiring is shared by the configuration information bus and scan chain. When data is to be stored in data registers and configuration registers constituting the scan chain in reconfig computing block  2010 , reg setting data selecting unit  3400  selects either a value stored in reg setting data storage unit  3000  or an initial value output from data reg data generating unit  4000 , based on the information stored in reg type managing unit  1100  that indicates the types of registers and the connection order of the registers in the scan chain, and outputs the selected value in sequence to the scan chain under control of scan/reconfig control unit  1000 . Each register in the scan chain then shifts data stored therein to the next register in the scan chain in sequence.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD FOR CONSTRUCTING A VARIABLE BITWIDTH VIDEO PROCESSOR]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327652.html</link>
            <description><![CDATA[A method for designing a video processor with a variable and programmable bitwidth parameter. The method comprises selecting logical operations having propagation delay that scales linearly with the bitwidth; determining a desired tradeoff curve; and grouping instances of a logic operation having same properties; for a single instance of each logic operation, matching an actual curve of the logic operation to the desired tradeoff curve, wherein the actual curve is determined by the propagation delay and bitwidth of the logic operation.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Information Handling System Including A Multiple Compute Element Processor With Distributed Data On-Ramp Data-Off Ramp Topology]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327651.html</link>
            <description><![CDATA[A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The processor distributes data on-ramps and data off-ramps across the data lanes of a data trunk of the primary interconnect trunk to enable communication with compute elements and other structures both on-chip and off-chip.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and System for Conducting Intensive Multitask and Multiflow Calculation in Real-Time]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327610.html</link>
            <description><![CDATA[The system for conducting intensive multitask and multistream calculation in real time comprises a central processor core (SPP) for supporting the system software and comprising a control unit (ESCU) for assigning threads of an application, the non-critical threads being run by the central processor core (SPP), whereas the intensive or specialized threads are assigned to an auxiliary processing part (APP) comprising a set of N auxiliary calculation units (APU 0 , . . . , APUN- 1 ) that are optimized for fast processing of certain operations, a memory space (SMS) shared by the auxiliary calculation units (APU 0 , . . . , APUN- 1 ) via an internal network and a unit (ACU) for controlling and assigning the auxiliary resources. The various elements of the system are arranged in such a manner that communication between the various auxiliary calculation units (APU 0 , . . . , APUN- 1 ) or between those auxiliary calculation units (APU 0 , . . . , APUN- 1 ) and the central processor core (SPP) is effected via the shared memory space (SMS) and the internal network.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD FOR IMPLEMENTING A BIT-REVERSED INCREMENT IN A DATA PROCESSING SYSTEM]]></title>
            <link>http://www.freepatentsonline.com./y2009/0327332.html</link>
            <description><![CDATA[In a data processing system, a first instruction is received at an input of a processor. A specifier indicates both a first portion of a value and a second portion of the value. The first portion of the value is identified to be modified by the processor and the second portion of the value is identified to remain unchanged. The first instruction is decoded, and in response the processor modifies the first portion of the value by performing a bit-reversed increment to form a modified first portion. The modified first portion is combined with the second portion of the value which remained unchanged to form a first address. The first address is stored in first storage circuitry. A second instruction is decoded and in response the processor accesses data located at the first address which is assigned to a second storage circuit.]]></description>
            <pubDate>Thu, 31 Dec 2009 08:00:00 EST</pubDate>
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