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<title>freepatentsonline.com</title>
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<title>freepatentsonline.com: Electrical computers and digital data processing systems: input/output</title>
<link>http://www.freepatentsonline.com/result.html?query_txt=ccl/710%20and%20isd/04/24/2008&amp;usapp=on</link>
<description>USPTO Class 710 Electrical computers and digital data processing systems: input/output</description>
<language>en-us</language>
<lastBuildDate>Wed Apr 30 17:03:31 EDT 2008</lastBuildDate>

<item>
<title><![CDATA[Protocol adapter for passing diagnostic messages between vehicle networks and a host computer]]></title>
<link>http://www.freepatentsonline.com/20080098137.html</link>
<description><![CDATA[A protocol adapter for transferring diagnostic messages between networks within a vehicle and a host computer. The protocol adapter operates as a voltage translator to support J1708 software. The protocol adapter also recognizes when the protocol adapter is connected to a host computer running the J1939 and/or J1708 protocols and automatically switches to that protocol.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Bridge and Transmitting Apparatus, and Information System]]></title>
<link>http://www.freepatentsonline.com/20080098141.html</link>
<description><![CDATA[A bridge is provided with a first portal connected to a first communication line forming one part of a network for transmitting/receiving information via the first communication line, and a second portal connected with a second communication line forming the other part of the network for transmitting/receiving information via the second communication line. These first and second portals can transfer information received, to each other. When one of the first and second portals receives, in case a connection has already been established on the network including that bridge, environment updating information for updating the using environment of the connection, via one of the first and second communication lines, one of the first and second portals transfers the environment updating information received, to the other. The other of the first and second portals updates the using environment of the other of the first and second communication lines in accordance with the environment updating information transferred.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Bi-Directional Wired Interface]]></title>
<link>http://www.freepatentsonline.com/20080098133.html</link>
<description><![CDATA[A wired interface for communicating between a first part and a second part of a device including a line for controlling activation of the second part of the device by a signal from the first part of the device, two lines for transfer of data from the first part of the device to the second part of the device, two lines for transfer of data from the second part of the device to the first part of the device, two lines for the transfer of an indication signal from the second part of the device to the first part of the device regarding the validity of the data transferred by two lines from the second part of the device, and five lines for transferring control signals between the two parts.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[SYSTEMS AND METHODS FOR ALLOWING MULTIPLE DEVICES TO SHARE THE SAME SERIAL LINES]]></title>
<link>http://www.freepatentsonline.com/20080098144.html</link>
<description><![CDATA[Methods and systems for allowing multiple devices to share the same serial lines (e.g., SDIO, SEN and SCLK) are provided. Such devices can be located, e.g., on an optical pick-up unit. Each device includes a serial interface, a device enable number (DEN) that differs from the DEN of each other device, and a plurality of registers, with at least one register being designated a device select register (DSR). The DSRs of the plurality of devices share a common address. The plurality of serial interfaces are collectively enabled and collectively disabled (e.g., via the SEN line). However, only one of the plurality of serial interfaces can be selected at one time, with the remaining of the plurality of serial interfaces being deselected. The serial interface of a device is selected when the DEN of the device is the same as the content of the DSR of the device, and deselected when the DEN of the device is not the same as the content of the DSR of the device.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Peripheral Unit for an Automation Device]]></title>
<link>http://www.freepatentsonline.com/20080098136.html</link>
<description><![CDATA[There is described a periphery unit for an automatic device, which can be actuated as an analog input and as an analog output. A number of connections which are to be used as inputs and the number of connections which are to be used as outputs can be adapted in a flexible manner on the respective application from a predetermined number of connections of the periphery unit. As a result, a redundant automatic device wherein said types of periphery units can be used, is provided.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[SHARING OF HOST BUS ADAPTER CONTEXT]]></title>
<link>http://www.freepatentsonline.com/20080098148.html</link>
<description><![CDATA[A system comprises a first host bus adapter (HBA) that uses a first context to facilitate the transmission of packets through a logical connection through the first HBA. The system also comprises a second HBA and memory in which the first context is stored. The memory is accessible by both of the first and second HBAs. Upon receiving a packet associated with the logical connection, the second HBA accesses the memory to use the first context to process the packet in accordance with the first context.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Bus repeater]]></title>
<link>http://www.freepatentsonline.com/20080098147.html</link>
<description><![CDATA[A bus repeater lying within a demodulation IC performs a bus repeat operation after a repeat operation has been made effective, and terminates the repeat operation on an autonomous basis when a stop condition for each serial data is detected. During the repeater operation, control on the direction of data transfer of a master-side IIC bus and control on the direction of data transfer of a tuner-side IIC bus corresponding to a repeat destination are performed by a master-side IIC bus transaction while they are being synchronized with each other. Therefore, the CPU-side IIC bus and the tuner-side IIC bus seem to be through-connected as the flow of the serial data. Further, data transfer can be done only when the swapping of the data with the tuner side is needed.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[ACCESS CONTROL DEVICE AND ACCESS CONTROL METHOD]]></title>
<link>http://www.freepatentsonline.com/20080098140.html</link>
<description><![CDATA[An access control device controls access to a first device and a second device. The first device is connected with a first bus conforming to a first standard and conforms to the first standard. The second device is connected with the first bus and conforms to a second standard. The access control device includes a first signal generator and a second signal generator. The first signal generator generates a first transaction start signal indicating start of a transaction for the first device. The second signal generator generates a second transaction start signal for the second device based on the first transaction start signal.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Apparatus Using A Time Division Multiple Access Bus For Providing Multiple Levels Of Security In A Communications System]]></title>
<link>http://www.freepatentsonline.com/20080098143.html</link>
<description><![CDATA[Systems including both distributed and centralized architectures for providing multiple levels of security using “virtual” switches. Ports and channels are assigned the same time slots on a TDMA bus only when they have matching security levels.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[FENCING OF RESOURCES ALLOCATED TO NON-COOPERATIVE CLIENT COMPUTERS]]></title>
<link>http://www.freepatentsonline.com/20080098135.html</link>
<description><![CDATA[Techniques are provided for processing an Input/Output (I/O) request. At least one data block is allocated for use in completing the I/O request. A current operations record is stored for the I/O request. It is determined whether the I/O request has been completed within a specified period of time. In response to determining that the I/O request has not been completed within the specified period of time, the allocated at least one data block is fenced.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[HIGH SPEED DATA TRANSMISSION SYSTEM AND METHOD]]></title>
<link>http://www.freepatentsonline.com/20080098139.html</link>
<description><![CDATA[A high speed transmission system comprises a host controller with a host logic unit and a device controller with a device logic unit. The host controller transmits and receives a digital signal through the first interface according to the first descriptor in a memory. The device controller transmits and receives the digital signal through the second interface according to the second descriptor in the memory.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Interrupt hooking method for a computing apparatus]]></title>
<link>http://www.freepatentsonline.com/20080098146.html</link>
<description><![CDATA[An interrupt hooking method for a computing apparatus, which includes a processing device and an interrupt controller, includes the steps of: enabling the processing device to convert a hardware interrupt request (IRQ) number of a system control interrupt (SCI) into a predefined interrupt vector according to an operating mode of the interrupt controller; and enabling the processing device to modify a pointer in an interrupt descriptor table that corresponds to the predefined interrupt vector for directing to a corresponding interrupt handler of the application program. A computing apparatus, which includes the processing device that performs the interrupt hooking method, is also disclosed.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Sliced Crossbar Architecture With No Inter-Slice Communication]]></title>
<link>http://www.freepatentsonline.com/20080098151.html</link>
<description><![CDATA[A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory transaction and a first portion of a second memory transaction. Each of the plurality of inputs ports also includes an arbiter coupled to the queue and adapted to independently select either the first portion of the first memory transaction or the first portion of the second memory transaction based on a priority associated with the first portion of the first memory transaction and the first portion of the second memory transaction and a multiplexer coupled to the arbiter.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Playback device and computer program]]></title>
<link>http://www.freepatentsonline.com/20080098131.html</link>
<description><![CDATA[A playback device includes: a USB interface; an information creation section for creating, based on operation in an operation section, information indicating playback sequence for files stored in an external storage device connected to the USB interface; a storage section for storing the created information into the external storage device connected to the USB interface; and a playback section for, based on information stored in an external storage device connected to the USB interface and indicating the playback sequence for the files stored in the external storage device, sequentially playing back the files.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[METHOD FOR FORMING ROUTE MAP IN WIRELESS 1394 BRIDGE NETWORK]]></title>
<link>http://www.freepatentsonline.com/20080098150.html</link>
<description><![CDATA[Provided is a method for forming a route map in a wireless 1394 bridge network. The method for forming a route map in a wireless 1394 bridge network, including the steps of: a) storing route map information; b) collecting changed bus information when a new network is formed according to addition/removal of a bridge; c) checking whether a quantity of the collected bus information exceeds a threshold; d) forming a route map having all bus information when the quantity of the collected bus information exceeds a threshold; and e) forming a route map having changed bus information when collected bus information does not exceed the threshold.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Portable Storage Device and Method For Exchanging Data]]></title>
<link>http://www.freepatentsonline.com/20080098134.html</link>
<description><![CDATA[A portable storage device (MC) is disclosed, which comprises a memory (MEM) for storing data (DAT), a data interface (INT) for exchanging data (DAT) between the memory (MEM) and a host device (DEV), radio communication interface (RI) designed for receiving a key (K) from a transponder (T), checking means (COMP) for checking if a key (K) has a predefined value (V, and access inhibit means (SW) for controlling access to the memory (MEM), wherein the access inhibit means (SW) are controlled by the checking means (COMP). Access to the memory (MEM) is only granted if a certain key (K) can be received, which means that a certain transponder (T) has to be in the vicinity of the portable storage device (MC) for granting access. Furthermore, data (DAT) which is transferred from host device (DEV) to memory (MEM) can be encrypted and data (DAT) which is transferred from memory (MEM) to host device (DEV) can be decrypted. In this way for example commonly used memory cards can be secured against unauthorized use.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[KEY DEVICE WITH EXTERNAL STORAGE AND THE USING METHOD THEREOF]]></title>
<link>http://www.freepatentsonline.com/20080098138.html</link>
<description><![CDATA[The present invention provides a key device with external storage and the using method thereof, which is an invention in computer security technology field. In order to solve the problem of the inconvenient using method that the prior art could not deal with, this invention provides a key device with external storage. It consists of a micro-controller unit and an off-chip mass storage. The micro-controller unit comprises a host interface module, a CPU, a key data storage module, a firmware program storage module and an off-chip mass storage interface module. The present invention provides a using method of the key device with external storage as well, which including: the key device builds connection with the host and reports itself as amass storage device; the host starts the application program; and the user uses and manages the information. The usability of the key device is improved by adding off-chip mass storage in the key device, which makes the user use and manage the files in the key device easily as well.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method and Apparatus of Arranging Priority Queue and Arbitrating for Memory Access Requests]]></title>
<link>http://www.freepatentsonline.com/20080098145.html</link>
<description><![CDATA[A method and an apparatus of memory access request priority queue arbitration comprises sorting the requests into plurality of different priority levels firstly. The priority queues of different priority levels are arranged respectively according to the following steps: counting the cycles and latencies of each access request; counting the total cycles; comparing the latencies of each access request and total cycles respectively, if the total cycles is larger than the latency of a request, then arranging one more the same request in the priority queue, else executing the priority queue in order.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[MEMORY CARD HAVING MEMORY DEVICE AND HOST APPARATUS ACCESSING MEMORY CARD]]></title>
<link>http://www.freepatentsonline.com/20080098142.html</link>
<description><![CDATA[A memory card includes a clock I/O circuit, a data I/O circuit, a delay element, and an adjustment value holding circuit. The clock input/output circuit receives a first clock from a host apparatus. The data I/O circuit receives a second clock from the host apparatus in a write timing adjustment mode. The data I/O circuit transmits and receives data to and from the host apparatus in a data transfer mode. In the write timing adjustment mode, the delay element adjusts a phase of the second clock in accordance with the first clock so as to receive the data received in the data transfer mode in response to the first clock. The adjustment value holding circuit holds an adjustment value for the phase of the second clock adjusted. In the data transfer mode, the delay element adjusts a phase of the data in accordance with the adjustment value.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[SIGNAL HISTORY CONTROLLED SLEW-RATE TRANSMISSION METHOD AND BUS INTERFACE TRANSMITTER]]></title>
<link>http://www.freepatentsonline.com/20080098149.html</link>
<description><![CDATA[A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis in conformity with the history of the transmitted signal. The pre-emphasis circuit may be implemented by a pair of current sources supplying the output of the transmitter, and having differing current values. The current sources are controlled such that upon a signal value change, a high slew rate is provided and when the signal value does not change for two consecutive signal periods, the slew rate is reduced. A current source having a controlled magnitude may be employed to provide a slew rate that changes over time and is continuously reduced until another transmission value change occurs.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Content Consumption Control Method]]></title>
<link>http://www.freepatentsonline.com/20080098474.html</link>
<description><![CDATA[When a process (interrupt process) causing no problem in the content copyright management but to be executed with a higher priority than a content reproduction such as a telephone call or alarm display is started or ended during a content reproduction/execution, process judgment means ( 308 ) reports it to control means ( 305 ). The control means ( 305 ) outputs a reproduction interrupt instruction for temporarily stopping the use time measurement and interrupting the content reproduction to reproduction/execution means ( 304 ) and outputs a reproduction resume instruction for resuming the use time measurement and resuming the content reproduction to the reproduction/execution means ( 304 ) in accordance with the end report of process judgment means ( 308 ).]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[COMPUTER HAVING AUXILIARY DISPLAY APPARATUS]]></title>
<link>http://www.freepatentsonline.com/20080098247.html</link>
<description><![CDATA[A computer includes a main body having a housing part, a main display unit connected to the main body which displays images, and an auxiliary display apparatus having an auxiliary display unit which displays additional images, wherein the auxiliary display apparatus is insertable into the housing part.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method and set of instructions for the dosed supply of printing instructions to a printer, and system for practicing the method]]></title>
<link>http://www.freepatentsonline.com/20080098132.html</link>
<description><![CDATA[In the printing and finishing of sheet-like objects, printing instructions are outputted to a printer. In accordance therewith, sheet-like objects are printed by the printer and are subsequently delivered by the printer directly to the finishing apparatus and then finished by the finishing apparatus. Output data concerning the printing instructions sent to the printer which are at least indicative of the printer capacity required for the printer to process the printing instructions outputted to the printer are registered. Sheet-like objects displaced by the printer are detected and signaled by the detector. At least periodically, production data in accordance with the signals received from the detector are generated. These data are at least indicative of a production quantity realized by the printer in response to the printing instructions sent to the printer. Depending on the production data, the output of next ones of the printing instructions to the printer is dosed.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[EMBEDDED SYSTEM AND INTERFACE APPARATUS THEREOF AND METHOD OF UPDATING DATA FOR NON-VOLATILE MEMORY]]></title>
<link>http://www.freepatentsonline.com/20080098162.html</link>
<description><![CDATA[An interface apparatus and a method of updating data for non-volatile memory are provided. The interface apparatus of the present invention is suitable for an embedded system having a universal-serial-bus (USB) interface and a non-volatile memory. The interface apparatus employs a command translator to directly translate the specific form command commanded by an external device, so that, the interface apparatus may well directly initialize and read/write data from/to the non-volatile memory of the embedded system, without being processed by the microprocessor inside the embedded system.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

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