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        <title>Free Patents Online: Electrical computers and digital data processing systems: input/output</title>
        <link>http://www.freepatentsonline.com./rssfeed/rssapp710.xml</link>
        <description>USPTO Class 710 Electrical computers and digital data processing systems: input/output</description>
        <language>en-us</language>
        <lastBuildDate>Thu, 24 Dec 2009 08:00:00 EST</lastBuildDate>
        <item>
            <title><![CDATA[SYSTEM AND METHOD FOR ACHIEVING HIGH PERFORMANCE DATA FLOW AMONG USER SPACE PROCESSES IN STORAGE SYSTEM]]></title>
            <link>http://www.freepatentsonline.com./y2009/0320042.html</link>
            <description><![CDATA[Fault isolation capabilities made available by user space can be provided for a embedded network storage system without sacrificing efficiency. By giving user space processes direct access to specific devices (e.g., network interface cards and storage adapters), processes in a user space can initiate Input/Output requests without issuing system calls (and entering kernel mode). The multiple user spaces processes can initiate requests serviced by a user space device driver by sharing a read-only address space that maps the entire physical memory one-to-one. In addition, a user space process can initiate communication with another user space process by use of transmit and receive queues similar to transmit and receiver queues used by hardware devices. And, a mechanism of ensuring that virtual addresses that work in one address space reference the same physical page in another address space is used.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[RECEIVING APPARATUS AND ACTIVATION CONTROL METHOD FOR RECEIVING APPARATUS]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319810.html</link>
            <description><![CDATA[A receiving apparatus does not frequently activate a host processor in a sleep mode, so that it is possible to reduce a time overhead when the host processor transitions from a sleep mode to a running mode, also suppress power consumed in the overhead time and improve communication performance. With this apparatus, a communication interface circuit ( 101 ) extracts packet data from a signal received from a network. A communication interface control circuit ( 102 ) decides whether or not packet data is packet data that must be received, and, when the packet data is packet data that must be received, issues an interrupt signal. A power supply circuit ( 106 ) supplies power. When receiving the interrupt signal, the host processor ( 107 ) executes a program including reception processing.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[MEMORY SYSTEM, ACCESS CONTROL METHOD THEREFOR, AND COMPUTER PROGRAM]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319730.html</link>
            <description><![CDATA[A memory system includes: a memory that has plural banks; a memory controller that includes a request queue and a bank monitor and controls access to the memory; a master group including plural masters that can request access to the memory; and a system bus which is connected between the memory controller and the master group and in which an arbiter is arranged, wherein the request queue has a scheduling function for receiving access requests issued from the master group through the system bus and appropriately rearranging the received access requests and provides the arbiter with queue information, the bank monitor monitors information concerning respective banks of the memory and provides the arbiter with the bank information, and the arbiter arbitrates requests issued in parallel from the masters of the master group on the basis of the queue information and the bank information provided thereto and transmits the information to the memory controller as access control information.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Methods, Systems and Computer Program Products for Detection of Frequent Improper Removals of and Changing Writing Policies to Prevent Data Loss in Memory Sticks]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319725.html</link>
            <description><![CDATA[Methods, system and computer program products for detection of frequent improper removals of and changing writing policies to prevent data loss in memory sticks. Exemplary embodiments include a method including detecting insertions of the memory stick, detecting removals of the memory stick, tracking a number of times the memory stick has been docked when removed, tracking a number of times the memory stick has been undocked when removed, determining a removal ratio of times the memory has been removed when docked to the number of times the memory stick has been removed when undocked, comparing the removal ratio to a predetermined threshold, caching writes and directory updates, and committing the writes and directory updates to the memory stick when the removal ratio is below the predetermined threshold and, flushing all writes and updates to the memory stick when in the removal ratio is equal to or above the predetermined threshold.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEMS AND ASSOCIATED METHODS]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319717.html</link>
            <description><![CDATA[A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[MEMORY SYSTEM AND BUS SWITCH]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319716.html</link>
            <description><![CDATA[A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Storage Router and Method for Providing Virtual Local Storage]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319715.html</link>
            <description><![CDATA[A storage router ( 56 ) and storage network ( 50 ) provide virtual local storage on remote SCSI storage devices ( 60, 62, 64 ) to Fibre Channel devices. A plurality of Fibre Channel devices, such as workstations ( 58 ), are connected to a Fibre Channel transport medium ( 52 ), and a plurality of SCSI storage devices ( 60, 62, 64 ) are connected to a SCSI bus transport medium ( 54 ) The storage router ( 56 ) interfaces between the Fibre Channel transport medium ( 52 ) and the SCSI bus transport medium ( 54 ). The storage router ( 56 ) maps between the workstations ( 58 ) and the SCSI storage devices ( 60, 62, 64 ) and implements access controls for storage space on the SCSI storage devices ( 60, 62, 64 ). The storage router ( 56 ) then allows access from the workstations ( 58 ) to the SCSI storage devices ( 60, 62, 64 ) using native low level, block protocol in accordance with the mapping and the access controls.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[SYSTEM AND METHOD FOR TRANSMITTING DATA PACKETS IN A COMPUTER SYSTEM HAVING A MEMORY HUB ARCHITECTURE]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319714.html</link>
            <description><![CDATA[A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus. The system further includes a breakpoint logic circuit coupled to the bypass multiplexer and configured to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. The system further includes a local memory coupled to the core logic circuit and operable to receive and send the data packets to the core logic circuit.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[EXPANSION CARD FOR EXTERNAL STORAGE DEVICE]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319713.html</link>
            <description><![CDATA[An expansion card for an external storage device includes a circuit board, and an input power jack, an output power jack, a voltage transforming unit, an input data transmission interface and an output data transmission interface are located on the circuit board. The circuit board includes a plate-like mounting portion which fits into a bus slot of a motherboard such that the expansion card is positioned but not electrically connected to a motherboard bus. During operation, the expansion card receives power from a power supply via the input power jack, transforms the power via the voltage transforming unit, and transmits the power to the external storage device via the output power jack. In addition, the expansion card receives data from a storage device data transmission interface of the motherboard via an input data transmission interface, and transmits the data to the external storage device via an output data transmission interface.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[REDUCING CORE WAKE-UP LATENCY IN A COMPUTER SYSTEM]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319712.html</link>
            <description><![CDATA[A power control unit (PCU) may reduce the core wake-up latency in a computer system by concurrently waking-up the remaining cores after the first core is woken-up. The power control unit may detect arrival of a first, second, and a third interrupt directed at a first, second, and a third core. The power control unit may check whether the second interrupt occurs within a first period, wherein the first period is counted after waking-up of the first core is complete. The power control unit may then wake-up the second and the third core concurrently if the second interrupt occurs within the first period after the wake-up activity of the first core is complete. The first period may at least equal twice the time required for a first credit to be returned and next credit to be accepted.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[SYSTEM AND METHOD FOR PROVISIONING A REMOTE LIBRARY FOR AN ELECTRONIC DEVICE]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319711.html</link>
            <description><![CDATA[The disclosure provides a system and method of provisioning a resource to an electronic device. The method comprises: after a triggering event, receiving from a network a data transmission at the device, the data transmission containing access information relating to a resource in a library that is in a remote server from the device, the resource relating to an application operating on the device; extracting the access information from the data transmission at the device; presenting the access information for the resource in a graphical user interface (GUI) on a display of the device; and after a selection event is initiated on the device for the resource, initiating a second data transmission containing a copy of the resource to the device and integrating the resource into the application as an output generated by the application.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[DEVICE AND METHOD FOR LOCKING TOUCH SCREEN]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319710.html</link>
            <description><![CDATA[An electronic device includes a central processing unit (CPU), a touch screen, a locking module, and a locking button. The locking module is configured for storing a locking program. When the touch screen is forced into an unlocked status, operation of the locking button is capable of causing the CPU to instruct the locking module to activate the locking program to lock the touch screen.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[CIRCUIT, METHOD AND ARRANGEMENT FOR IMPLEMENTING  SIMPLE AND RELIABLE DISTRIBUTED ARBITRATION ON A BUS]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319709.html</link>
            <description><![CDATA[An arbitrator circuit for accessing a bus comprises a logic gate arrangement ( 406 ), one input of which is coupled to a first bus line. The circuit comprises a switching arrangement ( 404, 405, 407 ). As a response to a control signal the switching arrangement disconnects a first half ( 402 ) of the first bus line from a second half ( 403 ), and couples the second half ( 403 ) to a first fixed potential. A second bus line ( 401 ) is decoupled from the logic gate arrangement ( 406 ), which is coupled to receive a second fixed potential. The second bus line is coupled to the first fixed potential. Two sources are available for providing the control signal to the switching arrangement ( 404, 405, 407 ). One of them is the output of the logic gate arrangement ( 406 ).]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[ELECTRONIC SYSTEM AND RELATED METHOD WITH TIME-SHARING BUS]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319708.html</link>
            <description><![CDATA[An electronic system with time-sharing bus includes a controller, a storage element, a first electronic element, and a shared bus. The controller receives a command to generate a set of enable signals and a set of operation signals. The storage element has a first set of input ends coupled to the controller for receiving a first enable signal of the set of enable signals. The first electronic element has a first input end coupled to the controller for receiving a second enable signal of the set of enable signals. The shared bus is coupled between the controller and the storage element, and is coupled between the controller and the first electronic element. The shared bus provides the set of operation signals to the storage element while the first electronic element is disabled and provides the set of operation signals to the first electronic element while the storage element is disabled.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Control of master/slave communication within an integrated circuit]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319707.html</link>
            <description><![CDATA[An integrated circuit  2  includes a transaction master  4  connected via interconnect circuitry  10  to a transaction slave  12.  The transaction slave  12  generates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction master  4,  then the transaction master  4  generates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[TRANSMITTING PARALLEL DATA VIA HIGH-SPEED SERIAL INTERCONNECTION]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319706.html</link>
            <description><![CDATA[Synchronized pseudo-random number outputs are produced at a transmitter and a receiver of a high-speed serial interconnection. At the transmitter, using logic XOR operations, each data word of parallel data is selectively scrambled with one of the pseudo-random numbers and transmitted via a high-speed serial interface. The receiver de-scrambles the received serial data stream and restores the parallel data.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[COMMUNICATION BETWEEN PROCESSOR CORE PARTITIONS]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319705.html</link>
            <description><![CDATA[In an embodiment, a method is provided that may include providing a first address space exclusively and coherently accessible by a first processor core partition in a platform. A second address space may be provided in this embodiment that is exclusively and coherently accessible by a second processor core partition in the platform. Also in this embodiment, a third address space in the platform may be provided that is accessible, at least in part, by both the first and second processor core partitions and may be to permit communication between the first and second processor core partitions of at least one packet and at least one descriptor associated with the at least one packet. The at least one descriptor may indicate, at least in part, one or more locations in the third address space to store, at least in part, the at least one packet. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[System and Method for Creating a Scalable Monolithic Packet Processing Engine]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319704.html</link>
            <description><![CDATA[A novel and efficient method is described that creates a monolithic high capacity Packet Engine (PE) by connecting N lower capacity Packet Engines (PEs) via a novel Chip-to-Chip (C2C) interface. The C2C interface is used to perform functions, such as memory bit slicing and to communicate shared information, and enqueue/dequeue operations between individual PEs.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[STACKED SEMICONDUCTOR MEMORY DEVICE WITH COMPOUND READ BUFFER]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319703.html</link>
            <description><![CDATA[A stacked memory apparatus operating with a compound read buffer is disclosed. The stacked memory apparatus includes an interface device having a main buffer and a plurality of memory devices each having a device read buffer. Systems incorporating one or more stacked memory apparatuses and related method of performing a read operation are also disclosed.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[STORAGE SYSTEM, STORAGE APPARATUS, AND METHOD FOR HOT SWAPPING OF FIRMWARE]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319702.html</link>
            <description><![CDATA[A storage system includes a host and a storage apparatus. The host having multiple paths connecting with the storage apparatus transfers path identification information received from the storage apparatus, to the storage apparatus via all paths other than a path through which the path identification information has been transmitted. The storage apparatus includes a table for storing the path identification information transmitted to the host and path tables for storing the path identification information received from the host. When the storage apparatus receives a request for replacing the firmware, it determines whether the path tables are matched by comparing the path tables with each other. If the path tables are matched, the storage apparatus sequentially replaces the firmware corresponding to the multiple paths in a hot swapping manner.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Simple Flow Control Protocol Over RDMA]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319701.html</link>
            <description><![CDATA[A method and system for directing data transfers between applications residing on different computers or devices using a simplified flow control protocol. The protocol eliminates the need for and use of flow control modes and supports all possible data transfer mechanisms. The protocol also allows source and sink applications to independently set their own local memory threshold over which data transfers are made using remote direct memory access (RDMA) or zero-copy transfers. Through adjusting its threshold value or size, a sink or receiving application or component adapts its behavior to the behavior of a sending or source application or component.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[USING DEVICE STATUS INFORMATION TO TAKEOVER CONTROL OF DEVICES ASSIGNED TO A NODE]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319700.html</link>
            <description><![CDATA[Provided are a method, system, and article of manufacture for using device status information to takeover control of devices assigned to a node. A first processing unit communicates with a second processing unit. The first processing unit uses a first device accessible to both the first and second processing units and the second processing unit uses a second device accessible to both the first and second processing units. The first processing unit receives status on the second device from the first device indicating whether the second device is available or unavailable. The first processing unit detects a failure of the second processing unit and determines from the received status on the second device whether the first device is available in response to detecting the failure of the second processing unit. The first processing unit configures the second device for use by the first processing unit in response to determining that the received status on the second device indicates that the second device is available and in response to detecting the failure.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Preventing Loss of Access to a Storage System During a Concurrent Code Load]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319699.html</link>
            <description><![CDATA[Illustrative embodiments provide a computer implemented method for minimizing loss of access to a storage system during a concurrent controller code load in a redundant dual controller subsystem. The computer implemented method receives a request for a controller code load, verifies all required hosts are connected with the second controller to form a first verification, and responsive to the first verification indicating that all required hosts are connected with the second controller, varies a first controller offline. The controller code load is performed in the first controller, and the first controller is varied back online. The computer implemented method performs a verification that all required hosts are connected with the first controller to form a second verification, and responsive to the second verification indicating that all required hosts are connected with the first controller, varies the second controller offline, and performs the controller code load in the second controller.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319698.html</link>
            <description><![CDATA[An information processing system has a power supply section which detects a predetermined potential applied to a USB terminal and supplying the potential as a source potential, an information detection section which detects the predetermined information supplied to the USB terminal, and a processing section which executes, subsequent to the detection of the predetermined potential, the encryption process or the decryption process in accordance with at least the operating information supplied from the operation key arranged on the body and in accordance with the predetermined information supplied to the USB terminal after detection of the predetermined information. The recording and reproducing operation can be performed with the operating key on the body with power supplied only from the USB terminal.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Computer System and Method for Indicating a Display Output Device Thereof]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319697.html</link>
            <description><![CDATA[A computer system and a method for indicating a display output device thereof are disclosed. The method for indicating a display output device comprises the following steps: detecting whether the computer system has a display function or not; if yes, selecting the display output device according to the setting of a BIOS; and signaling for indication to notify a user by using an indicator.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD AND APPARATUS FOR CONFIGURING AND CONTROLLING CLIENT DEVICE]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319696.html</link>
            <description><![CDATA[Provided is a method of allowing a host apparatus such as a personal computer (PC) to control a client apparatus such as a printer by using a virtual storage device and a virtual folder. In the method, if a mode of the client apparatus is set as a virtual storage device, the client apparatus is connected to the host apparatus via a network. Then, when the host apparatus recognizes the client apparatus as a virtual storage device, a file received in a virtual folder by a user performing an operation of copying the file into the virtual folder is processed by performing a function linked to the virtual folder. Accordingly, it is possible to use the client apparatus by easily connecting it to the host apparatus.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and architecture to support interaction between a host computer and remote devices]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319695.html</link>
            <description><![CDATA[A method and architecture for enabling interaction between a remote device and a host computer. A service provided by the remote device is discovered, and a description pertaining to the service is retrieved by the host computer. A network communication link is the established between the remote device and the host computer based on connection information provided by the description. Host-side and client-side software service modules are run on the host and remote devices to enable interaction between the devices using a service protocol that is specific to the service. Various service protocols are provided, including a display service protocol and an input service protocol. Using commands provided by each protocol, the host computer is enabled to control the service remotely by pushing data and appropriate commands to the remote device, whereupon these commands are processed by the client-side service module to perform service operations that employ the sent data.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[ASSOCIATION OF AN INPUT AND OUTPUT OF A PERIPHERAL DEVICE IN A COMPUTING SYSTEM]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319694.html</link>
            <description><![CDATA[A method on a computing system for associating an output of a coupled peripheral device to an input of the peripheral device is provided. The method comprises receiving a descriptor configuration input from the coupled peripheral device describing attributes of the peripheral device and an association between the input of the peripheral device and the output of the peripheral device; providing peripheral device classes of associated input attributes including associated output attributes of the peripheral device; and informing an instantiated application of attributes of the peripheral device through classes. In another implementation, the method comprises providing an interface set comprising associated input attributes and output attributes of a peripheral device; using an input logical layer to access attributes of an interface set for an input of the peripheral device including associated output attributes of the peripheral device; selecting an attribute associated with the input; and setting the selected attribute of the peripheral device. In yet another implementation, a computing system configured to be coupled to a peripheral device comprising an input and an associated output is provided. The computing system comprises an input logical layer configured to receive descriptor configuration information from the peripheral device and build interface sets including attributes of the input of the peripheral device and the associated output. The input logical layer uses the interface sets to select and set attributes of the output of the peripheral device.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD AND APPARATUS FOR INTERFACING HOST DEVICE AND SLAVE DEVICE]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319693.html</link>
            <description><![CDATA[Provided is a method and an apparatus for interfacing between a host device and a slave device using a simple script. The method of interfacing a slave device communicably linked to a host device includes detecting whether a connection event with the host device is generated; storing current state information in a script file that is recognized by the host device if the connection event with the host device is generated; and transmitting the stored script information to the host device.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[EXPOSING MULTI-MODE AUDIO DEVICE AS A SINGLE COHERENT AUDIO DEVICE]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319692.html</link>
            <description><![CDATA[The driving of an audio device that supports two or more audio modes is accomplished by associating a first physical device object of an audio device with a first device identifier, the first physical device object representing a first audio mode enumerated by a bus enumerator; associating a second physical device object of an audio device with a second device identifier, the second physical device object representing a second audio mode enumerated by the bus enumerator; and if the first device identifier matches the second device identifier, enabling a coupled kernel streaming audio interface compatible with both the first physical device object and the second physical device object.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[COMPUTING SYSTEM AND METHOD OF CHANGING I/O CONFIGURATION THEREOF]]></title>
            <link>http://www.freepatentsonline.com./y2009/0319604.html</link>
            <description><![CDATA[A computing system includes: first and second I/O interfaces that are associated with a server; and an I/O management unit that connects the server with the first and second I/O interfaces. The I/O management unit includes: an I/O buffer; an I/O mapping unit that stores an access request of the server to the first I/O interface in the I/O buffer in response to a change start request of the first I/O interface associated with the server to the second I/O interface; an I/O changing unit that associates the second I/O interface with the server; and an I/O synchronizing unit that converts the access request stored in the I/O buffer into an access request to the second I/O interface, in response to the completion of the association by the I/O changing unit, and executes the converted access request.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
        </item>
        <item>
            <title><![CDATA[HARDWARE ACCELERATION FOR WWAN TECHNOLOGIES]]></title>
            <link>http://www.freepatentsonline.com./y2009/0316904.html</link>
            <description><![CDATA[Systems and methods for wireless communications are provided. These include data deciphering components, interrupt processing components, adaptive aggregations methods, optimized data path processing, buffer pool processing, application processing where data is formatted in a suitable format for a destination process, and Keystream bank processing among other hardware acceleration features. Such systems and methods are provided to simplify logic designs and mitigate processing steps during wireless network data processing.]]></description>
            <pubDate>Thu, 24 Dec 2009 08:00:00 EST</pubDate>
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