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        <title>Free Patents Online: Active solid-state devices (e.g., transistors, solid-state diodes)</title>
        <link>http://www.freepatentsonline.com/rssfeed/rssapp257.xml</link>
        <description>USPTO Class 257 Active solid-state devices (e.g., transistors, solid-state diodes)</description>
        <language>en-us</language>
        <lastBuildDate>Thu, 13 Jun 2013 08:00:00 EDT</lastBuildDate>
        <item>
            <title><![CDATA[CHEMICAL VAPOR DEPOSITION FILM PROFILE UNIFORMITY CONTROL]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149871.html</link>
            <description><![CDATA[The present disclosure provides for methods and systems for controlling profile uniformity of a chemical vapor deposition (CVD) film. A method includes depositing a first layer on a substrate by CVD with a first shower head, the first layer having a first profile, and depositing a second layer over the first layer by CVD with a second shower head, the second layer having a second profile. The combined first layer and second layer have a third profile, and the first profile, the second profile, and the third profile are different from one another.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SUBSTRATE CARRIER AND APPLICATIONS THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149870.html</link>
            <description><![CDATA[A substrate carrier for performing a deposition process comprises a supporting element and a cover element. The supporting element having a through hole is used to carry a substrate. The cover element is removably engaged with the supporting element, so as to secure the substrate therebetween and expose a deposition surface of the substrate from the through hole.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SILICON ON INSULATOR ETCH]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149869.html</link>
            <description><![CDATA[A method etching features through a stack of a silicon nitride layer over a silicon layer over a silicon oxide layer in a plasma processing chamber is provided. The silicon nitride layer is etched in the plasma processing chamber, comprising; flowing a silicon nitride etch gas; forming the silicon nitride etch gas into a plasma to etch the silicon nitride layer, and stopping the flow of the silicon nitride etch gas. The silicon layer is, comprising flowing a silicon etch gas, wherein the silicon etch gas comprises SF6 or SiF4, forming the silicon etch gas into a, and stopping the flow of the silicon etch gas. The silicon oxide layer is etched in the plasma processing chamber, comprising flowing a silicon oxide etch gas, forming the silicon oxide etch gas into a plasma, and stopping the flow of the silicon oxide etch gas.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Masking Method and Apparatus]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149868.html</link>
            <description><![CDATA[A chamber for combinatorially processing a substrate is provided. The chamber includes a first mask and a second mask that share a common central axis. The first mask and the second mask are independently rotatable around the common central axis. The first mask has a first plurality of radial apertures and the second mask has a second plurality of radial apertures. An axis of the first plurality of radial apertures is offset from an axis of the second plurality of radial apertures. A substrate support that is operable to support a substrate below the first and second masks is included. The substrate support shares the common central axis.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[BAFFLE PLATE FOR SEMICONDUCTOR PROCESSING APPARATUS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149866.html</link>
            <description><![CDATA[A baffle plate for redirecting a reactive gas flow within a process chamber of a semiconductor plasma processing apparatus includes a topside surface having a plurality of topside apertures for receiving the reactive gas flow and a bottomside surface having a plurality of bottomside apertures for emitting the reactive gas flow toward a semiconductor substrate. An outer portion of the baffle plate includes both topside apertures and bottomside apertures, while within an inner portion of the baffle plate for at least one of the topside surface and bottomside surface is a solid region throughout exclusive of any apertures. The inner portion has an outer dimension that is at least ten (10) percent of an outer dimension of the outer portion.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD FOR FABRICATING SEMICONDUCTOR DEVICE BY DAMASCENE PROCESS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149863.html</link>
            <description><![CDATA[A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the isolation patterns, and forming plugs filled in the contact holes.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD FOR FORMING A SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149852.html</link>
            <description><![CDATA[A method for forming a semiconductor device includes providing in a process chamber a metal-containing gate electrode film on a substrate, flowing a process gas consisting of hydrogen (H2) and optionally a noble gas into the process chamber, forming plasma excited species from the process gas by a microwave plasma source, and exposing the metal-containing gate electrode film to the plasma excited species to form a modified metal-containing gate electrode film having a lower work function than the metal-containing gate electrode film. Other embodiments describe forming semiconductor devices with gate stacks containing modified metal-containing gate electrodes for NMOS and PMOS transistors.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Methods of Protecting Elevated Polysilicon Structures During Etching Processes]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149851.html</link>
            <description><![CDATA[Disclosed herein are various methods of protecting elevated polysilicon structures during etching processes. In one example, the method includes forming a layer stack above a semiconducting substrate for a memory device, forming a protective mask layer above the layer stack of the memory device and performing at least one etching process to define a gate electrode for a transistor while the protective mask is in position above the layer stack for the memory device.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149850.html</link>
            <description><![CDATA[A method for manufacturing a semiconductor device includes the steps of preparing a substrate made of silicon carbide and having an n type region formed to include a main surface, forming a p type region in a region including the main surface, forming an oxide film on the main surface across the n type region and the p type region, by heating the substrate having the p type region formed therein at a temperature of 1250° C. or more, removing the oxide film to expose at least a part of the main surface, and forming a Schottky electrode in contact with the main surface that has been exposed by removing the oxide film.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD FOR MANUFACTURING VERTICAL-CHANNEL TUNNELING TRANSISTOR]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149848.html</link>
            <description><![CDATA[The present invention belongs to the technical field of semiconductors and specifically relates to a method for manufacturing a vertical-channel tunneling transistor. In the present invention, the surrounding gate gate structure improves the control capacity of the gate and the source of narrow band gap material can enhance the device driving current. The method for manufacturing a vertical-channel tunneling transistor put forward by the present invention capable of controlling the channel length precisely features simple process, easy control and reduction of production cost.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD OF GROWING ZINC OXIDE NANOWIRE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149844.html</link>
            <description><![CDATA[Methods of growing a zinc oxide nanowire are provided. According to the method, developing a photoresist layer and etching a zinc oxide seed layer may be successively performed using a tetramethyl ammonium hydroxide aqueous solution. Thus, change of solutions may not be required, such that the number of processes may be reduced.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[In-situ Gettering Method for Removing Metal Impurities from the Surface and Interior of a Upgraded Metallurgical Grade Silicon Wafer]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149843.html</link>
            <description><![CDATA[An in-situ gettering method for removing impurities from the surface and interior of a upgraded metallurgical grade silicon wafer is continuously conducted in a reaction chamber. Chloride gas is mixed with carrier gas. The gaseous mixture is used to clean the surface of the silicon wafer. Then, the gaseous mixture is used to form a porous structure on the surface of the silicon wafer before hot annealing is executed. Finally, the gaseous mixture is used to execute hot etching on the surface of the silicon wafer and remove the porous structure from the surface of the silicon wafer. As the chloride gas is used to clean the surface of the silicon wafer and form the porous structure on the surface of the silicon wafer, external gettering is improved. Moreover, interstitial-type metal impurities are effectively removed from the interior of the silicon wafer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[WAFER DICING EMPLOYING EDGE REGION UNDERFILL REMOVAL]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149841.html</link>
            <description><![CDATA[In one embodiment, a dielectric material layer embedding metal structures is ablated from the chip-containing substrate by laser grooving, which is performed on dicing channels of the chip-containing substrate. Subsequently, an underfill layer is formed over the dielectric material layer in a pattern that excludes the peripheral areas of the chip-containing substrate. The physically exposed dicing channels at the periphery can be employed to align a blade to dice the chip-containing substrate. In another embodiment, an underfill layer is formed prior to any laser grooving. Mechanical cutting of the underfill layer from above dicing channels is followed by laser ablation of the dicing channels and subsequent mechanical cutting to dice a chip-containing substrate.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[APPARATUS FOR BONDING SUBSTRATES TO EACH OTHER]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149839.html</link>
            <description><![CDATA[An apparatus for bonding at least two substrates to each other comprises a plurality of substrate bonding machines arranged adjacent to one another and an input transporter extending adjacent to the plurality of substrate bonding machines which is operative to deliver the substrates to each of the substrate bonding machines. The input transporter is supplied with substrates by an onloading station. An output transporter extending adjacent to the plurality of substrate bonding machines is operative to receive bonded substrates from each of the substrate bonding machines and deliver the bonded substrates to an offloading station for removal from the apparatus.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHODS OF FORMING FIELD EFFECT TRANSISTORS HAVING SILICON-GERMANIUM SOURCE/DRAIN REGIONS THEREIN]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149830.html</link>
            <description><![CDATA[Methods of forming field effect transistors include selectively etching source and drain region trenches into a semiconductor region using a gate electrode as an etching mask. An epitaxial growth process is performed to fill the source and drain region trenches. Silicon germanium (SiGe) source and drain regions may be formed using an epitaxial growth process. During this growth process, the bottoms and sidewalls of the trenches may be used as “seeds” for the silicon germanium growth. An epitaxial growth step may then be performed to define silicon capping layers on the SiGe source and drain regions.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD FOR MANUFACTURING A TUNNELING FIELD EFFECT TRANSISTOR WITH A U-SHAPED CHANNEL]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149824.html</link>
            <description><![CDATA[The present invention belongs to the technical field of semiconductor device manufacturing and specifically relates to a method for manufacturing a tunneling field effect transistor with a U-shaped channel. The U-shaped channel can effectively extend the transistor channel length, restrain the generation of leakage current in the transistor, and decrease the chip power consumption. The method for manufacturing a tunneling field effect transistor with a U-shaped channel put forward in the present invention is capable of realizing an extremely narrow U-shaped channel, overcoming the alignment deviation introduced by photoetching, and improving the chip integration degree.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD FOR FABRICATING SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149822.html</link>
            <description><![CDATA[A method for fabricating a semiconductor device is provided. A method for fabricating a semiconductor device includes providing a semiconductor substrate having a first conductive type. An epitaxy layer having the first conductive type is formed on the semiconductor substrate. First trenches are formed in the epitaxy layer. First insulating liner layers are formed on sidewalls and bottoms of the first trenches. A first dopant having the first conductive type dopes the epitaxy layer from the sidewalls of the first trenches to form first doped regions. A first insulating material is filled into the first trenches. Second trenches are formed in the epitaxy layer. Second insulating liner layers are formed on sidewalls and bottoms of the second trenches. A second dopant having a second conductive type dopes the epitaxy layer from the sidewalls of the second trenches to form second doped regions.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149820.html</link>
            <description><![CDATA[A method for manufacturing a semiconductor device includes providing a substrate having a first transistor device and a second transistor device formed thereon; forming a patterned stress film covering the second transistor device and exposing the first transistor device on the substrate; performing a pre-amorphous implantation (PAI) process to form an amorphous layer respectively at two sides of the first transistor device, and removing the patterned stress film.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[FABRICATING METHODS OF SEMICONDUCTOR DEVICES AND PICK-UP APPARATUSES OF SEMICONDUCTOR DEVICES THEREIN]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149817.html</link>
            <description><![CDATA[A fabricating method of a semiconductor device may include forming a semiconductor die on a supporting wafer, and picking up the die from the wafer by attaching to the die a transfer unit, the transfer unit including a head unit configured to enable twisting movement, and performing the twisting movement. A fabricating method of a semiconductor device may include forming a first semiconductor device on a supporting wafer; and picking up the first semiconductor device from the wafer, moving the first semiconductor device onto a second semiconductor device, and bonding the first semiconductor device to the second semiconductor device while maintaining the first semiconductor device oriented so that a surface faces upwardly. A fabricating method of a semiconductor device may include forming a first semiconductor device on a supporting wafer, attaching to the first semiconductor device a transfer unit configured to enable twisting movement, and performing the twisting movement.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Backside Illuminated CMOS Image Sensor]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149807.html</link>
            <description><![CDATA[A backside illuminated CMOS image sensor comprises a photo active region formed over a substrate using a front side ion implantation process and an extended photo active region formed adjacent to the photo active region, wherein the extended photo active region is formed by using a backside ion implantation process. The backside illuminated CMOS image sensor may further comprise a laser annealed layer on the backside of the substrate. The extended photo active region helps to increase the number of photons converted into electrons so as to improve quantum efficiency.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHODS OF FORMING PHOTO DETECTORS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149806.html</link>
            <description><![CDATA[Methods of forming photo detectors are provided. The method includes providing a semiconductor layer on a substrate, forming a trench in the semiconductor layer, forming a first single crystalline layer and a second single crystalline layer using a selective single crystalline growth process in the trench, and patterning the first and second single crystalline layers and the semiconductor layer to form a first single crystalline pattern, a second single crystalline pattern and an optical waveguide.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD OF FABRICATING ORGANIC LIGHT EMITTING DIODE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149803.html</link>
            <description><![CDATA[Provided is a method of fabricating an organic light emitting diode. The method may include preparing a substrate, forming a textured portion on the substrate, the textured portion including protruding patterns randomly and irregularly arranged on the substrate, forming a planarization layer on the substrate to planarize the substrate formed with the textured portion, forming a first electrode on the planarization layer, forming an organic light emitting layer on the first electrode, and forming a second electrode on the organic light emitting layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0149794.html</link>
            <description><![CDATA[A method of manufacturing a semiconductor device includes: forming a conductive film over a semiconductor substrate; forming a first ferroelectric film over the conductive film; forming an amorphous second ferroelectric film over the first ferroelectric film; forming a transition metal oxide material film containing ruthenium over the second ferroelectric film; forming a first conductive metal oxide film over the transition metal oxide material film without exposing the transition metal oxide material film to the air; annealing and crystallizing the second ferroelectric film; and patterning the first conductive metal oxide film, the first ferroelectric film, the second ferroelectric film, and the conductive film to form a ferroelectric capacitor.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[RAM MEMORY CELL COMPRISING A TRANSISTOR]]></title>
            <link>http://www.freepatentsonline.com/y2013/0148441.html</link>
            <description><![CDATA[The invention relates to a memory cell consisting of an isolated MOS transistor having a drain (8), a source (7) and a body region covered with an insulated gate (12), in which the body region is divided through its thickness into two separate regions (13, 14) of opposite conductivity types extending parallel to the plane of the gate, the body region closest to the gate having the opposite conductivity type to that of the drain/source.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating]]></title>
            <link>http://www.freepatentsonline.com/y2013/0148422.html</link>
            <description><![CDATA[Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second locations and above a surface of the substrate and insulated from the surface by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell; and a control gate positioned above the floating gate or trapping layer and a second insulating layer between the floating gate or trapping layer and the control gate.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[MAGNETORESISTIVE DEVICE AND A WRITING METHOD FOR A MAGNETORESISTIVE DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0148418.html</link>
            <description><![CDATA[A magnetoresistive device including a fixed magnetic layer structure, a first free magnetic layer structure, and a second free magnetic layer structure, wherein the fixed magnetic layer structure is arranged in between the first free magnetic layer structure and the second free magnetic layer structure, wherein the magnetization orientation of the first free magnetic layer structure is variable in response to a first electrical signal of a first polarity and the magnetization orientation of the second free magnetic layer structure is at least substantially non-variable in response to the first electrical signal, and wherein the magnetization orientation of the second free magnetic layer structure is variable in response to a second electrical signal of a second polarity and the magnetization orientation of the first free magnetic layer structure is at least substantially non-variable in response to the second electrical signal, wherein the second polarity is opposite to the first polarity.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[CIRCUIT AND SYSTEM OF USING FINFET FOR BUILDING PROGRAMMABLE RESISTIVE DEVICES]]></title>
            <link>http://www.freepatentsonline.com/y2013/0148409.html</link>
            <description><![CDATA[Junction diodes or MOS devices fabricated in standard FinFET technologies can be used as program selectors or One-Time Programmable (OTP) element in a programmable resistive device, such as interconnect fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCRAM, CBRAM, or RRAM. The MOS or diode can be built on at least one fin structure or at least one active region that has at least one first active region and a second active region. The first and the second active regions can be isolated by a dummy MOS gate or silicide block layer (SBL) to construct a diode.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ANTIFUSE-BASED MEMORY CELLS HAVING MULTIPLE MEMORY STATES AND METHODS OF FORMING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0148404.html</link>
            <description><![CDATA[In some aspects, a memory cell is provided that includes a steering element and a metal-insulator-metal (“MIM”) stack coupled in series with the steering element. The MIM stack includes a first dielectric material layer and a second dielectric material layer disposed on the first dielectric material layer, without a metal or other conductive layer disposed between the first dielectric material layer and the second dielectric material layer. Numerous other aspects are provided.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SYSTEMS AND METHODS FOR STACKED SEMICONDUCTOR MEMORY DEVICES]]></title>
            <link>http://www.freepatentsonline.com/y2013/0148401.html</link>
            <description><![CDATA[Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR MEMORY DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0148399.html</link>
            <description><![CDATA[A semiconductor memory device in accordance with an embodiment includes a plurality of first word lines, a plurality of bit lines, a resistance varying material, a plurality of second word lines and an insulating film. The bit lines intersect the first word lines. The resistance varying material is disposed at respective intersections of the first word lines and the bit lines. The second word lines intersect the bit lines. The insulating film is disposed at respective intersections of the second word lines and the bit lines. One of the first word lines and one of the second word lines are disposed so as to sandwich the bit lines. The second word lines, the bit lines, and the insulating film configure a field-effect transistor at respective intersections of the second word lines and the bit lines. The field-effect transistor and the resistance varying material configure one memory cell.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND METHOD OF MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0148398.html</link>
            <description><![CDATA[A three-dimensional (3-D) non-volatile memory device according to an embodiment of the present invention includes a plurality of vertical channel layers protruding from a substrate, a plurality of interlayer insulating layers and a plurality of memory cells stacked alternately along the plurality of vertical channel layers, and an air gap formed in the plurality of interlayer insulating layers disposed between the plurality of memory cells, so that capacitance between word lines is reduced to thus improve a program speed.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[FILTER LAYER SUBSTRATE AND DISPLAY APPARATUS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0148062.html</link>
            <description><![CDATA[A filter layer substrate comprises a substrate, a black matrix layer, a filter layer, a protection layer, a first photoresist spacer, and a second photoresist spacer. The black matrix layer is disposed on the substrate. The filter layer covers the substrate and the black matrix layer. The protection layer is disposed on the filter layer. The first photoresist spacer is disposed on the protection layer corresponding to the black matrix layer. The second photoresist spacer is disposed on the protection layer corresponding to the black matrix layer. A bottom surface of the first photoresist spacer and a bottom surface of the second photoresist spacer have a height difference. A display apparatus containing the filter layer substrate is also disclosed. Accordingly, the liquid crystal margin of the LC filling can be enlarged, and the problems caused by the stress and the external collision or vibration can be avoided.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[DISPLAY DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0148049.html</link>
            <description><![CDATA[A display device includes a display area as an area having a plurality pixels each including a thin film transistor, and adapted to display an image, and a dummy pixel area formed outside the display area, and having a plurality of dummy pixels. The dummy pixel includes a dummy gate signal line parallel to a gate signal line of the thin film transistor, and a semiconductor layer intersecting with the dummy gate signal line via an insulating layer. Just one conductor layer is connected to the semiconductor layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Multi-functional active matrix organic light-emitting diode display]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147764.html</link>
            <description><![CDATA[A multi-functional active matrix display comprises a transparent front sheet, a semi-transparent layer of light emissive devices adjacent the rear side of the front sheet and forming a matrix of display pixels, and a solar cell layer located behind the light emissive devices for converting both ambient light and internal light7 from the light emissive devices into electrical energy, the solar cell layer including an array of electrodes on the front surface of the solar cell layer for use in detecting the location of a change in the amount of light impinging on a portion of the front surface of the solar cell layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Touch Screen Integrated Organic Light Emitting Display Device And Method For Fabricating The Same]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147727.html</link>
            <description><![CDATA[Disclosed are a touch screen integrated organic light emitting display device which has a thin profile and is implemented in a flexible type and a method for fabricating the same. The touch screen integrated organic light emitting display device includes a film substrate, a first etch stopper layer and a first buffer layer sequentially formed on the film substrate, a thin film transistor array including thin film transistors formed on the first buffer layer, organic light emitting diodes connected to the thin film transistors, a passivation layer covering the thin film transistor array and the organic light emitting diodes, a touch electrode layer contacting the passivation layer, a second buffer layer and a second etch stopper layer sequentially formed on the touch electrode layer, and a polarizing plate formed on the second etch stopper layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR MODULES AND METHODS OF FORMING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147540.html</link>
            <description><![CDATA[Electronic modules, and methods of forming and operating modules, are described. The modules include a capacitor, a first switching device, and a second switching device. The electronic modules further include a substrate such as a DBC substrate, which includes an insulating layer between a first metal layer and a second metal layer, and may include multiple layers of DBC substrates stacked over one another. The first metal layer includes a first portion and a second portion isolated from one another by a trench formed through the first metal layer between the two portions. The first and second switching devices are over the first metal layer, a first terminal of the capacitor is electrically connected to the first portion of the first metal layer, and a second terminal of the capacitor is electrically connected to the second portion of the first metal layer, with the capacitor extending over the trench.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147518.html</link>
            <description><![CDATA[In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[MONITORING TESTKEY USED IN SEMICONDUCTOR FABRICATION]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147510.html</link>
            <description><![CDATA[A monitoring testkey for a wafer is provided. The monitoring testkey includes a first metal oxide semiconductor (MOS) transistor having a channel extending in a first direction, a second MOS transistor having a channel extending in a second direction, a common gate pad electrically connected to gate electrodes of the first MOS transistor and the second MOS transistor, a first source pad electrically connected to source electrodes of the first MOS transistor and the second MOS transistor, a first drain pad electrically connected to a drain electrode of the first MOS transistor, and a second drain pad electrically connected to a drain electrode of the second MOS transistor. The monitoring testkey helps to improve the critical dimension uniformity and electrical characteristics uniformity of elements in a wafer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[TEST PATTERN OF SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING TEST PATTERN AND METHOD OF TESTING SEMICONDUCTOR DEVICE BY USING TEST PATTERN]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147509.html</link>
            <description><![CDATA[A test pattern of a semiconductor device includes a plurality of active regions defined in a semiconductor substrate and arranged in parallel with each other, a plurality of gate patterns formed over the plurality of active regions, a plurality of gate contacts formed over the plurality of gate patterns, first junction contacts formed over respective end portions of odd-numbered active regions among the plurality of active regions, second junction contacts formed over respective end portions of even-numbered active regions among the plurality of active regions, and a contact pad configured to couple the first junction contacts and the plurality of gate contacts.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Micro-Fabricated Atomic Magnetometer and Method of Forming the Magnetometer]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147472.html</link>
            <description><![CDATA[The cost and size of an atomic magnetometer are reduced by attaching a vapor cell structure that has a vapor cell cavity to a base die that has a laser light source that outputs light to the vapor cell cavity, and attaching a photo detection die that has a photodiode to the vapor cell structure to detect light from the laser light source that passes through the vapor cell cavity.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Apparatus and a Method of Manufacturing an Apparatus]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147420.html</link>
            <description><![CDATA[An apparatus including a charge storage component; and an energy harvesting component wherein the charge storage component and the energy harvesting component are integrated via a common electrode.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[COLOR CONVERSION FILTER]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147345.html</link>
            <description><![CDATA[A color conversion filter contains at least one kind of squarylium dye that radiates fluorescence light, has a wavelength conversion capability, absorbs light in an unneeded wavelength region, radiates fluorescence light in a preferable wavelength region, and does not allow decrease in brightness, and thus is preferable for color conversion light-emitting devices, photoelectric conversion devices and the like. Specifically, the color conversion filter has an absorption having a high intensity in the range of 570 to 600 nm, and thus is preferable for use in a color conversion filter that radiates fluorescence light having a high intensity in the range of 600 to 780 nm.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[LOADING ELEMENT OF A FILM BULK ACOUSTIC RESONATOR]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147319.html</link>
            <description><![CDATA[Manufacturing a semiconductor structure including modifying a frequency of a Film Bulk Acoustic Resonator (FBAR) device though a vent hole of a sealing layer surrounding the FBAR device.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[LOCALLY TAILORING CHEMICAL MECHANICAL POLISHING (CMP) POLISH RATE FOR DIELECTRICS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147067.html</link>
            <description><![CDATA[A method of manufacturing a semiconductor structure includes varying local chemical mechanical polishing (CMP) abrading rates of an insulator film by selectively varying a carbon content of the insulator film.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[STRUCTURE AND METHOD FOR E-BEAM IN-CHIP OVERLAY MARK]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147066.html</link>
            <description><![CDATA[The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Semiconductor Device and Method of Forming Adjacent Channel and Dam Material Around Die Attach Area of Substrate to Control Outward Flow of Underfill Material]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147065.html</link>
            <description><![CDATA[A semiconductor device has a flipchip or PoP semiconductor die mounted to a die attach area interior to a substrate. The substrate has a contact pad area around the die attach area and flow control area between the die attach area and contact pad area. A first channel is formed in a surface of the substrate within the flow control area. The first channel extends around a periphery of the die attach area. A first dam material is formed adjacent to the first channel within the flow control area. An underfill material is deposited between the die and substrate. The first channel and first dam material control outward flow of the underfill material to prevent excess underfill material from covering the contact pad area. A second channel can be formed adjacent to the first dam material. A second dam material can be formed adjacent to the first channel.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147064.html</link>
            <description><![CDATA[The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHODS OF FABRICATING FAN-OUT WAFER LEVEL PACKAGES AND PACKAGES FORMED BY THE METHODS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147063.html</link>
            <description><![CDATA[A fan-out wafer level package may include at least two semiconductor chips; an insulating layer covering portions of a first semiconductor chip; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and/or an external terminal on the insulating layer. The first semiconductor chip may be stacked relative to the second semiconductor chip. The redistribution line pattern may be electrically connected to the at least two semiconductor chips. The external terminal may be electrically connected to the redistribution line pattern. A fan-out wafer level package may include at least three semiconductor chips; an insulating layer covering portions of first semiconductor chips; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and/or an external terminal on the insulating layer. The first semiconductor chips may be stacked relative to the second semiconductor chip.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147062.html</link>
            <description><![CDATA[A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate. The first semiconductor chip may be electrically connected with the package substrate. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The second semiconductor chip may be electrically connected with the first semiconductor chip. The second semiconductor chip may have a protrusion overhanging an area beyond a side surface of the first semiconductor chip. The supporting member may be interposed between the protrusion of the second semiconductor chip and the package substrate to prevent a deflection of the protrusion. Thus, the protrusion may not be deflected.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Trap Rich Layer with Through-Silicon-Vias in Semiconductor Devices]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147061.html</link>
            <description><![CDATA[An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR PACKAGE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147060.html</link>
            <description><![CDATA[A semiconductor package includes a substrate, a first semiconductor chip module attached to the substrate, a conductive connection member attached to the first semiconductor chip module, and a second semiconductor chip module attached to the conductive connection member. The first and second semiconductor chip modules are formed to have step like shapes and extend laterally in opposite directions so as to define a zigzag arrangement together.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[CHIP-TO-WAFER BONDING METHOD AND THREE-DIMENSIONAL INTEGRATED SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147059.html</link>
            <description><![CDATA[A chip-to-wafer bonding method and a three-dimensional integrated semiconductor device are provided. The method comprises providing a chip and a wafer having a bonding region of the same size and shape as the chip; preparing hydrophilic areas and hydrophobic areas on the chip; preparing in the bonding region hydrophilic areas and hydrophobic areas respectively corresponding to the hydrophilic and hydrophobic areas on the chip; adding a liquid drop onto the hydrophilic areas in the bonding region; and pre-aligning and placing the chip on the bonding region of the wafer, such that the hydrophilic areas on the chip each contacts the corresponding hydrophilic area in the bonding region via the liquid. The sum of perimeters of the hydrophilic areas on the chip is larger than a perimeter of the chip. The sum of perimeters of the hydrophilic areas in the bonding region is larger than a perimeter of the bonding region.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[CHIP PACKAGE AND CHIP PACKAGE METHOD]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147058.html</link>
            <description><![CDATA[A chip package includes a substrate, a pad positioned on the substrate, a base board, at least one adhesive layer and at least one chip. The base board is positioned on the pad. At least one mounting hole is defined through the base board. The at least one adhesive layer is received in the at least one mounting hole. The at least one chip is received in the at least one mounting hole and adhere to the pad via the at least one adhesive layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147057.html</link>
            <description><![CDATA[Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[RESIZED WAFER WITH A NEGATIVE PHOTORESIST RING AND DESIGN STRUCTURES THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147056.html</link>
            <description><![CDATA[A resized wafer using a negative photoresist ring, methods of manufacture and design structures thereof are disclosed. The method includes forming a ring within a radius of a wafer. The method also includes patterning a photoresist formed on the wafer, by exposing the photoresist to energy. Additionally, the method includes forming troughs in a substrate of the wafer based on the patterning of the photoresist, wherein the ring blocks formation of the troughs underneath the ring. The method also includes filling the troughs with a metal and resizing the wafer at an area of the ring.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV through Semiconductor Wafer]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147055.html</link>
            <description><![CDATA[A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147054.html</link>
            <description><![CDATA[A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Semiconductor Device and Method of Making Single Layer Substrate with Asymmetrical Fibers and Reduced Warpage]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147053.html</link>
            <description><![CDATA[A semiconductor device includes a first carrier having a first resin disposed over the first carrier. A fabric is disposed over the first resin. A second resin is formed over the first resin and around the fabric to form an asymmetrical pre-impregnated (PPG) substrate. The first carrier is removed. A second carrier is provided and a first conductive layer is formed over the second carrier. A portion of the first conductive layer is removed. The first conductive layer is transferred from the second carrier to the first resin. The first conductive layer is oriented asymmetrically such that the first conductive layer is offset with respect to the fabric to minimize warpage. The second carrier is removed. A via is formed through the second resin and fabric to expose the first conductive layer. A second conductive layer formed in the via over the first conductive layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[OFFSET OF CONTACT OPENING FOR COPPER PILLARS IN FLIP CHIP PACKAGES]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147052.html</link>
            <description><![CDATA[An integrated circuit die has a dielectric layer positioned over all the contact pads on the integrated circuit die. Openings are provided in the dielectric layer over each of the contact pads of the integrated circuit die in order to permit electrical coupling to be made between the integrated circuit and circuit boards outside of the die. For those contact pads located in the central region of the die, the opening in the dielectric layer is in a central region of the contact pad. For those contact pads located in a peripheral region of the die, spaced adjacent the perimeter die, the opening in the dielectric layer is offset from the center of the contact pad and is positioned closer to the central region of the die than the center of the contact pad is to the central region of the die.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD OF PROTECTING AGAINST VIA FAILURE AND STRUCTURE THEREFOR]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147051.html</link>
            <description><![CDATA[A method is for forming a decoy via and a functional via. The method includes forming the functional via between a metal portion of a first interconnect layer and a portion of a second interconnect layer. The method further includes forming the decoy via in a protection region between the metal portion of the first interconnect layer and a metal portion of the third interconnect level.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR HAVING INTEGRALLY-FORMED ENHANCED THERMAL MANAGEMENT]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147050.html</link>
            <description><![CDATA[A semiconductor structure and method of manufacturing that has integrally-formed enhanced thermal management. During operation of a semiconductor device, electron flow between the source and the drain creates localized heat generation. A containment gap is formed by selectively removing a portion of the back side of the semiconductor device substrate directly adjacent to a localized heat generation area. A thermal management material is filled in the containment gap. This thermal management material enhances the thermal management of the semiconductor device by thermally coupling the localized heat generation area to a heat sink. The thermal management material may be a Phase Change Material (PCM) having a heat of fusion effective for absorbing heat generated in the localized heat generation area by the operation of the semiconductor device for reducing a peak operating temperature of the semiconductor device.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Circuit Probing Structures and Methods for Probing the Same]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147049.html</link>
            <description><![CDATA[A package component includes a stack-probe unit, which includes a first-type connector, and a second-type connector connected to the first-type connector. The first-type connector and the second-type connector are exposed through a surface of the package component.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[INTEGRATED CIRCUIT DEVICES INCLUDING ELECTRODE SUPPORT STRUCTURES AND METHODS OF FABRICATING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147048.html</link>
            <description><![CDATA[A semiconductor device includes a plurality of electrode structures perpendicularly extending on a substrate, and at least one support unit extending between the plurality of electrode structures. The support unit includes at least one support layer including a noncrystalline metal oxide contacting a part of the plurality of electrode structures. Related devices and fabrication methods are also discussed.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Integrated Circuit and Method of Forming an Integrated Circuit]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147047.html</link>
            <description><![CDATA[An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 μm and a ratio of average grain size to thickness of less than 0.7.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Integrated Technology for Partial Air Gap Low K Deposition]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147046.html</link>
            <description><![CDATA[A semiconductor device includes a semiconductor body and a low K dielectric layer overlying the semiconductor body. A first portion of the low K dielectric layer comprises a dielectric material, and a second portion of the low K dielectric layer comprise an air gap, wherein the first portion and the second portion are laterally disposed with respect to one another. A method for forming a low K dielectric layer is also disclosed and includes forming a dielectric layer over a semiconductor body, forming a plurality of air gaps laterally disposed from one another in the dielectric layer, and forming a capping layer over the dielectric layer and air gaps.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Flash Memory Having Multi-Level Architecture]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147045.html</link>
            <description><![CDATA[Subject matter disclosed herein relates to a multi-level flash memory and a process flow to form same.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[MULTI-CHIP PACKAGE HAVING A STACKED PLURALITY OF DIFFERENT SIZED SEMICONDUCTOR CHIPS, AND METHOD OF MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147044.html</link>
            <description><![CDATA[Provided is a multi-chip package in which a plurality of semiconductor chips having different sizes are stacked. A multi-chip package may include a substrate, and a plurality of semiconductor chips stacked on the substrate, each of the plurality of semiconductor chips having a different size. Each of the plurality of semiconductor chips including a pad group and a reference region associated with the pad group, each pad group having a plurality of pads, and the plurality of pads in each pad group located at same coordinates with respect to the associated reference region, and each of the plurality of semiconductor chips having their reference regions vertically aligned.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147043.html</link>
            <description><![CDATA[A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147042.html</link>
            <description><![CDATA[A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[STACK PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147041.html</link>
            <description><![CDATA[A stack package structure is provided, including: a substrate; an insulating layer formed on the substrate and having openings for exposing die attach pads and conductive pads of the substrate, respectively; a plurality of first and second conductive terminals formed on the insulating layer and electrically connected to the die attach pads and the conductive pads, respectively; a dielectric layer formed on the insulating layer and having a cavity for exposing the first conductive terminals and a plurality of openings exposing the second conductive terminals; copper pillars formed respectively in the openings of the dielectric layer; a semiconductor chip disposed in the cavity and electrically connected to the first conductive terminals; solder balls formed respectively on the copper pillars that are located proximate to the die attach area; and a package structure disposed on and electrically connected to the solder balls.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[MEMS CHIP SCALE PACKAGE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147040.html</link>
            <description><![CDATA[A flip-chip manufactured MEMS device. The device includes a substrate and a MEMS die. The substrate has a plurality of bumps, a plurality of connection points configured to electrically connect the MEMS device to another device, and a plurality of vias electrically connecting the bumps to the connections points. The MEMS die is attached to the substrate using flip-chip manufacturing techniques, but the MEMS die is not subjected to processing normally associated with creating bumps for flip-chip manufacturing.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147039.html</link>
            <description><![CDATA[A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS WITHOUT OCCURRING OF CRACK]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147038.html</link>
            <description><![CDATA[A device includes first and second semiconductor chips. The first semiconductor chip includes an edge defining a periphery of the first semiconductor chip. The second semiconductor chip is greater in size than the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip so that the second semiconductor chip hangs over from the edge of the first semiconductor chip. The second semiconductor chip includes a plurality of wiring patterns including a first wiring pattern that positions over the edge of the first semiconductor chip, an insulating film which covers the wiring patterns and which includes on or more holes that expose one or more the wiring patterns, and one or more bump electrodes formed on the one or more the wiring patterns. Remaining one or ones of the wiring patterns is kept covered by the insulating layer and includes the first wiring pattern.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR STRUCTURE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147037.html</link>
            <description><![CDATA[A semiconductor structure is provided. The semiconductor structure includes a substrate, at least two pads, a passivation layer, at least two under bump metallization (UBM) layers and at least two bumps. The pads are disposed adjacent to each other on the substrate along the first direction. The passivation layer covers the substrate and the peripheral upper surface of each pad to define an opening. Each of the openings defines an opening projection along the second direction. The opening projections are disposed adjacent to each other but not overlapping with each other. Furthermore, the first direction is perpendicular to the second direction. The UBM layers are disposed on the corresponding openings, and the bumps are respectively disposed on the corresponding UBM layers. With the above arrangements, the width of each bump of the semiconductor structure of the present invention could be widened without being limited by the bump pitch.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Semiconductor Device and Method of Forming UBM Structure on Back Surface of TSV Semiconductor Wafer]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147036.html</link>
            <description><![CDATA[A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Semiconductor Device and Method of Forming Recesses in Conductive Layer to Detect Continuity for Interconnect Between Semiconductor Die and Substrate]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147035.html</link>
            <description><![CDATA[A semiconductor device has a semiconductor die with composite bump structures over a surface of the semiconductor die. A conductive layer is formed over the substrate. The conductive layer has a channel in an interconnect site of the conductive layer. The channel extends beyond a footprint of the composite bump structures. The semiconductor die is disposed over the substrate. The bump material of the composite bump structures is melted. The composite bump structures are pressed over the interconnect site of the conductive layer so that the melted bump material flows into the channel. Electrical continuity between the composite bump structures and conductive layer is detected by a presence of the bump material in the channel. No electrical continuity between the composite bump structures and conductive layer is detected by an absence of the bump material in the channel. The electrical continuity can be detected by visual inspection or X-ray.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[BUMP STRUCTURE DESIGN FOR STRESS REDUCTION]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147034.html</link>
            <description><![CDATA[Low stress bumps can be used to reduce stress and strain on bumps bonded to a substrate with different coefficients of thermal expansion (CTEs) from the die. The low stress bumps include multiple polymer layers. More than one type of bump is coupled to a die, with low stress bumps placed on areas subjected to high stress.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[POST-PASSIVATION INTERCONNECT STRUCTURE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147033.html</link>
            <description><![CDATA[A semiconductor device includes a passivation layer overlying a semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer overlies the interconnect structure and includes a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[PASSIVATION LAYER FOR PACKAGED CHIP]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147032.html</link>
            <description><![CDATA[The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE WITH BUMP STRUCTURE ON POST-PASSIVATION INTERCONNCET]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147031.html</link>
            <description><![CDATA[A semiconductor device includes a post-passivation interconnect (PPI) structure having a landing pad region. A polymer layer is formed on the PPI structure and patterned with a first opening and a second opening to expose portions of the landing pad region. The second opening is a ring-shaped opening surrounding the first opening. A bump structure is formed on the polymer layer to electrically connect the landing pad region through the first opening and the second opening.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Landing Areas of Bonding Structures]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147030.html</link>
            <description><![CDATA[A device includes a first and a second package component. A metal trace is disposed on a surface of the first package component. The metal trace has a lengthwise direction. The metal trace includes a portion having an edge, wherein the edge is not parallel to the lengthwise direction of the metal trace. The second package component includes a metal pillar, wherein the second package component is disposed over the first package component. A solder region bonds the metal pillar to the metal trace, wherein the solder region contacts a top surface and the edge of the portion of the metal trace.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ULTRA-SMALL CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147029.html</link>
            <description><![CDATA[Some embodiments of the present disclosure provide the design and manufacture of an ultra-small chip assembly. The ultra-small chip assembly comprises a die, a plate-like back electrode disposed on the back-side of the die, and one or more plate-like positive electrodes disposed on the front-side of the die. The ultra-small chip assembly is configured such that one end of the plate-like back electrode extends beyond a first side of the die, and each of the one or more plate-like positive electrodes includes an end which extends beyond a second side of the die. By attaching both the plate-like back electrode and the plate-like positive electrodes on the surfaces of the die, and directly using the exposed ends of the plate-like electrodes as the lead-out electrodes for the chip assembly, the electrical connections outside of the die only occupy a very small volume.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[HEAT SPREADER FOR MULTIPLE CHIP SYSTEMS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147028.html</link>
            <description><![CDATA[Various heat spreaders and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a heat spreader that has a surface adapted to establish thermal contact with a first semiconductor chip and a second semiconductor chip on a substrate. The surface includes a first portion adapted to thermally contact a solder-based thermal interface material and a second portion having an opening adapted to hold an organic thermal interface material.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR PACKAGE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147027.html</link>
            <description><![CDATA[Disclosed herein is a semiconductor package. According to a preferred embodiment of the present invention, there is provided a semiconductor package, including: a first substrate having a first wiring pattern formed therein; a first semiconductor device mounted above the first substrate by being contacted with the first substrate; a second substrate having a second wiring pattern formed therein; a third semiconductor device mounted above the first semiconductor device and contacted with a lower portion of the second substrate; and a third substrate positioned between the first semiconductor device and the third semiconductor device and having a third wiring pattern including at least one upper electrode and lower electrode protruding outwardly, the lower electrode being contacted with the first semiconductor device and the upper electrode being contacted with the third semiconductor device.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[HEATSINK INTERPOSER]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147026.html</link>
            <description><![CDATA[According an embodiment, a package-on-package heatsink interposer for use between a top package and a bottom package of a package-on-package device, may include a top heatsink below the top package; an interposer substrate below the top heatsink; a bottom heatsink below the interposer substrate; a first interposer substrate metal layer between the interposer substrate and the top heatsink; a second interposer substrate metal layer between the interposer substrate and the bottom heatsink; and interposer solder balls between the second interposer substrate metal layer and the bottom package.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD OF STACKING FLIP-CHIP ON WIRE-BONDED CHIP]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147025.html</link>
            <description><![CDATA[A first chip is mounted on a substrate and includes a plurality of bump pads located on an active surface of the first chip. A wire bonds a first bump pad to the substrate. An intermediate layer is disposed on a portion of the active surface of the first chip, and a via within the intermediate layer extends to a second bump pad. A second chip is disposed on the intermediate layer, and wherein the second chip includes a third bump pad located on an active surface of the second chip and aligned with the via formed in the intermediate layer. A corresponding bump is disposed on one or more of the second bump pad and the third bump pad, and within the via, wherein the corresponding bump electrically connects the second bump pad with the third bump pad.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[BALANCED LEADFRAME PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147024.html</link>
            <description><![CDATA[An integrated circuit package structure includes a bottom portion having a cavity, an integrated circuit attached to a top surface of the stepped cavity, a leadframe attached to the bottom portion, wire bonding for electrically coupling the integrated circuit to the leadframe, and a top portion conformally covering the integrated circuit and the bottom portion.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[INTEGRATED CIRCUIT GROUND SHIELDING STRUCTURE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147023.html</link>
            <description><![CDATA[The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147022.html</link>
            <description><![CDATA[A semiconductor device may include an interlayer insulating layer containing hydrogen and a first passivation layer configured to prevent or inhibit an out-gassing of the hydrogen. In the method, a second passivation layer configured to control a warpage characteristic of a wafer may be formed on the first passivation layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[MULTI-LAYER SUBSTRATE STRUCTURE AND MANUFACTURING METHOD FOR THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147021.html</link>
            <description><![CDATA[A method for manufacturing a multi-layer substrate structure such as a CSOI wafer structure (cavity-SOI, silicon-on-insulator) comprising obtaining a first and second wafer, such as two silicon wafers, wherein at least one of the wafers may be optionally provided with a material layer such as an oxide layer (302, 404), forming a cavity on the bond side of the first wafer (306, 406), depositing, preferably by ALD (Atomic Layer Deposition), a material layer, such as thin alumina layer, on either wafer arranged so as to at least in places face the other wafer and cover at least portion of the cavity of the first wafer, such as bottom, wall and/or edge thereof, and enable stopping etching, such as dry etching, into the underlying material (308, 408), and bonding the wafers provided with at least the aforesaid ALD layer as an intermediate layer together to form the multi-layer semiconductor substrate structure (310, 312). A related multi-layer substrate structure is presented.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Component Having a Via and Method for Manufacturing It]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147020.html</link>
            <description><![CDATA[An advantageous method and system for realizing electrically very reliable and mechanically extremely stable vias for components whose functionality is realized in a layer construction on a conductive substrate. The via (Vertical Interconnect Access), which is led to the back side of the component and which is used for the electrical contacting of functional elements realized in the layer construction, includes a connection area in the substrate that extends over the entire thickness of the substrate and is electrically insulated from the adjoining substrate by a trench-like insulating frame likewise extending over the entire substrate thickness. According to the present system, the trench-like insulating frame is filled up with an electrically insulating polymer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Semiconductor Device and Method of Forming Insulating Layer Around Semiconductor Die]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147019.html</link>
            <description><![CDATA[A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Structure for Reducing Integrated Circuit Corner Peeling]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147018.html</link>
            <description><![CDATA[A crack prevention structure that reduces integrated circuit corner peeling and reduces cracking is disclosed. The crack prevention structure comprises a semiconductor substrate; a first plurality of dielectric layers of a first material disposed over the semiconductor substrate; a second plurality of dielectric layers of a second material different than the first material, disposed on the first plurality of dielectric layers, wherein the first plurality of dielectric layers and the second plurality of dielectric layers meet at an interface; and a plurality of metal structures and a plurality of via structures formed through the interface of the first plurality of dielectric layers and the second plurality of dielectric layers.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[BIPOLAR JUNCTION TRANSISTORS WITH A LINK REGION CONNECTING THE INTRINSIC AND EXTRINSIC BASES]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147017.html</link>
            <description><![CDATA[Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Semiconductor Package Having Internal Shunt and Solder Stop Dimples]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147016.html</link>
            <description><![CDATA[A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[DEEP TRENCH DECOUPLING CAPACITOR AND METHODS OF FORMING]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147015.html</link>
            <description><![CDATA[Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a method of forming a semiconductor device includes: forming an outer trench in a silicon substrate, the forming exposing portions of the silicon substrate below an upper surface of the silicon substrate; depositing a dielectric liner layer inside the trench; depositing a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench in the silicon substrate; forming a silicide layer over a portion of the doped polysilicon layer; forming an intermediate contact layer within the inner trench; and forming a contact over a portion of the intermediate contact layer and a portion of the silicide layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Wafer Level Package Having Cylindrical Capacitor and Method Of Fabrication The Same]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147014.html</link>
            <description><![CDATA[Disclosed is a wafer level package having a cylindrical capacitor, which is capable of increasing electrostatic capacity thanks to the use of a cylindrical capacitor structure and which includes a wafer chip having a bonding pad formed thereon and an insulating layer formed thereon and exposing the bonding pad, a redistribution layer connected to the bonding pad and extending to one side of the insulating layer, a cylindrical outer electrode connected to the redistribution layer and having a center opening therein, a cylindrical inner electrode formed in the center opening of the outer electrode so as to be separated from the outer electrode, a dielectric layer formed between the outer electrode and the inner electrode, and a resin sealing portion formed on the insulating layer to cover the redistribution layer, the inner electrode, the outer electrode and the dielectric layer and having a first recess for exposing an upper surface of the inner electrode. A method of fabricating the wafer level package having a cylindrical capacitor is also provided.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147013.html</link>
            <description><![CDATA[A semiconductor device comprises a conductor film and a capacitor comprising a lower electrode provided on the conductor film. The conductor film includes a first conductive film containing a first metal, a second conductive film containing a second metal on the first conductive film, and an oxide film of the second metal on the second conductive film. The oxide film of the second metal has a lower electric resistivity than an oxide film of the first metal.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[CIRCUIT BOARD COMPONENT SHIM STRUCTURE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147012.html</link>
            <description><![CDATA[Various circuit boards and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an electrically non-functional component to a surface of a first circuit board. The electrically non-functional component has a first elevation. The surface of the circuit board is adapted to have a semiconductor chip mounted thereon. An electrically functional component is mounted to the surface inward from the electrically non-functional component. The electrically functional component has a second elevation less than the first elevation.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147011.html</link>
            <description><![CDATA[A semiconductor device has: a signal pad; a power supply line; a ground line; an inductor section whose one end is connected to the signal pad; a terminating resistor connected between the other end of the inductor section and the power supply line or the ground line. The semiconductor device further has: a first ESD protection element connected to a first node in the inductor section; and a second ESD protection element connected to a second node whose position is different from that of the first node in the inductor section.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147010.html</link>
            <description><![CDATA[A semiconductor device (1) includes a wiring (10) and dummy conductor patterns (20). The wiring (10) is a wiring through which a current with a frequency of 5 GHz or higher flows. Near the wiring (10), the dummy conductor patterns (20) are formed. A planar shape of each of the dummy conductor patterns (20) is equivalent to a shape with an internal angle larger than 180°.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147009.html</link>
            <description><![CDATA[A semiconductor device includes: a fuse pattern formed at a first level, a first line pattern formed at a second level lower than the first level, a second line pattern formed at a third level higher than the first level, a first contact plug coupling the fuse pattern to the first line pattern 310, a second contact plug coupling the fuse pattern to the second line pattern, and a fuse blowing region provided over first line pattern and overlapping with the first contact plug at least partially.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Metal E-Fuse With Intermetallic Compound Programming Mechanism and Methods of Making Same]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147008.html</link>
            <description><![CDATA[Disclosed herein is a metal e-fuse device that employs an intermetallic compound programing mechanism and various methods of making such an e-fuse device. In one example, a device disclosed herein includes a first metal line, a second metal line and a fuse element that is positioned between and conductively coupled to each of the first and second metal lines, wherein the fuse element is adapted to be blown by passing a programming current therethrough, and wherein the fuse element is comprised of a material that is different from a material of construction of at least one of the first and second metal lines.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[DEEP ISOLATION TRENCH STRUCTURE AND DEEP TRENCH CAPACITOR ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147007.html</link>
            <description><![CDATA[Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147006.html</link>
            <description><![CDATA[A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ELECTROPLATING METHODS FOR FABRICATING INTEGRATED CIRCUIT DEVICES AND DEVICES FABRICATED THEREBY]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147005.html</link>
            <description><![CDATA[Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of a suppressor contained in a plating solution near the dummy pattern region, to make the concentration of the suppressor more uniform in the cell pattern region, and to supply an electric current more effectively to the cell pattern region. As a result, a plating layer can be more uniformly formed in the cell pattern region, without void formation therein.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Integrated Capacitive Device Having a Thermally Variable Capacitive Value]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147004.html</link>
            <description><![CDATA[An integrated circuit, comprising a capacitive device having a thermally variable capacitive value and comprising a thermally deformable assembly disposed within an enclosure, and comprising an electrically-conducting fixed body and a beam held at at least two different locations by at least two arms rigidly attached to edges of the enclosure, the beam and the arms being metal and disposed within the first metallization level. A part of the said thermally deformable assembly may form a first electrode of the capacitive device and a part of the said fixed body may form a second electrode of the capacitive device. The thermally deformable assembly has a plurality of configurations corresponding respectively to various temperatures of the said assembly and resulting in a plurality of distances separating the two electrodes and various capacitive values in the capacitive device corresponding to the plurality of distances.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[PHOTOVOLTAIC DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147003.html</link>
            <description><![CDATA[A photovoltaic device includes a substrate, the substrate having a base region and an emitter region, the base region having a first width and the emitter region having a second width, a first electrode in contact with and electrically connected to the base region, the first electrode having a third width where it overlies the base region, the third width being greater than the first width such that the first electrode overhangs the base region at at least one side thereof, and a second electrode in contact with and electrically connected to the emitter region, the second electrode having a fourth width where it overlies the emitter region, a ratio of the third width to the fourth width being about 0.3 to about 3.4.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[RECEIVER MODULE AND DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147002.html</link>
            <description><![CDATA[Provided is a receiver module, including: a semiconductor light receiving element including an electrode; and a sub-mount including: an electrical wiring joined to the electrode with solder; and a trap region arranged around a joining surface of the electrical wiring, the trap region retaining solder by solder wetting.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[WAFER SCALE IMAGE SENSOR PACKAGE AND OPTICAL MECHANISM]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147001.html</link>
            <description><![CDATA[There is provided an optical mechanism including a substrate, an image chip, a light source and a securing member. The image chip and the light source are attached to the substrate. The securing member is secured to the substrate and includes a first containing space for accommodating the light source, a second containing space for accommodating the image chip and a blocking region between the first containing space and the second containing space.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[WAFER SCALE IMAGE SENSOR PACKAGE AND OPTICAL MECHANISM INCLUDING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0147000.html</link>
            <description><![CDATA[There is provided an optical mechanism including a substrate, an image sensor chip, a light source, a blocking member and a securing member. The image sensor chip is attached to the substrate and has an active area. The light source is attached to the substrate. The blocking member covers the image sensor chip and has an opening to expose at least the active area of the image sensor chip. The securing member fits on the blocking member to secure the blocking member to the substrate.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD FOR FORMING A SELECTIVE CONTACT]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146999.html</link>
            <description><![CDATA[A method for forming a selective contact for a photovoltaic cell is disclosed. The method includes forming a doped contact layer at the surface of a semiconductor substrate and annealing a portion of the doped contact layer with a laser beam, the portion having a 2D-pattern corresponding to at least a portion of a respective selective contact grid. Wherein the laser beam is pulsed and shaped to the 2D-pattern. A photovoltaic cell having a selective contact formed by the method is also provided.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SINGLE-BAND AND DUAL-BAND INFRARED DETECTORS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146998.html</link>
            <description><![CDATA[Bias-switchable dual-band infrared detectors and methods of manufacturing such detectors are provided. The infrared detectors are based on a back-to-back heterojunction diode design, where the detector structure consists of, sequentially, a top contact layer, a unipolar hole barrier layer, an absorber layer, a unipolar electron barrier, a second absorber, a second unipolar hole barrier, and a bottom contact layer. In addition, by substantially reducing the width of one of the absorber layers, a single-band infrared detector can also be formed.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[MAGNETIC DEVICE AND METHOD OF MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146997.html</link>
            <description><![CDATA[A method of manufacturing a magnetic device includes forming a stack structure, the stack structure including a magnetic layer, and etching the stack structure by using an etching gas, the etching gas including at least 80% by volume of H2 gas.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[MAGNETIC DEVICE FABRICATION]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146996.html</link>
            <description><![CDATA[The present disclosure provides for magnetic devices and methods of fabricating such a device. In one embodiment, a magnetic device includes a first elliptical pillar of first material layers; a second elliptical pillar concentrically disposed over the first elliptical pillar, the second elliptical pillar includes second material layers. The second elliptical pillar is smaller than the first elliptical pillar in size.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[THREE-DIMENSIONAL, ULTRASONIC TRANSDUCER ARRAYS, METHODS OF MAKING ULTRASONIC TRANSDUCER ARRAYS, AND DEVICES INCLUDING ULTRASONIC TRANSDUCER ARRAYS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146995.html</link>
            <description><![CDATA[Systems, apparatus, and associated methods of forming the systems and/or apparatus may include imaging devices that may comprise multiple arrays of ultrasonic transducer elements for use in a variety of applications. These multiple arrays of ultrasonic transducer elements can be arranged to form a three-dimensional imaging device. Non-coplanar arrays of ultrasonic transducer elements can be coupled together. These imaging devices may be used as medical imaging devices. Additional apparatus, systems, and methods are disclosed.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD FOR MANUFACTURING A HERMETICALLY SEALED STRUCTURE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146994.html</link>
            <description><![CDATA[A method for providing hermetic sealing within a silicon-insulator composite wafer for manufacturing a hermetically sealed structure, comprising the steps of: patterning a first silicon wafer to have one or more recesses that extend at least partially through the first silicon wafer; filling said recesses with an insulator material able to be anodically bonded to silicon to form a first composite wafer having a plurality of silicon-insulator interfaces and a first contacting surface consisting of insulator material; and using an anodic bonding technique on the first contacting surface and an opposing second contacting surface to create hermetic sealing between the silicon-insulator interfaces, wherein the second contacting surface consists of silicon.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR STRUCTURE HAVING A POLYSILICON STRUCTURE AND METHOD OF FORMING SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146993.html</link>
            <description><![CDATA[The present application discloses a method of forming a semiconductor structure. In at least one embodiment, the method includes forming a polysilicon layer over a substrate. A mask layer is formed over the polysilicon layer. The mask layer is patterned to form a patterned mask layer. A polysilicon structure is formed by etching the polysilicon layer using the patterned mask layer as a mask. The polysilicon structure has an upper surface and a lower surface, and the etching of the polysilicon layer is arranged to cause a width of the upper surface of the polysilicon structure greater than that of the lower surface of the polysilicon structure.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[DEEP TRENCH EMBEDDED GATE TRANSISTOR]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146992.html</link>
            <description><![CDATA[A semiconductor device includes a source extending into a surface of a substrate, a drain extending into the surface of the substrate, and an embedded gate in the substrate extending from the source to the drain.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Device Including Two Power Semiconductor Chips and Manufacturing Thereof]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146991.html</link>
            <description><![CDATA[A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND RELATED METHOD]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146990.html</link>
            <description><![CDATA[Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region; forming a first interlayer insulating film; and patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions. The method further comprises forming a first ohmic film, a first barrier film, and a metal film; and removing portions of each of the metal film, the first barrier film, and the first ohmic film.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[INTEGRATED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146989.html</link>
            <description><![CDATA[An integrated device includes a field effect transistor formed within and upon an active region of a substrate and a resistor formed on an isolation region of the substrate. The field effect transistor includes a gate stacked structure having respective portions of a dielectric layer, a first conductive layer and a second conductive layer arranged in order from bottom to top. The resistor includes a resistor body being an enclosure portion of the first conductive layer and resistor terminals being portions of the second conductive layer on distal ends of the resistor body. A method for manufacturing a semiconductor device includes forming a gate stacked structure and a resistor stacked structure at the same time by patterning a dielectric layer, a first conductive layer and a second conductive layer. The method also includes forming a resistor having a resistor body by patterning the resistor stacked structure.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Shared Diffusion Regions on Opposite Sides of Two-Transistor-Forming Gate Level Feature]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146988.html</link>
            <description><![CDATA[A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Integrated Semiconductor Structure for SRAM and Fabrication Methods Thereof]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146987.html</link>
            <description><![CDATA[A SRAM device with metal gate transistors is provided. The SRAM device includes a PMOS structure and an NMOS structure over a substrate. Each of the PMOS and the NMOS structure includes a p-type metallic work function layer and an n-type metallic work function layer. The p-type work metallic function layer and the n-type metallic work function layer form a combined work function for the PMOS and the NMOS structures.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146986.html</link>
            <description><![CDATA[A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[TRENCH ISOLATION STRUCTURE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146985.html</link>
            <description><![CDATA[A trench isolation structure and method of forming the trench isolation structure are disclosed. The method includes forming a shallow trench isolation (STI) structure having an overhang and forming a gate stack. The method further includes forming source and drain recesses adjacent to the STI structure and the gate stack. The source and drain recesses are separated from the STI structure by substrate material. The method further includes forming epitaxial source and drain regions associated with the gate stack by filling the source and drain recesses with stressor material.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146984.html</link>
            <description><![CDATA[A semiconductor device includes isolation layers formed at isolation regions of a semiconductor substrate, silicon patterns formed over the semiconductor substrate between the isolation layers, insulating layers formed between the silicon patterns and the semiconductor substrate, and junctions formed in the semiconductor substrate between the silicon patterns, wherein each of the silicon patterns has a sloped top surface.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[NITRIDE BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146983.html</link>
            <description><![CDATA[Disclosed herein is a nitride based semiconductor device, including: a substrate; a nitride based semiconductor layer having a lower nitride based semiconductor layer and an upper nitride based semiconductor layer on the substrate; an isolation area including an interface between the lower nitride based semiconductor layer and the upper nitride based semiconductor layer; and drain electrodes, source electrode, and gate electrodes formed on the upper nitride based semiconductor layer. According to preferred embodiments of the present invention, in the nitride based semiconductor device, by using the isolation area including the interface between the lower nitride based semiconductor layer and the upper nitride based semiconductor layer, problems of parasitic capacitance and leakage current are solved, and as a result, a switching speed can be improved through a gate pad.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146982.html</link>
            <description><![CDATA[A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ANTENNA CELL DESIGN TO PREVENT PLASMA INDUCED GATE DIELECTRIC DAMAGE IN SEMICONDUCTOR INTEGRATED CIRCUITS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146981.html</link>
            <description><![CDATA[An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[APPARATUSES AND METHODS FOR TRANSPOSING SELECT GATES]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146980.html</link>
            <description><![CDATA[Apparatuses and methods for transposing select gates, such as in a computing system and/or memory device, are provided. One example apparatus can include a group of memory cells and select gates electrically coupled to the group of memory cells. The select gates are arranged such that a pair of select gates are adjacent to each other along a first portion of each of the pair of select gates and are non-adjacent along a second portion of each of the pair of select gates.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Compensated Well ESD Diodes With Reduced Capacitance]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146979.html</link>
            <description><![CDATA[An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[TRANSISTOR ASSISTED ESD DIODE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146978.html</link>
            <description><![CDATA[An integrated circuit includes a diode/bipolar ESD protection device. The diode/bipolar ESD device includes at least one gate separated ESD diode and at least one gate spaced ESD bipolar transistor coupled in parallel between a fixed voltage and an input/output pin.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146977.html</link>
            <description><![CDATA[The present invention discloses a semiconductor structure comprising: a semiconductor base located on an insulating layer, which is located on a semiconductor substrate; source/drain regions adjacent to opposite first sides of the semiconductor base; gates, positioned on a second set of two sides of the semiconductor base and said second set of two sides are opposite to each other; an insulating plug located on the insulating layer and embedded into the semiconductor base; and an epitaxial layer located between the insulating plug and the semiconductor base wherein the epitaxial layer is SiC for an NMOS device and the epitaxial layer is SiGe for a PMOS device. The present invention further discloses a method for manufacturing a semiconductor structure. The stress at the channel region is adjusted by forming a strained epitaxial layer, thus carrier mobility is improved and the performance of the semiconductor device is improved.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[INTEGRATED CIRCUITS FORMED ON STRAINED SUBSTRATES AND INCLUDING RELAXED BUFFER LAYERS AND METHODS FOR THE MANUFACTURE THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146976.html</link>
            <description><![CDATA[Embodiments of a method for producing an integrated circuit are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes providing a strained substrate having an n-active region and a p-active region, etching a cavity into one of the n-active region and the p-active region, embedding a relaxed buffer layer within the cavity, forming a body of strain material over the relaxed buffer layer having a strain orientation opposite that of the strained substrate, and fabricating n-type and t-type transistors over the n-active and p-active regions, respectively. The channel of the n-type transistor extends within one of the strained substrate and the body of strain material, while the channel of the p-type transistor extends within the other of the strained substrate and the body of strain material.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT WITH HIGH-K/METAL GATE WITHOUT HIGH-K DIRECT CONTACT WITH STI]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146975.html</link>
            <description><![CDATA[A method, semiconductor device, and integrated circuit with a high-k/metal gate without high-k direct contact with STI. A high-k dielectric and a pad film are deposited directly onto a semiconductor substrate. Shallow trench isolation is performed, with shallow trenches etched directly into the pad film, the high-k material, and the substrate. The shallow trench is lined with an oxygen diffusion barrier and is subsequently filled with an insulating dielectric material. Thereafter the pad film and the insulating dielectric are recessed to a point where the oxygen diffusion barrier still remains between the insulating dielectric and the high-k material, preventing any contact there between. Afterwards a conductive gate is formed overlying the device.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146974.html</link>
            <description><![CDATA[A method of forming a semiconductor device is provided. The method includes preparing a substrate having a transistor region and an alignment region, forming a first trench and a second trench in the substrate of the transistor region and in the substrate of the alignment region, respectively, forming a drift region in the substrate of the transistor region, forming two third trenches respectively adjacent to two ends of the drift region, and forming an isolation pattern in the first trench, a buried dielectric pattern in the second trench, and dielectric patterns in the two third trenches, respectively. A depth of the first trench is less than a depth of the third trenches, and the depth of the first trench is equal or substantially equal to a depth of the second trench.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[CUSTOMIZED SHIELD PLATE FOR A FIELD EFFECT TRANSISTOR]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146973.html</link>
            <description><![CDATA[A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE HAVING ISOLATION TRENCHES]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146972.html</link>
            <description><![CDATA[A semiconductor uses an isolation trench, and one or more additional trenches to those required for isolation are provided. These additional trenches can be connected between a transistor gate and the drain to provide additional gate-drain capacitance, or else they can be used to form series impedance coupled to the transistor gate. These measures can be used separately or in combination to reduce the switching speed and thereby reduce current spikes.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Semiconductor Device Including First and Second Semiconductor Elements]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146971.html</link>
            <description><![CDATA[A semiconductor device includes a first semiconductor element including a first pn junction between a first terminal and a second terminal. The semiconductor device further includes a semiconductor element including a second pn junction between a third terminal and a fourth terminal. The semiconductor element further includes a semiconductor body including the first semiconductor element and the second semiconductor element monolithically integrated. The first and third terminals are electrically coupled to a first device terminal. The second and fourth terminals are electrically coupled to a second device terminal. A temperature coefficient α1 of a breakdown voltage Vbr1 of the first pn junction and a temperature coefficient α2 of a breakdown voltage Vbr2 of the second pn junction have a same algebraic sign and satisfy 0.6×α1]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Semiconductor Device Including First and Second Semiconductor Elements]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146970.html</link>
            <description><![CDATA[A semiconductor device includes a first semiconductor element including a first pn junction between a first terminal and a second terminal. The semiconductor device further includes a semiconductor element including a second pn junction between a third terminal and a fourth terminal. The semiconductor element further includes a semiconductor body including the first semiconductor element and the second semiconductor element monolithically integrated. The first and third terminals are electrically coupled to a first device terminal. The second and fourth terminals are electrically coupled to a second device terminal. A temperature coefficient α1 of a breakdown voltage Vbr1 of the first pn junction and a temperature coefficient α2 of a breakdown voltage Vbr2 of the second pn junction have a same algebraic sign and satisfy 0.6×α1]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SWITCHING ELEMENT AND MANUFACTURING METHOD THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146969.html</link>
            <description><![CDATA[A switching element is provided having a semiconductor substrate. A trench gate electrode is formed in the upper surface of the semiconductor substrate. An n-type first semiconductor region, a p-type second semiconductor region, and an n-type third semiconductor region are formed in a region in contact with a gate insulating film in the semiconductor substrate. At a position below the second semiconductor region, there is formed a p-type fourth semiconductor region connected to the second semiconductor region and opposing the gate insulating film via the third semiconductor region and containing boron. A high-concentration-carbon containing region having a carbon concentration higher than that of a semiconductor region exposed on the lower surface of the semiconductor substrate is formed in at least a part of the portion of the third semiconductor region, positioned between the fourth semiconductor region and the gate insulating film, that is in contact with the fourth semiconductor region.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146968.html</link>
            <description><![CDATA[In the semiconductor device, a line-type buried gate is formed by burying a non-operating gate (isolation gate) with a polysilicon material to reduce a work function and a Gate Induced Drain Leakage (GIDL) caused by the non-operating gate, resulting in improvement of refresh characteristics of the semiconductor device. Operating gates including a metal conductive material may be formed in a separate step.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Trench-Gate Resurf Semiconductor Device and Manufacturing Method]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146967.html</link>
            <description><![CDATA[A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR STRUCTURE WITH ENHANCED CAP AND FABRICATION METHOD THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146966.html</link>
            <description><![CDATA[A semiconductor structure includes a substrate, a feature on the substrate, a spacer on a sidewall surface of the feature, and an enhanced cap disposed on an upper surface of the spacer. The enhanced cap compensates the thinner upper portion of the spacer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED DRAIN REGIONS OF CMOS TRANSISTORS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146965.html</link>
            <description><![CDATA[A method for fabricating recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD OF PRODUCING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146964.html</link>
            <description><![CDATA[A method for producing a semiconductor device includes the steps of forming a planar silicon layer, first and second pillar-shaped silicon layers on a silicon substrate; forming a gate insulating film, depositing a metal film and a polysilicon around the gate insulating film, conducting planarization, conducting etching to expose upper portions of the first and second pillar-shaped silicon layers, forming first and second insulating film sidewalls, and forming first and second gate electrodes and a gate line; forming n-type diffusion layers in upper and lower portions of the first pillar-shaped silicon layer, and forming p-type diffusion layers in upper and lower portions of the second pillar-shaped silicon layer; forming a third insulating film sidewall on side walls of the first and second insulating film sidewalls, the first and second gate electrodes, and the gate line; and forming a silicide.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHODS OF FORMING NON-VOLATILE MEMORY]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146963.html</link>
            <description><![CDATA[Methods of forming non-volatile memory is described. The non-volatile memory includes a substrate having a source region, a drain region and a channel region. The channel region separates the source region and the drain region. An electrically insulating layer is adjacent to the source region, drain region and channel region. A floating gate electrode is adjacent to the electrically insulating layer. The electrically insulating layer separates the floating gate electrode from the channel region. The floating gate electrode has a floating gate major surface. A control gate electrode has a control gate major surface and the control gate major surface opposes the floating gate major surface. A vacuum layer or gas layer at least partially separates the control gate major surface from the floating gate major surface.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146962.html</link>
            <description><![CDATA[A semiconductor device includes a plurality of first trenches having a first depth formed in a semiconductor substrate, a plurality of second trenches having a second depth formed in the semiconductor substrate, wherein the second depth is different from the first depth and the second trenches are formed between the first trenches, a plurality of isolation layers formed at the plurality of first trenches and the plurality of second trenches, wherein the isolation layers have upper portions formed above the semiconductor substrate, and a plurality of memory cells formed over the semiconductor substrate between the isolation layers.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146961.html</link>
            <description><![CDATA[Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[MEMORY CELLS HAVING A PLURALITY OF CONTROL GATES AND MEMORY CELLS HAVING A CONTROL GATE AND A SHIELD]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146960.html</link>
            <description><![CDATA[Various embodiments comprise apparatuses having a number of memory cells. In one such apparatus, each cell has a plurality of control gates. For example, each of two control gates is adjacent a respective side of a charge storage structure. In another apparatus, each cell has a control gate and a shield, such as where the control gate is adjacent one side of a charge storage structure and the shield is adjacent another side of the charge storage structure. Additional apparatuses and methods are described.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and Structure For Forming On-Chip High Quality Capacitors With ETSOI Transistors]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146959.html</link>
            <description><![CDATA[An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD FOR FORMING BURIED BIT LINE, SEMICONDUCTOR DEVICE HAVING THE SAME, AND FABRICATING METHOD THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146958.html</link>
            <description><![CDATA[A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE FORMED IN AN EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) SUBSTRATE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146957.html</link>
            <description><![CDATA[A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[FIELD EFFECT TRANSISTORS (FETS) AND METHODS OF MANUFACTURE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146956.html</link>
            <description><![CDATA[An improved field effect transistors (FETs) and methods of manufacturing the field effect transistors (FETs) are provided. The method of manufacturing a zero capacitance random access memory cell (ZRAM) includes comprises forming a finFET on a substrate and enhancing a storage capacitance of the finFET. The enhancement can be by either adding a storage capacity to the finFET or altering a portion of the finFET after formation of a fin body of the finFET.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ELECTRONIC CHIP HAVING CHANNELS THROUGH WHICH A HEAT TRANSPORT COOLANT CAN FLOW, ELECTRONIC COMPONENTS AND COMMUNICATION ARM INCORPORATING SAID CHIP]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146955.html</link>
            <description><![CDATA[The invention relates to an electronic chip, comprising: a semiconductor substrate (6) having an active area (8) formed by at least one P doped region and at least one N doped region which form one or more P-N junctions through which most of the useful current flows when said electronic chip is in a conductive state, and at least one channel (44) through which a heat transport coolant can flow, the channel(s) passing through at least said P or N doped region of the active area. Each channel (44) is rectilinear and passes through the substrate (6) in a direction which is collinear with a direction F to the nearest ±45°, where the direction F is perpendicular to the plane of the substrate.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Method Of Memory Array And Structure Form]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146954.html</link>
            <description><![CDATA[The present invention provides a memory array including a substrate, an isolation region, a plurality of active regions, a plurality of buried bit lines, a plurality of word lines, a plurality of drain regions and a plurality of capacitors. The isolation region and the active regions are disposed in the substrate and the active regions are encompassed and isolated by the isolation region. The buried bit lines are disposed in the substrate and extend in the second direction. The word lines are disposed in the substrate extend in the first direction. The drain regions are disposed in the active region not covered by the word lines. The capacitors are disposed on the substrate and electrically connected to the drain regions.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Method and Structure For Forming ETSOI Capacitors, Diodes, Resistors and Back Gate Contacts]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146953.html</link>
            <description><![CDATA[An ETSOI transistor and a combination of capacitors, junction diodes, bank end contacts and resistors are respectively formed in a transistor and capacitor region thereof by etching through an ETSOI and BOX layers in a replacement gate HK/MG flow. The capacitor and other devices formation are compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor, and devices. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ON-CHIP CAPACITORS IN COMBINATION WITH CMOS DEVICES ON EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) SUBSTRATES]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146952.html</link>
            <description><![CDATA[A device including a semiconductor on insulator (SOI) substrate including a semiconductor device region and a capacitor device region. A semiconductor device present in the semiconductor device region. The semiconductor device including a gate structure present on a semiconductor on insulator (SOI) layer of the SOI substrate, extension source and drain regions present in the SOI layer on opposing sides of the gate structure, and raised source and drain regions composed of a first portion of an epitaxial semiconductor material on the SOI layer. A capacitor is present in the capacitor device region, said capacitor including a first electrode comprised of a second portion of the epitaxial semiconductor material that has a same composition and crystal structure as the first portion of the epitaxial semiconductor material, a node dielectric layer present on the second portion of the epitaxial semiconductor material, and a second electrode comprised of a conductive material.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[CROSS-HAIR CELL WORDLINE FORMATION]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146951.html</link>
            <description><![CDATA[Methods and devices depicting fabrication of non-planar access devices having fins and narrow trenches, among which is a method that includes wet etching a conductor to form a recessed region and subsequently etching the conductor to form gates on the fins. The wet etching may include formation of recesses which are may be backfilled with a fill material to form spacers on the conductor. Portions of a plug may be removed during the wet etch to form overhanging spacers to provide further protection of the conductor during the dry etch.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146950.html</link>
            <description><![CDATA[A semiconductor device and manufacture method thereof include a silicide material formed on a source region and a drain region on opposite sides of a gate, wherein the gate having sidewalls on both side surfaces is formed on a substrate. The gate has a first sidewall spacer and a second sidewall spacer on each sidewall, the first spacer has a horizontal portion and a vertical portion, the horizontal portion is located between the second sidewall spacer and the substrate, the vertical portion is located between the second sidewall spacer and the sidewalls. A protecting layer is selectively deposited on the silicide material.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[MECHANISMS FOR FORMING STRESSOR REGIONS IN A SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146949.html</link>
            <description><![CDATA[The embodiments of processes and structures described above provide mechanisms for improving mobility of carriers. The dislocations in the source and drain regions and the strain created by the doped epitaxial materials next to the channel region of a transistor both contribute to the strain in the channel region. As a result, the device performance is improved.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[MICROMECHANICAL DEVICE AND METHODS TO FABRICATE SAME USING HARD MASK RESISTANT TO STRUCTURE RELEASE ETCH]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146948.html</link>
            <description><![CDATA[A structure includes a silicon layer disposed on a buried oxide layer that is disposed on a substrate; at least one transistor device formed on or in the silicon layer, the at least one transistor having metallization; a released region of the silicon layer disposed over a cavity in the buried oxide layer; a back end of line (BEOL) dielectric film stack overlying the silicon layer and the at least one transistor device; a nitride layer overlying the BEOL dielectric film stack; a hard mask formed as a layer of hafnium oxide overlying the nitride layer; and an opening made through the layer of hafnium oxide, the layer of nitride and the BEOL dielectric film stack to expose the released region of the silicon layer disposed over the cavity in the buried oxide layer. The hard mask protects the underlying material during a MEMS/NEMS HF vapor release procedure.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SELF-ALIGNED EMITTER-BASE IN ADVANCED BiCMOS TECHNOLOGY]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146947.html</link>
            <description><![CDATA[A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146946.html</link>
            <description><![CDATA[A semiconductor device includes: a buffer layer provided on a substrate and made of a group III-V nitride semiconductor; a first semiconductor layer provided on the buffer layer and made of a group III-V nitride semiconductor; a second semiconductor layer provided on the first semiconductor layer and made of a group III-V nitride semiconductor; a back electrode provided on a back surface of the substrate and connected to a ground; a source electrode and a drain electrode provided on the second semiconductor layer so as to be apart from each other; a gate electrode provided on the second semiconductor layer; and a plug which passes through the second semiconductor layer, the first semiconductor layer, and the buffer layer, and reaches at least the substrate to electrically connect the source electrode and the back electrode.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146945.html</link>
            <description><![CDATA[A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE INCLUDING STEPPED GATE ELECTRODE AND FABRICATION METHOD THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146944.html</link>
            <description><![CDATA[Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[IN SITU GROWN GATE DIELECTRIC AND FIELD PLATE DIELECTRIC]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146943.html</link>
            <description><![CDATA[Methods and apparatuses are disclosed for providing heterostructure field effect transistors (HFETs) with high-quality gate dielectric and field plate dielectric. The gate dielectric and field plate dielectric are in situ deposited on a semiconductor surface. The location of the gate electrode may be defined by etching a first pattern in the field plate dielectric and using the gate dielectric as an etch-stop. Alternatively, an additional etch-stop layer may be in situ deposited between the gate dielectric and the field plate dielectric. After etching the first pattern, a conductive material may be deposited and patterned to define the gate electrode. Source and drain electrodes that electrically contact the semiconductor surface are formed on opposite sides of the gate electrode.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Method for Making FinFETs and Semiconductor Structures Formed Therefrom]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146942.html</link>
            <description><![CDATA[A method for making FinFETs and semiconductor structures formed therefrom is disclosed, comprising: providing a SiGe layer on a Si semiconductor substrate and a Si layer on the SiGe layer, wherein the lattice constant of the SiGe layer matches that of the substrate; patterning the Si layer and the SiGe layer to form a Fin structure; forming a gate stack on top and both sides of the Fin structure and a spacer surrounding the gate stack; removing a portion of the Si layer which is outside the spacer with the spacer as a mask, while keeping a portion of the Si layer which is inside the spacer; removing a portion of the SiGe layer which is kept after the patterning, to form a void; forming an insulator in the void; and epitaxially growing stressed source and drain regions on both sides of the Fin structure and the insulator.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146941.html</link>
            <description><![CDATA[A semiconductor device includes a transistor having a gate electrode, a first electrode, and a second electrode and first and second protection circuits each having one end commonly connected to the gate electrode and the other end connected to the first and second electrodes, respectively. The first and second protection circuits are formed in first and second polysilicon layers, respectively, formed separately on a single field insulating film.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[DESIGN STRUCTURE INCLUDING VOLTAGE CONTROLLED NEGATIVE RESISTANCE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146940.html</link>
            <description><![CDATA[Aspects of the invention provide a semiconductor tunneling device including voltage controlled negative resistance. In one embodiment, the semiconductor tunneling device includes: at least one pair of spaced apart terminals; an inter-level dielectric (ILD) layer between the at least one pair of spaced apart terminals; and a dielectric capping layer extending continuously over the at least one pair of spaced apart terminals and the ILD layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SILICONE ADHESIVE FOR SEMICONDUCTOR ELEMENT]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146939.html</link>
            <description><![CDATA[A silicone adhesive for a semiconductor element that is suitable as a die bonding material for fixing a light emitting diode chip to a substrate. The adhesive includes (a) an addition reaction-curable silicone resin composition having a viscosity at 25° C. of not more than 100 Pa·s, and yielding a cured product upon heating at 150° C. for 3 hours that has a type D hardness prescribed in JIS K6253 of at least 30, (b) a white pigment powder having an average particle size of less than 1 μm, and (c) a white or colorless and transparent powder having an average particle size of at least 1 μm but less than 10 μm. The adhesive exhibits high levels of concealment, effectively reflects light emitted from the LED chip, and also exhibits favorable chip positioning properties, superior adhesive strength, and excellent durability.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146938.html</link>
            <description><![CDATA[An exemplary embodiment described technology relates generally to an organic light emitting diode (OLED) display and a manufacturing method thereof. The organic light emitting diode (OLED) display according to an exemplary embodiment includes: a substrate; an encapsulation member; an organic light emitting element between the substrate and the encapsulation member; a middle sealing member including one side disposed between the substrate and the encapsulation member and another side extended from the one side to be bent and enclosing an edge of the encapsulation member; a first sealant sealing and combining the one side of the middle sealing member and the substrate to each other; a second sealant sealing and combining the other side of the middle sealing member and the encapsulation member to each other; and a getter at the one side of the middle sealing member and the encapsulation member.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[MOUNTING SUBSTRATE, LIGHT-EMITTING DEVICE, AND LAMP]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146937.html</link>
            <description><![CDATA[A substrate having a mounting surface on which an LED is mounted, including: a conductive member provided on the mounting surface and including an electrode and wiring which are electrically connected to the LED; a fitting portion to which a metal body is fitted; and a discharge-reducing portion provided between the conductive member and the fitting portion and having a face tilted with respect to a surface of the mounting substrate, thereby increasing a creeping distance between the conductive member and the fitting portion compared to the case where the discharge-reducing portion is not provided.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[LIGHT EMITTING DIODE CHIP, LIGHT EMITTING DIODE PACKAGE STRUCTURE, AND METHOD FOR FORMING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146936.html</link>
            <description><![CDATA[A light emitting diode chip, a light emitting diode package structure and a method for forming the same are provided. The light emitting diode chip includes a bonding layer, which has a plurality of voids, or a minimum horizontal distance between a surrounding boundary of the light emitting diode chip and the bonding layer is larger than O. The light emitting diode chip, the light emitting diode package structure and the method may improve the product yields and enhance the light emitting efficiency.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146935.html</link>
            <description><![CDATA[Provided is a semiconductor light emitting device. The semiconductor light emitting device includes a light emitting structure disposed under an insulating layer having a plurality of holes. A first electrode is disposed on the insulating layer and a second electrode disposed is disposed under the light emitting structure. A conductive supporting member is disposed under the second electrode. The plurality of contact protrusions are disposed in the holes of the insulating layer and include filler connected to the first conductive semiconductor layer and disposed in the plurality of holes. The conductive supporting member physically contacts with the second electrode and has a thickness thicker than that of the insulating layer. The first electrode is located at a higher position than an entire region of the insulating layer and the insulating layer is located at a higher position than an entire region of the light emitting structure.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[LIGHT-EMITTING DIODE DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146934.html</link>
            <description><![CDATA[A light-emitting diode device includes a substrate, an epitaxial layer and a first electrode. The epitaxial layer is disposed on the substrate. The first electrode is disposed on the epitaxial layer and includes a connecting portion and a conductive finger. The conductive finger has a first end and a second end, and the first end is connected to the connecting portion. At least one portion of the conductive finger is tapered along an extending direction of the conductive finger.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF FORMING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146933.html</link>
            <description><![CDATA[A semiconductor light-emitting device has a first principal surface, a second principal surface formed on a side opposite to the first principal surface, and a light-emitting layer. A p-electrode on the second principal surface is in the region of the light-emitting layer and surrounds an n-electrode. An insulating layer on the side of the semiconductor layer surrounds the p- and the n-electrodes. A p-metal pillar creates an electrical connection for the p-electrode, and an n-metal pillar creates an electrical connection for the n-electrode. A resin layer surrounds the end. portions of the p- and the n-metal pillars, and also covers the side surface of the semiconductor layer, the second principal surface, the p-electrode, the n-electrode, the insulating layer, the p-metal pillar and the n-metal pillar.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[LIGHT-EMITTING DIODE ARCHITECTURES FOR ENHANCED PERFORMANCE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146932.html</link>
            <description><![CDATA[The present invention relates to light-emitting diodes (LEDs), and related components, processes, systems, and methods. In certain embodiments, an LED that provides improved optical and thermal efficiency when used in optical systems with a non-rectangular input aperture (e.g., a circular aperture) is described. In some embodiments, the emission surface of the LED and/or an emitter output aperture can be shaped (e.g., in a non-rectangular shape) such that enhanced optical and thermal efficiencies are achieved. In addition, in some embodiments, chip designs and processes that may be employed in order to produce such devices are described.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[PIXEL STRUCTURE AND MANUFACTURING METHOD OF THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146931.html</link>
            <description><![CDATA[A pixel structure and manufacturing method of the same are described. The pixel structure includes a substrate, a switch transistor, a dielectric layer, a conducting connection line, a driving transistor, a capacitor and a pixel electrode. The substrate defines a transistor region and the switch transistor is disposed on the transistor region. The dielectric layer is disposed on the substrate and covers the switch transistor. The conducting connection line disposed on the dielectric layer is located over the transistor region. The driving transistor disposed on the dielectric layer is vertically stacked over the switch transistor and transistor region. The conducting connection line electrically connects the switch transistor to the driving transistor. The pixel electrode is electrically connected to the driving transistor.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[PHOSPHOR AND LIGHT EMITTING DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146930.html</link>
            <description><![CDATA[The present invention provides a phosphor emitting green fluorescence when being effectively excited by excitation light in a wavelength range from blue light to near-ultraviolet light, having an emission intensity that does not vary significantly with variation in the wavelength of the excitation light, and being manufactured easily. The phosphor includes a chemical structure represented by the following general formula (A): A(M1-a-xEuaMnx)L(Si1-bGeb)2O7 , (A), where A is one or more elements selected from Li, Na, and K, M is one or more elements selected from Mg, Ca, Sr, Ba, and Zn, L is one or more elements selected from Ga, Al, Sc, Y, La, Gd, and Lu, a is a numerical value satisfying 0.001≦a≦0.3, b is a numerical value satisfying 0≦b≦0.5, and x is a numerical value satisfying 0≦x≦0.2.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[LIGHT EMITTING DIODE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146929.html</link>
            <description><![CDATA[Disclosed is a light emitting diode (LED) comprising a light emitting stacked structure and an electrode structure formed to have a pattern on the light emitting stacked structure. The electrode structure of the LED includes a cluster of reflectors disposed along the pattern on the light emitting stacked structure, and a pad material layer formed to entirely cover the reflectors.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR LIGHT-EMITTING DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146928.html</link>
            <description><![CDATA[A nitride semiconductor light-emitting element 300 is a nitride semiconductor light-emitting element which has a multilayer structure 310, the multilayer structure 310 including an active layer which is made of an m-plane nitride semiconductor. The multilayer structure 310 has a light extraction surface 311a which is parallel to an m-plane in the nitride semiconductor active layer 306 and light extraction surfaces 311b which are parallel to a c-plane in the nitride semiconductor active layer 306. The ratio of an area of the light extraction surfaces 311b to an area of the light extraction surface 311a is not more than 46%.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD FOR COATING PHOSPHOR, APPARATUS TO PERFORM THE METHOD, AND LIGHT EMITTING DIODE COMPRISING PHOSPHOR COATING LAYER]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146927.html</link>
            <description><![CDATA[A method of forming a phosphor coating layer on a light emitting diode (LED) chip using electrophoresis includes separating phosphor particles in a suspension according to a particle size, and coating the phosphor particles on a surface of the LED chip by sequentially depositing the separated phosphor particles on the surface of the LED chip according to the particle size. An apparatus to form a phosphor coating layer on an LED chip includes an electrophoresis bath to accommodate a suspension containing phosphor particles separated into layers according to a particle size, and electrodes disposed inside the electrophoresis bath. The electrodes may include a cathode electrode on which the LED chip may be arranged, and an anode electrode.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ILLUMINATING APPARATUS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146926.html</link>
            <description><![CDATA[Provided is a lighting apparatus that is suitable as a substitute for a conventional halogen lamp when positively utilizing leaked light. The lighting apparatus comprises: a heat dissipator 12 that is in one of a bottomed cylindrical shape and a bowl shape, and that has a bottom portion, a circumferential wall portion, and an opening; and a light-emitting device 18b that is provided inside the heat dissipator 12 at the bottom portion and is operable to emit light, wherein the heat dissipator 12 has one or more windows 19 for leaking the emitted light outside the heat dissipator 12.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[LIGHT EMITTING DIODE HAVING DISTRIBUTED BRAGG REFLECTOR]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146925.html</link>
            <description><![CDATA[A light-emitting diode (LED) according to an exemplary embodiment includes a light-emitting structure arranged on a first surface of a substrate, the light-emitting structure including a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer. A first distributed Bragg reflector is arranged on a second surface of the substrate opposite to the first surface, the first distributed Bragg reflector to reflect light emitted from the light-emitting structure. The first distributed Bragg reflector has a reflectivity of at least 90% with respect to blue, green, and red light.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[LIGHT EMITTING DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146924.html</link>
            <description><![CDATA[According to one embodiment, a light emitting device includes a semiconductor light emitting element, a mounting member, a first wavelength conversion layer, and a first transparent layer. The semiconductor light emitting element emits a first light. The semiconductor light emitting element is placed on the mounting member. The first wavelength conversion layer is provided between the semiconductor light emitting element and the mounting member in contact with the mounting member. The first wavelength conversion layer absorbs the first light and emits a second light having a wavelength longer than a wavelength of the first light. The first transparent layer is provided between the semiconductor light emitting element and the first wavelength conversion layer in contact with the semiconductor light emitting element and the first wavelength conversion layer. The first transparent layer is transparent to the first light and the second light.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[LIGHT EMITTING APPARATUS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146923.html</link>
            <description><![CDATA[Provided is a light emitting apparatus. The light emitting apparatus includes a substrate; a light emitting device on the substrate; a fluorescent layer formed on the substrate and the light emitting device to surround the light emitting device; an encapsulant resin layer formed on the substrate and the fluorescent layer to surround the fluorescent layer; and a lens disposed on the light emitting device and supported by the substrate, wherein the lens includes a lens body having a first recess formed at a center of a top surface of the lens body and a second recess formed at a center of a bottom surface of the lens body, and a lens supporter provided at the bottom surface of the lens body to support the lens body such that the lens body is spaced apart from the substrate.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR LIGHT EMITTING DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146922.html</link>
            <description><![CDATA[Disclosed is a semiconductor light emitting device. The light emitting device includes a first conductive type semiconductor layer; an active layer on the first conductive type semiconductor layer; and a first electrode pad including a plurality of reflective layers on the first conductive type semiconductor layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[LIGHT EMITTING DEVICE AND FABRICATING METHOD THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146921.html</link>
            <description><![CDATA[A light emitting device and a fabricating method thereof are described. The light emitting device includes a substrate, a light emitting chip, a tubular structure, and a fluorescent conversion layer. The tubular structure is formed on a surface of the substrate. The light emitting chip is disposed on the surface of the substrate and is surrounded by the tubular structure. The fluorescent conversion layer is disposed in the tubular structure and covers the light emitting chip. A ratio of a maximal vertical thickness and a maximal horizontal thickness of the fluorescent conversion layer at the light emitting chip is between 0.1 and 10. A distance for the light ray to pass through the fluorescent conversion layer is controlled by using the tubular structure, so as to solve a problem of the conventional art that fluorescent powder coating package technique results in non-uniform color temperature of the emitted light.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ULTRAVIOLET LIGHT EMITTING DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146920.html</link>
            <description><![CDATA[The ultraviolet light emitting device includes a substrate; a light emitting structure on the substrate, and including a plurality of compound semiconductors, each including at least a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; a first electrode layer on the first conductive semiconductor layer; and a second electrode layer on the second conductive semiconductor layer. The first electrode layer is spaced apart from a side surface of the active layer, and is provided along a peripheral portion of the active layer. At least one of the first and second electrode layers is a reflective layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[RADIATION-EMITTING COMPONENT]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146919.html</link>
            <description><![CDATA[A radiation-emitting component includes a semiconductor layer stack having an active region that emits electromagnetic radiation, and at least one surface of the semiconductor layer stack or of an optical element that transmits the electromagnetic radiation wherein the surface has a normal vector, wherein on the at least one surface of the semiconductor layer stack or of the optical element through which the electromagnetic radiation passes, an antireflection layer is arranged such that, for a predetermined wavelength, it has a minimum reflection at a viewing angle relative to the normal vector of the surface at which an increase in a zonal luminous flux of the electromagnetic radiation has approximately a maximum.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Yttrium aluminum garnet phosphor, method for preparing the same, and light-emitting diode containing the same]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146918.html</link>
            <description><![CDATA[The present invention relates to yttrium aluminum garnet phosphor, a method of preparing the same and a light-emitting diode containing the same. The yttrium aluminum garnet phosphor of the present invention is represented by the following formula (I): (Y3-aMa)Al5-bSibO12 (I) wherein, 0.01≦a≦0.2, 0]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR LIGHT EMITTING DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146917.html</link>
            <description><![CDATA[A semiconductor light emitting device includes: a semiconductor lamination including a first semiconductor layer of a first conductivity type, an active layer formed on the first semiconductor layer, and a second semiconductor layer of a second conductivity type formed on the active layer; a rhodium (Rh) layer formed on one surface of the semiconductor lamination; a light reflecting layer containing Ag, formed on the Rh layer and having an area smaller than the Rh layer; and a cap layer covering the light reflecting layer. Migration of Ag is suppressed.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[NITRIDE SEMICONDUCTOR ULTRAVIOLET LIGHT-EMITTING DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146916.html</link>
            <description><![CDATA[A nitride semiconductor ultraviolet light-emitting device includes at least one first conductivity-type nitride semiconductor layer, a nitride semiconductor emission layer, at least one second conductivity-type nitride semiconductor layer and a transparent conductive film of crystallized Mgx1Zn1-x1O (0]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[LIGHT EMITTING DIODE AND FLIP-CHIP LIGHT EMITTING DIODE PACKAGE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146915.html</link>
            <description><![CDATA[A light emitting diode including a first doped layer, a light emitting layer, a second doped layer and a substrate is provided. A plurality of first grooves penetrate through the second doped layer and the light emitting layer. Thus, a partial surface of the first doped layer is exposed. At least one of the plurality of first grooves extends to edges of the second dope layer and the light emitting layer. An insulating layer is disposed over a part of second doped layer and extends to sidewalls of the first grooves. A first contact is set in the first grooves and electrically connected to the first doped layer. A second contact is set on the second doped layer and electrically connected to the second doped layer. By the first grooves, the first contact can be electrically connected to the first doped layer for improving current spreading.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING APPARATUS AND SEMICONDUCTOR LIGHT EMITTING APPARATUS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146914.html</link>
            <description><![CDATA[A method for manufacturing a semiconductor light emitting apparatus having first semiconductor layer and second semiconductor layer sandwiching a light emitting layer, first and second electrodes provided on respective major surfaces of the first semiconductor and second semiconductor layers to connect thereto, stacked dielectric films having different refractive indexes provided on portions of the major surfaces not covered by the first and second electrodes, and a protruding portion erected on at least a portion of a rim of at least one of the first and second electrodes. The mounting member includes a connection member connected to at least one of the first and second electrodes. The method includes causing the semiconductor light emitting device and a mounting member to face each other, and causing the connection member to contact and join to the at least one of the first and second electrodes using the protruding portion as a guide.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ELECTRONIC DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146913.html</link>
            <description><![CDATA[An electronic device including an insulating substrate, a chip and a patterned conductive layer is provided. The insulating substrate has an upper surface and a lower surface opposite to each other. The chip is disposed above the upper surface of the insulating substrate. The patterned conductive layer is disposed between the upper surface of the insulating substrate and the chip. The chip is electrically connected to an external circuit via the patterned conductive layer. Heat generated by the chip is transferred to external surroundings via the patterned conductive layer and the insulating substrate.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ELECTRONIC DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146912.html</link>
            <description><![CDATA[An electronic device including an insulating substrate, a plurality of conductive vias and a chip is provided. The insulating substrate has an upper surface and a lower surface opposite to each other. The conductive vias pass through the insulating substrate. The chip is disposed on the upper surface of the insulating substrate and includes a chip substrate, a semiconductor layer and a plurality of contacts. The semiconductor layer is located between the chip substrate and the contacts. The contacts are electrically connected to the conductive vias. The material of the insulating substrate and the material of the chip substrate are the same.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[LIGHT EMITTING DIODE PACKAGE AND LENS MODULE USED THEREIN]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146911.html</link>
            <description><![CDATA[An LED package includes an LED die and a lens module. The lens module covers the LED die. Light emitted from the LED die travels through the lens module. The lens module includes a concave lens and a convex lens with a smaller radial dimension than that of the concave lens. The concave lens covers the LED die. The convex lens is attached on a center of a surface of the concave lens away from the LED die. Optical axes of the concave lens and the convex lens are both collinear with a central axis of the LED die. Light from the LED die is diverged by the lens module to a peripheral side of the LED package.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[LIGHT EMITTING DIODE CHIP]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146910.html</link>
            <description><![CDATA[A light emitting diode chip includes a semiconductor layer sequence, the semiconductor layer sequence having an active layer that generates electromagnetic radiation, wherein the light emitting diode chip has a radiation exit area at a front side. At a rear side lying opposite the radiation exit area, the light emitting diode chip has, at least in regions, a mirror layer containing silver. A functional layer that reduces corrosion and/or improves adhesion of the mirror layer is arranged on the mirror layer, wherein a material from which the functional layer is formed is also distributed in the entire mirror layer. The material of the functional layer has a concentration gradient in the mirror layer, wherein the concentration of the material of the functional layer in the mirror layer decreases proceeding from the functional layer in the direction toward the semiconductor layer sequence.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR LIGHT EMITTING DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146909.html</link>
            <description><![CDATA[A semiconductor light emitting device includes a semiconductor layer including a light emitting layer, a p-side electrode provided on a second surface of the semiconductor layer, and an n-side electrode provided on the semiconductor layer to be separated from the p-side electrode. The p-side electrode includes a plurality of contact metal selectively provided on the semiconductor layer in contact with the second surface, a transparent film provided on the semiconductor layer in contact with the second surface between the plurality of contact metal, and a reflective metal provided on the contact metal and on the transparent film in contact with the contact metal, the reflective metal including silver. A surface area of a surface of the reflective metal on the light emitting layer side is greater than the sum total of a surface area of the plurality of contact metal contacting the semiconductor layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ILLUMINATION DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146908.html</link>
            <description><![CDATA[An illumination device including a substrate, a first conductive layer, a second conductive layer, a self-illuminating layer, and a first auxiliary conductive pattern layer is provided. The first conductive layer and the second conductive layer are disposed on the substrate. The self-illuminating layer is located between the first conductive layer and the second conductive layer to define an illumination region on the substrate. The first auxiliary conductive pattern layer is in contact with the first conductive layer and has an impedance smaller than that of the first conductive layer. A ratio of a perimeter (um) of the first auxiliary conductive pattern layer occupied in the illumination region to an area (um2) of the illumination region is greater than about 0 and smaller than or equal to about 0.0262 (1/um).]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Ultraviolet Reflective Contact]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146907.html</link>
            <description><![CDATA[A contact including an ohmic layer and a reflective layer located on the ohmic layer is provided. The ohmic layer is transparent to radiation having a target wavelength, while the reflective layer is at least approximately eighty percent reflective of radiation having the target wavelength. The target wavelength can be ultraviolet light, e.g., having a wavelength within a range of wavelengths between approximately 260 and approximately 360 nanometers.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ULTRAVIOLET SEMICONDUCTOR LIGHT EMITTING DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146906.html</link>
            <description><![CDATA[An ultraviolet light emitting device includes a first conductive semiconductor layer; an active layer under the first conductive semiconductor layer; a first reflective layer under the active layer; and a second conductive semiconductor layer under the first reflective layer. The first reflective layer comprises a plurality of compound semiconductor layers. The compound semiconductor layer comprises at least two semiconductor materials. The contents of the at least two semiconductor materials are different from each other.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Light Emitting, Photovoltaic Or Other Electronic Apparatus and System]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146905.html</link>
            <description><![CDATA[The present invention provides an electronic apparatus, such as a lighting device comprised of light emitting diodes (LEDs) or a power generating apparatus comprising photovoltaic diodes, which may be created through a printing process, using a semiconductor or other substrate particle ink or suspension and using a lens particle ink or suspension. An exemplary apparatus comprises a base; at least one first conductor; a plurality of substantially spherical or optically resonant diodes coupled to the at least one first conductor; at least one second conductor coupled to the plurality of diodes; and a plurality of substantially spherical lenses suspended in a polymer attached or deposited over the diodes. The lenses and the suspending polymer have different indices of refraction. In some embodiments, the lenses and diodes have a ratio of mean diameters or lengths between about 10:1 and 2:1. The diodes may be LEDs or photovoltaic diodes, and in some embodiments, have a junction formed at least partially as a hemispherical shell or cap.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Optoelectronic Structures with High Lumens Per Wafer]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146904.html</link>
            <description><![CDATA[An optoelectronic structure includes a wafer, a plurality of light emitting diode structures on a surface of the wafer, and a coating including a wavelength conversion material on the plurality of light emitting diode structures. The light emitting diode structures and the coating are configured to emit white light in response to electrical energy supplied to the light emitting diode structures. The light emitting diode structures from a single wafer are configured to generate an aggregate light output in excess of 800,000 lumens.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[DISPLAY UNIT AND METHOD OF MANUFACTURING THE SAME, ELECTRONIC APPARATUS, ILLUMINATION UNIT, AND LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146903.html</link>
            <description><![CDATA[A display unit includes: a plurality of light-emitting devices; and a separation section disposed between any adjacent two of the plurality of light-emitting devices and including a photoexcited material. A light-emitting device includes: an excitation light source; a wavelength conversion layer converting excitation light emitted from the excitation light source into light of a wavelength different from a wavelength of the excitation light; and a wavelength selection film disposed on a surface farther from the excitation light source of the wavelength conversion layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146902.html</link>
            <description><![CDATA[A display substrate includes a metal pattern, a first insulation layer pattern and a second insulation layer pattern. The metal pattern is on a base substrate. The first insulation pattern is on the metal pattern and includes one of a silicon nitride (SiNx) and a silicon oxide (SiOx). The second insulation pattern is on the first insulation pattern and includes a remaining one of the silicon nitride (SiNx) and the silicon oxide (SiOx).]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[COMPRESSION VOLUME COMPENSATION]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146901.html</link>
            <description><![CDATA[A liquid-filled light emitting diode (LED) bulb including a base, a shell, one or more LEDs, a thermally conductive liquid, and a bladder. The shell is connected to the base and the thermally conductive liquid is held within the shell. The one or more LEDs are disposed within the shell and immersed in the thermally conductive liquid. The bladder is also immersed in the thermally conductive liquid and is configured to compensate for expansion of the thermally conductive liquid.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146900.html</link>
            <description><![CDATA[A display substrate includes a base substrate, a switching element, a protecting layer, an organic layer, a first pixel electrode and a second pixel electrode. The switching element is on the base substrate, and includes a gate electrode, a source electrode and a drain electrode. The protecting layer is on the switching element, and includes a first hole exposing the drain electrode. The organic layer is on the protecting layer, and includes a second hole which exposes a side surface of the protecting layer which defines the first hole and exposes a top surface of the protecting layer which is adjacent to the side surface of the protecting layer. The first pixel electrode is on the organic layer. The second pixel electrode overlaps the first pixel electrode, and is electrically connected to the drain electrode via the first and second holes.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[CMOS SENSOR WITH IMAGE SENSING UNIT INTEGRATED THEREIN]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146899.html</link>
            <description><![CDATA[A complementary metal-oxide semiconductor (CMOS) sensor with an image sensing unit integrated therein is provided. The CMOS sensor includes a first substrate, a CMOS circuit, and a sensing device. The first substrate has the image sensing unit formed thereon. The CMOS circuit is disposed on the first substrate and has a receiving space. The sensing device is disposed in the receiving space. The image sensing unit is located at a position from which the image sensing unit can monitor the sensing device. Accordingly, the image sensing unit monitors the sensing device by sensing its image.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SiC MOSFETS AND SELF-ALIGNED FABRICATION METHODS THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146898.html</link>
            <description><![CDATA[The present application provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[4h-SiC SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146897.html</link>
            <description><![CDATA[A trench groove is formed and a silicon oxide film is buried in the periphery of a channel region of (0001) surface 4h-SiC semiconductor element. The oxide film in the trench groove is defined in such a planar layout that a tensile strain is applied along the direction of the c-axis and a compressive strain is applied along two or more of axes on a plane perpendicular to the c-axis. For example, trench grooves buried with an oxide film may be configured to such a layout that they are in a trigonal shape surrounding the channel, or are arranged symmetrically with respect to the channel as a center when arranged discretely.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR OPTICAL DEVICE HAVING AN AIR MEDIA LAYER AND THE METHOD FOR FORMING THE AIR MEDIA LAYER THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146896.html</link>
            <description><![CDATA[A method for fabricating air media layer within the semiconductor optical device is provided. The step of method includes a substrate is provided, a GaN thin film is formed on the substrate, a sacrificial layer is formed on the GaN thin film, and a nitride-containing semiconductor layer is formed on the sacrificial layer. The semiconductor optical device is immersed with an acidic solution to remove the portion of sacrificial layer to form an air media layer around the residual sacrificial layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[PINCH-OFF CONTROL OF GATE EDGE DISLOCATION]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146895.html</link>
            <description><![CDATA[The embodiments of processes and structures described provide mechanisms for improving the mobility of carriers. A dislocation is formed in a source or drain region between gate structures or between a gate structure and an isolation structure by first amortizing the source or drain region and then recrystallizing the region by using an annealing process with a low pre-heat temperature. A doped epitaxial material may be formed over the recrystallized region. The dislocation and the strain created by the doped epitaxial material in the source or drain region help increase carrier mobility.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[BIPOLAR JUNCTION TRANSISTOR STRUCTURE FOR REDUCED CURRENT CROWDING]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146894.html</link>
            <description><![CDATA[The present disclosure relates to a bipolar junction transistor (BJT) structure that significantly reduces current crowding while improving the current gain relative to conventional BJTs. The BJT includes a collector, a base region, and an emitter. The base region is formed over the collector and includes at least one extrinsic base region and an intrinsic base region that extends above the at least one extrinsic base region to provide a mesa. The emitter is formed over the mesa. The BJT may be formed from various material systems, such as the silicon carbide (SiC) material system. In one embodiment, the emitter is formed over the mesa such that essentially none of the emitter is formed over the extrinsic base regions. Typically, but not necessarily, the intrinsic base region is directly laterally adjacent the at least one extrinsic base region.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SIC CRYSTALLINE ON SI SUBSTRATES TO ALLOW INTEGRATION OF GAN AND SI ELECTRONICS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146893.html</link>
            <description><![CDATA[A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate is provided. The silicon substrate includes the GaN-based device on a SiC crystalline region. The SiC crystalline region is formed in the silicon substrate. The silicon substrate also includes the Si-based device on a silicon region, and the silicon region is next to the SiC crystalline region on the silicon substrate.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD FOR MANUFACTURING SUBSTRATE FOR SEMICONDUCTOR LIGHT EMITTING ELEMENT AND SEMICONDUCTOR LIGHT EMITTING ELEMENT USING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146892.html</link>
            <description><![CDATA[A light emitting element having a recess-protrusion structure on a substrate is provided. A semiconductor light emitting element 100 has a light emitting structure of a semiconductor 20 on a first main surface of a substrate 10. The first main surface of the substrate 10 has substrate protrusion portion 11, the bottom surface 14 of each protrusion is wider than the top surface 13 thereof in a cross-section, or the top surface 13 is included in the bottom surface 14 in a top view of the substrate. The bottom surface 14 has an approximately polygonal shape, and the top surface 13 has an approximately circular or polygonal shape with more sides than that of the bottom surface 14.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ENHANCEMENT-MODE HFET CIRCUIT ARRANGEMENT HAVING HIGH POWER AND A HIGH THRESHOLD VOLTAGE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146891.html</link>
            <description><![CDATA[A circuit includes input drain, source and gate nodes. The circuit also includes a group III nitride enhancement-mode HFET having a source, drain and gate and a voltage shifter having a first terminal connected to the gate of the enhancement mode HFET at a common junction. The circuit also includes a load resistive element connected to the common junction. The drain of the enhancement-mode HFET serves as the input drain node, the source of the enhancement-mode HFET serves as the input source node and a second terminal of the voltage shifter serves as the input gate node.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[HIGH ELECTRON MOBILITY TRANSISTOR]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146890.html</link>
            <description><![CDATA[A high electron mobility transistor (HEMT) according to example embodiments includes a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a reverse diode gate structure on the second semiconductor layer. A source and a drain may be on at least one of the first semiconductor layer and the second semiconductor layer. A gate electrode may be on the reverse diode gate structure.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146889.html</link>
            <description><![CDATA[An embodiment of a compound semiconductor device includes: a substrate; a nitride compound semiconductor stacked structure formed on or above the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. A recess positioning between the gate electrode and the drain electrode in a plan view is formed at a surface of the compound semiconductor stacked structure.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[MONOLITHIC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146888.html</link>
            <description><![CDATA[Disclosed herein is a monolithic semiconductor device including: a substrate; a high electron mobility transistor (HEMT) structure that is a first device structure formed on the substrate; and a laterally diffused metal oxide field effect transistor (LDMOSFET) structure that is a second device structure formed to be connected with the HEMT structure on the substrate.The monolithic semiconductor device according to preferred embodiments of the present invention is a device having characteristics of a normally-off device while maintaining high current characteristics in a normally-on state, thereby improving high current and high voltage operation characteristics.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[DIODE FOR USE IN A SWITCHED MODE POWER SUPPLY]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146887.html</link>
            <description><![CDATA[A tunable depletion diode is provided. Within this depletion diode, there is a depletion mode transistor that is coupled to the anode terminal at its gate and the cathode terminal at its drain. A diode is coupled between the source of the depletion mode transistor and the anode terminal, and a variable capacitor is coupled between the source of the depletion mode transistor and the anode terminal, where the capacitance of the variable capacitor is controls the reverse recovery time of the tunable depletion diode.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Vertical GaN JFET with Gate Source Electrodes on Regrown Gate]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146886.html</link>
            <description><![CDATA[A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Vertical GaN-Based Metal Insulator Semiconductor FET]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146885.html</link>
            <description><![CDATA[A semiconductor structure includes a III-nitride substrate having a top surface and an opposing bottom surface and a first III-nitride layer of a first conductivity type coupled to the top surface of the III-nitride substrate. The semiconductor structure also includes a second III-nitride layer of a second conductivity type coupled to the first III-nitride layer along a vertical direction and a third III-nitride layer of a third conductivity type coupled to the second III-nitride layer along the vertical direction. The semiconductor structure further includes a first trench extending through a portion of the third III-nitride layer to the first III-nitride layer, a second trench extending through another portion of the third III-nitride layer to the second III-nitride layer, and a first metal layer coupled to the second and the third III-nitride layers.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146884.html</link>
            <description><![CDATA[In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include depositing a first amorphous film having a first impurity, depositing a third amorphous lower-layer film on the first amorphous film, forming microcrystals on the third amorphous lower-layer film, depositing a third amorphous upper-layer film on the third amorphous lower-layer film to cover the microcrystals, depositing a second amorphous film having a second impurity on the third amorphous upper-layer film, and radiating microwaves to crystallize the third amorphous lower-layer film and the third amorphous upper-layer film to form a third crystal layer, and crystallize the first amorphous film and the second amorphous film to form a first crystal layer and a second crystal layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR THIN FILM, THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING SAME, AND MANUFACTURING EQUIPMENT OF SEMICONDUCTOR THIN FILM]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146883.html</link>
            <description><![CDATA[A method for manufacturing a semiconductor thin film is provided which can form its crystal grains having a uniform direction of crystal growth and being large in size and a manufacturing equipment using the above method, and a method for manufacturing a thin film transistor. In the above method, by applying an energy beam partially intercepted by a light shielding element, melt and re-crystallization occur with a light-shielded region as a starting point. The irradiation of the beam gives energy to the light-shielded region of the silicon thin film so that melt and re-crystallization occur with the light-shielded region as the starting point and so that a local temperature gradient in the light-shielded region is made to be 1200° C./μm or more. In the manufacturing method, a resolution of an optical system used to apply the energy beam is preferably 4 μm or less.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146882.html</link>
            <description><![CDATA[An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[AREA SENSOR AND DISPLAY APPARATUS PROVIDED WITH AN AREA SENSOR]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146881.html</link>
            <description><![CDATA[An area sensor of the present invention has a function of displaying an image in a sensor portion by using light-emitting elements and a reading function using photoelectric conversion devices. Therefore, an image read in the sensor portion can be displayed thereon without separately providing an electronic display on the area sensor. Furthermore, a photoelectric conversion layer of a photodiode according to the present invention is made of an amorphous silicon film and an N-type semiconductor layer and a P-type semiconductor layer are made of a polycrystalline silicon film. The amorphous silicon film is formed to be thicker than the polycrystalline silicon film. As a result, the photodiode according to the present invention can receive more light.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[TFT-LCD ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146880.html</link>
            <description><![CDATA[A thin film transistor liquid crystal display (TFT-LCD) array substrate and a manufacturing method thereof are provided. The TFT-LCD array substrate comprises a gate line and a data line. A pixel electrode and a thin film transistor (TFT) are formed in a pixel region defined by intersecting of the gate line and the data line. A light-blocking layer is formed over a TFT channel region of the thin film transistor.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146879.html</link>
            <description><![CDATA[Disclosed is a semiconductor device in which an n-channel type first thin film transistor and a p-channel type second thin film transistor are provided on the same substrate. The first thin film transistor has a first semiconductor layer (11), and the second thin film transistor has a second semiconductor layer (20), a third semiconductor layer (21), and a fourth semiconductor layer (22). The first semiconductor layer (11), the second semiconductor layer (20), the third semiconductor layer (21) and the fourth semiconductor layer (22) are formed of the same film, and the first and second semiconductor layers (11, 20) respectively have slanted portions (11e, 20e) positioned at respective peripheries, and main portions (11m, 20m) made of portions other than the slanted portions. A p-type impurity is implanted into the slanted portion (11e) of the first semiconductor layer at a concentration higher than that in the main portion (11m) of the first semiconductor layer and that in the main portion (20m) of the second semiconductor layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146878.html</link>
            <description><![CDATA[An organic light-emitting display apparatus includes a buffer layer that is on a substrate and includes nanoparticles including nickel (Ni), a pixel electrode on the buffer layer, an organic emission layer on the pixel electrode, and an opposite electrode on the organic emission layer. A method of manufacturing the organic light-emitting display apparatus is provided.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ORGANIC LIGHT-EMITTING DISPLAY APPARATUS]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146877.html</link>
            <description><![CDATA[An organic light-emitting display apparatus including: a substrate; a first electrode on the substrate; a second electrode on the first electrode; an intermediate layer between the first electrode and the second electrode, the intermediate layer being electrically connected with the first electrode and the second electrode, and including an organic emission layer; and a light reflection member overlapping a portion of the intermediate layer, the portion of the intermediate layer being less than an entire region of the intermediate layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146876.html</link>
            <description><![CDATA[A manufacturing method of a thin film transistor array substrate includes the following two steps: depositing a first metal layer on a substrate; and processing the first metal layer through coating photoresist, exposing, developing, etching, and stripping photoresist processes to form a light blocking metal portion and a lower electrode of a first storage capacitor simultaneously. With the manufacturing method of the present disclosure, the light blocking metal portion can protect components of TFTs from being exposed to strong light during the manufacturing process, which can improve a stability of the TFT.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SPLIT ELECTRODE FOR ORGANIC DEVICES]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146875.html</link>
            <description><![CDATA[A device is provided. The device includes a first electrode, an organic layer disposed over the first electrode and a second electrode disposed over the organic layer. The second electrode further includes a first conductive layer having an extinction coefficient and an index of refraction, a first separation layer disposed over the first conductive layer, and a second conductive layer disposed over the first separation layer. The first separation layer has an extinction coefficient that is at least 10% different from the extinction coefficient of the first conductive layer at 500 nm, or an index of refraction that is at least 10% different from the index of refraction of the first conductive layer at 500 nm. The device also includes a barrier layer disposed over the second conductive layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[SEMICONDUCTOR INTEGRATED CIRCUIT]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146874.html</link>
            <description><![CDATA[There is offered a semiconductor integrated circuit provided with a function to electrically identify a location where a defect such as chipping of an LSI die or separation of resin is caused. Corresponding to each of the four corners of a semiconductor substrate, each of L-shaped first through fourth peripheral wirings having a first end and a second end is disposed on a periphery of the semiconductor substrate. The first end of each of the first through fourth peripheral wirings is connected with a power supply wiring. Each of first through fourth detection circuits detects breaking of corresponding each of the first through fourth peripheral wirings in response to a voltage at the second end of corresponding each of the first through fourth peripheral wirings, and outputs corresponding each of first through fourth detection signals to corresponding each of output pads.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Integrated Mechanical Device for Electrical Switching]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146873.html</link>
            <description><![CDATA[An integrated circuit comprising a mechanical device for electrical switching comprising a first assembly being thermally deformable and having a beam held at at least two different locations by at least two arms, the beam and the arms being metal and disposed within the same metallization level, and further comprising at least one electrically conducting body. The first assembly has a first configuration at a first temperature and a second configuration at a second temperature different from the first temperature. The beam is out of contact with the electrically conducting body in one configuration in contact with the body in the other configuration. The beam establishes or breaks an electrical link passing through the said at least one electrically conducting body and through the said beam in the different configurations.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[Semiconductor Device and Method of Forming Conductive Pillars Having Recesses or Protrusions to Detect Interconnect Continuity Between Semiconductor Die and Substrate]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146872.html</link>
            <description><![CDATA[A semiconductor device has a semiconductor die and conductive pillar with a recess or protrusion formed over a surface of the semiconductor die. The conductive pillar is made by forming a patterning layer over the semiconductor die, forming an opening with a recess or protrusion in the patterning layer, depositing conductive material in the opening and recess or protrusion, and removing the patterning layer. A substrate has bump material deposited over a conductive layer formed over a surface of the substrate. The bump material is melted. The semiconductor die is pressed toward the substrate to enable the melted bump material to flow into the recess or over the protrusion if the conductive pillar makes connection to the conductive layer. A presence or absence of the bump material in the recess or protrusion of the conductive pillar is detected by X-ray or visual inspection.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[THIN FILM SEMICONDUCTOR MATERIAL PRODUCED THROUGH REACTIVE SPUTTERING OF ZINC TARGET USING NITROGEN GASES]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146871.html</link>
            <description><![CDATA[The present invention generally comprises a semiconductor film and the reactive sputtering process used to deposit the semiconductor film. The sputtering target may comprise pure zinc (i.e., 99.995 atomic percent or greater), which may be doped with aluminum (about 1 atomic percent to about 20 atomic percent) or other doping metals. The zinc target may be reactively sputtered by introducing nitrogen and oxygen to the chamber. The amount of nitrogen may be significantly greater than the amount of oxygen and argon gas. The amount of oxygen may be based upon a turning point of the film structure, the film transmittance, a DC voltage change, or the film conductivity based upon measurements obtained from deposition without the nitrogen containing gas. The reactive sputtering may occur at temperatures from about room temperature up to several hundred degrees Celsius. After deposition, the semiconductor film may be annealed to further improve the film mobility.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146870.html</link>
            <description><![CDATA[One object of one embodiment of the present invention is to provide a highly reliable semiconductor device including an oxide semiconductor, which has stable electrical characteristics. In a method for manufacturing a semiconductor device, a first insulating film is formed; source and drain electrodes and an oxide semiconductor film electrically connected to the source and drain electrodes are formed over the first insulating film; heat treatment is performed on the oxide semiconductor film so that a hydrogen atom in the oxide semiconductor film is removed; oxygen doping treatment is performed on the oxide semiconductor film, so that an oxygen atom is supplied into the oxide semiconductor film; a second insulating film is formed over the oxide semiconductor film; and a gate electrode is formed over the second insulating film so as to overlap with the oxide semiconductor film.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[TRANSISTOR AND METHOD FOR MANUFACTURING THE TRANSISTOR]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146869.html</link>
            <description><![CDATA[It is an object to reduce characteristic variation among transistors and reduce contact resistance between an oxide semiconductor layer and a source electrode layer and a drain electrode layer, in a transistor where the oxide semiconductor layer is used as a channel layer. In a transistor where an oxide semiconductor is used as a channel layer, at least an amorphous structure is included in a region of an oxide semiconductor layer between a source electrode layer and a drain electrode layer, where a channel is to be formed, and a crystal structure is included in a region of the oxide semiconductor layer which is electrically connected to an external portion such as the source electrode layer and the drain electrode layer.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[FIELD EFFECT TRANSISTOR]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146868.html</link>
            <description><![CDATA[A field effect transistor (FET) is provided. The active layer of this FET is composed of at least two different amorphous metal oxide semiconductor layer stacked together. Therefore, the two opposite surfaces of the active layer can have different band gap values.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[DISPLAY PANEL AND DISPLAY DEVICE]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146867.html</link>
            <description><![CDATA[In a transparent substrate (10), there are formed a semiconductor layer (14) formed of an oxide semiconductor, the semiconductor layer (14) functioning as a channel portion of a TFT (2); an electrode (16) formed of a transparent conductive material and located over the semiconductor layer (14), and a light-shielding conductor (17) formed on the electrode (16), the light-shielding conductor being formed of a material which has a conductivity higher than that of the transparent conductive material and which has light-shielding property, the light-shielding conductor covering the semiconductor layer (14). This structure can inhibit exposure of the oxide semiconductor which forms the channel portion toward a light, and can lower the resistance of the electrode formed of the transparent conductive material.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[CIRCUIT BOARD, DISPLAY DEVICE, AND METHOD FOR PRODUCING CIRCUIT BOARD]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146866.html</link>
            <description><![CDATA[A circuit board (1) includes a plurality of transistor elements on an insulating substrate (2). At least one of the plurality of transistor elements is an oxide TFT (10) including, as a channel layer (11), an oxide semiconductor. At least one of the plurality of transistor elements is an a-SiTFT (20) (i) being different from the oxide TFT (10) in functions as circuit components and (ii) including, as a channel layer (21), an amorphous silicon semiconductor. The oxide TFT (10) is a top gate transistor, and the a-SiTFT (20) is a bottom gate transistor. This provides: a configuration that can (a) enhance the performance of the circuit board equipped with the TFTs differing in their respective functions as circuit components and (b) reduce the area necessary for mounting the TFTs; and a method for producing the circuit board.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[HIGH-SENSITIVITY TRANSPARENT GAS SENSOR AND METHOD FOR MANUFACTURING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146865.html</link>
            <description><![CDATA[Disclosed are a high-sensitivity transparent gas sensor and a method for manufacturing the same. The transparent gas sensor includes a transparent substrate, a transparent electrode formed on the transparent substrate and a transparent gas-sensing layer formed on the transparent electrode. The transparent gas-sensing layer has a nanocolumnar structure having nanocolumns formed on the transparent electrode and gas diffusion pores formed between the nanocolumns.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146864.html</link>
            <description><![CDATA[A method for manufacturing a thin film transistor array panel includes forming a gate line and a gate electrode protruding from the gate line on a substrate; forming a gate insulating layer on the gate line and the gate electrode; depositing sequentially a semiconductor material and a metal material on the gate insulating layer; performing a first etching operation on the semiconductor material and the metal material using a first mask to form a semiconductor layer and a metal layer, the metal layer including a data line, a source electrode, and a drain electrode, in which the drain electrode protrudes from the data line, and the source electrode and the drain electrode having an integral shape; and performing a second etching operation on the metal layer using a second mask to divide the source electrode and the drain electrode.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[HIGH QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146863.html</link>
            <description><![CDATA[Substrates of GaN over silicon suitable for forming electronics devices such as heterostructure field effect transistors (HFETs), and methods of making the substrates, are disclosed. Voids in a crystalline Al2O3 film on a top surface of a silicon wafer are formed. The top surface of the silicon wafer is along the  silicon crystal orientation. A plurality of laminate layers is deposited over the voids and the Al2O3 film. Each laminate layer includes an AlN film and a GaN film. A transistor or other device may be formed in the top GaN film.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ARRAY SUBSTRATE INCLUDING THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146862.html</link>
            <description><![CDATA[An array substrate includes: a substrate; a gate line and a gate electrode on the substrate; a gate insulating layer on the gate line and the gate electrode, the gate insulating layer including a first insulator and a second insulator on the first insulator, wherein the first insulator includes an aluminum oxide material and has a first thickness, and the second insulator includes a hafnium oxide material and has a second thickness; an oxide semiconductor layer on the gate insulating layer over the gate electrode; a data line over the gate insulating layer; a source electrode and a drain electrode contacting the oxide semiconductor layer; a passivation layer on the data line, the source electrode and the drain electrode; and a pixel electrode on the passivation layer, the pixel electrode connected to a drain electrode through a drain contact hole.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
        <item>
            <title><![CDATA[ORGANIC EL PANEL, DISPLAY DEVICE USING SAME, AND METHOD FOR PRODUCING ORGANIC EL PANEL]]></title>
            <link>http://www.freepatentsonline.com/y2013/0146861.html</link>
            <description><![CDATA[An organic EL panel includes first electrode, second electrode; organic light-emitting layer of each of RGB colors, and functional layer disposed between the first electrode and the light-emitting layer. The functional layers of RGB colors have the same film thickness. Film thickness of each of the functional layers of RG colors corresponds to a first local maximum of light-extraction efficiency of light before passing through a color filter, and film thickness of the functional layer of B color corresponds to a value of light-extraction efficiency smaller than a first local maximum of light-extraction efficiency of light before passing through a color filter. The light-emitting layers of RGB colors differ in film thickness, such that the functional layers of RGB colors have the film thickness. Accordingly, the light of each of RGB colors emitted externally after passing through the color filter exhibits a local maximum of light-extraction efficiency.]]></description>
            <pubDate>Thu, 13 Jun 2013 08:00:00 EDT</pubDate>
        </item>
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