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US20040143705 Memory cache bank prediction  
A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an...
999
US20030051099 MEMORY CACHE BANK PREDICTION  
A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an...
999
7644236 Memory cache bank prediction  
A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an...
999
US20050132138 Memory cache bank prediction  
A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an...
995
6880063 Memory cache bank prediction  
A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an...
981
US20110225367 MEMORY CACHE DATA CENTER  
A data center system includes a memory cache coupled to a data center controller. The memory cache includes volatile memory and stores data that is persisted in a database in a different data...
942
8380931 Memory cache data center  
A data center system includes a memory cache coupled to a data center controller. The memory cache includes volatile memory and stores data that is persisted in a database in a different data...
938
US20160239432 APPLICATION-LAYER MANAGED MEMORY CACHE  
In order to prevent data thrashing and the resulting performance degradation, a computer system may maintain an application-layer cache space to more effectively use physical memory and, thus,...
823
7058864 Test for processor memory cache  
Systems, methods, software products test a memory cache of a processor that includes a test engine (e.g., a BISTE). High level test source code is formulated to use routines in API source code...
821
9195604 Dynamic memory cache size adjustment in a memory device  
Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size...
753
9411727 Split write operation for resistive memory cache  
A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes...
751
9858187 Buffering request data for in-memory cache  
Techniques are disclosed relating to an in-memory cache for web application data. In some embodiments, received transactions include multiple operations, including one or more cache operations to...
745
US20170116124 Buffering Request Data for In-Memory Cache  
Techniques are disclosed relating to an in-memory cache for web application data. In some embodiments, received transactions include multiple operations, including one or more cache operations to...
745
US20150026416 DYNAMIC MEMORY CACHE SIZE ADJUSTMENT IN A MEMORY DEVICE  
Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size...
745
6260119 Memory cache management for isochronous memory access  
Isochronous information is transferred between an IO device and a first buffer (N) of a plurality of buffers in a system memory. The isochronous information stored in the plurality of buffers is...
740
US20120311293 DYNAMIC MEMORY CACHE SIZE ADJUSTMENT IN A MEMORY DEVICE  
Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size...
734
9535843 Managed memory cache with application-layer prefetching  
In order to prevent data thrashing and the resulting performance degradation, a computer system may maintain an application-layer cache space to more effectively use physical memory and, thus,...
726
8886911 Dynamic memory cache size adjustment in a memory device  
Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size...
719
6389509 Memory cache device  
A memory cache device for a CD-ROM for use with a host computer capable of initially filling a clone area of the hard disk with data from the compact disc using a sequential striped fill process...
716
US20080082755 Administering An Access Conflict In A Computer Memory Cache  
Administering an access conflict in a computer memory cache, including receiving in a memory cache controller a write address and write data from a store memory instruction execution unit of a...
714
US20160239423 MANAGED MEMORY CACHE WITH APPLICATION-LAYER PREFETCHING  
In order to prevent data thrashing and the resulting performance degradation, a computer system may maintain an application-layer cache space to more effectively use physical memory and, thus,...
711
7203798 Data memory cache unit and data memory cache system  
A data memory cache unit is provided which is capable of heightening the speed of memory access. The cache unit 117 executes reading and writing of data in a 16-byte width line unit in a main...
706
US20040186959 Data memory cache unit and data memory cache system  
A data memory cache unit is provided which is capable of heightening the speed of memory access. The cache unit 117 executes reading and writing of data in a 16-byte width line unit in a main...
690
US20150121006 SPLIT WRITE OPERATION FOR RESISTIVE MEMORY CACHE  
A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes...
686
9239788 Split write operation for resistive memory cache  
A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes...
685
9990400 Builder program code for in-memory cache  
Techniques are disclosed relating to an in-memory cache. In some embodiments, in response to determining that data for a requested entry is not present in the cache (e.g., because it has been...
665
6078316 Display memory cache  
An optimized refresh strategy for increasing bandwidth of an LCD. The present invention results in an LCD suitable for dynamic display of information. In the present invention, a display memory is...
659
US20180322063 UNIFIED IN-MEMORY CACHE  
A pinned memory space for caching data can be provided in a data node. The data that is cached in the pinned memory space can be prevented from being swapped out. A virtual address can be assigned...
658
US20180074966 UNIFIED IN-MEMORY CACHE  
In-memory caching can include providing, in a data node, a pinned memory space for caching data in a distributed file system. The data that is cached in the pinned memory space is prevented from...
658
10031853 Unified in-memory cache  
In-memory caching can include providing, in a data node, a pinned memory space for caching data in a distributed file system. The data that is cached in the pinned memory space is prevented from...
658
US20160092355 SPLIT WRITE OPERATION FOR RESISTIVE MEMORY CACHE  
A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes...
658
10013501 In-memory cache for web application data  
Techniques are disclosed relating to caching web application data. In some embodiments, a computing system maintains a multi-tenant database and an in-memory cache for the database. In some...
657
US20170116125 Builder Program Code for In-Memory Cache  
Techniques are disclosed relating to an in-memory cache. In some embodiments, in response to determining that data for a requested entry is not present in the cache (e.g., because it has been...
656
US20170116135 In-Memory Cache for Web Application Data  
Techniques are disclosed relating to caching web application data. In some embodiments, a computing system maintains a multi-tenant database and an in-memory cache for the database. In some...
650
6711043 Three-dimensional memory cache system  
The preferred embodiments described herein provide a three-dimensional memory cache system. In one preferred embodiment, a modular memory device removably connectable to a host device is provided....
640
US20120151232 CPU in Memory Cache Architecture  
One exemplary CPU in memory cache architecture embodiment comprises a demultiplexer, and multiple partitioned caches for each processor, said caches comprising an I-cache dedicated to an...
635
US20020167829 Three-dimensional memory cache system  
The preferred embodiments described herein provide a three-dimensional memory cache system. In one preferred embodiment, a modular memory device removably connectable to a host device is provided....
635
US20120297142 DYNAMIC HIERARCHICAL MEMORY CACHE AWARENESS WITHIN A STORAGE SYSTEM  
Described is a system and computer program product for implementing dynamic hierarchical memory cache (HMC) awareness within a storage system. Specifically, when performing dynamic read operations...
629
9201794 Dynamic hierarchical memory cache awareness within a storage system  
Described is a system and computer program product for implementing dynamic hierarchical memory cache (HMC) awareness within a storage system. Specifically, when performing dynamic read operations...
625
9817765 Dynamic hierarchical memory cache awareness within a storage system  
A computing device-implemented method for implementing dynamic hierarchical memory cache (HMC) awareness within a storage system is described. Specifically, when performing dynamic read operations...
623
5550774 Memory cache with low power consumption and method of operation  
A memory cache (46) has a plurality of tag arrays (20, 22, 24, 26), a plurality of comparators (38, 40, 42, 44), a plurality a data arrays (12, 14, 16, 18), and a plurality of sense amplifiers...
622
US20120297144 DYNAMIC HIERARCHICAL MEMORY CACHE AWARENESS WITHIN A STORAGE SYSTEM  
A computing device-implemented method for implementing dynamic hierarchical memory cache (HMC) awareness within a storage system is described. Specifically, when performing dynamic read operations...
622
US20160048452 DYNAMIC HIERARCHICAL MEMORY CACHE AWARENESS WITHIN A STORAGE SYSTEM  
A computing device-implemented method for implementing dynamic hierarchical memory cache (HMC) awareness within a storage system is described. Specifically, when performing dynamic read operations...
618
9201795 Dynamic hierarchical memory cache awareness within a storage system  
A computing device-implemented method for implementing dynamic hierarchical memory cache (HMC) awareness within a storage system is described. Specifically, when performing dynamic read operations...
607
5636354 Data processor with serially accessed set associative memory cache interface and method  
A memory cache interface (12) serially accesses each way in an M-way set asociative memory cache (11) when it performs a read operation. The memory cache returns a data quantum and a tag...
606
US20180210843 REFRESH AWARE REPLACEMENT POLICY FOR VOLATILE MEMORY CACHE  
A method for replacing data on a volatile memory cache is provided. The volatile memory cache includes one or more memory banks and each of the memory banks includes a plurality of memory lines....
599
9984002 Visibility parameters for an in-memory cache  
Techniques are disclosed relating to an in-memory, software-managed cache configured to store web application data. In some embodiments, operations to cache data specify a visibility parameter for...
588
9223707 Mobile memory cache read optimization  
Examples of enabling cache read optimization for mobile memory devices are described. One or more access commands may be received, from a host, at a memory device. The one or more access commands...
584
US20180157418 SOLID STATE DRIVE (SSD) MEMORY CACHE OCCUPANCY PREDICTION  
Embodiments of the inventive concept include a solid state drive (SSD) shared array memory cache system including memory cache occupancy prediction. The system can include multiple SSD modules...
583
US20160147446 SOLID STATE DRIVE (SSD) MEMORY CACHE OCCUPANCY PREDICTION  
Embodiments of the inventive concept include a solid state drive (SSD) shared array memory cache system including memory cache occupancy prediction. The system can include multiple SSD modules...
583

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