Match Document Document Title Score
US20150324287 A METHOD AND APPARATUS FOR USING A CPU CACHE MEMORY FOR NON-CPU RELATED TASKS  
There is provided a processor for use in a computing system, said processor including at least one Central Processing Unit (CPU), a cache memory coupled to the at least one CPU, and a control unit...
1000
7472218 Assisted trace facility to improve CPU cache performance  
A system and method for recording trace data while conserving cache resources includes generating trace data and creating a cache line containing the trace data. The cache line is assigned a tag...
878
US20080065810 ASSISTED TRACE FACILITY TO IMPROVE CPU CACHE PERFORMANCE  
A system and method for recording trace data while conserving cache resources includes generating trace data and creating a cache line containing the trace data. The cache line is assigned a tag...
878
US20170285997 LOCAL PRIMARY MEMORY AS CPU CACHE EXTENSION  
A system may be provided comprising: a local primary memory; an interconnect; and a processor, the processor configured to cause, in response to a memory allocation request from an application,...
873
US20110161969 Consolidating CPU - Cache - Memory Access Usage Metrics  
A computer system is provided with a processing chip having one or more processor cores, with the processing chip in communication with an operating system having kernel space and user space. Each...
873
9921771 Local primary memory as CPU cache extension  
A system may be provided comprising: a local primary memory; an interconnect; and a processor, the processor configured to cause, in response to a memory allocation request from an application,...
873
5940588 Parallel testing of CPU cache and instruction units  
A method for testing CPU microprocessors having internal cache involves testing one IU and a portion of the internal cache, then loading a cache test routine to the tested portion of internal...
747
US20180067859 SELECTIVE ALLOCATION OF CPU CACHE SLICES TO DATABASE OBJECTS  
A central processing unit (CPU) forming part of a computing device, initiates execution of code associated with each of a plurality of objects used by a worker thread. The CPU has an associated...
731
9842052 Selective allocation of CPU cache slices to database objects  
A central processing unit (CPU) forming part of a computing device, initiates execution of code associated with each of a plurality of objects used by a worker thread. The CPU has an associated...
730
US20160306666 Selective Allocation of CPU Cache Slices to Objects  
A central processing unit (CPU) forming part of a computing device, initiates execution of code associated with each of a plurality of objects used by a worker thread. The CPU has an associated...
730
US20170289068 METHOD AND APPARATUS FOR ACCELERATING VM-TO-VM NETWORK TRAFFIC USING CPU CACHE  
Methods and apparatus for accelerating VM-to-VM Network Traffic using CPU cache. A virtual queue manager (VQM) manages data that is to be kept in VM-VM shared data buffers in CPU cache. The VQM...
730
5539878 Parallel testing of CPU cache and instruction units  
A method for testing CPU microprocessors having internal cache involves testing one IU and a portion of the internal cache, then loading a cache test routine to the tested portion of internal...
728
US20130246696 System and Method for Implementing a Low-Cost CPU Cache Using a Single SRAM  
One embodiment of the present invention relates to a CPU cache system that stores tag information and cached data in the same SRAM. The system includes an SRAM memory device, a lookup buffer, and...
708
8832376 System and method for implementing a low-cost CPU cache using a single SRAM  
One embodiment of the present invention relates to a CPU cache system that stores tag information and cached data in the same SRAM. The system includes an SRAM memory device, a lookup buffer, and...
708
9569265 Optimization of data locks for improved write lock performance and CPU cache usage in multi core architectures  
Data access optimization features the innovative use of a writer-present flag when acquiring read-locks and write-locks. Setting a writer-present flag indicates that a writer desires to modify a...
513
US20160098361 Optimization of Data Locks for Improved Write Lock Performance and CPU Cache usage in Mulit Core Architectures  
Data access optimization features the innovative use of a writer-present flag when acquiring read-locks and write-locks. Setting a writer-present flag indicates that a writer desires to modify a...
513
6675316 Method and system for recovery of the state of a failed CPU/cache/memory node in a distributed shared memory system  
A method of (and system for) recovering the state of a failed node in a distributed shared memory system, includes directing a flush of data from a failed node, and flushing the data from the...
451
5828860 Data processing device equipped with cache memory and a storage unit for storing data between a main storage or CPU cache memory  
A data processing device includes a cache memory, a load buffer primary (LBP) for storing 1-line instruction data including an instruction requested to be transmitted by an instruction processing...
436
US20140108727 STORAGE APPARATUS AND DATA PROCESSING METHOD  
To raise the CPU cache hit rate and improve the I/O processing. Controller is CPU configured from a CPU core and a CPU cache wherein the CPU selects memory bus optimization execution processing or...
364
8799580 Storage apparatus and data processing method  
To raise the CPU cache hit rate and improve the I/O processing. Controller is CPU configured from a CPU core and a CPU cache wherein the CPU selects memory bus optimization execution processing or...
364
5526508 Cache line replacing system for simultaneously storing data into read and write buffers having multiplexer which controls by counter value for bypassing read buffer  
A cache line replacing apparatus for use in a computer system having a central processing unit (CPU), a main memory and a cache memory, in which a cache line information of a CPU/cache bus is...
326
US20130335779 IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND STORAGE MEDIUM  
An image processing apparatus rendering a plurality of objects includes a CPU cache used for rendering, a determination unit configured to determine whether a cache miss of the CPU cache occurs in...
240
US20130275649 Access Optimization Method for Main Memory Database Based on Page-Coloring  
An access optimization method for a main memory database based on page-coloring is described. An access sequence of all data pages of a weak locality dataset is ordered by page-color, and all the...
234
8966171 Access optimization method for main memory database based on page-coloring  
An access optimization method for a main memory database based on page-coloring is described. An access sequence of all data pages of a weak locality dataset is ordered by page-color, and all the...
232
5673414 Snooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and cacheable memory in another I/O device  
In a computer system that contains an input output (I/O) bus connecting to I/O devices, a central processing unit (CPU), a CPU cache memory, a system memory not directly accessible via the I/O...
195
US20130207987 TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS  
A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing...
192
US20120200585 TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS  
A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing...
192
US20060248312 Systems and methods for CPU repair  
In one embodiment, a CPU cache management system is provided. The CPU management system includes, for example, a CPU chip and cache management logic. The CPU chip include cache elements that are...
191
8661289 Systems and methods for CPU repair  
In one embodiment, a CPU cache management system is provided. The CPU management system includes, for example, a CPU chip and cache management logic. The CPU chip include cache elements that are...
188
US20060248313 Systems and methods for CPU repair  
In one embodiment, a CPU cache management system is provided. The CPU management system includes, for example, a CPU chip and cache management logic. The CPU chip include cache elements that are...
183
6094203 Architecture for a graphics processing unit using main memory  
A CPU and a CPU cache memory unit is coupled to a system memory bus. A graphics processor with a graphics cache memory unit is also coupled to the system memory bus as a peer. The graphics...
179
9035962 Technique to share information among different cache coherency domains  
A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing...
174
US20020156977 Virtual caching of regenerable data  
A system includes a virtual caching mechanism. A virtual cache is mapped to an address range separate from the main memory address range within a cacheable address space of the system. Regenerable...
154
6124865 Duplicate cache tag store for computer graphics system  
A duplicate cache tag store, accessible to a graphics processor and to devices connected to the I/O bus without creating traffic on the system bus. Any entry into, or displacement from, the CPU...
154
US20050102477 Multiprocessor system  
A splittable/connectible bus 140 and a network 1000 for transmitting coherence transactions between CPUs are provided between the CPUs, and a directory 160 and a group setup register 170 for...
146
7159079 Multiprocessor system  
A splittable/connectible bus 140 and a network 1000 for transmitting coherence transactions between CPUs are provided between the CPUs, and a directory 160 and a group setup register 170 for...
146
5671372 Data processing system with microprocessor/cache chip set directly coupled to memory bus of narrower data width  
A cache of a CPU/cache chip set, has a wide data path that is directly coupled, to a memory data bus having a narrow data path. The coupling is effected by a data transfer path comprising only...
144
5831987 Method for testing cache memory systems  
A method for testing cache memory components of a computer system. The method tests RAM by detecting whether external memory caching can be disabled via software, and if not, the RAM is tested in...
135
4463424 Method for dynamically allocating LRU/MRU managed memory among concurrent sequential processes  
Short traces of consecutive CPU references to storage are accumulated and processed to ascertain hit ratio as a function of cache size. From this determination, an allocation of cache can be made....
133
5966728 Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device  
A computer system and method allow memory locations in both system memory and expansion memory devices coupled to an input/output (I/O) bus to be cacheable in a central processing unit (CPU)...
130
US20090031289 MEMORY MANAGEMENT FOR REMOTE SOFTWARE DEBUGGERS AND METHODS  
During software development for embedded systems, it is very common to use a remote debugger to debug the software applications. In such a debugging environment, the debugger will be running on a...
127
4464712 Second level cache replacement method and apparatus  
The disclosure controls the replacement selection of entries in a second level (L2) cache directory of a storage hierarchy using replaced and hit addresses of a dynamic look-aside translation...
126
9443174 Image processing apparatus, image processing method, and storage medium  
An image processing apparatus rendering a plurality of objects includes a CPU cache used for rendering, a determination unit configured to determine whether a cache miss of the CPU cache occurs in...
124
6292705 Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system  
A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased...
118
6466825 Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system  
A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased...
118
4195342 Multi-configurable cache store system  
In a data processing system which includes a plurality of system units such as a central processing unit (CPU), main memory, and cache memory all connected in common to a system bus and...
118
9035959 Technique to share information among different cache coherency domains  
A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing...
116
6885378 Method and apparatus for the implementation of full-scene anti-aliasing supersampling  
According to one embodiment, a computer system is disclosed. The computer system includes a graphics accelerator and a graphics cache coupled to the graphics accelerator. The graphics cache stores...
113
US20060230230 Systems and methods for CPU repair  
In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element...
113
US20020073296 Method and apparatus for mapping address space of integrated programmable devices within host system memory  
A Method and Apparatus for Mapping Address Space of Integrated Programmable Devices within Host System Memory is described herein.
110


Search
« search again