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7391245 |
Delay locked loop and method for setting a delay chain
A delay locked loop includes a delay chain that contains a plurality of series-connected delay cells, a phase detector arrangement that contains a plurality of phase detector cells and a control...
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7380152 |
Daisy chained multi-device system and operating method
A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the...
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7301831 |
Memory systems with variable delays for write data signals
Systems and methods for generating write data signals having variable delays for use in write operations to memory components are provided. These memory systems and methods include receiving a...
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7266024 |
***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Memory systems with variable delays for write data signals
Systems and methods for generating write data signals having variable delays for use in write operations to memory components are provided. These memory systems and methods include receiving a...
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7225311 |
Method and apparatus for coordinating memory operations among diversely-located memory components
A memory controller is disclosed. In one particular exemplary embodiment, the memory controller may comprise a first transmitter to output first and second write commands synchronously with respect...
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7225292 |
Memory module with termination component
A memory module having a termination component. The memory module includes multiple memory devices, a termination component, a control signal path and multiple data signal paths. The control signal...
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7210016 |
Method, system and memory controller utilizing adjustable write data delay settings
A method, system and memory controller that uses adjustable write data delay settings. The memory controller includes control transmit circuitry, data transmit circuitry and timing circuitry. The...
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7209397 |
Memory device with clock multiplier circuit
A memory device having a clock multiplier circuit. The memory device includes a clock generating circuit to receive a first clock signal having a first frequency and to generate a second clock...
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7200055 |
Memory module with termination component
A memory module having a termination component. The memory module includes first and second memory devices, a termination component and three sets of signal lines. A first set of signal lines is...
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7177998 |
Method, system and memory controller utilizing adjustable read data delay settings
A method, system and memory controller that uses adjustable read data delay settings. The memory controller includes control transmit circuitry, data reception circuitry and timing circuitry. The...
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