Matches 1 - 15 out of 15
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7413480 Silicon pillars for vertical transistors  
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide...
7371627 Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines  
A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a...
7368365 Memory array buried digit line  
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is...
7368344 Methods of reducing floating body effect  
Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion...
7285812 Vertical transistors  
Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to connect the digit line with the...
7247570 Silicon pillars for vertical transistors  
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide...
7229895 Memory array buried digit line  
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is...
7183164 Methods of reducing floating body effect  
Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion...
7120046 Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines  
A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward...
7015525 Folded bit line DRAM with vertical ultra thin body transistors  
A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly...
6995057 Folded bit line DRAM with vertical ultra thin body transistors  
A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly...
6903367 Programmable memory address and decode circuits with vertical body transistors  
Various embodiments provide a decoder for a memory array, comprising an array of address and output lines, vertical pillars, vertical floating gate transistors, and buried source lines. Each pillar...
6894532 Programmable logic arrays with ultra thin body transistors  
Structures and methods for programmable logic arrays are provided. In one embodiment, the programmable logic array includes a first logic plane and a second logic plane. The first logic plane...
6890812 Method of forming a memory having a vertical transistor  
Structures and method for an open bit line DRAM device are provided. The open bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar...
6881627 Flash memory with ultra thin vertical body transistors  
Structures and method for Flash memory with ultra thin vertical body transistors are provided. The Flash memory includes an array of memory cells including floating gate transistors. Each floating...
Matches 1 - 15 out of 15