Matches 1 - 41 out of 41
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7425491 Nanowire transistor with surrounding gate  
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a...
7416943 Peripheral gate stacks and recessed array gates  
Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices...
7413480 Silicon pillars for vertical transistors  
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide...
7372092 Memory cell, device, and system  
A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the...
7371627 Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines  
A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a...
7368365 Memory array buried digit line  
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is...
7368344 Methods of reducing floating body effect  
Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion...
7355230 Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array  
A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and...
7324367 Memory cell and method for forming the same  
A semiconductor memory cell structure having 4 F 2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the...
7323380 Single transistor vertical memory gain cell  
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region...
7298638 Operating an electronic device having a vertical gain cell that includes vertical MOS transistors  
A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a...
7285812 Vertical transistors  
Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to connect the digit line with the...
7276418 Memory cell and method for forming the same  
A semiconductor memory cell structure having 4F 2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the...
7247570 Silicon pillars for vertical transistors  
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide...
7241658 Vertical gain cell  
A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a...
7229895 Memory array buried digit line  
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is...
7224024 Single transistor vertical memory gain cell  
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region...
7205598 Random access memory device utilizing a vertically oriented select transistor  
A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the...
7199417 Merged MOS-bipolar capacitor memory cell  
A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a...
7183164 Methods of reducing floating body effect  
Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion...
7176513 Memory cell and method for forming the same  
A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, an epitaxial post...
7151690 6F2 3-Transistor DRAM gain cell  
A high density vertical three transistor memory cell is provided. The high density vertical three transistor memory cell is formed in a vertical pillar. The vertical pillar includes a first...
7149109 Single transistor vertical memory gain cell  
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region...
7120046 Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines  
A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward...
7045844 Memory cell and method for forming the same  
A semiconductor memory cell structure having 4F 2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the...
7034351 Memory cell and method for forming the same  
A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, an epitaxial post...
6975531 6F2 3-transistor DRAM gain cell  
A high density vertical three transistor memory cell is provided. The high density vertical three transistor memory cell is formed in a vertical pillar. The vertical pillar includes a first...
6956256 Vertical gain cell  
A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a...
6951789 Method of fabricating a random access memory device utilizing a vertically oriented select transistor  
A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the...
6943083 Merged MOS-bipolar capacitor memory cell  
A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a...
6940761 Merged MOS-bipolar capacitor memory cell  
A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a...
6934209 Temperature compensated T-RAM memory device and method  
A T-RAM memory cell includes a temperature compensation device to adjust the gate-to-source voltage of an access transistor for the memory cell as a function of temperature so that the...
6921935 Memory cell and method for forming the same  
A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, an epitaxial post...
6888199 High-density split-gate FinFET  
Disclosed is a method and structure for forming a split-gate fin-type field effect transistor (FinFET). The invention produces a split-gate fin-type field effect transistor (FinFET) that has...
6838723 Merged MOS-bipolar capacitor memory cell  
A high density vertical merged MOS bipolar capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a...
6806535 Non-volatile memory and fabricating method thereof  
A method of fabricating a non-volatile memory is provided. A longitudinal strip of stacked layer is formed over a substrate. The longitudinal strip is a stacked layer including a gate dielectric...
6804142 6F2 3-transistor DRAM gain cell  
A high density vertical three transistor memory cell is provided. The high density vertical three transistor memory cell is formed in a vertical pillar. The vertical pillar includes a first...
6797573 Memory cell and method for forming the same  
A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, an epitaxial post...
6781907 Temperature compensated T-RAM memory device and method  
A T-RAM memory cell includes a temperature compensation device to adjust the gate-to-source voltage of an access transistor for the memory cell as a function of temperature so that the...
6756625 Memory cell and method for forming the same  
A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, an epitaxial post...
6597203 CMOS gate array with vertical transistors  
Structures and methods for CMOS gate arrays with vertical transistors are provided. The CMOS gate arrays with vertical transistors comprise a logic circuit. The logic circuit includes a dynamic...
Matches 1 - 41 out of 41